TPS54352-EP, TPS54353-EP, TPS54354-EP
TPS54355-EP, TPS54356-EP, TPS54357-EP
www.ti.com ....................................................................................................................................................... SLVS684A – JANUARY 2007 – REVISED JULY 2009
4.5-V TO 20-V INPUT, 3-A OUTPUT SYNCHRONOUS PWM SWITCHES
WITH INTEGRATED FET (SWIFT™)
FEATURES
1
SIMPLIFIED SCHEMATIC
• 100-mΩ, 4.5-A Peak MOSFET Switch for High
Efficiency at 3-A Continuous Output Current
• Use External Low-Side MOSFET or Diode
• Fixed-Output Versions – 1.2 V/1.5 V/1.8 V/
2.5 V/3.3 V/5 V
• Internally Compensated for Low Parts Count
• Synchronize to External Clock
• 180° Out-of-Phase Synchronization
• Wide Pulse Width Modulation (PWM)
Frequency – Fixed 250 kHz,
500 kHz, or Adjustable 250 kHz to 700 kHz
• Internal Slow Start
• Load Protected by Peak Current Limit and
Thermal Shutdown
• Adjustable Undervoltage Lockout
• 16-Pin PowerPAD™ Thin Shrink Small-Outline
Package (TSSOP) (PWP)
2
Input
Voltage
TPS54356
VIN
SYNC
PWRGD
ENA
BOOT
BIAS
PH
Output
Voltage
LSG
PGND
VSENSE
PWRPAD
EFFICIENCY
vs
OUTPUT CURRENT
100
VI = 6 V
95
VI = 12 V
APPLICATIONS
•
•
•
•
Industrial and Commercial Low-Power
Systems
LCD Monitors and TVs
Computer Peripherals
Point-of-Load Regulation for High
Performance DSPs, FPGAs, ASICs, and
Microprocessors
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Efficiency − %
90
85
80
75
70
65
60
VI= 12 V
VO= 3.3 V
fs = 500 kHz
55
50
0
1
2
3
4
IO − Output Current − A
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Additional temperature ranges are available - contact factory
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
TPS54352-EP, TPS54353-EP, TPS54354-EP
TPS54355-EP, TPS54356-EP, TPS54357-EP
SLVS684A – JANUARY 2007 – REVISED JULY 2009 ....................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION
The TPS5435x is a medium-output-current synchronous buck PWM converter with an integrated high-side
MOSFET and a gate driver for an optional low-side external MOSFET. Features include a high-performance
voltage error amplifier that enables maximum performance under transient conditions. The TPS5435x has an
undervoltage lockout (UVLO) circuit to prevent start-up until the input voltage reaches a preset value, an internal
slow-start circuit to limit in-rush currents, and a power-good (PWRGD) output to indicate valid output conditions.
The synchronization feature is configurable as either an input or an output for easy 180° out-of-phase
synchronization.
The TPS5435x devices are available in a thermally enhanced 16-pin PowerPAD™ Thin Shrink Small-Outline
Package (TSSOP). TI provides evaluation modules and the SWIFT™ Designer software tool to aid in quickly
achieving high-performance power-supply designs to meet aggressive equipment development cycles.
2
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Copyright © 2007–2009, Texas Instruments Incorporated
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TPS54355-EP, TPS54356-EP, TPS54357-EP
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
–55°C to 125°C
OUTPUT VOLTAGE
PART NUMBER
Plastic HTSSOP – PWP
1.2 V
TPS54352MPWPREP (2)
TBD
Plastic HTSSOP – PWP
1.5 V
TPS54353MPWPREP (2)
TBD
Plastic HTSSOP – PWP
1.8 V
TPS54354MPWPREP
Plastic HTSSOP – PWP
2.5 V
TPS54355MPWPREP (2)
Plastic HTSSOP – PWP
3.3 V
TPS54356MPWPREP
Plastic HTSSOP – PWP
(1)
(2)
PACKAGE
MARKING
PACKAGE (1)
TJ
5V
TPS54357MPWPREP
PMDM
TBD
PMEM
(2)
TBD
The PWP package also is available taped and reeled. Add an R suffix to the device type (i.e., TPS5435xPWPR).
Product preview
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VIN
Input voltage range, VI
Output voltage range, VO
Source current, IO
VSENSE
–0.3 V to 8 V
UVLO
–0.3 V to 8 V
SYNC
–0.3 V to 4 V
ENA
–0.3 V to 4 V
BOOT
VI(PH) + 8 V
VBIAS
–0.3 V to 8.5 V
LSG
–0.3 V to 8.5 V
SYNC
–0.3 V to 4 V
RT
–0.3 V to 4 V
PWRGD
–0.3 V to 6 V
COMP
–0.3 V to 4 V
PH
–1.5 V to 22 V
PH
Internally Limited (A)
LSG (steady-state current)
10 mA
COMP, VBIAS
3 mA
SYNC
Sink current, IS
Voltage differential
–0.3 V to 21.5 V
5 mA
LSG (steady-state current)
100 mA
PH (steady-state current)
500 mA
COMP
3 mA
ENA, PWRGD
10 mA
AGND to PGND
±0.3 V
Operating virtual junction temperature range, TJ
–55°C to 150°C
Storage temperature range, Tstg
–65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(1)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2007–2009, Texas Instruments Incorporated
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Electrostatic Discharge (ESD) Protection
MIN
MAX
UNIT
Human-Body Model (HBM)
600
V
Charged-Device Model (CDM)
1.5
kV
Recommended Operating Conditions
TPS54352-6
Input voltage range, VI
TPS54357
Operating junction temperature, TJ
MIN
MAX
4.5
20
6.65
20
–55
125
UNIT
V
°C
Electrical Characteristics
TJ = –55°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Current
IQ
VIN
Quiescent current
Operating current, PH pin open,
No external low side MOSFET, RT = Hi-Z
5
Shutdown, ENA = 0 V
1
Start threshold
voltage
TPS54352-6
Stop threshold
voltage
TPS54352-6
3.69
3.97
TPS54357
5.45
5.8
Hysteresis
TPS54357
mA
4.32
4.48
6.4
6.65
TPS54352-6
350
TPS54357
600
V
V
mV
Output Voltage
TPS54352
TPS54353
TPS54354
VO
Output voltage
TPS54355
TPS54356
TPS54357
TJ = 25°C, IO = 100 mA to 3 A
1.88
1.2
1.212
IO = 100 mA to 3 A
1.176
1.2
1.224
TJ = 25°C, IO = 100 mA to 3 A
1.485
1.5
1.515
1.47
1.5
1.53
TJ = 25°C, IO = 100 mA to 3 A
1.782
1.8
1.818
IO = 100 mA to 3 A
1.764
1.8
1.836
TJ = 25°C, IO = 100 mA to 3 A
2.475
2.5
2.525
2.45
2.5
2.55
TJ = 25°C, VIN = 5.5 V to 20 V,
IO = 100 mA to 3 A
3.267
3.3
3.333
VIN = 5.5 V to 20 V, IO = 100 mA to 3 A
3.234
3.3
3.366
4.95
5
5.05
4.9
5
5.1
1.2
1.25
IO = 100 mA to 3 A
IO = 100 mA to 3 A
TJ = 25°C, VIN = 7.5 V to 20 V,
IO = 100 mA to 3 A
VIN = 7.5 V to 20 V, IO = 100 mA to 3 A
V
Under Voltage Lockout (UVLO)
Start threshold voltage
UVLO
Stop threshold voltage
1.02
Hysteresis
V
1.1
V
100
mV
Bias Voltage (VBIAS)
VBIAS
Output voltage
IVBIAS = 5 mA, VIN ≥ 12 V
7.5
7.8
8
IVBIAS = 5 mA, VIN = 4.5 V
4.4
4.47
4.5
RT grounded
200
250
300
RT open
400
500
600
RT = 100 kΩ (1% resistor to AGND)
425
500
575
V
Oscillator (RT)
Internally set PWM switching frequency
Externally set PWM switching frequency
4
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kHz
kHz
Copyright © 2007–2009, Texas Instruments Incorporated
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www.ti.com ....................................................................................................................................................... SLVS684A – JANUARY 2007 – REVISED JULY 2009
Electrical Characteristics (continued)
TJ = –55°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Falling-Edge-Triggered Bidirectional Sync System (SYNC)
SYNC out low-to-high rise time
(10%/90%) (1)
25 pF to ground
200
500
ns
SYNC out high-to-low fall time
(90%/10%) (1)
25 pF to ground
5
10
ns
Falling-edge delay time (1)
Delay from rising edge to rising edge of PH
pins, See Figure 19
180
°
RT = 100 kΩ
100
ns
Delay
RT = 100 kΩ
(falling-edge SYNC to rising-edge PH) (1)
360
ns
Minimum input pulse width
(1)
SYNC out high-level voltage
50-kΩ resistor to ground, No pullup resistor
2.5
V
SYNC out low-level voltage
0.6
SYNC in low-level threshold
0.8
V
SYNC in high-level threshold
SYNC in frequency range (1)
2.3
Percentage of programmed frequency
V
–10%
10%
225
770
V
kHz
Feed-Forward Modulator (Internal Signal)
Modulator gain
VIN = 12 V, TJ = 25°C
8
Modulator gain variation
±25%
Minimum controllable ON time (1)
Maximum duty factor (1)
180
VIN = 4.5 V
80%
ns
86%
VSENSE
Input bias current, VSENSE
µA
1
Enable (ENA)
Disable low-level input voltage
TPS54352
TPS54353
Internal
slow-start time
(10% to 90%)
TPS54354
TPS54355
TPS54356
TPS54357
0.5
fs = 250 kHz, RT = ground (1)
3.2
fs = 500 kHz, RT = Hi-Z (1)
1.6
fs = 250 kHz, RT = ground (1)
4
fs = 500 kHz, RT = Hi-Z (1)
2
fs = 250 kHz, RT = ground
4.6
fs = 500 kHz, RT = Hi-Z (1)
2.3
fs = 250 kHz, RT = ground (1)
4.4
fs = 500 kHz, RT = Hi-Z (1)
2.2
fs = 250 kHz, RT = ground (1)
5.9
fs = 500 kHz, RT = Hi-Z (1)
2.9
fs = 250 kHz, RT = ground (1)
5.4
fs = 500 kHz, RT = Hi-Z
(1)
Pullup current source
Pulldown MOSFET
(1)
V
ms
2.7
1.8
5
II(ENA) = 1 mA
0.1
Rising voltage
97%
10
µA
V
Power Good (PWRGD)
Power-good threshold
Rising-edge delay (1)
PWRGD
(1)
fs = 250 kHz
4
fs = 500 kHz
2
Output saturation voltage
Isink = 1 mA, VIN > 4.5 V
0.05
Output saturation voltage
Isink = 100 µA, VIN = 0 V
0.76
Open-drain leakage current
Voltage on PWRGD = 6 V
ms
V
V
3
µA
Specified by design, not production tested
Copyright © 2007–2009, Texas Instruments Incorporated
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TPS54355-EP, TPS54356-EP, TPS54357-EP
SLVS684A – JANUARY 2007 – REVISED JULY 2009 ....................................................................................................................................................... www.ti.com
Electrical Characteristics (continued)
TJ = –55°C to 125°C, VIN = 4.5 V to 20 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.3
4.5
6.5
UNIT
Current Limit
Current limit
Current-limit hiccup time
VIN = 12 V
(2)
fs = 500 kHz
A
4.5
ms
165
°C
7
°C
15
ns
ns
Thermal Shutdown
Thermal-shutdown trip point (2)
Thermal-shutdown hysteresis
(2)
Low-Side MOSFET Driver (LSG)
Turn-on rise time, (10/90%) (2)
VIN = 4.5 V, Capacitive load = 1000 pF
Deadtime
VIN = 12 V
60
VIN = 4.5 V sink/source
7.5
VIN = 12 V sink/source
5
Driver ON resistance
Ω
Output Power MOSFETS (PH)
Phase-node voltage when disabled
Voltage drop, low-side FET and diode
rDS(ON)
(2)
(3)
6
High-side power MOSFET switch (3)
DC coinditions and no load, ENA = 0 V
0.5
V
VIN = 4.5 V, Idc = 100 mA
1.13
1.42
VIN = 12 V, Idc = 100 mA
1.08
1.38
VIN = 4.5 V, BOOT-PH = 4.5 V, IO = 0.5 A
150
300
VIN = 12 V, BOOT-PH = 8V, IO = 0.5 A
100
200
V
mΩ
Specified by design, not production tested
Resistance from VIN to PH pins
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TPS54355-EP, TPS54356-EP, TPS54357-EP
www.ti.com ....................................................................................................................................................... SLVS684A – JANUARY 2007 – REVISED JULY 2009
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
VIN
VIN
UVLO
PWRGD
RT
SYNC
ENA
COMP
1
2
3
4
5
6
7
8
THERMAL
PAD
16
15
14
13
12
11
10
9
BOOT
PH
PH
LSG
VBIAS
PGND
AGND
VSENSE
NOTE: If there is not a pin 1 indicator, turn device to enable
reading the symbol from left to right. Pin 1 is at the lower
left corner of the device.
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NO.
NAME
1, 2
VIN
Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10-µF ceramic capacitor. Place cap as
close to device as possible; see Figure 23 for an example.
3
UVLO
Undervoltage lockout. Connecting an external resistive voltage divider from VIN to the pin overrides the
internal default VIN start and stop thresholds.
4
PWRGD
Power good output. Open-drain output. A low on the pin indicates that the output is less than the desired
output voltage. There is an internal rising-edge filter on the output of the PWRGD comparator.
5
RT
Frequency setting. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT
pin to ground or floating will set the frequency to an internally preselected frequency.
SYNC
Bidirectional synchronization I/O. SYNC is an output when the RT pin is floating or connected low. The
output is a falling-edge signal out of phase with the rising edge of PH. SYNC may be used as an input to
synchronize to a system clock by connecting to a falling edge signal when an RT resistor is used. See 180°
Out of Phase Synchronization operation in the Application Information section. In all cases, a 10-kΩ resistor
must be tied to the SYNC pin in parallel with ground. For information on how to extend slow start, see the
Enable (ENA) and Internal Slow Start section.
6
7
ENA
8
COMP
Enable. Below 0.5 V, the device stops switching. Float pin to enable.
9
VSENSE
10
AGND
Analog ground. Internally connected to the sensitive analog ground circuitry. Connect to PGND and
PowerPAD package.
11
PGND
Power ground. Noisy internal ground. Return currents from the LSG driver output return through the PGND
pin. Connect to AGND and PowerPAD package.
12
VBIAS
Internal 8-V bias voltage. A 1-µF ceramic bypass capacitance is required on the VBIAS pin.
13
LSG
Error amplifier output. Do not connect anything to this pin.
Feedback
Gate drive for optional low-side MOSFET. Connect gate of n-channel MOSFET for a higher efficiency
synchronous buck converter configuration. Otherwise, leave open and connect Schottky diode from ground
to PH pins.
14, 15
PH
16
BOOT
Phase node. Connect to external L-C filter.
Bootstrap capacitor for high-side gate driver. Connect a 0.1-µF ceramic capacitor from BOOT to PH pins.
PowerPAD
PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 23 for an
example PCB layout.
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FUNCTIONAL BLOCK DIAGRAM
BOOT
VIN
PH
320 kΩ
Hiccup
UVLO
UVLO
125 kΩ(1)
SYNC
Current Limit
1.2V
2x Oscillator
RT
Bias + Drive
Regulator
PWM Ramp
(FeedFoward)
Z3
VBIAS
PWM
Comparator
COMP
S
Q
Adaptive Deadtime
and
Control Logic
Z1
Z4
VSENSE
VBIAS2
Z2
R
Error
Amplifier
LSG
Z5
Thermal
Shutdown
Reference
System
PWRGD
UVLO
5 µA
VSENSE
97% Ref
ENA
Hiccup
Timer
VBIAS
UVLO
Rising
Edge
Delay
Hiccup
TPS5435x
(1) 75
POWERPAD
kΩ for the TPS54357
VBIAS
PGND
AGND
DETAILED DESCRIPTION
Undervoltage Lockout (UVLO)
The UVLO system has an internal voltage divider from VIN to AGND. The defaults for the start/stop values are
labeled VIN and are given in Table 1. The internal UVLO threshold can be overridden by placing an external
resistor divider from VIN to ground. The internal divider values are approximately 320 kΩ for the high-side
resistor and 125 kΩ for the low-side resistor. The divider ratio (and, therefore, the default start/stop values) is
quite accurate, but the absolute values of the internal resistors may vary as much as 15%. If high accuracy is
required for an externally adjusted UVLO threshold, select lower-value external resistors to set the UVLO
threshold. Using a 1-kΩ resistor for the low-side resistor (R2 see Figure 1) is recommended. Under no
circumstances should the UVLO pin be connected directly to VIN.
Table 1. Start/Stop Voltage Threshold
VIN (default)
START VOLTAGE THRESHOLD
STOP VOLTAGE THRESHOLD
TPS54352-6
4.49
3.69
TPS54357
6.65
5.45
1.24
1.02
UVLO
The equations for selecting the UVLO resistors are:
VIN(start)
1 kW
R1 +
* 1 kW
1.24 V
(R1 ) 1 kW)
1.02 V
VIN(stop) +
1 kW
8
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(1)
(2)
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Input
Voltage
Supply
R2
(1) 75
320 kΩ
R1
1 kΩ
125 kΩ (1)
kΩ for the TPS54357
Figure 1. Circuit Using External UVLO Function
For applications that require an UVLO threshold greater than 4.49 V (6.6 V for TPS54357), external resistors
may be implemented (see Figure 1) to adjust the start-voltage threshold. For example, an application needing a
UVLO start voltage of approximately 7.8 V using equation 1, R1 is calculated to the nearest standard resistor
value of 5.36 kΩ. Using equation 2, the input voltage stop threshold is calculated as 6.48 V.
Enable (ENA) and Internal Slow Start
The TPS5435x has an internal digital slow start that ramps the reference voltage to its final value in 1150
switching cycles. The internal slow-start time (10% to 90%) is approximated by the following expression:
1.15k
T
(ms) +
SS_INTERNAL
ƒs (kHz) n
Use n in Table 2.
(3)
Table 2. Slow-Start Characteristics
DEVICE
n
TPS54352
1.485
TPS54353
1.2
TPS54354
1
TPS54355
1.084
TPS54356
0.818
TPS54357
0.900
Once the TPS5435x device is in normal regulation, the ENA pin is high. If ENA is pulled below the stop threshold
of 0.5 V, switching stops and the internal slow start resets. If an application requires the TPS5435x to be
disabled, use open-drain or open-collector output logic to interface to ENA (see Figure 2). ENA has an internal
pullup current source. Do not use external pullup resistors.
5 µA
Disabled
RSS
CSS
Enabled
Figure 2. Interfacing to the ENA Pin
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Extending Slow-Start Time
In applications that use large values of output capacitance, there may be a need to extend the slow-start time to
prevent the startup current from tripping the current limit. The current-limit circuit is designed to disable the
high-side MOSFET and reset the internal voltage reference for a short amount of time when the high-side
MOSFET current exceeds the current-limit threshold. If the output capacitance and load current cause the startup
current to exceed the current-limit threshold, the power-supply output will not reach the desired output voltage.
To extend the slow-start time and to reduce the startup current, an external resistor and capacitor can be added
to the ENA pin. The slow-start capacitance is calculated using the following equation:
CSS (µF) = 5.55 10−3
n
Tss (ms)
Use n in Table 2.
(4)
The RSS resistor must be 2 kΩ and the slow-start capacitor must be less than 0.47 µF.
Switching Frequency (RT)
The TPS5435x has an internal oscillator that operates at twice the PWM switching frequency. The internal
oscillator frequency is controlled by the RT pin. Grounding RT sets the PWM switching frequency to a default
frequency of 250 kHz. Floating RT sets the PWM switching frequency to 500 kHz.
Connecting a resistor from RT to AGND sets the frequency according to the following equation (also see
Figure 30).
46000
RT (kW) +
ƒ s (kHz) * 35.9
(5)
RT controls the SYNC pin functions. If RT is floating or grounded, SYNC is an output. If the switching frequency
has been programmed using a resistor from RT to AGND, SYNC functions as an input.
The internal voltage-ramp charging current increases linearly with the set frequency and keeps the feed-forward
modulator constant (Km = 8), regardless of the frequency set point.
Table 3.
SWITCHING FREQUENCY
SYNC PIN
RT PIN
250 kHz, internally set
Generates SYNC output signal
AGND
500 kHz, internally set
Generates SYNC output signal
Float
Externally set from 250 kHz to 700 kHz
Terminate to quiet ground
with 10-kΩ resistor
R = 215 kΩ to 69 kΩ
Synchronization signal
Set RT resistor equal to 90% to 110% of external
synchronization frequency. When using a dual setup (see
Figure 27 for example), if the master 35x device RT pin is
left floating, use a 110-kΩ resistor to tie the slave RT pin
to ground. Conversely, if the master 35x device RT pin is
grounded, use a 237-kΩ resistor to tie the slave RT pin to
ground.
Externally synchronized frequency
180° Out-of-Phase Synchronization (SYNC)
The SYNC pin is configurable as an input or as an output, as noted in the previous section. When operating as
an input, SYNC is a falling-edge-triggered signal (see Figure 3, Figure 4, and Figure 19). When operating as an
output, the signal's falling edge is approximately 180° out of phase with the rising edge of the PH pins. Thus, two
TPS5435x devices operating in a system can share an input capacitor and draw ripple current at twice the
frequency of a single unit.
When operating the two TPS5435x devices 180° out of phase, the total RMS input current is reduced, thus,
reducing the amount of input capacitance needed and increasing efficiency.
When synchronizing a TPS5435x to an external signal, the timing resistor on the RT pin must be set so that the
oscillator is programmed to run at 90% to 110% of the synchronization frequency.
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VI(SYNC)
VO(PH)
Figure 3. SYNC Input Waveform
Internal Oscillator
VO(PH)
VO(SYNC)
Figure 4. SYNC Output Waveform
Power Good (PWRGD)
The VSENSE pin is compared to an internal reference signal if the VSENSE is greater than 97% and no other
faults are present. The PWRGD pin presents a high impedance. A low on PWRGD indicates a fault. PWRGD
has been designed to provide a weak pulldown and indicates a fault even when the device is unpowered. If the
TPS5435x has power and has any fault flag set, the TPS5435x indicates the power is not good by driving the
PWRGD pin low. The following events, singly or in combination, indicate power is not good:
• VSENSE pin out of bounds
• Overcurrent
• Thermal shutdown
• UVLO undervoltage
• Input voltage not present (weak pulldown)
• Slow starting
• VBIAS voltage is low.
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Once the PWRGD pin presents a high impedance (i.e., power is good), a VSENSE pin out-of-bounds condition
forces PWRGD low (i.e., power is bad) after a time delay. This time delay is a function of the switching frequency
and is calculated using equation 6:
T
+ 1000 ms
delay
ƒs (kHz)
(6)
Bias Voltage (VBIAS)
The VBIAS regulator provides a stable supply for the internal analog circuits and the low-side gate driver. Up to 1
mA of current can be drawn for use in an external application circuit. The VBIAS pin must have a bypass
capacitor value of 1 µF. X7R- or X5R-grade dielectric ceramic capacitors are recommended because of their
stable characteristics over temperature.
Bootstrap Voltage (BOOT)
The BOOT capacitor obtains its charge cycle by cycle from the VBIAS capacitor. A capacitor from the BOOT pin
to the PH pins is required for operation. The bootstrap connection for the high-side driver must have a bypass
capacitor of 0.1 µF.
Error Amplifier
The VSENSE pin is the error amplifier inverting input. The error amplifier is a true voltage amplifier, with 1.5 mA
of drive capability with a minimum of 60 dB of open-loop voltage gain and a unity-gain bandwidth of 2 MHz.
Voltage Reference
The voltage-reference system produces a precision reference signal by scaling the output of a
temperature-stable bandgap circuit. During production testing, the bandgap and scaling circuits are trimmed to
produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim
procedure improves the regulation, since it cancels offset errors in the scaling and error-amplifier circuits.
PWM Control and Feed Forward
Signals from the error-amplifier output, oscillator, and current-limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control logic includes the PWM comparator, PWM latch, and
the adaptive dead-time control logic. During steady-state operation below the current-limit threshold, the PWM
comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is reset, the low-side driver and integrated pulldown MOSFET remain on for a minimum
duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to the valley
voltage. When the ramp begins to charge back up, the low-side driver turns off and the high-side FET turns on.
The peak PWM ramp voltage varies inversely with input voltage to maintain a constant modulator and
power-stage gain of 8 V.
As the PWM ramp voltage exceeds the error-amplifier output voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side FET. The low-side driver remains on until the next
oscillator pulse discharges the PWM ramp.
During transient conditions, the error-amplifier output can be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the internal low-side FET and
driver on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set point,
setting VSENSE to approximately the same voltage as the internal voltage reference. If the error-amplifier output
is low, the PWM latch is reset continually and the high-side FET does not turn on. The internal low-side FET and
low-side driver remain on until the VSENSE voltage decreases to a range that allows the PWM comparator to
change states. The TPS5435x is capable of sinking current through the external low-side FET until the output
voltage reaches the regulation set point.
The minimum on time is designed to be 180 ns. During the internal slow-start interval, the internal reference
ramps from 0 V to 0.891 V. During the initial slow-start interval, the internal reference voltage is very small,
resulting in skipped pulses because the minimum on time causes the actual output voltage to be slightly greater
than the preset output voltage, until the internal reference ramps up.
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Deadtime Control
Adaptive dead-time control prevents shoot-through current from flowing in the integrated high-side MOSFET and
the external low-side MOSFET during the switching transitions by actively controlling the turn-on times of the
drivers. The high-side driver does not turn on until the voltage at the gate of the low-side MOSFET is below 1 V.
The low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 1 V.
Low-Side Gate Driver (LSG)
LSG is the output of the low-side gate driver. The 100-mA MOSFET driver is capable of providing gate drive for
most popular MOSFETs suitable for this application. Use the SWIFT Designer Software Tool to find the most
appropriate MOSFET for the application. Connect the LSG pin directly to the gate of the low-side MOSFET. Do
not use a gate resistor, as the resulting turn-on time may be too slow.
Integrated Pulldown MOSFET
The TPS5435x has a diode-MOSFET pair from PH to PGND. The integrated MOSFET is designed for light-load
continuous-conduction-mode operation when only an external Schottky diode is used. The combination of
devices keeps the inductor current continuous under conditions where the load current drops below the inductor's
critical current. Care should be taken in the selection of inductor in applications using only a low-side Schottky
diode. Since the inductor ripple current flows through the integrated low-side MOSFET at light loads, the
inductance value should be selected to limit the peak current to less than 0.3 A during the high-side FET turn-off
time. The minimum value of inductance is calculated using the following equation:
ǒ1 * VO
Ǔ
VI
VO
L(H) +
ƒs
0.6
(7)
Thermal Shutdown
The device uses the thermal shutdown to turn off the MOSFET drivers and controller if the junction temperature
exceeds 165°C. The device is restarted automatically when the junction temperature decreases to 7°C below the
thermal shutdown trip point and starts up under control of the slow-start circuit.
Overcurrent Protection
Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET and
compared to a voltage level that represents the overcurrent threshold limit. If the drain-to-source voltage exceeds
the overcurrent threshold limit for more than 100 ns, the ENA pin is pulled low, the high-side MOSFET is
disabled, and the internal digital slow-start is reset to 0 V. ENA is held low for approximately the time that is
calculated by the following equation:
T
(ms) + 2250
HICCUP
ƒs (kHz)
(8)
Once the hiccup time is complete, ENA is released and the converter initiates the internal slow start.
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TYPICAL CHARACTERISTICS
Conditions are VI = 12 V, VO = 3.3 V, fs = 500 kHz, IO = 3 A, TA = 25°C (unless otherwise noted).
Gain
0
0
−10
−30
−20
−60
−30
−90
−120
See Figure 25
−50
−60
100
1k
10 k
−150
−180
1M
100 k
VI = 12 V
0.1
VI = 6 V
0
−0.2
See Figure 25
0
0.5
1
0
−0.02
IO = 0 A
−0.04
−0.06
1.5
2
2.5
3
3.5
−0.1
4
See Figure 25
6
10
8
12
14
16
18
20
22
VI − Input Voltage − V
Figure 6.
INPUT RIPPLE VOLTAGE
Figure 7.
OUTPUT RIPPLE VOLTAGE
VI(RIPPLE) = 100 mV/div (ac coupled)
VO(RIPPLE) = 10 mV/div (ac coupled)
VI = 6 V
95
IO = 1.5 A
0.02
IO − Output Current − A
Figure 1
Figure 5.
EFFICIENCY
vs
OUTPUT CURRENT
IO = 3 A
0.04
−0.08
−0.3
f − Frequency − Hz
100
VI = 18 V
−0.1
0.06
VI = 12 V
Amplitude
90
85
80
V(PH) = 5 V/div
Amplitude
−40
0.2
Output Voltage Change − %
30
Output Voltage Change − %
60
Phase − Degrees
90
20
10
0.08
120
Phase
30
Efficiency − %
0.1
150
40
G − Gain − dB
0.3
180
50
LINE REGULATION
LOAD REGULATION
MEASURED LOOP RESPONSE
60
V(PH) = 5 V/div
VI = 18 V
75
70
65
See Figure 25
60
See Figure 25
50
0
1
See Figure 25
Time − 1 µs/div
55
2
3
Time − 1 µs/div
4
IO − Output Current − A
Figure 8.
GATE DRIVE VOLTAGE
See Figure 25
Figure 11.
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VI = 5 V/div
VO= 2 V/div
V(PWRGD)= 2 V/div
See Figure 25
See Figure 25
Time − 1 µs/div
14
I(PH) = 1 A/div
Power Up Response − mV
V(PH) = 5 V/div
Figure 10.
POWER UP
VO = 50 mV/div (ac coupled)
Load Transient Response − mV
Amplitude
V(LSG) = 5 V/div
Figure 9.
LOAD TRANSIENT RESPONSE
Time − 200 µs/div
Figure 12.
Time − 2 ms/div
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
Conditions are VI = 12 V, VO = 3.3 V, fs = 500 kHz, IO = 3 A, TA = 25°C (unless otherwise noted).
EFFICIENCY
vs
OUTPUT CURRENT
100
VI = 5 V/div
CONTINUOUS CONDUCTION MODE
V(PH) = 5 V/div
Continuous Conduction Mode
Power Down Waveforms − V
POWER DOWN
VI = 6 V
95
VI = 12 V
90
85
Efficiency − %
VO= 2 V/div
V(PWRGD)= 2 V/div
VI = 18 V
80
75
70
I(L1) = 200 mA/div
65
See Figure 25
See Figure 26
60
Time − 1 µs/div
55
Time − 2 ms/div
See Figure 26
50
0
1
2
3
4
IO − Output Current − A
Figure 14.
LIGHT LOAD CONDUCTION
Figure 15.
SEQUENCING WAVEFORMS
Figure 16.
INPUT RIPPLE CANCELLATION
V(PH1) = 10 V/div
VO1(3.3)= 2 V/div
V(PWRGD1)= 2 V/div
V(PH2) = 10 V/div
VI = 50 mV/div (ac coupled)
VO2 (1.8)= 2 V/div
See Figure 26
Time − 1 µs/div
50
40
120
40
120
30
90
30
90
20
60
90
20
60
10
0
Gain
30
0
0
−60
−90
−30
−90
−120
−40
−120
−40
−150
−50
−60
−150
−180
1M
−50
−40
100 k
30
0
−30
−30
10 k
0
60
Gain
10
−30
−60
1k
0
20
−20
−20
−60
100
30
150
−60
−30
See Figure 28
Gain
10
180
Phase
−10
−10
−50
G − Gain − dB
30
Phase − Degrees
120
Phase
G − Gain − dB
60
150
50
Phase
Figure 19.
MEASURED LOOP RESPONSE
330-mF OSCON
180
60
150
40
G − Gain − dB
Figure 18.
MEASURED LOOP RESPONSE
2 y 180-mF SP CAPACITORS
180
50
Time − 1 µs/div
Time − 2 ms/div
Figure 17.
MEASURED LOOP RESPONSE
100-mF POSCAP
Phase − Degrees
60
See Figure 27
See Figure 27
−10
−30
−20
−90
−180
1M
f − Frequency − Hz
Figure 20.
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See Figure 29
100
1k
10 k
100 k
f − Frequency − Hz
Figure 21.
Phase − Degrees
I(L1) = 200 mA/div
Input Ripple Cancellation − V
VI = 10 V/div
Sequencing Waveforms − V
Light Load Conduction
V(PH) = 5 V/div
−120
See Figure 30
−60
100
1k
−150
10 k
100 k
−180
1M
f − Frequency − Hz
Figure 22.
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LAYOUT INFORMATION
Figure 23. TPS5435x PCB Layout
PCB Layout
The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low-ESR
ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS5435x ground pins. The minimum recommended bypass capacitance is
10-µF ceramic with a X5R or X7R dielectric, and the optimum placement is closest to the VIN pins and the
AGND and PGND pins. See Figure 23 for an example of a board layout. The AGND and PGND pins should be
tied to the PCB ground plane at the pins of the IC. The source of the low-side MOSFET and the anode of the
Schottky diode should be connected directly to the PCB ground plane. The PH pins should be tied together and
routed to the drain of the low-side MOSFET or to the cathode of the external Schottky diode. Since the PH
connection is the switching node, the MOSFET (or diode) should be located very close to the PH pins, and the
area of the PCB conductor minimized to prevent excessive capacitive coupling. The recommended conductor
width from pins 14 and 15 is 0.050 in to 0.075 in of 1-oz copper. The length of the copper land pattern should be
no more than 0.2 in.
For operation at full-rated load, the analog ground plane must provide adequate heat dissipating area. A 3-in ×
3-in plane of copper is recommended, though not mandatory, dependent on ambient temperature and airflow.
Most applications have larger areas of internal ground plane available, and the PowerPAD package should be
connected to the largest area available. Additional areas on the bottom or top layers also help dissipate heat,
and any area available should be used when 3 A or greater operation is desired. Connection from the exposed
area of the PowerPAD package to the analog ground-plane layer should be made using 0.013-in diameter vias to
avoid solder wicking through the vias. Four vias should be in the PowerPAD area, with four additional vias
outside the pad area and underneath the package. Additional vias beyond those recommended to enhance
thermal performance should be included in areas not under the device package.
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0.0130
8 PL
Minimum recommended exposed copper
area for PowerPAD package . 5-mil
stencils may require 10-% larger area.
Minimum recommended thermal vias:
4 0.013 diameter inside PowerPAD area and
4 0.013 diameter under device as shown.
Additional 0.018 diameter vias may be used if
top-side analog ground area is extended.
0.0150
0.06
0.0371
0.0400
0.1970
0.1942
0.0570
0.0400
0.0400
0.0256
Minimum recommended
top-side analog ground area.
0.1700
0.1340
0.0690
0.0400
Connect pin 10 AGND
and pin 11 PGND to
analog ground plane in
this area for optimum
performance.
Figure 24. Thermal Considerations for PowerPAD™ Layout
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APPLICATION INFORMATION
Figure 25 shows the schematic for a typical TPS54356 application. The TPS54356 can provide up to 3-A output
current at a nominal output voltage of 3.3 V. For proper thermal performance, the exposed PowerPAD package
underneath the device must be soldered down to the printed circuit board.
+
+
Figure 25. Application Circuit, 12 V to 3.3 V
Design Procedure
The following design procedure can be used to select component values for the TPS54356. Alternately, the
SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency
For this design example, use the following as the input parameters:
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
6 V to 18 V
Output voltage
3.3 V
Input ripple voltage
300 mV
Output ripple voltage
10 mV
Output current rating
3A
Operating frequency
500 kHz
Switching Frequency
The switching frequency is set using the RT pin. Grounding RT sets the PWM switching frequency to a default
frequency of 250 kHz. Floating RT sets the PWM switching frequency to 500 kHz. By connecting a resistor from
RT to AGND, any frequency in the range of 250 kHz to 700 kHz can be set. Use equation 9 to determine the
proper value of RT.
46000
RT (kW) +
ƒ s (kHz) * 35.9
(9)
In this example circuit, RT is not connected and the switching frequency is set at 500 kHz.
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Input Capacitors
The TPS54356 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The minimum value for the decoupling capacitor, C9, is 10 µF. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. Additionally, some bulk
capacitance may be needed, especially if the TPS54356 circuit is not located within about 2 in from the input
voltage source. The value for this capacitor is not critical, but it also should be rated to handle the maximum
input voltage including ripple voltage and should filter the output so that input ripple voltage is acceptable.
This input ripple voltage can be approximated by equation 10:
I OUT(MAX) 0.25
DV IN +
) (I OUT(MAX) ESR (MAX))
CBULK ƒ sw
(10)
Where:
IOUT(MAX) = Maximum load current
ƒSW= Switching frequency
CBULK = Bulk capacitor value
and ESRMAX = Maximum series resistance of the bulk capacitor
The maximum RMS ripple current also needs to be checked. For worst-case conditions, this can be
approximated by equation 11:
I
OUT(MAX)
I
+
CIN
2
(11)
In this case, the input ripple voltage is 140 mV and the RMS ripple current is 1.5 A. The maximum voltage across
the input capacitors is VIN max plus delta VIN/2. The chosen bulk and bypass capacitors are each rated for 25 V
and the combined ripple current capacity is greater than 3 A, both providing ample margin. It is very important
that the maximum ratings for voltage and current are not exceeded under any circumstance.
Output Filter Components
Inductor Selection
To calculate the minimum value of the output inductor, use equation 12:
V
L
(MIN)
+
V
OUT
IN(MAX)
ǒVIN(MAX) * VOUTǓ
K
I
IND
OUT
ƒ sw
(12)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
For designs using low ESR output capacitors such as ceramics, use KIND = 0.3. When using higher ESR output
capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.1 to keep the inductor ripple current small. The minimum inductor value is
calculated to be 17.96 µH. The next-highest standard value is 22 µH, which is used in this design.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be derived from equation 13:
I L(RMS) +
Ǹ
I 2OUT(MAX) ) 1
12
ǒ
V OUT
V IN(MAX)
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ǒV IN(MAX) * V OUTǓ
L OUT
ƒ sw
Ǔ
2
0.8
(13)
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and the peak inductor current can be determined using equation 14:
I L(PK) + I OUT(MAX) )
ǒVIN(MAX) * VOUTǓ
V OUT
1.6
V IN(MAX)
L OUT
ƒ sw
(14)
For this design, the RMS inductor current is 3.007 A and the peak inductor current is 3.15 A. The chosen
inductor is a Coiltronics DR127-220 22 µH. It has a saturation current rating of 7.57 A and a RMS current rating
of 4 A, easily meeting these requirements. A lesser-rated inductor could be used if less margin is desired. In
general, inductor values for use with the TPS54356 are in the range of 6.8 µH to 47 µH.
Capacitor Requirements
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because, along with the inductor current, it determines the amount of output ripple voltage. The actual value of
the output capacitor is not critical, but some practical limits do exist.
Consider the relationship between the desired closed-loop crossover frequency of the design and LC corner
frequency of the output filter. In general, it is desirable to keep the closed-loop crossover frequency at less than
one-fifth of the switching frequency. With high switching frequencies such as the 500-kHz frequency of this
design, internal circuit limitations of the TPS54356 limit the practical maximum crossover frequency to about 70
kHz. Additionally, the capacitor type and value must be chosen to work with the internal compensation network of
the TPS5435x family of dc/dc converters. To allow for adequate phase gain in the compensation network, the LC
corner frequency should be approximately one decade or so below the closed-loop crossover frequency. This
limits the minimum capacitor value for the output filter to:
C
OUT(MIN)
+
1
LOUT
(2pƒK )
2
CO
(15)
Where K is the frequency multiplier for the spread between fLC and fCO. K should be between 5 and 15, typically
10, for one decade difference. For a desired crossover of 20 kHz and a 22-µH inductor, the minimum value for
the output capacitor is 288 µF. The selected output capacitor must be rated for a voltage greater than the desired
output voltage, plus one-half the ripple voltage. Any derating amount also must be included. The maximum RMS
ripple current in the output capacitor is given by equation 16:
I COUT(RMS) + 1
Ǹ12
ȡVOUT ǒVIN(MAX) * VOUTǓȣ
ȧ VIN(MAX) LOUT ƒsw ȧ
Ȣ
Ȥ
(16)
The calculated RMS ripple current is 156 mA in the output capacitors.
Choosing Capacitor Value
For this design example, a relatively large aluminum electrolytic capacitor is combined with a smaller-value
ceramic capacitor. This combination provides a stable high-performance design at a relatively low cost. Also, by
carefully choosing the capacitor values and ESRs, the design can be tailored to complement the internal
compensation poles and zeros of the TPS54356.
These preconfigured poles and zeroes, internal to the TPS54356, limit the range of output filter configurations. A
variety of capacitor values and types of dielectric are supported. There are a number of different ways to
calculate the output filter capacitor value and ESR to work with the internal compensation network. This
procedure outlines a relatively simple procedure that produces good results with an output filter consisting of a
high-ESR dielectric capacitor in parallel with a low-ESR ceramic capacitor. SWIFT Designer Software is used for
designs with unusually high closed-loop crossover frequencies, low value, low-ESR output capacitors such as
ceramics, or if the designer is unsure about the design procedure.
20
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The TPS54356 contains a compensation network with the following nominal characteristics:
ƒINT = 1.7 kHz
ƒZ1 = 2.5 kHz
ƒZ2 = 4.8 kHz
ƒP1 = 95 kHz
ƒP2 = 125 kHz
For a stable design, the closed-loop crossover frequency should be set less than one-fifth of the switching
frequency, and the phase margin at crossover must be greater than 45 degrees. The general procedure outlined
here produces results consistent with these requirements, without going into great detail about the theory of loop
compensation.
In this case, the output filter LC corner frequency should be selected to be near the first compensation zero
frequency, as described by equation 17:
1
ƒ
+
^ƒ
LC
Z1
2p L
C2
OUT
(17)
Ǹ
Placement of the LC corner frequency at fZ1 is not critical; it only needs to be close. For the design example,
fLC = 2 kHz.
Solving for C2 using equation 18:
C2 ^ 2 2 1
4p ƒ
L
Z1 OUT
(18)
The desired value for C2 is calculated as 184 µF. A close standard value of 330 µF is chosen, with a resulting
LC corner frequency of 1.9 kHz. As shown, this value is not critical as long as it results in a corner frequency in
the vicinity of fZ1.
Next, when using a large ceramic capacitor in parallel with a high-ESR electrolytic capacitor, there is a pole in
the output filter that should be at fZ2, as shown in equation 19:
1
ƒ
+
+ƒ
P(ESR)
Z2
2pR
C5
(C2ESR)
(19)
Now, the actual C2 capacitor must be selected based on the ESR and the value of capacitor C5, so that the
above equation is satisfied. In this example, the R(C2ESR)C5 product should be 3.18 × 10–5. From the available
capacitors, by choosing a Panasonic EEVFKOJ331XP aluminum electrolytic capacitor with a nominal ESR of
0.34 Ω yields a calculated value for C5 of 98 µF. The closest standard value is 100 µF. As the actual ESR of the
capacitor can vary by a large amount, this value also is not critical.
The closed-loop crossover frequency should be greater than fLC and less than one-fifth of the switching
frequency. Also, the crossover frequency should not exceed 70 kHz, as the error amplifier may not provide the
desired gain. As stated previously, closed loop-crossover frequencies between 5 and 15 times fLC work well. For
this design, the crossover frequency can be estimated by:
ƒ
+ 1.125 10 *3 ƒ
ƒ
CO
P(ESR)
LC
(20)
This simplified equation is valid for this design because the output filter capacitors are mixed technology.
Compare this result to the actual measured loop response plot of Figure 5. The measured closed-loop crossover
frequency of 19.95 kHz differs from the calculated value because the actual output filter capacitor component
parameters differed slightly from the specified data-sheet values.
Capacitor ESR and Output Ripple
The amount of output ripple voltage, as specified in the initial design parameters, is determined by the maximum
ESR of the output capacitor and the input ripple current. The output ripple voltage is the inductor ripple current
times the ESR of the output filter, so the maximum specified ESR as listed in the capacitor data sheet is given by
equation 21:
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ESR (MAX) +
ǒ
VIN(MAX)
LOUT
V OUT
ǒV IN(MAX)
ƒsw
Ǔ
0.8
* VOUTǓ
DV p*p(MAX)
(21)
and the maximum ESR required is 33 mΩ. In this design, the aluminum electrolytic capacitor has an ESR of
0.340 mΩ, but it is in parallel with an ultra-low ESR ceramic capacitor of 2 mΩ maximum. The measured output
ripple voltage for this design is approximately 4 mVp-p, as shown in Figure 10.
Bias AND Bootstrap Capacitors
Every TPS54356 design requires a bootstrap capacitor, C3, and a bias capacitor, C4. The bootstrap capacitor
must be 0.1 µF. The bootstrap capacitor is located between the PH pins and BOOT pin. The bias capacitor is
connected between the VBIAS pin and AGND. The value should be 1 µF. Both capacitors should be high-quality
ceramic types with X7R or X5R grade dielectric for temperature stability. They should be placed as close to the
device connection pins as possible.
Low-Side FET
The TPS54356 is designed to operate using an external low-side FET, and the LSG pin provides the gate drive
output. Connect the drain to the PH pin, the source to PGND, and the gate to LSG. The TPS54356 gate drive
circuitry is designed to accommodate most common n-channel FETs that are suitable for this application. The
SWIFT Designer Software can be used to calculate all the design parameters for low-side FET selection. There
are some simplified guidelines that can be applied that produce an acceptable solution in most designs.
The selected FET must meet the absolute maximum ratings for the application:
• Drain-source voltage (VDSS) must be higher than the maximum voltage at the PH pin, which is
VINMAX + 0.5 V.
• Gate-source voltage (VGSS) must be greater than 8 V.
• Drain current (ld) must be greater than 1.1 × IOUTMAX.
• Drain-source on resistance (RDSON) should be as small as possible; less than 30 mΩ is desirable. Lower
values for RDSON result in designs with higher efficiencies. It is important to note that the low-side FET on
time typically is longer than the high-side FET on time, so attention paid to low-side FET parameters can
make a marked improvement in overall efficiency.
• Total gate charge (Qg) must be less than 50 nC. Again, lower Qg characteristics result in higher efficiencies.
• Additionally, check that the device chosen is capable of dissipating the power losses.
For this design, a Fairchild FDR6674A 30-V n-channel MOSFET is used as the low-side FET. This particular FET
is designed specifically to be used as a low-side synchronous rectifier.
Power Good
The TPS54356 is provided with a power-good (PWRGD) output pin. This output is an open-drain output and is
intended to be pulled up to a 3.3-V or 5-V logic supply. A 10-kΩ pullup resistor works well in this application. The
absolute maximum voltage is 6 V, so care must be taken not to connect this pullup resistor to VIN if the
maximum input voltage exceeds 6 V.
Snubber Circuit
R10 and C11 of the application schematic in Figure 25 comprise a snubber circuit. The snubber is included to
reduce overshoot and ringing on the phase node when the internal high-side FET turns on. Since the frequency
and amplitude of the ringing depends to a large degree on parasitic effects, it is best to choose these component
values, based on actual measurements of any design layout. See literature number SLUP100 for more detailed
information on snubber design.
Figure 26 shows an application where a clamp diode is used in place of the low-side FET. The TPS54352-7
incorporates an integrated pulldown FET so that the circuit remains operating in continuous mode during light
load operation. A 3-A 40-V Schottky diode, such as the Motorola MBRS340T3 or equivalent, is recommended.
See Figure 15, Figure 16, and Figure 17 for efficiency data and switching waveforms for this circuit.
22
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+
+
Figure 26. Power Supply With Schottky Diode
Figure 27 is an example of power-supply sequencing using a TPS54356 (U1) to generate an output of 3.3 V, and
a TPS54354 (U2) to generate a 1.8-V output. These output voltages are typical I/O and core voltages for
microprocessors and FPGAs. In the circuit, the 3.3-V supply is designed to power up first.
+
+
Pull up to
3.3 V or 5 V
+
+
Figure 27. Power Supply With Sequencing
The PWRGD pin of U1 is tied to the ENA pin of U2 so that the 1.8-V supply starts to ramp up after the 3.3-V
supply is within regulation. Figure 18 shows these start-up sequence waveforms.
Since the RT pin of U1 is floating, the SYNC pin is an output. This synchronization signal is fed the SYNC pin of
U2. RT of U2 has a 110-kΩ resistor to ground, and SYNC for this device acts as an input. The 1.8-V supply
operates synchronously with the 3.3-V supply, and their switching node rising edges are approximately 180
degrees out of phase, allowing for a reduction in the input voltage ripple. See Figure 19 for this waveform.
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TPS54355-EP, TPS54356-EP, TPS54357-EP
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Alternate Output Filter Designs
The previous design procedure example demonstrated a technique to design a 3.3-V power supply using both
aluminum electrolytic and ceramic output filter capacitors. Other types of output filter capacitors are supported by
the TPS5435x family of dc/dc converters. Figure 26, Figure 27, and Figure 28 show designs using other popular
capacitor types.
In Figure 28, the TPS54356 is shown with a single 100-µF 6-V POSCAP as the output filter capacitor. C10 is a
high-frequency bypass capacitor and does not enter into the design equations. The design procedure is similar to
the previous example, except in the design of the output filter. In the previous example, the output filter LC corner
was set at the first zero in the compensation network, while the second compensation zero was used to
counteract the output filter pole caused by the interaction of the C2 capacitor ESR with C5. In this design
example, the output LC corner frequency is to be set at the second zero frequency (fZ2) of the internal
compensation network, approximately 5 kHz, while the first zero is used to provide phase boost prior to the LC
corner frequency.
+
+
Figure 28. 3.3-V Power Supply With Sanyo POSCAP Output Filter Capacitor
Inductor Selection
Using equation 12 and a KIND 0.2, the minimum inductor value required is 8.98 µH. The closest standard value,
10 µH, is selected. RMS and peak inductor currents are the same as calculated previously.
Capacitor Selection
With the inductor set at 10 µH and a desired corner frequency of 5 kHz, the output capacitor value is given by:
1
1
C2 +
+
+ 101 mF
4
p 2 5000 2 10 *5
4p 2ƒ Z2 2 Lout
Use 100 µF as the closest standard value.
Calculating the RMS ripple current in the output capacitor using equation 16 yields 156 mA. The POSCAP
6TPC100M capacitor selected is rated for 1700 mA. See the closed-loop response curve for this design in
Figure 20.
+
+
+
Figure 29. 3.3-V Power Supply With Panasonic SP Output Filter Capacitors
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In Figure 29, the TPS54356 is shown with two 180-mF 4-V special polymer dielectric output filter capacitors (C2
and C5). C10 is a high-frequency bypass capacitor and does not enter into the design equations. In the previous
example, the output LC corner frequency is to be set at the second zero frequency fZ2 of the internal
compensation network, approximately 5 kHz, while the first zero is used to provide phase boost prior to the LC
corner frequency. The special polymer electrolytic capacitors used in this design require that the closed-loop
crossover frequency be lowered due to the significantly lower ESR of this type of capacitor.
Inductor Selection
The inductor is the same 10-µH value as the previous example.
Capacitor Selection
To lower the closed-loop crossover, it is necessary to reduce the LC corner frequency below 5 kHz. Using a
target value of 2500 Hz, the output capacitor value is given by:
1
1
C2 +
+
+ 405 mF
4
p 2 2500 2 10 *5
4p 2ƒ Z2 2 Lout
Use 2 × 180 µF = 360 µF as a combination of standard values that is close to 405 µF.
The RMS ripple current in the output capacitor is the same as before. The selected capacitors are each 3.3 A.
See the closed-loop response curve for this design in Figure 21.
In Figure 30, the TPS54356 is shown with a Sanyo OSCON output filter capacitor (C2). C10 is a high-frequency
bypass capacitor and does not enter into the design equations. This design is identical to the previous example,
except that a single OSCON capacitor of 330 µF is used for the calculated value of 405 µF. Compare the
closed-loop response for this design in Figure 22 to the closed-loop response in Figure 21. Note that there is only
a slight difference in the response and the general similarity in both the gain and phase plots. This is the
expected result for these two similar output filters.
+
+
Figure 30. 3.3-V Power Supply With Sanyo OSCON Output Filter Capacitor
Many other additional output filter designs are possible. Use the SWIFT Designer Software to generate other
designs or follow the general design procedures illustrated in this application section.
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MAXIMUM SWITCHING FREQUENCY
vs
INPUT VOLTAGE
RT RESISTANCE
vs
SWITCHING FREQUENCY
TPS54357
TPS54356
6.0
TPS54355
400
TPS54354
300
TPS54353
TPS54352
200
VI − Input Voltage − V
500
175
150
125
100
100
IO > 0.5 A
Stop
5.0
4.5
TPS54352−6
Start
75
4.0
50
200
3.5
−50 −25
300
400
500
600
700
Switching Frequency − kHz
0
25
50
75
100 125 150
TA − Free-Air Temperature − 5C
Figure 31.
Figure 32.
Figure 33.
ENABLED SUPPLY CURRENT
vs
INPUT VOLTAGE
DISABLED SUPPLY CURRENT
vs
INPUT VOLTAGE
BIAS VOLTAGE
vs
INPUT VOLTAGE
1.3
TJ = 25°C
fS = 500 kHz
8.0
TJ = 25°C
TJ = 25°C
8
7
6
5
4
7.5
VBIAS − Bias Voltage − V
Disabled Supply Current − mA
9
TPS54357
5.5
Stop
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
10
1.2
1.1
1.0
7.0
6.5
6.0
5.5
5.0
4.5
3
0.9
0
5
10
15
20
4.0
25
0
5
10
15
20
0
25
5
10
15
VI − Input Voltage − V
VI − Input Voltage − V
VI − Input Voltage − V
Figure 34.
Figure 35.
Figure 36.
POWER-GOOD THRESHOLD
vs
JUNCTION TEMPERATURE
INTERNAL VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
CURRENT LIMIT
vs
INPUT VOLTAGE
98.0
Vref − Internal Voltage Reference − V
97.5
97.0
96.5
96.0
−50 −25
0
25
50
75
100 125 150
TJ − Junction Temperature − 5C
Figure 37.
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20
25
6.0
0.8912
TJ = 25°C
VIN = 12 V
0.8910
5.5
0.8908
Current Limit − A
Enabled Supply Current − mA
200
Start
VI − Input Voltage − V
PWRGD − Power Good Threshold − %
6.5
600
0
26
225
700
RT Resistance − kW
Maximum Switching Frequency − kHz
800
VIN(UVLO) START AND STOP
vs
FREE-AIR TEMPERATURE
0.8906
0.8904
0.8902
5.0
4.5
0.8900
0.8898
−50 −25
4.0
0
25
50
75
100 125 150
TJ − Junction Temperature − 5C
Figure 38.
5.0
7.5
10.0
12.5
15.0
17.5
20.0
VI − Input Voltage − V
Figure 39.
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PH VOLTAGE
vs
SINK CURRENT
ON RESISTANCE
vs
JUNCTION TEMPERATURE
SLOW-START CAPACITANCE
vs
TIME
2
0.50
150
VI = 12 V
IO = 0.5 A
1.75
PH Voltage − V
On Resistance − mW
130
Slow Start Capacitance − µ F
0.45
110
90
VI = 4.5 V
1.50
VI = 12 V
1.25
70
RSS = 2 kΩ
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
50
−50 −25
0
1
0
25
50
75
100
100 125 150
150
200
250
0
300
10
20
TJ − Junction Temperature − 5C
Figure 40.
Figure 41.
4.5
40
50
60
70
80
Figure 42.
HICCUP TIME
vs
SWITCHING FREQUENCY
POWER-GOOD DELAY
vs
SWITCHING FREQUENCY
30
t − Time − ms
I CC − Sink Current − mA
INTERNAL SLOW START TIME
vs
SWITCHING FREQUENCY
10
5
9
4.5
8
4
Hiccup Time − ms
3
2.5
2
1.5
7
6
5
4
1
3
2.5
2
3
0.5
250
350
450
550
650
1.5
2
250
0
750
Switching Frequency − kHz
350
450
550
650
1
250
750
350
Figure 44.
FREE-AIR TEMPERATURE
vs
MAXIMUM OUTPUT CURRENT
V O − Output Voltage − V
5
80
60
40
4
TPS54356
3
TPS54355
TPS54354
2
1
20
750
2.5
TPS54357
100
650
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
6
TJ= 125°C
120
550
Figure 45.
MAXIMUM OUTPUT VOLTAGE
vs
INPUT VOLTAGE
140
450
Switching Frequency − kHz
Switching Frequency − kHz
Figure 43.
T A − Free-Air Temperature − ° C
3.5
PD − Power Dissipation − W
Power Good Delay − ms
3.5
Slow Start Time − ms
TPS54354
4
2
θJA = 42.1°C/W
1.5
1
θJA = 191.9°C/W
0.5
TPS54352
TPS54353
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0
5
10
15
I O − Output Current − A
V I − Input Voltage − V
Figure 46.
Figure 47.
Copyright © 2007–2009, Texas Instruments Incorporated
20
25
25
45
65
85
105
125
TA − Free-Air Temperature − °C
Figure 48.
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TPS54355-EP, TPS54356-EP, TPS54357-EP
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THERMAL PAD MECHANICAL DATA
PWP (R-PDSO-G16) ............................................................................ PowerPAD™ PLASTIC SMALL-OUTLINE
PPTD024
28
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54354MPWPREP
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
PMDM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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