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TPS54361-Q1
SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
TPS54361-Q1 4.5-V to 60-V Input, 3.5-A, Step Down DC-DC Converter with Soft-Start
and Eco-mode™
1 Features
3 Description
•
•
The TPS54361-Q1 device is a 60-V, 3.5-A, step
down regulator with an integrated high side MOSFET.
The device survives load dump pulses up to 65 V per
ISO 7637. Current mode control provides simple
external compensation and flexible component
selection. A low ripple pulse skip mode and supply
current of 152-µA enables high efficiency at light
loads. Shutdown supply current is reduced to 2 μA
when the enable pin is pulled low.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H1C
– Device CDM ESD Classification Level C3B
High Efficiency at Light Loads with Pulse Skipping
Eco-mode™
87-mΩ High-Side MOSFET
152-μA Operating Quiescent Current and
2-μA Shutdown Current
100-kHz to 2.5-MHz Adjustable Switching
Frequency
Synchronizes to External Clock
Low Dropout at Light Loads with Integrated BOOT
Recharge FET
Adjustable UVLO Voltage and Hysteresis
UV and OV Power Good Output
Adjustable Soft-Start and Sequencing
0.8-V 1% Internal Voltage Reference
10-Pin WSON with Thermal Pad Package
–40°C to 150°C TJ Operating Range
Create a Custom Design using the TPS54361-Q1
with the WEBENCH® Power Designer
•
•
A wide adjustable switching-frequency range allows
for optimization of either efficiency or external
component
size.
Cycle-by-cycle
current-limit,
frequency foldback and thermal shutdown protects
internal and external components during an overload
condition.
The TPS54361-Q1 device is available in a 10-pin
4 mm × 4 mm WSON exposed thermal pad package.
Device Information(1)
DEVICE NAME
TPS54361-Q1
Vehicle Accessories: GPS (see SLVA412),
Entertainment
USB Dedicated Charging Ports and Battery
Chargers (see SLVA464)
12-V, 24-V and 48-V Industrial, Automotive and
Communications Power Systems
Simplified Schematic
VI
PACKAGE
BODY SIZE
WSON (10)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Undervoltage lockout is internally set at 4.3 V but can
increase using an external resistor divider at the
enable pin. The output voltage startup ramp is
controlled by the soft start pin that can also be
configured for sequencing/tracking. An open-drain
power-good signal indicates the output is within 93%
to 106% of the nominal voltage.
Efficiency vs Load Current
PWRGD
VIN
100
95
TPS54361-Q1
SS/TR
90
BOOT
RT/CLK
SW
VO
COMP
Efficiency (%)
EN
85
80
75
70
FB
GND
36 V to 12 V
12 V to 5 V
12 V to 3.3 V
VO = 12 V, gs = 630 kHz
VO = 5 V and 3.3 V, gs = 400 kHz
65
60
0
0.5
1
1.5
2
Output Current (A)
2.5
3
3.5
D029
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54361-Q1
SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 28
8
Application and Implementation ........................ 30
8.1 Application Information............................................ 30
8.2 Typical Application .................................................. 30
9 Power Supply Recommendations...................... 40
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 42
11 Device and Documentation Support ................. 43
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
44
44
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
Changes from Revision A (April 2014) to Revision B
Page
•
Changed package SON To: WSON in the Features and throughout the data sheet............................................................. 1
•
Changed PowerPAD™ To Thermal Pad in the Features and throughout the data sheet ..................................................... 1
•
Added the WEBENCH information in the Features, Detailed Design Procedure, and Device Support sections .................. 1
•
Added SW, 5-ns Transient to the Absolute Maximum Ratings .............................................................................................. 4
•
Moved Storage temperature to the Absolute Maximum Ratings table .................................................................................. 4
•
Changed the Handling Ratings table to the ESD Ratings table ............................................................................................ 4
•
Changed Equation 10 and Equation 11 .............................................................................................................................. 20
•
Changed Equation 30 .......................................................................................................................................................... 31
Changes from Original (April 2014) to Revision A
•
2
Page
Changed device status from Product Preview to Production Data ....................................................................................... 1
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SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
5 Pin Configuration and Functions
10-Pin WSON
DPR Package
(Top View)
BOOT
1
10
PWRGD
VIN
2
9
SW
EN
3
8
GND
SS/TR
4
7
COMP
RT/CLK
5
6
FB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the gate drive is switched off until the capacitor is
refreshed.
COMP
7
O
This pin is the error amplifier output and input to the output switch current (PWM) comparator. Connect
frequency compensation components to this pin.
EN
3
I
This pin is the enable pin, with an internal pullup current source. Pull EN below 1.2 V to disable. Float EN
to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjust
Undervoltage Lockout section.
FB
6
I
This pin is the Inverting input of the transconductance (gm) error amplifier.
GND
8
–
Ground
VIN
2
I
This pin is the input supply voltage with 4.5-V to 60-V operating range.
PWRGD
10
O
The PWRGD pin is an open drain output that asserts low if the output voltage is out of regulation because
of thermal shutdown, dropout, over-voltage, or EN shut down.
RT/CLK
5
I
This pin is the resistor timing and external clock pin. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL
upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal
amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop,
the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
SS/TR
4
I
This pin is the soft-start and tracking pin. An external capacitor connected to this pin sets the output rise
time. Because the voltage on this pin overrides the internal reference, SS/TR can be used for tracking and
sequencing.
SW
9
O
The SW pin is the source of the internal high-side power MOSFET and switching node of the converter.
–
The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
Thermal Pad
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SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
–0.3
65
EN
–0.3
8.4
BOOT
Input voltage
73
FB
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
–0.6
65
–7
65
BOOT-SW
Output voltage
UNIT
V
8
SW
SW, 5-ns Transient
SW, 10-ns Transient
V
–2
65
Operating junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC-Q100-011
VALUE
UNIT
±2000
V
Corner pins (1, 5, 6,
and 10)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
V(VIN)
Supply input voltage
4.5
60
V
VO
Output voltage
0.8
58.8
V
IO
Output current
0
3.5
A
TJ
Junction Temperature
–40
150
°C
4
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SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
6.4 Thermal Information
TPS54361-Q1
THERMAL METRIC (1) (2)
RθJA
Junction-to-ambient thermal resistance (standard board)
35.1
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
12.5
RθJCtop
Junction-to-case(top) thermal resistance
34.1
RθJCbot
Junction-to-case(bottom) thermal resistance
2.2
RθJB
Junction-to-board thermal resistance
12.3
(1)
(2)
UNIT
DPS (10 PINS)
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Power rating at a specific ambient temperature TA must be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See the power dissipation estimate in the Power Dissipation Estimate section of this data sheet
for more information.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
V
4.3
4.48
V
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
4.5
Internal undervoltage lockout threshold Rising
4.1
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
V(EN) = 0 V, 25°C, 4.5 V ≤ V(VIN) ≤ 60 V
2.25
4.5
Operating: nonswitching supply
current
V(FB) = 0.9 V, TA = 25°C
152
200
1.2
1.3
μA
ENABLE AND UVLO (EN PIN)
V(EN)th
Enable threshold voltage
II
Input current
Ihys
Hysteresis current
No voltage hysteresis, rising and falling
1.1
Enable threshold 50 mV
V
–4.6
Enable threshold –50 mV
μA
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
μA
0.792
0.8
0.808
V
87
185
VOLTAGE REFERENCE
Voltage reference
HIGH-SIDE MOSFET
On-resistance
V(VIN) = 12 V, V(BOOT-SW) = 6 V
mΩ
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gm)
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V
Error amplifier transconductance (gm)
during soft-start
–2 μA < I(COMP) < 2 μA, V(COMP) = 1 V, V(FB) = 0.4 V
Error amplifier dc gain
V(FB) = 0.8 V
Min unity gain bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100-mV overdrive
COMP to SW current
transconductance
50
nA
350
μMhos
77
μMhos
10 000
V/V
2500
kHz
±30
μA
12
A/V
CURRENT-LIMIT
All VIN and temperatures, open loop (1)
Current-limit threshold
All temperatures, V(VIN) = 12 V, open loop
(1)
V(VIN) = 12 V, TA = 25°C, open loop (1)
4.5
5.5
6.8
4.5
5.5
6.3
5.2
5.5
5.9
A
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
176
°C
12
°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
(1)
1.55
2
V
Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RT/CLK low threshold
MIN
TYP
0.5
1.2
MAX
UNIT
V
SOFT START AND TRACKING (SS/TR PIN)
ISS
Charge current
V(SS/TR) = 0.4 V
1.7
µA
VSS(ofs)
SS/TR-to-FB matching
V(SS/TR) = 0.4 V
42
mV
SS/TR-to-reference crossover
98% nominal
1.16
V
SS/TR discharge current (overload)
V(FB) = 0 V, V(SS/TR) = 0.4 V
354
µA
SS/TR discharge voltage
V(FB) = 0 V
54
mV
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low
FB falling
FB threshold for PWRGD high
FB rising
90%
93%
FB threshold for PWRGD low
FB rising
108%
FB threshold for PWRGD high
FB falling
106%
Hysteresis
FB falling
2.5%
Output high leakage
V(PWRGD) = 5.5 V, TA = 25°C
10
On resistance
I(PWRGD) = 3 mA, V(FB) < 0.79 V
45
Minimum VIN for defined output
V(PWRGD) < 0.5 V, I(PWRGD) = 100 µA
0.9
2
TYP
MAX
nA
Ω
V
6.6 Timing Requirements
MIN
UNIT
RT/CLK
Minimum CLK input pulse width
15
ns
6.7 Switching Characteristics
TJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE AND UVLO (EN PIN)
Enable to COMP active
V(VIN) = 12 V, TA = 25°C
540
µs
60
ns
100
ns
CURRENT-LIMIT
Current limit threshold delay
SW
ton
Minimum on time
V(VIN) = 23.7 V, VO = 5 V, IO = 3.5 A,
R(RT) = 39.6 kΩ, TA = 25°C
RT/CLK
Switching frequency range using RT mode
ƒS
Switching frequency
100
R(RT) = 200 kΩ
Switching frequency range using CLK
mode
450
500
160
2500
kHz
550
kHz
2300
kHz
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
6
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with an RT
resistor (R(RT)) in series
55
ns
PLL lock in time
Measured at 500 kHz
78
μs
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SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
0.25
0.814
0.809
0.2
V o lta g e R e fe r e n c e ( V )
S ta tic D r a in - S o u r c e O n - S ta te R e s is ta n c e (: )
6.8 Typical Characteristics
0.15
0.1
0.05
0.804
0.799
0.794
0.789
BOOT-SW = 3 V
BOOT-SW = 6 V
0
0.784
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (qC)
D004
D028
V(VIN) = 12 V
Figure 1. On Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
6.5
6.5
6.3
6.3
H ig h - S id e S w itc h C u r r e n t ( A )
H ig h - S id e S w itc h C u r r e n t ( A )
-40q
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
25q
150q
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
4.5
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
150
0
10
20
30
40
50
60
Input Voltage (V)
D027
D026
V(VIN) = 12 V
Figure 3. Switch Current-Limit vs Junction Temperature
Figure 4. Switch Current-Limit vs Input Voltage
500
550
450
530
S w itc h in g F r e q u e n c y ( k H z )
S w itc h in g F r e q u e n c y ( k H z )
540
520
510
500
490
480
470
350
300
250
200
150
460
450
-50
400
100
-25
0
25
50
75
100
Junction Temperature (qC)
V(VIN) = 12 V
125
150
200
300
400
500
600
700
800
900
Resistance at RT/CLK (k:)
D025
R(RT) = 200 kΩ
Figure 5. Switching Frequency vs Junction Temperature
1000
D024
Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
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Typical Characteristics (continued)
500
450
2000
T r a n s c o n d u c ta n c e ( P A /V )
S w itc h in g F r e q u e n c y ( k H z )
2500
1500
1000
500
400
350
300
250
0
200
0
50
100
150
200
Resistance at RT/CLK (k:)
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
D023
150
D022
V(VIN) = 12 V
Figure 7. Switching Frequency vs RT/CLK Resistance
High Frequency Range
Figure 8. EA Transconductance vs Junction Temperature
1.33
120
1.3
100
90
E N T h r e s h o ld ( V )
T r a n s c o n d u c ta n c e ( P A /V )
110
80
70
60
50
40
1.27
1.24
1.21
1.18
30
20
1.15
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
150
-50
25
50
75
100
125
150
D020
V(VIN) = 12 V
Figure 9. EA Transconductance During Soft-Start vs
Junction Temperature
Figure 10. EN Pin Voltage vs Junction Temperature
-3.5
-0.5
-3.7
-0.7
-3.9
-0.9
In p u t C u r r e n t a t E N ( P A )
In p u t C u r r e n t a t E N ( P A )
0
Junction Temperature (qC)
V(VIN) = 12 V
-4.1
-4.3
-4.5
-4.7
-4.9
-1.1
-1.3
-1.5
-1.7
-1.9
-5.1
-2.1
-5.3
-2.3
-5.5
-2.5
-50
-25
0
25
50
75
Junction Temperature (qC)
V(VIN) = 12 V
100
125
150
-50
-25
0
V(EN) = Threshold + 50 mV
25
50
75
Junction Temperature (qC)
D019
Figure 11. EN Pin Current vs Junction Temperature
8
-25
D021
V(VIN) = 12 V
100
125
150
D018
V(EN) = Threshold – 50 mV
Figure 12. EN Pin Current vs Junction Temperature
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Typical Characteristics (continued)
-2.5
100
V (FB) Falling
N o m in a l S w itc h in g F r e q u e n c y ( % )
-2.7
I ( E N ) H y s te r e s is ( P A )
-2.9
-3.1
-3.3
-3.5
-3.7
-3.9
-4.1
-4.3
-4.5
V (FB) Rising
75
50
25
0
-50
-25
0
25
50
75
100
125
150
Junction Temperature (qC)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Voltage at FB (V)
D017
0.8
D016
V(VIN) = 12 V
Figure 14. Switching Frequency vs FB
3
3
2.5
2.5
S u p p ly C u r r e n t a t V IN (P A )
S u p p ly C u r r e n t a t V IN (P A )
Figure 13. EN Pin Current Hysteresis vs Junction
Temperature
2
1.5
1
0.5
2
1.5
1
0.5
0
0
-50
-25
0
25
50
75
100
125
150
Junction Temperature (qC)
0
20
30
40
50
Input Voltage (V)
V(VIN) = 12 V
60
D014
TJ = 25 °C
Figure 15. Shutdown Supply Current vs Junction
Temperature
Figure 16. Shutdown Supply Current vs Input Voltage
210
210
190
190
S u p p ly C u r r e n t a t V IN ( P A )
S u p p ly C u r r e n t a t V IN ( P A )
10
D015
170
150
130
110
90
170
150
130
110
90
70
70
-50
-25
0
25
50
75
Junction Temperature (qC)
100
125
150
0
10
V(VIN) = 12 V
20
30
40
50
Input Voltage (V)
D013
60
D012
TJ = 25°C
Figure 17. I(VIN) Supply Current vs Junction Temperature
Figure 18. I(VIN) Supply Current vs Input Voltage
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2.6
4.5
2.5
4.4
2.4
4.3
In p u t V o lta g e ( V )
In p u t V o lta g e a t B O O T - P H ( V )
Typical Characteristics (continued)
2.3
2.2
2.1
2
4.2
4.1
4
3.9
1.9
3.8
BOOT-PH UVLO Falling
UVLO Start Switching
BOOT-PH UVLO Rising
UVLO Stop Switching
1.8
3.7
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
150
-50
Figure 19. BOOT-SW UVLO vs Junction Temperature
50
75
100
125
150
D010
Figure 20. Input Voltage UVLO vs Junction Temperature
108
P o w e r - G o o d T h r e s h o ld ( % )
P o w e r - G o o d R e s is ta n c e (: )
25
110
70
60
50
40
30
20
10
106
104
102
FB
100
FB Falling
98
FB Rising
FB Falling
96
94
92
90
0
88
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
150
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
D009
V(VIN) = 12 V
150
D008
V(VIN) = 12 V
Figure 21. PWRGD On Resistance vs Junction Temperature
Figure 22. PWRGD Threshold vs Junction Temperature
900
60
800
55
S S /T R to F B O ffs e t ( m V )
700
600
O ffs e t ( m V )
0
Junction Temperature (qC)
80
500
400
300
200
50
45
40
35
30
25
100
0
20
0
100
200
300
400
500
600
700
SS/TR (mV)
V(VIN) = 12 V
800
-50
-25
0
25°C
25
50
75
100
125
Junction Temperature (qC)
D007
V(VIN) = 12 V
Figure 23. SS/TR to FB Offset vs FB
10
-25
D011
150
D006
V(FB) = 0.4 V
Figure 24. SS/TR to FB Offset vs Temperature
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Typical Characteristics (continued)
5.6
Start
5.5
Stop
I n p u t V o lta g e ( V )
5.4
5.3
5.2
5.1
Dropout
Voltage
5
4.9
Dropout
Voltage
4.8
4.7
4.6
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Output Current (A)
0.45
0.5
D005
Figure 25. 5-V Start and Stop Voltage (see Low Dropout Operation and Bootstrap Voltage (BOOT))
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7 Detailed Description
7.1 Overview
The TPS54361-Q1 device is a 60-V, 3.5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. The device implements constant-frequency current-mode control which reduces output capacitance
and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz
allows either efficiency or size optimization when selecting the output filter components. The switching frequency
is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked
loop (PLL) connected to the RT/CLK pin that synchronizes the power switch turn-on to a falling edge of an
external clock signal.
The TPS54361-Q1 device has a default input start-up voltage of 4.3 V typical. The EN pin adjusts the input
voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current source
enables operation when the EN pin is floating. The operating current is 152 μA under no load condition when not
switching. When the device is disabled, the supply current is 2 μA.
The integrated 87-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54361-Q1 device reduces the
external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is
monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54361-Q1 device to operate at
high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply
voltage of the application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than
106% of the desired output voltage.
The SS/TR (soft-start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor must be connected to the pin to adjust the soft-start time. A resistor
divider can be connected to the pin for critical power supply sequencing requirements. The SS/TR pin is
discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature
fault, UVLO fault or a disabled condition. When the overload condition is removed, the soft-start circuit controls
the recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces the
switching frequency during start up and overcurrent fault conditions to help maintain control of the inductor
current.
12
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7.2 Functional Block Diagram
EN
PWRGD
VIN
Shutdown
UV
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Boot
UVLO
Current
Sense
PWM
Comparator
FB
BOOT
SS/TR
Logic
Shutdown
6
Slope
Compensation
SW
COMP
Frequency
Foldback
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
10/9/2013 A0272435
GND
Thermal Pad
RT/ CLK
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7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS54361-Q1 device uses fixed-frequency peak current-mode control with adjustable switching frequency.
The output voltage is compared through external resistors connected to the FB pin to an internal voltage
reference by an error amplifier. An internal oscillator initiates the turn on of the high-side power switch. The error
amplifier output at the COMP pin controls the high-side power-switch current. When the high-side MOSFET
switch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP
pin voltage increases and decreases as the output current increases and decreases. The device implements
current-limiting by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is
implemented with a minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54361-Q1 device adds a compensating ramp to the MOSFET switch-current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current-limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.
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Feature Description (continued)
7.3.3 Pulse-Skip Eco-mode
The TPS54361-Q1 device operates in a pulse-skipping Eco-mode at light load currents to improve efficiency by
reducing switching and gate drive losses. The device enters Eco-mode if the output voltage is within regulation
and the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold. The
pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.
Because the device is not switching, the output voltage begins to decay. The voltage control-loop responds to
the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54361-Q1 device senses and controls the peak switch current and not the
average load current. Therefore the load current at which the device enters Eco-mode is dependent on the
output inductor value. The circuit in Figure 48 enters Eco-mode at about a 25-mA output current. As the load
current approaches zero, the device enters a pulse-skip mode. During the time period when there is no switching
the input current is reduced to the 152-µA quiescent current.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54361-Q1 device provides an integrated bootstrap voltage-regulator. A small capacitor between the
BOOT and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed
when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the
BOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R-grade dielectric with a voltage rating of 10 V
or higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54361-Q1
device operates at a 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the
voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side
MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at
high output voltages, the small low-side MOSFET disables at 24-V output and re-enables when the output
reaches 21.5 V.
Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on
for many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle
of the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during
dropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the lowside diode voltage and the printed circuit board (PCB) resistance.
The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage is
plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty-cycle (low-dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged which results in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cycle
PWM control.
14
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Feature Description (continued)
At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 1
calculates the minimum input voltage for this condition.
VOmax = Dmax × (V(VIN)min – IOmax × rDS(on) + Vd) – Vd + IOmax × RDC
where
•
•
•
•
•
•
Dmax ≥ 0.9
rDS(on) = 1 / (–0.3 × V(BOOT_SW)2 + 3.577 x V(BOOT_SW) – 4.246)
I(BOOT_SW) = 100 µA
V(BOOT_SW) = V(BOOT) + Vd
V(BOOT) = (1.41 × V(VIN) – 0.554 – Vd × ƒS × 10-6 – 1.847 × 103 × I(BOOT_SW)) / (1.41 + ƒS × 10-6)
Vd = Forward Drop of the Catch Diode
(1)
7.3.5 Error Amplifier
The TPS54361-Q1 voltage-regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start operation,
the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-start voltage.
The frequency compensation components (capacitor, series resistor, and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. Divider resistors with a 1%-tolerance or better are recommended.
Select the low-side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors from the FB input current may become noticeable.
æ V - 0.8 V ö
R(HS) = R(LS) ´ ç O
÷
è 0.8 V ø
(2)
7.3.7 Enable and Adjust Undervoltage Lockout
The TPS54361-Q1 device enables when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds
the enable threshold of 1.2 V. The TPS54361-Q1 device disables when the VIN pin voltage falls below 4 V or
when the EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source, I1, of 1.2 μA that
enables operation of the TPS54361-Q1 device when the EN pin floats.
If an application requires a higher undervoltage-lockout (UVLO) threshold, use the circuit shown in Figure 26 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.- μA
Ihys current is removed. This additional current facilitates the adjustable input-voltage UVLO hysteresis. Use
Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, from 40 V to 60 V), the EN pin experiences a voltage greater than the absolute maximum
voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the EN
resistors, the EN pin is clamped internally with a 5.8-V Zener diode that sinks up to 150 μA.
- VSTOP
V
RUVLO1 = START
Ihys
(3)
RUVLO2 =
V(EN)th
VSTART - V(EN)th
RUVLO1
+ I1
(4)
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Feature Description (continued)
VIN
TPS54361-Q1
I1
RUVLO1
V(VIN)
Ihys
TPS54361-Q1
RUVLO1
EN
EN
V(EN)th
RUVLO2
RUVLO2
Figure 26. Adjustable Undervoltage Lockout
(UVLO)
10 kΩ
Node
5.8 V
Figure 27. Internal EN Pin Clamp
7.3.8 Soft-Start/Tracking Pin (SS/TR)
The TPS54361-Q1 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the reference voltage of the power-supply and regulates the output accordingly. A capacitor on the
SS/TR pin to ground implements a soft-start time. The TPS54361-Q1 has an internal pullup current source of 1.7
μA that charges the external soft-start capacitor. The calculations for the soft-start time (10% to 90%) are shown
in Equation 5. The voltage reference (Vref) is 0.8 V and the soft-start current (ISS) is 1.7 μA. The soft-start
capacitor must remain lower than 0.47 μF and greater than 0.47 nF.
t (ms) ´ ISS (μA)
CSS (nF) = SS
Vref (V) ´ 0.8
(5)
At power up, the TPS54361-Q1 device does not start switching until the soft-start pin is discharged to less than
54 mV to ensure a proper power up, see Figure 28.
Also, during normal operation, the TPS54361-Q1 device stops switching and the SS/TR must discharge to 54
mV when one of the following occurs: the VIN UVLO is exceeded, the EN pin pulled below 1.2 V, or a thermal
shutdown event occurs.
The FB voltage follows the SS/TR pin voltage with a 42 mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).
The SS/TR voltage ramps linearly until clamped at 2.7 V typically as shown in Figure 28.
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Feature Description (continued)
V(EN)
V(SS/TR)
V(FB)
VO
Figure 28. Operation of SS/TR Pin When Starting
7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain output of a power on reset pin of another
device. The sequential method is illustrated in Figure 29 using two TPS54361-Q1 devices. The power good is
connected to the EN pin on the TPS54361-Q1 which enables the second power supply once the primary supply
reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1ms start-up delay. Figure 30 shows the results of Figure 29.
TPS54361-Q1
TPS54361-Q1
PWRGD
EN
SS/TR
EN
V(EN)(1)
V(PWRGD)
SS/TR
PWRGD
VO(1)
VO(2)
Figure 29. Schematic for Sequential Start-Up
Sequence
Figure 30. Sequential Startup using EN and
PWRGD
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Feature Description (continued)
TPS54361-Q1
3
EN
4
SS/TR
6
PWRGD
V(EN)(1), V(EN)(2)
VO(1)
VO(2)
TPS54361-Q1
3
EN
4
SS/TR
6
PWRGD
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Schematic for Ratiometric Start-Up
Sequence
Figure 32. Ratio-Metric Startup Using Coupled
SS/TR pins
Figure 31 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs ramps up and reaches regulation at the same time. When calculating the soft-start time the
pullup current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.
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Feature Description (continued)
TPS54361-Q1
EN
VO(1)
SS /TR
PWRGD
TPS54361-Q1
VO(2)
EN
R (TR)1
SS / TR
R(TR)2
PWRGD
FB
R (HS)
R(LS)
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R(TR)1 and R(TR)2 shown in Figure 33 to the output of the power supply that needs to be tracked or another
voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the
VO(2) slightly before, after or at the same time as VO(1). Equation 8 is the voltage difference between VO(1) and
VO(2) at the 95% of nominal output regulation.
The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset
(VSS(ofs)) in the soft-start circuit and the offset created by the pullup current source (ISS) and tracking resistors, the
VSS(ofs) and ISS are included as variables in the equations.
To design a ratio-metric start up in which the VO(2) voltage is slightly greater than the VO(1) voltage when VO(2)
reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 8 results in a
positive number for applications which the VO(2) is slightly lower than VO(1) when VO(2) regulation is achieved.
Because the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO or thermal shutdown
fault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. Make sure the
calculated R(TR)1 value from Equation 6 is greater than the value calculated in Equation 9 to ensure the device
can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSS(ofs) becomes larger as
the soft-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
VO(2) + DV VSS(ofs)
´
R(TR)1 =
Vref
ISS
(6)
R(TR)2 =
Vref ´ R(TR)1
VO(2) + DV - Vref
(7)
(8)
(9)
ΔV = VO(1) – VO(2)
R(TR)1 > 2800 × VO(1) – 180 × ΔV
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Feature Description (continued)
V(EN)
V(EN)
VO(1)
VO(1)
VO(2)
VO(2)
Figure 34. Ratiometric Startup With Tracking Resistors
Figure 35. Ratiometric Startup With Tracking Resistors
V(EN)
VO(1)
VO(2)
Figure 36. Simultaneous Startup With Tracking Resistor
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54361-Q1 is adjustable over a wide range from 100 kHz to 2500 kHz by
placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution size
one would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,
maximum input voltage and minimum controllable on time must be considered. The minimum controllable on
time is typically 100 ns which limits the maximum operating frequency in applications with high input to output
step down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A more
detailed discussion of the maximum switching frequency is provided in the next section.
101756
RT (kW) =
f sw (kHz)1.008
(10)
f sw (kHz) =
20
92417
RT (kW)0.991
(11)
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Feature Description (continued)
7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency
The TPS54361-Q1 implements peak current mode control in which the COMP pin voltage controls the peak
current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage
are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side
switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets
the peak switch current-limit. The TPS54361-Q1 provides an accurate current-limit threshold with a typical
current-limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. The
relationship between the inductor value and the peak inductor current is shown in Figure 37.
Inductor Current (A)
Peak inductor current
ΔCL(peak)
Open-loop Current-limit
ΔCL(peak) = V(VIN) / L × td(CL)
td(CL)
ton
Figure 37. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54361-Q1 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB
pin voltage falls from 0.8 V to 0 V. The TPS54361-Q1 device uses a digital frequency foldback to enable
synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the
inductor current may exceed the peak current limit because of the high input voltage and the minimum
controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases
slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the
period of the switching cycle providing more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 12 calculates the maximum switching frequency at
which the inductor current remains under control when VO is forced to VO(SC). The selected operating frequency
must not exceed the calculated value.
Equation 13. calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.
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Feature Description (continued)
ƒS(skip ) max =
1
ton
æ
IO ´ RDC + VO + Vd
´ç
ç V(VIN) max - IO ´ rDS(on ) + Vd
è
ö
÷
÷
ø
where
•
•
•
•
•
•
ton = controllable on time
IO = output current
RDC = inductor resistance
V(VIN)max = maximum input voltage
VO = output voltage
Vd = diode voltage drop
ƒS(shift) =
ƒdiv æç ICL ´ RDC + VO(SC ) + Vd
´
ton ç V(VIN) - ICL ´ rDS(on ) + Vd
è
(12)
ö
÷
÷
ø
where
•
•
•
•
ƒdiv = frequency divide equals (1, 2, 4, or 8)
VO(SC) = output voltage during short
ICL = current limit
rDS(on) = switch on resistance
(13)
7.3.12 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 38. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V and
have a pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The rising
edge of the SW is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit
must be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground when
the synchronization signal is off. When using a low impedance signal source, the frequency set resistor is
connected in parallel with an ac coupling capacitor to a termination resistor (for example, 50 Ω) as shown in
Figure 38. The two resistors in series provide the default frequency setting resistance when the signal source is
turned off. The sum of the resistance must set the switching frequency close to the external CLK frequency. AC
coupling the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin is recommended.
The first time the RT/CLK is pulled above the PLL threshold the TPS54361-Q1 switches from the RT resistor
free-running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and
the RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 ms. During the
transition from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and
then increases or decreases to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to
the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and
fault conditions. Figure 39, Figure 40 and Figure 41 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
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Feature Description (continued)
TPS54361-Q1
TPS54361-Q1
RT/CLK
R(RT)
Clock
Source
PLL
PLL
RT/CLK
Hi-Z
Clock
Source
R(RT)
Figure 38. Synchronizing to a System Clock
V(SW)
V(SW)
EXT
EXT
IL
IL
Figure 39. Plot of Synchronizing in CCM
Figure 40. Plot of Synchronizing in DCM
V(SW)
EXT
IL
Figure 41. Plot of Synchronizing in Eco-mode
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Feature Description (continued)
7.3.13 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. When the FB pin is between 93% and 106% of the internal voltage
reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩ to a voltage source that is
5.5 V or less is recommended. A higher pull-up resistance reduces the amount of current drawn from the pull up
voltage source when the PWRGD pin is asserted low. A lower pull-up resistance reduces the switching noise
seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but
with reduced current sinking capability. The PWRGD achieves full current-sinking capability as VIN input voltage
approaches 3 V.
The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
7.3.14 Overvoltage Protection
The TPS54361-Q1 device incorporates an output overvoltage protection (OVP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients in designs with low output
capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual
output voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage
for a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the
peak current limit threshold. When the overload condition is removed, the regulator output rises and the error
amplifier output transitions to the normal operating level. In some applications, the power supply output voltage
can increase faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the
internal voltage reference, the high-side MOSFET resumes normal operation.
7.3.15 Thermal Shutdown
The TPS54361-Q1 device provides an internal thermal shutdown to protect the device when the junction
temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the
thermal trip threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence
controlled by discharging the SS/TR pin.
7.3.16 Small Signal Model for Loop Response
Figure 42 shows a simplified equivalent model for the TPS54361-Q1 control loop which can be simulated to
check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier
with a gmea of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source.
The resistor, R(OEA), and capacitor, C(OEA), model the open loop gain and frequency response of the amplifier.
The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency
response measurements. Plotting c-a provides the small signal response of the frequency compensation. Plotting
a-b provides the small signal response of the overall loop. The dynamic loop response can be evaluated by
replacing the load resistor, R(L), with a current source with the appropriate load step amplitude and step rate in a
time domain analysis. This equivalent model is only valid for continuous conduction mode (CCM) operation.
24
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Feature Description (continued)
SW
VO
Power Stage
gm ps 12 A/V
a
b
R(ESR)
R(HS)
R(L)
COMP
c
0.8 V
R(COMP)
C(OEA)
R(OEA)
C(POLE)
C(O)
FB
gmea
R(LS)
350 µA/V
C(ZERO)
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Small Signal Model for Loop Response
7.3.17 Simple Small Signal Model for Peak Current Mode Control
Figure 43 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54361-Q1 device power stage can be approximated by a voltage-controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 14 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 42) is the power stage
transconductance, gmps. The gmps for the TPS54361-Q1 device is 12 A/V. The low-frequency gain of the power
stage is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 43. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 17).
VO
ADC
V(c)
R(ESR)
ƒP
R(L)
gmps
C(O)
ƒZ
Figure 43. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
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Feature Description (continued)
VO
= ADC
V(c )
æ
s
ç1 +
2p ´ ƒ Z
´ è
æ
s
ç1 +
2p ´ ƒP
è
ö
÷
ø
ö
÷
ø
(14)
(15)
ADC = gmps × R(L)
ƒP =
ƒZ =
C(O)
1
´ R(L) ´ 2p
(16)
1
C(O) ´ R(ESR) ´ 2p
(17)
7.3.18 Small Signal Model for Frequency Compensation
The TPS54361-Q1 device uses a transconductance amplifier for the error amplifier and supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 44. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to
the small signal model in Figure 44. The open-loop gain and bandwidth are modeled using the R(OEA) and C(OEA)
shown in Figure 44. See the application section for a design example using a Type 2A network with a low ESR
output capacitor.
Equation 18 through Equation 27 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
VO
R(HS)
FB
Type 2A
gmea
R(LS)
Type 2B
Type 1
COMP
Vref
R(COMP)
R(OEA)
R(COMP)
C(POLE)
C(POLE)
C(OEA)
C(ZERO)
C(ZERO)
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Types of Frequency Compensation
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Feature Description (continued)
Aol
P1
A0
Z1
P2
A1
BW
Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation
R(OEA) =
C(OEA)
Aol (V/V )
gmea
gmea
=
2p ´ BW (Hz )
(18)
(19)
æ
ö
s
ç1 +
÷
2p ´ ƒ Z1 ø
è
EA = A0 ´
æ
ö æ æ
öö
s
s
ç1 +
÷ ´ çç 1 + ç
÷÷
2p ´ ƒP1 ø è è 2p ´ ƒP2 ø ÷ø
è
A0 = gm ea ´ R(OEA) ´
R(HS) + R(LS)
A1 = gm ea ´ R(OEA) P R(COMP) ´
P1 =
Z1 =
P2 =
(20)
R(LS)
(21)
R(LS)
R(HS) + R(LS)
(22)
1
2p ´ R(OEA) ´ C(ZERO)
(23)
1
2p ´ R(COMP) ´ C(ZERO)
(24)
1
(
2p ´ R(COMP) P R(OEA) ´ C(POLE) + C(OEA)
Type 2A
)
(25)
1
P2 =
Type 2B
2p ´ R(COMP) P R(OEA) ´ C(OEA)
P2 =
2π ´ R(OEA)
(26)
1
type 1
´ (C(POLE) + C(OEA) )
(27)
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7.4 Device Functional Modes
7.4.1 Operation with V(VIN) = < 4.5 V (Minimum V(VIN))
The device is recommended to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 V
and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device will not switch. If EN is externally pulled up to V(VIN) using an external resistor divider or
left floating, when V(VIN) passes the UVLO threshold the device will become active. Switching is enabled, and
the soft start sequence is initiated. The TPS54361-Q1 device starts at the soft start time determined by the
external capacitance at the SS/TR pin.
7.4.2 Operation with EN Control
The enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled and
switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If
the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes
active. Switching is enabled, and the soft start sequence is initiated. The TPS54361-Q1 device starts at the softstart time determined by the external capacitance at the SS/TR pin.
7.4.3 Alternate Power Supply Topologies
7.4.3.1 Inverting Power Supply
The TPS54361-Q1 can be used to convert a positive input voltage to a negative output voltage. Idea applications
are amplifiers requiring a negative power supply. For a more detailed example see SLVA317.
VI
+
CI
C(BOOT)
LO
VIN
C(VIN)
PH
BOOT
GND
R(HS)
+
GND
TPS54361-Q1
R(LS)
FB
C(O)
VO
EN
COMP
SS /TR
R(COMP)
RT /CLK
C(SS)
R(RT)
C(ZERO)
C(POLE)
Copyright © 2016, Texas Instruments Incorporated
Figure 46. TPS54361-Q1 Inverting Power Supply based on the Application Note, SLVA317
7.4.3.2 Split Rail Power Supply
The TPS54361-Q1 device can be used to convert a positive input voltage to a split rail positive and negative
output voltage by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive and
negative voltage power supply. For a more detailed example see SLVA369.
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Device Functional Modes (continued)
+
VI
CO+
+
CI
C(BOOT)
BOOT
VIN
VO+
GND
PH
LO
C(VIN)
R(HS)
GND
+
CO–
R(LS)
TPS54361-Q1
FB
VO–
EN
SS /TR
COMP
R(COMP)
RT /CLK
C(SS)
R(RT)
C(ZERO)
C(POLE)
Copyright © 2016, Texas Instruments Incorporated
Figure 47. TPS54361-Q1 Split Rail Power Supply based on the Application Note, SLVA369
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54361-Q1 device is a 60-V, 3.5-A, step down regulator with an integrated high side MOSFET. This
device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output
current of 3.5 A. Example applications are: 12 V, 24 V and 48 V Industrial, Automotive and Communications
Power Systems. Use the following design procedure to select component values for the TPS54361-Q1 device.
This procedure illustrates the design of a high frequency switching regulator using ceramic output capacitors.
Calculations can be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, use
the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
8.2 Typical Application
PWRGD
PWRGD PULL UP
R8
U1
DNPC10 DNPC3
2.2 µF 2.2 µF
C1
2.2 µF
C2
2.2 µF
R1
442 kΩ
5
SS/TR
2
J2
3
4
R3
162 kΩ
TP2
7
VIN
PWRGD
EN
BOOT
RT/CLK
SS/TR
COMP
GND
C13
0.01 µF
2
1
GND
J4
GND
EN
GND
R2
90.9 kΩ
2
1
R4
13 kΩ
SW
FB
GND
PAD
10
TP10 1.00 kΩ
TP9
C4
1
L1
TP5
TP6
TP7
8.2µH
FB
8
D1
C6
47 µF
TPS54361-Q1
C8
39 pF
5 V at 3.5 A
0.1 µF
9
6
R7
49.9 Ω
1
C11
+
DNP
GND
C7 DNPC9
47 µF
47µF
+
C12
DNP
1
TP8
1
VO
2
GND
J1
GND
TP4
2
2
TP1
2
1
1
2
1
VI
GND
3
7 V to 60 V
R5
53.6 kΩ
C5
6800 pF
GND
J3
FB
R6
10.2 kΩ
TP3
GND
GND
2 SS/TR
1
SS/TR
GND
J5
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 48. 5-V Output TPS54361-Q1 Design Example
8.2.1 Design Requirements
A few parameters must be known in order to start the design process. These requirements are typically
determined at the system level. This example is designed to the following known parameters:
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Output Voltage (VO)
5V
Transient Response 0.875-A to 2.625-A load step
ΔVO = ±4 %
Maximum Output Current (IO)
3.5 A
Input Voltage (VI)
12 V nominal 7 V to 60 V
Output Voltage Ripple (VO(rip))
0.5% of VO
Start Input Voltage (rising VI)
6.5 V
Stop Input Voltage (falling VI)
5V
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54361-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible because the highest switching frequency produces the smallest solution size. High
switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply
that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum ontime of the internal power switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 28 and Equation 29 must be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, ton, is 100 ns for the TPS54361-Q1 device. For this example, the output voltage is
5 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 960 kHz to
avoid pulse skipping from Equation 28. To ensure overcurrent runaway is not a concern during short circuits use
Equation 28 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 25 mΩ, switch resistance of 87
mΩ, a current limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is
1220 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 30 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 48. For 600 kHz operation, the closest
standard value resistor is 162 kΩ.
1
æ 3.5 A ´ 25 mW + 5 V + 0.7 V ö
´ ç
ƒS(skip) max =
÷ = 960 kHz
100 ns
è 60 V – 3.5 A ´ 87 mW + 0.7 V ø
(28)
8
æ 4.7 A ´ 25 mW + 0.1 V + 0.7 V ö
´ ç
÷ = 1220 kHz
100 ns
è 60 V – 4.7 A ´ 87 mW + 0.7 V ø
101756
RT (kW) =
= 161 kW
600 (kHz)1.008
ƒS(shift) =
(29)
(30)
8.2.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 31.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal
to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the
designer, however, the following guidelines may be used.
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For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current must always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, choosing a relatively large inductor ripple current is
best to provide sufficient ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 7.3 μH. The nearest
standard value is 8.2 μH. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from Equation 33 and Equation 34. For this design,
the RMS inductor current is 3.5 A and the peak inductor current is 3.97 A. The chosen inductor has a saturation
current rating of 5.8 A and an RMS current rating of 5.05 A.
As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the
regulator but allows for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54361-Q1 which is nominally 5.5 A.
V max - VO
VO
60 V – 5 V
5V
LO min = I
´
=
´
= 7.3 µH
IO ´ KIND
VI max ´ ƒS 3.5 A ´ 0.3
60 V ´ 600 kHz
(31)
spacer
V ´ (VI max - VO )
5 V ´ (60 V – 5 V)
Irip = O
=
= 0.932 A
VI max´ LO ´ ƒS
60 V ´ 8.2 µH ´ 600 kHz
(32)
spacer
2
IL(RMS ) =
(IO ) +
2
æ VO ´ (VI max - VO ) ö
1
´ ç
÷ =
12 èç VI max ´ LO ´ ƒS ø÷
2
(3.5 A ) +
2
æ 5 V ´ (60 V – 5 V ) ö
1
´ ç
÷ = 3.5 A
ç
÷
12
è 60 V ´ 8.2 µH ´ 600 kHz ø
(33)
spacer
IL(peak ) = IO +
Irip
2
= 3.5 A +
0.932 A
= 3.97 A
2
(34)
8.2.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 35 shows the minimum output capacitance necessary, where ΔIO is the change in output current, ƒS is
the regulators switching frequency and ΔVO is the allowable change in the output voltage. For this example, the
transient load response is specified as a 4% change in VO for a load step from 0.875 A to 2.625 A. Therefore,
ΔIO is 2.625 A - 0.875 A = 1.75 A and ΔVO = 0.04 × 5 = 0.2 V. Using these numbers gives a minimum
capacitance of 29.2 μF. This value does not take the ESR of the output capacitor into account in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic
and tantalum capacitors have higher ESR that must be included in load step calculations.
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The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 49. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.
The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 36
calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LO
is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
peak output voltage, and V(int) is the initial voltage. For this example, the worst case load step is from 2.625 A to
0.875 A. The output voltage increases during this load transition and the stated maximum in our specification is
4 % of the output voltage which makes Vf = 1.04 × 5 = 5.2. V(int) is the initial capacitor voltage which is the
nominal output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of 25 μF.
Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VO(rip) is the maximum allowable output voltage ripple, and Irip is the
inductor ripple current. Equation 37 yields 7.8 μF.
Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 38 indicates the ESR must be less than 27 mΩ.
The most stringent criteria for the output capacitor is 29 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, two
47-μF, 10-V ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 58 µF, well above the
minimum required capacitance of 29 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the root-mean-square (RMS) value of the maximum ripple current.
Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For this
example, Equation 39 yields 269 mA.
2 ´ DIO
2 ´ 1.75 A
C(O) >
=
= 29.2 µF
ƒS ´ DVO 600 kHz ´ 0.2 V
(35)
C(O) > LO ´
((I
OH
)2 - (IOL )2
) = 8.2 µH ´ (2.625 A
2
- 0.875 A 2
(
)
2ö
2
æ
5.2 V 2 – 5 V 2
ç (Vf ) - V(int) ÷
è
ø
1
1
1
1
C(O) >
´
=
´
= 7.8 µF
8 ´ ƒS æ VO(rip) ö 8 ´ 600 kHz
æ 25 mV ö
ç 0.932 A ÷
ç
÷
ç Irip ÷
è
ø
è
ø
VO(rip)
25 mV
R(ESR) <
=
= 27 mW
Irip
0.932 A
ICO(RMS) =
(
)
VO ´ (VI min - VO )
12 ´ VI min ´ LO ´ ƒS
=
5V ´
)=
(60 V – 5 V )
12 ´ 60 V ´ 8.2 µH ´ 600 kHz
24.6 µF
(36)
(37)
(38)
= 269 mA
(39)
8.2.2.5 Catch Diode
The TPS54361-Q1 device requires an external catch diode between the SW pin and GND. The selected diode
must have a reverse voltage rating equal to or greater than VImax. The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode
because of the low forward voltage of these diodes. The lower the forward voltage of the diode, the higher the
efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
60 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54361-Q1
device.
For the example design, the Schottky diode was selected for its lower forward voltage and good thermal
characteristics compared to smaller devices. The typical forward voltage of the diode is 0.55 V at 3.5 A.
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The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode are
because of the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 is
used to calculate the total power dissipation, including conduction losses and AC losses of the diode.
The selected diode has a junction capacitance of 90 pF. Using Equation 40 with the nominal voltage VI of 12 V,
the total loss in the diode is 1.13 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD =
(VI - VO )
´ IO ´ Vd
VI
(12 V
2
+
C j ´ ƒS ´ (VI + Vd )
2
- 5 V ) ´ 3.5 A ´ 0.55 V
12 V
+
=
90 pF ´ 600 kHz ´ (12 V + 0.55 V)2
= 1.13 W
2
(40)
8.2.2.6 Input Capacitor
The TPS54361-Q1 device requires a high quality ceramic type X5R or X7R input decoupling capacitor with at
least 3 μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance because of DC-bias effects. The voltage rating of the input
capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating
greater than the maximum input current ripple of the TPS54361-Q1 device. The input ripple current can be
calculated using Equation 41.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations because of temperature can be minimized by selecting a dielectric material that is
more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator
capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The
input capacitor must also be selected with consideration for the dc bias. The effective value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V. For this example, two 2.2-μF, 100-V capacitors in parallel are used.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 42. Using the design example values, IO = 3.5 A, CI = 4.4 μF, ƒS = 600 kHz, yields an
input voltage ripple of 331 mV and a RMS input ripple current of 1.72 A.
ICI(RMS ) = IO x
VO
´
VI min
(VI min - VO )
VI min
= 3.5 A
5V
´
8.5 V
(8.5 V
I ´ 0.25
3.5 A ´ 0.25
DVI = O
=
= 331 mV
CI ´ ƒS
4.4 µF ´ 600 kHz
– 5 V)
8.5 V
= 1.72 A
(41)
(42)
8.2.2.7 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time required for the output voltage to reach its
nominal programmed value during power-up. This feature of the slow-start capacitor is useful if a load requires a
controlled voltage slew rate. This feature is also used if the output capacitance is large and would require large
amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to
charge the capacitor can make the TPS54361-Q1 device reach the current limit or excessive current draw from
the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both
of these problems.
34
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The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 43 can be used to find the minimum slow start time, tSS,
necessary to charge the output capacitor, C(O), from 10% to 90% of the output voltage, VO, with an average slow
start current of ISS(AV). In the example, to charge the effective output capacitance of 58 µF up to 5 V with an
average current of 1 A requires a 0.2 ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using Equation 5. For the
example circuit, the slow start time is not too critical because the output capacitor value is 2 × 47 μF which does
not require much current to charge to 5 V. The example circuit has the slow start time set to an arbitrary value of
3.5 ms which requires a 9.3-nF slow start capacitor calculated by Equation 44. For this design, the next larger
standard value of 10 nF is used.
C(O) ´ VO ´ 0.8
t SS >
ISS(AV)
(43)
CSS (nF) =
t SS (ms) ´ ISS (µA) 3.5 ms ´ 1.7 µA
=
= 9.3 nF
Vref (V) ´ 0.8
(0.8 V ´ 0.8 )
(44)
8.2.2.8 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor must have a 10 V or higher voltage
rating.
8.2.2.9 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54361-Q1 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one
for power down or brown outs when the input voltage is falling. For the example design, the supply must turn on
and start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts
switching, it must continue to do so until the input voltage falls below 5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of R1 and R2 between the VIN pin and
ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For the
example application, a 442 kΩ between the VIN and EN pins (R1) and a 90.9 kΩ between EN and ground (R2)
are required to produce the 6.5-V and 5-V start and stop voltages.
V
– VSTOP
6.5 V – 5 V
R1 = START
=
= 441 kW
Ihys
3.4 µA
(45)
R2 =
V(EN)
VSTART – V(EN)
R1
=
+ I1
1.2 V
= 90.9 kW
6.5 V – 1.2 V
+ 1.2 µA
442 kW
(46)
8.2.2.10 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Because of the
input current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but
may also introduce noise immunity problems.
V - 0.8 V
æ 5 V - 0.8 V ö
= 10.2 kW ´ ç
R5 = R6 ´ O
÷ = 53.5 kW
0.8 V
0.8 V
è
ø
(47)
8.2.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least ten-times greater the modulator pole.
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To get started, the modulator pole, ƒP(mod), and the ESR zero, ƒZ1 must be calculated using Equation 48 and
Equation 49. For C(O), use a derated value of 58.3 μF. Use equations Equation 50 and Equation 51 to estimate a
starting point for the crossover frequency, ƒCO. For the example design, ƒP(mod) is 1912 Hz and ƒZ(mod) is 1092
kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of
modulator pole and the switching frequency. Equation 50 yields 45.7 kHz and Equation 51 gives 23.9 kHz. Use
the lower value of Equation 50 or Equation 51 for an initial crossover frequency. For this example, the target ƒco
is 23.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IO max
3.5 A
ƒP(mod) =
=
= 1912 Hz
2 ´ p ´ VO ´ C(O) 2 ´ p ´ 5 V ´ 58.3 µF
(48)
ƒ Z(mod) =
1
1
=
= 1092 kHz
2 ´ p ´ R6 ´ C4
2 ´ p ´ 2.5 mW ´ 58.3 µF
where
•
C(O) is the parallel combination of C6 and C7 Figure 48
ƒCO = ƒP(mod) ´ ƒZ(mod) =
ƒCO = ƒP(mod) ´
ƒS
=
2
1912 Hz ´ 1092 kHz
1912 Hz ´
600 kHz
2
= 45.7 kHz
= 23.9 kHz
(49)
(50)
(51)
To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance, gmps,
is 12 A/V. The output voltage, VO, reference voltage, Vref, and amplifier transconductance, gmea, are 5 V, 0.8 V
and 350 μA/V, respectively. R4 is calculated to be 13 kΩ which is a standard value. Use Equation 53 to set the
compensation zero to the modulator pole frequency. Equation 53 yields 6404 pF for compensating capacitor C5.
6800 pF is used for this design.
æ 2 ´ p ´ ƒCO ´ CO ö
æ
ö
VO
ö
5V
æ 2 ´ p ´ 23.9 kHz ´ 58.3 µF ö æ
÷ ´ ç
R4 = ç
´ç
÷ = ç
÷ = 13 kW
÷
ç
÷
gmps
12 A / V
è
ø è 0.8 V ´ 350 µA / V ø
è Vref ´ gmea ø
è
ø
(52)
C5 =
1
1
=
= 6404 pF
2 ´ p ´ R4 ´ ƒP(mod)
2 ´ p ´ 13 kW ´ 1912 Hz
(53)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the
compensation pole. The selected value of C8 is 39 pF for this design example.
C4 ´ R 6
58.3 µF ´ 2.5 mW
=
= 11.2 pF
C8 =
R4
13 kW
(54)
1
1
C8 =
=
= 40.8 pF
R4 ´ ƒS ´ p
13 kW ´ 600 kHz ´ p
(55)
8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 300 mA. The power supply enters Eco-mode when the output current is lower than 24 mA. The input
current draw is 260 μA with no load.
36
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10 V/div
1 A/div
8.2.3 Application Curves
C4: IO
VI
20 mV/div
C3: VO AC coupled
Time = 5 ms/div
Figure 49. Load Transient
Figure 50. Line Transient (8 V to 40 V)
C1: VI
2 V/div
5 V/div 2 V/div
C2
C3: VO
C3
C2: V(SS/TR)
C2
C3: VO
C4: V(PGOOD)
C3
C4
Time = 2 ms/div
Time = 2 ms/div
Figure 51. Startup With VIN
Figure 52. Startup With EN
C1
C4: IL
C3: VO AC coupled
C3
C4
C1: V(SW)
C1
C4: IL
500 mA/div
10 V/div
C1: V(SW)
C4
20 mV/div
1 V/div
2 V/div
10 V/div
C1: V(EN)
C1
C2: V(EN)
1 A/div
–5-V offset
Time = 100 µs/div
C1
20 mV/div
VO
2 V/div
C3
5 V/div
100 mV/div
C4
C3
C3: VO AC coupled
Time = 2 µs/div
Time = 2 µs/div
IO = 3.5 A
IO = 100 mA
Figure 53. Output Ripple CCM
Figure 54. Output Ripple DCM
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C1: V(SW)
C1
C1: V(SW)
C1
1 A/div
C4: IL
C4: IL
C4
C3: VO AC coupled
C3: VI AC coupled
C3
200 mV/div
20 mV/div
200 mA/div
10 V/div
SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
C3
C4
Time = 2 µs/div
Time = 2 ms/div
No Load
IO = 3.5 A
C1: V(SW)
2 V/div
C1: V(SW)
C1
C4: IL
C4
20 mV/div
C3: VI AC coupled
20 mV/div
Figure 56. Input Ripple CCM
200 mA/div
500 mA/div
10 V/div
Figure 55. Output Ripple PSM
C3
C4
C4: IL
C3
C3: VO AC coupled
Time = 2 µs/div
IO = 100 mA
VI = 5.5 V
VO = 5 V
Figure 58. Low-Dropout Operation
2 V/div
2 V/div
Figure 57. Input Ripple DCM
VI
VO
VI
VO
IO = 100 mA
Time = 40 µs/div
EN floating
IO = 1 A
Figure 59. Low-Dropout Operation
38
Time = 20 µs/div
No load
EN floating
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Time = 40 µs/div
EN floating
Figure 60. Low-Dropout Operation
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100
100
90
95
80
90
E ffic ie n c y ( % )
E ffic ie n c y ( % )
70
85
80
75
VI =7V
60
50
40
VI =7V
30
V I = 12 V
V I = 12 V
70
V I = 24 V
V I = 24 V
20
V I = 36 V
V I = 36 V
65
V I = 48 V
V I = 48 V
10
V I = 60 V
V I = 60 V
60
0
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
VO = 5 V
0.001
0.01
0.1
1
Output Current (A)
D030
ƒS = 600 kHz
VO = 5 V
Figure 61. Efficiency Versus Load Current
D031
ƒS = 600 kHz
Figure 62. Light-Load Efficiency
100
100
VI =6 V
V I = 12 V
95
90
V I = 24 V
V I = 36 V
80
V I = 48 V
90
V I = 60 V
E ffic ie n c y ( % )
E ffic ie n c y ( % )
70
85
80
75
60
50
40
VI =6V
30
V I = 12 V
70
V I = 24 V
20
65
V I = 36 V
V I = 48 V
10
V I = 60 V
60
0
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
VO = 3.3 V
0.001
0.01
ƒS = 600 kHz
VO = 3.3 V
Figure 63. Efficiency Versus Load Current
60
0.1
1
Output Current (A)
D032
D034
ƒS = 600 kHz
Figure 64. Light-Load Efficiency
180
0.1
Gain
0.08
20
60
0
0
-20
-60
-40
-120
-60
-180
O u tp u t V o lta g e D e v ia tio n ( % )
120
P h a s e (q)
G a in ( d B )
Phase
40
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
10
100
1000
10000
Frequency (Hz)
VO = 5 V
VI = 12 V
ƒS = 600 kHz
100000
-0.1
0
0.5
IO = 3.5 A
Figure 65. Overall Loop-Frequency Response
1
1.5
2
2.5
3
3.5
Output Current (A)
D036
VO = 5 V
ƒS = 600 kHz
D033
VI = 12 V
Figure 66. Regulation Versus Load Current
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0.1
O u tp u t V o lta g e D e v ia tio n ( % )
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
10
20
30
40
50
Input Voltage (V)
VO = 5 V
ƒS = 600 kHz
60
D035
IO = 1.75 A
Figure 67. Regulation Versus Input Voltage
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4.5 V and 60 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS54361-Q1 converter
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. See Figure 68 for a PCB layout example.
• To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
• Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and
the anode of the catch diode. The SW pin should be routed to the cathode of the catch diode and to the
output inductor. Since the SW connection is the switching node, the catch diode and output inductor should
be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive
capacitive coupling.
• The GND pin should be tied directly to the thermal pad under the IC. The thermal pad should be connected to
internal PCB ground planes using multiple vias directly under the IC.
• For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
• The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and
routed with minimal lengths of trace.
• The additional external components can be placed approximately as shown.
• It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
Boxing in the components in the design of Figure 48 the estimated printed circuit board surface area is 1.025 in2
(661 mm2). This area does not include test points or connectors. If the area needs to be reduced, this can be
done by using a two sided assembly and replacing the 0603 sized passives with a smaller sized equivalent.
40
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Layout Guidelines (continued)
10.1.1 Power Dissipation Estimate
The following formulas show how to estimate the TPS54361-Q1 power dissipation under continuous conduction
mode (CCM) operation. These equations must not be used if the device is operating in discontinuous conduction
mode (DCM).
The power dissipation of the IC includes conduction loss (PCON), switching loss E, gate drive loss (Pg) and supply
current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.
1. Conduction loss
æV ö
5V
2
PCON = (IO ) ´ rDS(on ) ´ ç O ÷ = 3.5 A 2 ´ 87 mW ´
= 0.45 W
12 V
è VI ø
where
•
•
•
•
IO is the output current (A)
rDS(on) is the on-resistance of the high-side MOSFET (Ω)
VO is the output voltage (V)
V(VIN) is the input voltage (V)
(56)
2. Switching loss:
E = VI × ƒS × IO × tr = 12 V × 600 kHz × 3.5 A × 4.9 ns = 0.123 A
where
•
•
•
E is the switching loss
ƒS is the switching frequency (Hz)
tr is the SW pin voltage rise time and can be estimated by trise = V(VIN) × 0.16 ns/V + 3 ns
(57)
3. Gate charge loss:
PG = V(VIN) × Qg × ƒS = 12 V × 3 nC × 600 kHz = 0.022 W
where
•
Qg is the total gate charge of the internal MOSFET
(58)
4. Quiescent current loss:
PQ = V(VIN) × IQ = 12 V × 152 µA = 0.0018 W
where
•
IQ is the operating nonswitching supply current
(59)
Therefore,
Ptot = PCON + E + PG + PQ = 0.45 W + 0.123 W + 0.022 W + 0.0018 W = 0.597 W
(60)
For given TA:
TJ = TA + Rth × Ptot
where
•
•
•
•
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
Ptot is the total device power dissipation (W)
Rth is the thermal resistance of the package (°C/W)
(61)
For given TJmax = 150°C:
TAmax = TJmax – Rth × Ptot
where
•
•
TJmax is maximum junction temperature (°C)
TAmax is maximum ambient temperature (°C)
(62)
Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode,
and PCB trace resistance impacting the overall efficiency of the regulator.
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10.2 Layout Example
VO
Output
Capacitor
Topside
Ground
Area
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
VI
UVLO
Adjust
Resistors
BOOT
Catch
Diode
PWRGD
VIN
SW
EN
GND
SS/TR
RT/CLK
COMP
FB
Compensation
Network
Resistor
Divider
Thermal VIA
Soft-Start
Capacitor
Frequency
Set Resistor
Signal VIA
Figure 68. PCB Layout Example
42
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Product Folder Links: TPS54361-Q1
TPS54361-Q1
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SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the TPS54360 and TPS54361 Family Design Excel Tool, see SLVC452
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Create an Inverting Power Supply From a Step-Down Regulator, SLVA317
• Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369
• Evaluation Module for the TPS54361 Step-Down Converter, SLVU922
11.2.2 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54361-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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43
TPS54361-Q1
SLVSCC4B – APRIL 2014 – REVISED JANUARY 2017
www.ti.com
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
44
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Product Folder Links: TPS54361-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54361QDPRRQ1
ACTIVE
WSON
DPR
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54361Q
TPS54361QDPRTQ1
ACTIVE
WSON
DPR
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54361Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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