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TPS544C25, TPS544B25
SLUSC81 – MAY 2015
TPS544x25 4.5-V to 18-V, 20-A and 30-A SWIFT™
Synchronous Buck Converters with PMBus™ and Frequency Synchronization
1 Features
3 Description
•
•
•
•
•
•
The TPS544x25 devices are PMBus 1.2 Compliant,
non-isolated DC-DC converters with integrated FETs,
capable of high-frequency operation and 20-A or 30-A
current output from a 5 mm × 7 mm package. Highfrequency, low-loss switching, provided by an
integrated NexFET™ power stage and optimized
drivers, allows for very high-density power solutions.
The PMBus interface enables the AVS through
VOUT_COMMAND, flexible converter configuration,
as well as key parameters monitoring including output
voltage, current and an optional external temperature.
Response to fault conditions can be set to either
restart, latch-off or ignore depending on system
requirements.
•
•
•
•
•
•
•
•
•
•
•
•
•
PMBus 1.2 Compliant Converters: 20 A and 30 A
Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.5 V to 5.5 V
5 mm × 7 mm LQFN Package
Single Thermal Pad
Integrated 5.5-mΩ and 2.0-mΩ Stacked
NexFET™ Power Stage
500-mV to 1500-mV Reference for Adapative
Voltage Scaling (AVS) and Margining through
PMBus
0.5% Reference Accuracy at 600 mV and Above
Lossless Low-Side MOSFET Current Sensing
Voltage Mode Control with Input Feed-Forward
Differential Remote Sensing
Monotonic Start-Up into Pre-Biased Output
Output Voltage and Output Current Reporting
External Temperature Monitoring with 2N3904
Transistor
Programmable via the PMBus interface
– VOUT_COMMAND and AVS VOUT Transition
Rate
– Overcurrent Protection with Thermal
Compensation
– UVLO, Soft-Start and Soft-Stop
– PGOOD, OV, UV, OT Levels
– Fault Responses
– Turn-On and Turn-Off Delays
Thermal Shutdown
Pin Strapping for Switching Frequency: 200 kHz to
1 MHz
Frequency Synchronization to an External Clock
Footprint Compatible 20-A, 30-A Converters
Device Information
DEVICE NAME
PACKAGE
BODY SIZE
TPS544B25RVFT
LQFN (40)
5.00 mm × 7.00 mm
TPS544C25RVFT
LQFN (40)
5.00 mm × 7.00 mm
.
.
Efficiency
100
95
90
Efficiency (%)
1
85
80
75
VOUT = 0.5
VOUT = 1.0
VOUT = 1.5
VOUT = 2.5
VOUT = 3.3
70
65
60
0
4
•
•
•
Test and Instrumentation
Ethernet Switches, Optical Switches, Routers,
Base Stations
Servers
Enterprise Storage SSD
High-Density Power Solutions
12
16
20
24
28
32
Load Current (A)
2 Applications
•
•
8
VIN = 12 V
No Snubber
L = 470 nH
fSW = 500 kHz
RDCR = 0.3mŸ
RBOOT = 0 Ÿ
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS544C25, TPS544B25
SLUSC81 – MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
8.5 Supported PMBus Commands ............................... 36
8.6 Register Maps ......................................................... 39
1
1
1
2
3
3
5
9
9.1 Application Information............................................ 77
9.2 Typical Applications ................................................ 77
10 Power Supply Recommendations ..................... 86
11 Layout................................................................... 87
11.1 Layout Guidelines ................................................. 87
11.2 Layout Example .................................................... 88
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 12
12 Device and Documentation Support ................. 90
12.1
12.2
12.3
12.4
12.5
12.6
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Applications and Implementation ...................... 77
18
18
19
36
Device Support ....................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
90
91
91
92
92
92
13 Mechanical, Packaging, and Orderable
Information ........................................................... 92
4 Revision History
2
DATE
REVISION
NOTES
May 2015
*
Initial release.
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5 Device Comparison Table
DEVICE NAME
CURRENT OPTION (A)
TPS544B25RVFR
20
TPS544B25RVFT
TPS544C25RVFR
30
TPS544C25RVFT
6 Pin Configuration and Functions
FB
DIFFO
COMP
TSNS/SS
PGOOD
SYNC/RESET_B
AGND
RT
RVF Package
40-Pin LQFN
(Top View)
40 39 38 37 36 35 34 33
1
32 VOUTSt
ADDR1 2
31 VOUTS+
ADDR0
3
30 VSET
DATA
4
29 VDD
CLK
5
28 BP6
SMBALERT
6
27 BP3
BOOT
7
26 PGND
SW
8
25 VIN
SW
9
24 VIN
SW 10
23 VIN
CNTL
SW 11
22 VIN
Thermal Tab
21 VIN
SW 12
GND
GND
GND
GND
GND
GND
GND
GND
13 14 15 16 17 18 19 20
Pin Functions
NAME
NO.
ADDR0
3
Sets low-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND.
DESCRIPTION
ADDR1
2
Sets high-order 3-bits of the PMBus address. Connect a resistor between this pin and AGND.
AGND
38
Analog ground return for controller device. Connect to GND at the thermal tab.
BP3
27
Output of the 3.3-V on-board regulator. This regulator powers the controller and should be bypassed with a
minimum of 2.2 µF to AGND. BP3 is not designed to power external circuit.
BP6
28
Output of the 6.5-V on-board regulator. This regulator powers the driver stage of the controller and should
be bypassed with a minimum of 2.2 µF to GND. TI recommends using an additional 100-nF typical bypass
capacitor for reduce ripple on BP6.
BOOT
7
Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this pin to the
SW pin.
CLK
5
PMBus CLK pin. See Supported PMBus Commands section.
CNTL
1
PMBus CNTL pin. See Supported PMBus Commands section. The CNTL pin has an internal pull-up and
floats high when left floating.
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Pin Functions (continued)
NAME
NO.
COMP
35
Output of the error amplifier. Connect compensator network from this pin to the FB pin.
DESCRIPTION
DATA
4
PMBus DATA pin. See Supported PMBus Commands section.
DIFFO
33
Output of the differential remote sense amplifier.
FB
34
Feedback pin for the control loop. Negative input of the error amplifier.
13
14
15
16
GND
17
Power stage ground return.
18
19
20
PGND
26
Power ground return for controller device. Connect to GND at the thermal tab.
PGOOD
36
Power good output. Open drain output that floats up when the device is operating and in regulation. Any
fault condition causes this pin to pull low. Please refer to Table 6 for the possible sources to pull down
PGOOD pin.
RT
40
Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching frequency.
Do not leave this pin floating.
SMBALERT
6
SMBus alert pin. See SMBus specification.
8
9
SW
10
Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this
group of pins.
11
12
SYNC/RESET_B
39
For switching frequency synchronization or output voltage reset. The SYNC function allows synchronizing
the oscillator to an external source that is either slower of faster than the nominal free running oscillator
frequency. To use the SYNC function, VSET pin should be pulled up to BP3 or set the FORCE_SYNC bit
in register MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) if VSET function is used; if
synchronization is not required, pull the SYNC pin to BP3. If the VSET pin is connected to AGND through a
valid resistor to configure default output voltage, SYNC/RESET_B is configured as RESET_B function
when FORCE_SYNC is not set. Then the logic low on the SYNC/RESET_B pin restores the output voltage
to default value set by VSET without power cycling. When SYNC/RESET_B is configured as RESET_B
function, there is an internal 200kΩ pull-up resistor to BP3.
TSNS/SS
37
External temperature sense signal input or alternatively used to set default soft-start time by connecting a
resistor from this pin to AGND. Do not leave this pin floating. Disable TSNS by pulling TSNS to AGND and
unsetting SS_DET_DIS in OPTIONS (MFR_SPECIFIC_21) (E5h) in applications where neither is needed.
VDD
29
Input power to the controller. Connect a low impedance bypass with a minimum of 1 µF to AGND. The
VDD voltage is also used for input feed-forward. VIN and VDD must be the same potential for accurate
short circuit protection.
21
22
VIN
23
Input power to the power stage. Low impedance bypassing of these pins to GND is critical.
24
25
VOUTS+
31
Load voltage sensing, positive side. This sensing provides remote sensing for the PMBus interface
reporting and the voltage control loop.
VOUTS–
32
Load voltage sensing, negative or common side. This sensing provides remote sensing for the PMBus
interface reporting and the voltage control loop.
VSET
30
Optionally configures default output voltage setting by connecting a resistor from this pin to AGND. See Set
Default Output Voltage by VSET for details. If VSET is not used, pull this pin up to BP3. Do not leave this
pin floating.
Thermal tab
4
Package thermal tab. Connect to GND. The thermal tab must have adequate solder coverage for proper
operation.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
VIN, VDD
–0.3
18
VIN, VDD
VOUT_UV_WARN_LIMIT, then the VOUT_UV_WARN_LIMIT value is set to VOUT_UV_FAULT_LIMIT (rounded)
+ 1 LSB.
For the case when VOUT_UV_FAULT_LIMIT = 0 (which indicates it is disabled), the VOUT_UV_WARN_LIMIT
default shall be the minimum value for the configured VOUT_SCALE_LOOP (179d/VOUT_SCALE_LOOP).
NOTE
Changing the VOUT_UV_WARN_LIMIT (or Fault, or OV Fault, or Warn limit) during
regulation causes a brief overshoot/undershoot on the output voltage. This is due to the
Vref DAC being shared with OVUV DAC.
8.6.21 VOUT_UV_FAULT_LIMIT (44h)
The VOUT_UV_FAULT_LIMIT command sets the value of the output voltage that causes an output undervoltage
fault. This fault is masked until the unit reaches the programmed output voltage. This fault is also masked when
the unit is disabled. Attempts to write values outside of the acceptable range is treated as invalid data, causing
the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers
as well as assert the SMBALERT signal. Additionally, the value of VOUT_UV_FAULT_LIMIT remains
unchanged. Maintaining values within “acceptable range” also means:
• 176d/VOUT_SCALE_LOOP < VOUT_UV_FAULT_LIMIT < VOUT_UV_WARN_LIMIT
A VOUT_UV_FAULT_LIMIT of 0000h shall be a means of disabling VOUT_UV_FAULT response and reporting
completely and is the only exception to the above “acceptable range” requirements. Disabling means that the unit
does not check for Vout_UVF faults; thus there is no setting of UVF status bits, nor associated SMBALERT
triggering. Disabling VOUT_UV_FAULT_LIMIT (by setting it to 0000h) has no bearing on
VOUT_UV_WARN_LIMIT checking – which is considered a completely separate function.
The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
Note the lower 4 bits can not be backed up in EEPROM.
The VOUT_UV_FAULT_LIMIT takes a two-byte data word formatted as shown below:
COMMAND
VOUT_UV_FAULT_LIMIT
Format
Linear, unsigned binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/w
r/w
r/w
r/w
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
Function
Default Value
Mantissa
0
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8.6.21.1 Exponent
Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in
VOUT_MODE command).
8.6.21.2 Mantissa
default: 0000 0001 0011 0000 (bin) 304(dec) (equivalent UVW 0.594 V or 62.5% of 0.95 V default reference
(VOUT_COMMAND))
•
•
NOTE
Changing the VOUT_UV_FAULT_LIMIT (or Warn, or OV Fault, or Warn limit) during
regulation causes a brief overshoot/undershoot on the output voltage. This is due to
the Vref DAC being shared with OVUV DAC.
Since the output undervoltage fault detection is masked until the unit reaches the
programmed output voltage, if the output voltage did not reach the programmed value
during the soft start time UPPER limit required by TON_MAX_FAULT_LIMIT, the
device
asserts
a
TON_MAX
fault
and
reponse
according
to
TON_MAX_FAULT_RESPONSE instead of VOUT_UV_FAULT_RESPONSE
8.6.22 VOUT_UV_FAULT_RESPONSE (45h)
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to a
VOUT_UV_FAULT_LIMIT fault. The device also:
• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the UVF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT
The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a output
undervoltage fault.
The default response to a output undervoltage fault is to shut down and restart with 7 × TON_RISE time delay.
COMMAND
VOUT_UV_FAULT_RESPONSE
Format
Unsigned binary
Bit Position
7
E
Access
Function
6
5
4
E
3
2
1
0
r/w
r
r/w
r/w
r/w
r
r
r
RSP[1]
0
RS[2]
RS[1]
RS[0]
X
X
X
1
0
1
1
1
1
1
1
Default Value
8.6.22.1 RSP[1]
This bit sets the output voltage under voltage response to either ignore or not. Default is 1.
0:
The PMBus device continues operation without interruption. Note: In this “ignore” fault response
mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if
it is not masked.
1:
The PMBus device shuts down and restarts according to RS[2:0].
8.6.22.2 RS[2:0]
These bits are output voltage under voltage retry setting. Default is 111b.
000:
54
A zero value for the Retry Setting means that the unit does not attempt to restart. The output
remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)
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111:
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A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)
continuously, without limitation, until it is commanded off or bias power is removed or another fault
condition causes the unit to shutdown.
Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing
the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in
STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.
8.6.23 IOUT_OC_FAULT_LIMIT (46h)
The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the
overcurrent detector to indicate an overcurrent fault condition. The IOUT_OC_FAULT_LIMIT should be set equal
to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than
IOUT_OC_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd)
bit in the STATUS_CML registers as well as assert the SMBALERT signal. The contents of this register can be
stored to non-volatile memory using the STORE_DEFAULT_ALL command.
The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as shown below:
COMMAND
IOUT_OC_FAULT_LIMIT
Format
Bit Position
Access
Linear, two's complement binary
7
r
Function
6
r
5
4
r
r
3
r
2
r
1
r
0
r
7
r
6
5
E
r/w
Exponent
4
E
3
E
r/w
r/w
2
E
r/w
1
E
r/w
0
E
r/wE
r/w
Mantissa
Default Value
See Below
8.6.23.1 Exponent
default: 11111 (bin) -1 (dec) (0.5 amps)
These default settings are not programmable.
8.6.23.2 Mantissa
The upper four bits are fixed at 0.
The lower seven bits are programmable.
The actual output current for a given mantissa and exponent is shown in Equation 6.
Mantissa
IOUT(oc) = Mantissa ´ 2Exponent =
2
(6)
The default values and allowable ranges for each device are summarized below:
DEVICE
OC_FAULT_LIMIT
UNIT
MIN
DEFAULT
MAX
TPS544C25
5
36
40
A
TPS544B25
5
24
36
A
8.6.24 IOUT_OC_FAULT_RESPONSE (47h)
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an
IOUT_OC_FAULT_LIMIT or a VOUT undervoltage (UV) fault. The device also:
• Sets the OCF bit in the STATUS_BYTE
• Sets the OCFW bit in the STATUS_WORD
• Sets the OCF bit in the STATUS_IOUT register, and
• Notifies the host by asserting SMBALERT
The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
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Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to an over current
fault.
The default response to an over current fault is to shut down and restart with 7 × TON_RISE time delay.
COMMAND
IOUT_OC_FAULT_RESPONSE
Format
Unsigned binary
Bit Position
7
6
E
Access
Function
5
4
E
3
2
1
0
r/w
r
r/w
r/w
r/w
r
r
r
RSP[1]
0
RS[2]
RS[1]
RS[0]
X
X
X
1
0
1
1
1
1
1
1
Default Value
8.6.24.1 RSP[1]
This bit sets the over current fault response to either ignore or not. Default is 1.
0:
The PMBus device continues operation without interruption. Note: In this “ignore” fault response
mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if
it is not masked.
1:
The PMBus device shuts down and restarts according to RS[2:0].
8.6.24.2 RS[2:0]
These bits are over current fault retry setting. Default is 111b.
000:
A zero value for the Retry Setting means that the unit does not attempt to restart. The output
remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)
111:
A one value for the Retry Setting means that the unit goes through a normal startup (soft-start)
continuously, without limitation, until it is commanded off or bias power is removed or another fault
condition causes the unit to shutdown.
Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing
the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in
STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.
8.6.25 IOUT_OC_WARN_LIMIT (4Ah)
The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an over-current warning. When this current level is exceeded the device:
• Sets the oth bit in the STATUS_BYTE
• Sets the OCFW bit in the STATUS_WORD
• Sets the OCW bit in the STATUS_IOUT register, and
• Notifies the host by asserting SMBALERT
The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the
IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT
causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML
registers as well as assert the SMBALERT signal.
The default IOUT_OC_WARN_LIMIT is always set to fixed, relative IOUT_OC_FAULT_LIMIT - 2 A. Since the
IOUT_OC_WARN_LIMIT is not stored in EEPROM, the IOUT_OC_WARN_LIMIT register is set to 2 A less than
the stored IOUT_OC_FAULT_LIMIT upon any RESTORE from EEPROM.
The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as shown below:
COMMAND
IOUT_OC_WARN_LIMIT
Format
Linear, two's complement binary
Bit Position
56
7
6
5
4
3
2
1
0
7
6
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5
4
3
2
1
0
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COMMAND
Access
IOUT_OC_WARN_LIMIT
r
r
Function
r
r
r
r
r
r
r
r/w
Exponent
r/w
r/w
r/w
r/w
r/w
r/w
Mantissa
Default Value
See Below
8.6.25.1 Exponent
default: 11111 (bin) -1 (dec) (0.5 amps)
These default settings are not programmable.
8.6.25.2 Mantissa
The upper four bits are fixed at 0.
Lower seven bits are programmable.
The actual output warning current level for a given mantissa and exponent is:
Mantissa
2
IOUT (OCW ) = Mantissa × 2Exponent =
(7)
The default values and allowable ranges for each device are summarized below:
OC_WARN_LIMIT
DEVICE
MIN
DEFAULT
MAX
TPS544C25
4
34
39.5
TPS544B25
4
22
35.5
UNIT
A
8.6.26 OT_FAULT_LIMIT (4Fh)
The OT_FAULT_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an overtemperature fault condition, when the sensed temperature from the external sensor exceeds this limit.
The OT_FAULT_LIMIT must always be greater than the OT_WARN_LIMIT. Writing a value to OT_FAULT_LIMIT
less than or equal to OT_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the
invalid data (ivd) bit in the STATUS_CML registers as well as asserts the SMBALERT signal. The contents of
this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
The OT_FAULT_LIMIT takes a two byte data word formatted as shown below.
COMMAND
OT_FAULT_LIMIT
Format
Linear, two's complement binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
0
0
0
0
0
0
0
0
1
1
1
1
0
1
Function
Default Value
Exponent
0
Mantissa
1
8.6.26.1 Exponent
default: 00000 (bin) 0 (dec) (represents mantissa with steps of 1 degree Celcius)
These default settings are not programmable.
8.6.26.2 Mantissa
default: 000 0111 1101 (bin) 125 (dec) (125 °C)
Minimum : 000 0111 1000 (bin) (equivalent OTF = 120 °C)
Maximum: 000 1010 0101 (bin) (equivalent OTF = 165 °C)
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8.6.27 OT_FAULT_RESPONSE (50h)
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an
OT_FAULT_LIMIT. The device also:
• Sets the OTFW bit in the STATUS_BYTE
• Sets the OTF bit in the STATUS_TEMPERATURE
• Notifies the host by asserting SMBALERT
Once the over-temperature fault is tripped, the fault flag is latched until the external sensed temperature falls
20°C from the OT_FAULT_LIMIT.
The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to an over
temperature fault.
The default response to an over current fault is to shut down and restart with 7 × TON_RISE time delay.
COMMAND
OT_FAULT_RESPONSE
Format
Unsigned binary
Bit Position
7
E
Access
Function
6
5
4
E
3
2
1
0
r/w
r
r/w
r/w
r/w
r
r
r
RSP[1]
0
RS[2]
RS[1]
RS[0]
X
X
X
1
0
1
1
1
1
1
1
Default Value
8.6.27.1 RSP[1]
This bit sets the over temperature fault response to either ignore or not. Default is 1.
0:
The PMBus device continues operation without interruption. Note: In this “ignore” fault response
mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if
it is not masked.
1:
The PMBus device shuts down and restarts according to RS[2:0].
8.6.27.2 RS[2:0]
These bits are over temperature fault retry setting. Default is 111b.
000:
A zero value for the Retry Setting means that the unit does not attempt to restart. The output
remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)
111:
A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)
continuously, without limitation, until it is commanded off or bias power is removed or another fault
condition causes the unit to shutdown.
Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing
the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in
STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.
NOTE
The programmed response here is also applied to internally detected Over Temperture
faults – with the one exception of the “ignore” response. Internal OT faults are never
ignored. Internal OT faults always respond in a shutdown and attempted re-start once the
part cools.
8.6.28 OT_WARN_LIMIT (51h)
The OT_ WARN _LIMIT command sets the value of the temperature, in degrees Celsius, that causes an overtemperature warning condition, when the sensed temperature from the external sensor exceeds this limit. Upon
triggering the over-temperature warning, the device takes the following actions:
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Sets the TEMPERATURE bit in the STATUS_BYTE
Sets the OT Warning bit in the STATUS_TEMPERATURE
Notifies the host by asserting SMBALERT
Once the over-temperature warning is tripped, the warning flag is latched until the external sensed temperature
falls 20°C from the OT_WARN_LIMIT.
The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT
greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the
invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal.
The default OT_WARN_LIMIT is mathematically derived from the EEPROM backed OTF limit by subtracting 25
from (4Fh) OT_FAULT_LIMIT to reach the default OT_WARN_LIMIT. If the calculated OTW is less than 100 °C,
then the default value is set to 100 °C. OTW=max(OTF-25, 100)
The OT_WARN_LIMIT takes a two byte data word formatted as shown below:
COMMAND
OT_WARN_LIMIT
Format
Unsigned binary
Bit Position
7
6
Access
r
r
Function
5
4
3
2
1
0
7
6
r
r
r
r
r
r
r/w
r/w
Exponent
Default Value
0
0
0
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
1
0
1
0
0
Mantissa
0
0
0
0
0
0
1
1
8.6.28.1 Exponent
default: 00000 (bin) 0 (dec) (represents mantissa with steps of 1 degree Celcius)
These default settings are not programmable.
8.6.28.2 Mantissa
default: 000 0110 0100 (bin) 100 (dec) (100 °C) 25°C less than default OTF
Minimum : 000 0110 0100 (bin) (equivalent OTF = 100°C)
Maximum: 000 1000 1100 (bin) (equivalent OTF = 140°C)
8.6.29 TON_DELAY (60h)
The TON_DELAY command sets the time in milliseconds, from when a start condition is received to when the
output voltage starts to rise. The contents of this register can be stored to non-volatile memory using the
STORE_DEFAULT_ALL command.
The TON_DELAY command is formatted as a linear mode two’s complement binary integer.
COMMAND
TON_DELAY
Format
Linear, two's complement binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
0
0
0
0
Function
Default Value
Exponent
0
0
0
Mantissa
0
0
0
0
0
0
0
0
0
8.6.29.1 Exponent
default: 00000 (bin) 0 (dec) (1 millisecond)
These default settings are not programmable.
8.6.29.2 Mantissa
The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0000
(bin) (0 ms).
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Only 16 fixed TON_DELAY times are available in the device. As such, the range of programmed TON_DELAY
settings are sub-divided into 16 “buckets” that then selects one of the 16 supported times. Programmed values
are rounded to the nearest “bucket/transition rate” as outlined in the table Supported TON_DELAY Values:
Table 11. Supported TON_DELAY Values
EFFECTIVE
TON_DELAY
(ms)
PROGRAMMED TON_DELAY MANTISSA (dec)
Greater than
Less than or equal to
0 (50 us)
0
1
0
1
2
1
2
3
2
3
4
3
4
5
4
5
6
5
6
7
6
9
10
9
12
14
12
17
19
17
22
27
22
32
37
32
44
52
44
62
72
62
86
100
86
8.6.30 TON_RISE (61h)
The TON_RISE command sets the time in milliseconds, from when the reference starts to rise until the voltage
has entered the regulation band. The contents of this register can be stored to non-volatile memory using the
STORE_DEFAULT_ALL command.
Programming a value of 0 instructs the unit to bring its output voltage to the programmed regulation value as
quickly as possible. For TPS544x25, this results in an effective TON_RISE time of 1ms (fastest time supported).
If the Soft-Start Detection feature is being used (bit in MFR_??), then the Mantissa value decoded or derived by
from the appropriate SS resistor writes into the TON_RISE register as the initial default. Note: This write
overwrites any value restored from the EEPROM restore operation at initial power-up.
TON_RISE should always be set less than the TON_MAX_FAULT_LIMIT. Attempting to write a value to
TON_RISE greater than TON_MAX_FAULT_LIMIT is not accepted and causes the device to set the ’cml’ bit in
the STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers and asserts the SMBALERT signal.
There is one exception to this rule: when TON_MAX_FAULT_LIMIT is set to 0. This indicates that the
TON_MAX_FAULT timer is disabled, which means that there is no limit and that the unit can attempt to bring up
the output voltage indefinitely. If TON_MAX_FAULT_LIMIT = 0 (disabled), the relational cross check against
TON_MAX_FAULT_LIMIT is also disabled.
The TON_RISE command is formatted as a linear mode two’s complement binary integer.
COMMAND
TON_RISE
Format
Linear, two's complement binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
0
0
0
0
0
0
0
0
0
0
1
0
1
Function
Default Value
60
Exponent
0
Mantissa
0
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8.6.30.1 Exponent
default: 00000 (bin) 0 (dec) (1 millisecond)
These default settings are not programmable.
8.6.30.2 Mantissa
The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0101
(bin) (5 ms).
The supported TON_RISE times over PMBus are shown in Table 12:
Table 12. Supported TON_RISE Values
Effective
TON_RISE (ms)
Programmed TON_RISE Mantissa (d)
Greater than
Less than or equal to
1
1
2
1
2
3
2
3
4
3
4
5
4
5
6
5
6
7
6
9
10
9
12
14
12
17
19
17
22
27
22
32
37
32
44
52
44
62
72
62
86
100
86
8.6.31 TON_MAX_FAULT_LIMIT (62h)
The TON_MAX_FAULT_LIMIT command sets an UPPER limt in milliseconds, on how long the unit can attempt
to power up the output without reaching the output undervoltage fault limit. The time begins counting as soon as
the device enters the soft-start state begins to ramp the output. In other words, the TON_MAX_FAULT_LIMIT
timer starts at the beginning of the TON_RISE state.
The TON_MAX_FAULT_LIMIT should always be set greater than the TON_RISE. Attempting to write a value to
TON_MAX_FAULT_LIMIT less than TON_RISE is not accepted and causes the device to set the ’cml’ bit in the
STATUS_BYTE and the ‘ivd’ bit in the STATUS_CML registers and asserts the SMBALERT signal.
There is one exception to this rule: when TON_MAX_FAULT_LIMIT is set to 0. This setting indicates that the
TON_MAX_FAULT timer is disabled, which means that there is no limit and that the unit can attempt to bring up
the output voltage indefinitely. If TON_MAX_FAULT_LIMIT = 0 (disabled), the relational cross check against
TON_MAX_FAULT_LIMIT is also disabled.
The TON_MAX_FAULT_LIMIT command is formatted as a linear mode two’s complement binary integer.
COMMAND
TON_MAX_FAULT_LIMIT
Format
Linear, two's complement binary
Bit Position
7
6
Access
r
r
Function
Default Value
5
4
3
2
1
0
7
6
r
r
r
r
r
r
r
r/w
Exponent
0
0
0
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
0
0
1
0
0
Mantissa
0
0
0
0
0
0
1
1
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8.6.31.1 Exponent
default: 00000 (bin) 0 (dec) (1 millisecond)
These default settings are not programmable.
8.6.31.2 Mantissa
The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0110 0100
(bin) (100 ms).
Even though this register is not EEPROM backed, a RESTORE_DEFAULT_ALL command causes the
TON_MAX_FAULT_LIMIT to restore to the default 100 ms value.
The supported TON_MAX_FAULT_LIMIT times over PMBus are shown in Supported TON_MAX_FAULT_LIMIT
Values:
Table 13. Supported TON_MAX_FAULT_LIMIT Values
Effective
TON_MAX_FAUL
T_LIMIT (ms)
Programmed TON_MAX_FAULT_LIMIT Mantissa (d)
Greater than
Less than or equal to
No Limit (timer
disabled)
0
1
0
1
2
1
2
3
2
3
4
3
4
5
4
5
6
5
6
7
6
9
10
9
12
14
12
17
19
17
22
27
22
32
37
32
44
52
44
62
72
62
86
100
86
8.6.32 TON_MAX_FAULT_RESPONSE (63h)
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to an
TON_MAX_FAULT_LIMIT.
The device also:
• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the TONMAXF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT
The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
Bits [2:0] are hard-wired to 0x7 (111b) to indicate the 7 × TON_RISE time delay in response to a
TON_MAX_FAULT.
The default response to a TON_MAX_FAULT is to shut down and restart with 7 × TON_RISE time delay.
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COMMAND
TON_MAX_FAULT_RESPONSE
Format
Unsigned binary
Bit Position
Access
Function
7
6
5
4
3
2
1
r/wE
r
r/wE
r/w
r/w
r
r
r
RSP[1]
0
RS[2]
RS[1]
RS[0]
X
X
X
1
0
1
1
1
1
1
1
Default Value
0
8.6.32.1 RSP[1]
This bit sets the TON_MAX_FAULT response to either ignore or not. Default is 1.
0:
The PMBus device continues operation without interruption. Note: In this “ignore” fault response
mode, the associated fault status bits are set. Additionally, SMBALERT continues to be triggered if
it is not masked.
1:
The PMBus device shuts down and restarts according to RS[2:0].
8.6.32.2 RS[2:0]
These bits are TON_MAX_FAULT retry setting. Default is 111b.
000:
A zero value for the Retry Setting means that the unit does not attempt to restart. The output
remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.)
111:
A one value for the Retry Setting means that the unit goes through a normal startup (Soft start)
continuously, without limitation, until it is commanded off or bias power is removed or another fault
condition causes the unit to shutdown.
Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing
the device to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in
STATUS_CML. Note, that since all 3 bits must be the same, only one (bit 5) is stored in EEPROM.
8.6.33 TOFF_DELAY (64h)
The TOFF_DELAY command sets the time in milliseconds, from when a stop condition is received and when the
output voltage starts to fall. The contents of this register can be stored to non-volatile memory using the
STORE_DEFAULT_ALL command.
The TOFF_DELAY command is formatted as a linear mode two’s complement binary integer.
COMMAND
TOFF_DELAY
Format
Linear, two's complement binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
0
0
0
0
Function
Default Value
Exponent
0
0
0
Mantissa
0
0
0
0
0
0
0
0
0
8.6.33.1 Exponent
default: 00000 (bin) 0 (dec) (1 millisecond)
These default settings are not programmable.
8.6.33.2 Mantissa
The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0000
(bin) (0 ms).
Only 16 fixed TOFF_DELAY times are available in the device. As such, the range of programmed TOFF_DELAY
settings are sub-divided into 16 “buckets” that then selects one of the 16 supported times. Programmed values
are rounded to the nearest “bucket/transition rate” as outlined in the table Supported TOFF_DELAY Values:
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Table 14. Supported TOFF_DELAY Values
EFFECTIVE
TOFF_DELAY
(ms)
PROGRAMMED TOFF_DELAY MANTISSA (dec)
Greater than
Less than or equal to
0
0
1
0
1
2
1
2
3
2
3
4
3
4
5
4
5
6
5
6
7
6
9
10
9
12
14
12
17
19
17
22
27
22
32
37
32
44
52
44
62
72
62
86
100
86
8.6.34 TOFF_FALL (65h)
The TOFF_FALL command sets the time in ms, from the end of the TOFF_DELAY time until the voltage reaches
0 V. The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL
command.
Programming a value of 0 instructs the unit to bring its output voltage down to 0 as quickly as possible. For
TPS544x25, this results in actively ramping down the output voltage in 1 ms (the fastest supported ramp down).
The TOFF_FALL command is formatted as a linear mode two’s complement binary integer.
COMMAND
TOFF_FALL
Format
Linear, two's complement binary
Bit Position
Access
7
6
r
r
0
0
Function
Default Value
5
r
4
3
2
1
0
7
6
r
r
r
r
r
r
r/w
0
0
0
0
0
0
0
Exponent
0
5
E
4
E
3
E
r/w
r/w
2
E
1
E
0
E
r/w
r/w
r/w
r/wE
0
0
0
0
Mantissa
0
0
8.6.34.1 Exponent
default: 00000 (bin) 0 (dec) (1 millisecond)
These default settings are not programmable.
8.6.34.2 Mantissa
The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 000 0000 0000
(bin) (0 ms).
The supported TOFF_FALL times over PMBus are shown in Supported TOFF_FALL Values:
Table 15. Supported TOFF_FALL Values
Effective
TOFF_FALL (ms)
Programmed TOFF_FALL Mantissa (d)
Greater than
64
Less than or equal to
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Table 15. Supported TOFF_FALL Values (continued)
Effective
TOFF_FALL (ms)
Programmed TOFF_FALL Mantissa (d)
1
1
2
1
2
3
2
3
4
3
4
5
4
5
6
5
6
7
6
9
10
9
12
14
12
17
19
17
22
27
22
32
37
32
44
52
44
62
72
62
86
100
86
8.6.35 STATUS_BYTE (78h)
The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults.
COMMAND
STATUS_BYTE
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
Function
X
OFF
OVF
OCF
X
OTFW
CML
oth
Default Value
0
X
0
0
0
0
0
1
A "1" in any of these bit positions indicates that:
OFF:
The device is not providing power to the output, regardless of the reason. In this family of devices,
this flag means that the converter is not enabled.
OVF:
An output overvoltage fault has occurred. This bit directly reflects the state of STATUS_VOUT[7] –
OVF. If the user wants this fault sourc to be masked and not trigger SMBALERT, they must do it by
masking STATUS_VOUT[7]. Per the PMBus v1.2 spec sections 10.2.4 and 10.2.5, this bit is not
clearable via a PMBus write. In contast, the bit is to be cleared by clearing the bit(s) in
STATUS_VOUT that cause this bit to be set.
OCF:
An output over current fault has occurred. This bit directly reflect the state of STATUS_IOUT[7] –
OCF. If the user wants this fault sourced to be masked and not trigger SMBALERT, they must do it
by masking STATUS_IOUT[7]. Per the PMBus v1.2 spec sections 10.2.4 and 10.2.5, this bit is not
clearable via a PMBus write. In contrast, the bit is to be cleared by clearing the bit(s) in
STATUS_IOUT that cause this bit to be set.
OTFW:
A temperature fault or warning has occurred. Check STATUS_TEMPERATURE. Per the PMBus
v1.2 spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is
to be cleared by clearing the bit(s) in STATUS_TEMPERATURE that cause this bit to be set.
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CML:
A Communications, Memory or Logic fault has occurred. Check STATUS_CML. Per the PMBus v1.2
spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to
be cleared by clearing the bit(s) in STATUS_CML that cause this bit to be set.
oth:
A fault or warning not listed through bits 1-7 has occurred, for example an undervoltage condition or
an over current warning condition. Check other status registers. Per the PMBus v1.2 spec sections
10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to be cleared by
clearing the bit(s) in STATUS_VOUT and STATUS_IOUT that cause this bit to be set. The default
for this bit is 1 because the default of STATUS_INPUT[3] LOW_Vin defaulting to 1.
8.6.36 STATUS_WORD (79h)
The STATUS_WORD command returns two bytes of information with a summary of the device fault and warning
conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning
conditions for output overvoltage and overcurrent, as well as the power good status of the converter.
COMMAND
STATUS_WORD (low byte) = STATUS_BYTE
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
Access
r
r
r
r
r
r
r
r
Function
X
OFF
OVF
OCF
x
OTFW
CML
oth
Default Value
0
X
0
0
0
0
0
1
COMMAND
0
STATUS_WORD (high byte)
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
Access
r
r
r
r
rE
r
r
r
VFW
OCFW
INPUT
MFR
PGOOD_Z
X
X
X
0
0
X
0
X
0
0
0
Function
Default Value
0
A "1" in any of the high byte bit positions indicates that:
VFW:
An output voltage fault or warning has occurred (OVF or OVW or UVW or UVF or
VOUT_MAX_Warning or TONMAXF). Check STATUS_VOUT. Per the PMBus v1.2 spec sections
10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to be cleared by
clearing the bit(s) in STATUS_VOUT that cause this bit to be set.
OCFW:
An output current warning or fault has occurred (OCF or OCW). Check STATUS_IOUT. Per the
PMBus v1.2 spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast,
the bit is to be cleared by clearing the bit(s) in STATUS_IOUT that cause this bit to be set.
INPUT:
INPUT fault or warning in STATUS_INPUT is present. Check STATUS_INPUT. Per the PMBus v1.2
spec sections 10.2.4 and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to
be cleared by clearing the bit(s) in STATUS_INPUT that cause this bit to be set.
MFR:
An manufacturer specific fault/warning condition has occurred (Internal over temperature fault or
VOUT_MIN_Warning). Check STATUS_MFR_SPECIFIC. Per the PMBus v1.2 spec sections 10.2.4
and 10.2.5, this bit is not clearable via a PMBus write. In contast, the bit is to be cleared by clearing
the bit(s) in STATUS_MFR_SPECIFIC that cause this bit to be set.
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PGOOD_Z:
Power is Not Good, and the following condition is present: output over or under voltage warning or
fault, TON_MAX_FAULT, over temperature warning or fault, over current warning or fault,
insufficient input voltage. Please refer to the FAULT RESPONSE table for the possible sources to
trigger PGOOD_Z. The signal is unlatched and always represents the current state of the device.
Unless masked, it triggers SMBALERT; however, the default for this mask bit is 1, indicating that
PGOOD_z cannot trigger SMBALERT by default. The user must clear the associated
SMBALERT_MASK bit if SMBALERT triggering is desired for this condition.
8.6.37 STATUS_VOUT (7Ah)
The STATUS_VOUT command returns one byte of information relating to the status of the output voltage related
faults.
COMMAND
STATUS_VOUT
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
0
Access
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r
r
Function
OVF
OVW
UVW
UVF
X
X
0
0
0
0
0
0
Default Value
VOUT_MA
TONMAXF
X_Warning
0
0
A "1" in any of these bit positions indicates that:
OVF:
The device has seen the output voltage rise above the output overvoltage fault threshold
VOUT_OV_FAULT_LIMIT. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK.
OVW:
The device has seen the output voltage rise above the output overvoltage warn threshold
VOUT_OV_WARN_LIMIT. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK.
UVW:
The device has seen the output voltage fall below the output undervoltage warn threshold
VOUT_UV_WARN_LIMIT. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK.
UVF:
The device has seen the output voltage fall below the output undervoltage fault threshold
VOUT_UV_FAULT_LIMIT. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK.
VOUT_MAX_Warning:
An attempt is made to program the VOUT_COMMAND in excess of the value in VOUT_MAX. This
bit is writeable to clear and the EEPROM bit is for SMBALERT_MASK.
TONMAXF:
A TON_MAX_FAULT has occurred. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK.
8.6.38 STATUS_IOUT (7Bh)
The STATUS_IOUT command returns one byte of information relating to the status of the output current related
faults.
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COMMAND
STATUS_IOUT
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
Access
r/wE
r
r/wE
r
r
r
r
r
Function
OCF
X
OCW
X
X
X
X
X
0
0
0
0
0
0
0
0
Default Value
0
A "1" in any of these bit positions indicates that:
OCF:
The device has seen the output current rise above the level set by IOUT_OC_FAULT_LIMIT. This
bit is writeable to clear and the EEPROM bit is for SMBALERT_MASK.
OCW:
The device has seen the output current rise above the level set by IOUT_OC_WARN_LIMIT. This bit
is writeable to clear and the EEPROM bit is for SMBALERT_MASK.
8.6.39 STATUS_INPUT (7Ch)
The STATUS_INPUT command returns one byte of information relating to the status of the converter's input
related faults.
COMMAND
STATUS_INPUT
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
0
Access
r
r
r
r
r/wE
r
r
r
Function
X
X
X
X
LOW_Vin
X
X
X
Default Value
0
0
0
0
0
0
0
0
A "1" in any of these bit positions indicates that:
LOW_Vin:
The unit is Off due to insufficient input voltage. The bit sets when the unit powers up and stays set
until the first time VIN exceeds VIN_ON. During the initial power up, LOW_Vin is not latched and
does not trigger SMBALERT. Once VIN does exceed VIN_ON for the first time, any subsequent VIN
< VIN_OFF events are latched, trigger SMBALERT. This bit is writeable to clear and the EEPROM
bit is for SMBALERT_MASK.
8.6.40 STATUS_TEMPERATURE (7Dh)
The STATUS_TEMPERATURE command returns one byte of information relating to the status of the external
temperature related faults.
COMMAND
STATUS_TEMPERATURE
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
Access
r/wE
r/wE
r
r
r
r
r
r
Function
OTF
OTW
X
X
X
X
X
X
0
0
0
0
0
0
0
0
Default Value
0
A "1" in any of these bit positions indicates that:
OTF:
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The measured external temperature value of READ_TEMPERATURE_2 is equal to or greater than
the level set by OT_FAULT_LIMIT. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK. However, once cleared, the bit is set again unless the value in
READ_TEMPERATURE_2 has fallen 20°C from the OT_FAULT_LIMIT.
OTW:
The measured external temperature value of READ_TEMPERATURE_2 is equal to or greater than
the level set by OT_WARN_LIMIT. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK. However, once cleared, the bit is set again unless the value in
READ_TEMPERATURE_2 has fallen 20°C from the OT_WARN_LIMIT.
8.6.41 STATUS_CML (7Eh)
The STATUS_CML command returns one byte of information relating to the status of the converter’s
communication related faults.
COMMAND
STATUS_CML
Format
Unsigned binary
Bit Position
Access
Function
Default Value
7
6
5
4
3
2
1
0
r/wE
r/wE
r/wE
r/wE
r
r
r/wE
r
ivc
ivd
pec
mem
X
X
oth
X
0
0
0
0
0
0
0
0
A "1" in any of these bit positions indicates that:
ivc:
An invalid or unsupported command has been received. This bit is writeable to clear and the
EEPROM bit is for SMBALERT_MASK.
ivd:
An invalid or unsupported data has been received. This bit is writeable to clear and the EEPROM bit
is for SMBALERT_MASK.
pec:
A Packet Error Check failed. This bit is writeable to clear and the EEPROM bit is for
SMBALERT_MASK.
mem:
A fault has been detected with the internal memory. This bit is writeable to clear and the EEPROM
bit is for SMBALERT_MASK.
oth:
Some other communication fault or error has occurred. This bit is writeable to clear and the
EEPROM bit is for SMBALERT_MASK.
8.6.42 STATUS_MFR_SPECIFIC (80h)
The STATUS_MFR_SPECIFIC command returns one byte of information relating to the status of manufacturerspecific faults or warnings.
COMMAND
STATUS_MFR_SPECIFIC
Format
Bit Position
Unsigned binary
7
6
5
4
3
2
1
0
Access
r/wE
r
r
r/w
r/w
r
r/wE
r
Function
otfi
illzero
illmany1s
iv_vset
iv_ss
reset_ VOUT_MIN_Wa
vout
rning
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COMMAND
STATUS_MFR_SPECIFIC
Default Value
0
0
0
0
0
0
0
0
A "1" in any of these bit positions indicates that:
otfi:
The internal temperature is above the thermal shutdown (TSD) fault threshold. This bit is writeable to
clear and the EEPROM bit is for SMBALERT_MASK.
illzero:
The operation FSM has hit an illegal “ZERO” state. The FSM is a one-hot implementation, so all
zeros in the state is illegal and should never occur. This event is informational only and would not
trigger SMBALERT.
illmany1s:
The operation FSM for has hit an illegal “more than one hot” state. The FSM is a one-hot
implementation, so a state where multiple state bits are HI is illegal and should never occur. This
event is informational only and would not trigger SMBALERT.
iv_vset:
the VSET detection results in an “illegal high”. This condition is intended as “information only” - and
does not trigger SMBALERT. To avoid initial turn-on events from clearing this condition and the user
not being aware why the default vset value was used, this bit is only clearable via the
CLEAR_FAULTS command or writing a logic 1 to this bit. Off and on events do not clear it as with
the other, standard status bits.
iv_ss:
the TON_RISE/SS detection results in an “illegal low” or an “illegal high”. This condition is intended
as “information only” - and does not trigger SMBALERT. To avoid initial turn-on events from clearing
this condition and the user not being aware why the default vset value was used, this bit is only
clearable via the CLEAR_FAULTS command or writing a logic 1 to this bit. Off and on events do not
clear it as with the other, standard status bits.
reset_vout:
The SYNC/RESET_B pin voltage is low and the device is requested to reset the output voltage to
the initial boot-up voltage set by VSET resistor. This event is informational only and would not trigger
SMBALERT.
VOUT_MIN_Warning:
an attempt is made to program the output voltage below the value in (A4h) MFR_VOUT_MIN. This
bit is writeable to clear and the EEPROM bit is for SMBALERT_MASK.
8.6.43 READ_VOUT (8Bh)
The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage
of the controller. The output voltage is sensed at the remote sense amplifier output pin so voltage drop to the
load is not accounted for. The data format is as shown below:
COMMAND
READ_VOUT
Format
Linear, two's complement binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
Default Value
70
Mantissa
0
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8.6.43.1 Exponent
Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in
VOUT_MODE command).
8.6.43.2 Mantissa
The output voltage calculation is shown below.
VOUT = Mantissa ´ 2Exponent
(8)
8.6.44 READ_IOUT (8Ch)
The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current
of the converter. The average output current is sensed according to the method described in Low-Side MOSFET
Current Sensing and Overcurrent Protection. The data format is as shown below:
COMMAND
READ_IOUT
Format
Linear, two's complement binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
Function
Default Value
Exponent
1
1
1
Mantissa
0
0
0
0
0
0
0
0
The device scales the output current before it reaches the internal analog to digital converter so that resolution of
the output current read is 62.5 mA. The maximum value that can be reported is 40 A. The user must set the
IOUT_CAL_OFFSET parameter correctly in order to obtain accurate results. Calculate the output current using
Equation 9.
IOUT = Mantissa ´ 2Exponent
(9)
8.6.44.1 Exponent
default: 11100 (bin) -4 (dec) (62.5 mA lsb)
These default settings are not programmable.
8.6.44.2 Mantissa
The lower 10 bits are the result of the ADC conversion of the average output current, as indicated by the output
of the internal current sense amplifier. The 11th bit is fixed at 0 because only positive numbers are considered
valid. Any computed negative current is reported as 0 A.
8.6.45 READ_TEMPERATURE_2 (8Eh)
The READ_TEMPERATURE_2 command returns the external temperature in degrees Celsius.
COMMAND
READ_TEMPERATURE_2
Format
Linear, two's complement binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
1
1
0
0
1
Function
Default Value
Exponent
0
Mantissa
0
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8.6.45.1 Exponent
default: 00000 (bin) 0 (dec)
These default settings are not programmable.
8.6.45.2 Mantissa
The lower 11 bits are the result of the ADC conversion of the external temperature.
The default reading is 000 00011001 (bin) 25 (dec), corresponding to a temperature of 25°C.
NOTE
The READ_TEMPERATURE_2 (8Eh) value remains at 25°C when SS_DET_DIS in
OPTIONS (MFR_SPECIFIC_21) (E5h) is set to 0 since the TSNS/SS pin is configured to
set TON_RISE time and not used for external temperature sensing.
8.6.46 PMBUS_REVISION (98h)
The PMBUS_REVISION command returns a single, unsigned binary byte that indicates that these devices are
compatible with the 1.2 revision of the PMBus™ specification.
COMMAND
PMBUS_REVISION
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
Access
r
r
r
r
r
r
r
0
r
Default Value
0
0
0
1
0
0
1
0
8.6.47 MFR_VOUT_MIN (A4h)
The MFR_VOUT_MIN command sets the minimum output voltage. The purpose is to protect the device(s) on the
output rail supplied by this device from a lower than acceptable output voltage. MFR_VOUT_MIN imposes a
lower bound to any attempted output voltage setting:
• programmed VOUT_COMMAND
• VSET pin default
If any attempt is made to program the output voltage (using the VOUT_COMMAND ) below the value in
MFR_VOUT_MIN, the device also:
• Clamps the output voltage at the programmed MFR_VOUT_MIN value
• Sets the oth (other) bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD
• Sets the VOUT_MIN_Warning bit in the STATUS_MFR_SPECIFIC register, and
• Notifies the host via the SMBALERT pin.
The exponent is set by VOUT_MODE at –9 (equivalent of 1.953 mV/count). The programmed output voltage is
computed as:
Minimum VOUT allowed = MFR_VOUT_MIN × VOUT_MODE (V) = MFR_VOUT_MIN × 2-9 (V)
(10)
There are 2 “invalid data” situations that are possible and checked in hardware. They are handled differently:
• If the commanded MFR_VOUT_MIN is outside the valid data range for the VOUT_SCALE_LOOP configured,
but, is still relationally correct (below VOUT_COMMAND), then that value is not accepted; but,
MFR_VOUT_MIN is set to the lowest allowed value.
• The second case is the opposite, where the attempted write value is within the absolute range of
MFR_VOUT_MIN; but, is not relationally correct (it is above VOUT_COMMAND). In this case, the
MFR_VOUT_MIN remains unchanged.
Both cases equally cause the device to set the ’cml’ bit in the STATUS_BYTE and the ‘ivd’ bit in the
STATUS_CML registers, and triggers SMBALERT signal.
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COMMAND
MFR_VOUT_MIN
Format
Linear, unsigned binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Mantissa
8.6.47.1 Exponent
Value fixed at 10111, Exponent for Linear mode values is –9 (equivalent of 1.95mV/count, specified in
VOUT_MODE command).
8.6.47.2 Mantissa
The range of valid MFR_VOUT_MIN values is dependent upon the configured (29h) VOUT_SCALE_LOOP as
follows.
If VOUT_SCALE_LOOP = 1:
• default: 0000 0001 0000 0000 (bin) 256 (dec) (equivalent Vout default = 0.5V)
• Minimum : 0000 0001 0000 0000 (bin) 256 (dec) (equivalent VOUT_MAX = 0.5V)
• Maximum: 0000 0010 1110 0110 (bin) 742 (dec) (equivalent VOUT_MAX = 1.45V)
If VOUT_SCALE_LOOP = 0.5:
• default: 0000 0010 0000 0000 (bin) 512 (dec) (equivalent Vout default = 1V)
• Minimum : 0000 0010 0000 0000 (bin) 512 (dec) (equivalent VOUT_MIN = 1V)
• Maximum: 0000 0101 1100 1100 (bin) 1484 (dec) (equivalent VOUT_MIN = 2.9V)
If VOUT_SCALE_LOOP = 0.25:
• default: 0000 0100 0000 0000 (bin) 1024 (dec) (equivalent Vout default = 2V)
• Minimum : 0000 0100 0000 0000 (bin) 1024 (dec) (equivalent VOUT_MIN = 2V)
• Maximum: 0000 1011 1001 1000 (bin) 2968 (dec) (equivalent VOUT_MIN = 2.9V)
8.6.48 IC_DEVICE_ID (ADh)
This Read-only Block Read command returns a single word (16 bits) with the unique Device Code identifier for
each device for which this IC can be configured. The BYTE_COUNT field in the Block Read command is 2
(indicating 2 bytes follow): Low Byte first, then High Byte.
COMMAND
IC_DEVICE_ID
Format
Linear, binary
Bit Position
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
Default Value
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
See below
Device Identifier Code default:
• 0027h – Code Identifier for TPS544C25 – 30A device
• 0028h – Code Identifier for TPS544B25 – 20A device
8.6.49 IC_DEVICE_REV (AEh)
This Read-only Block Read command returns a single word (16 bits) with the unique Device revision identifier.
The DEVICE_REV starts at 0 with the first silicon and is incremented with each subsequent silicon revision. The
BYTE_COUNT field in the Block Read command is 2 (indicating 2 bytes follow): Low Byte first, then High
Byte.
COMMAND
IC_DEVICE_REV
Format
Linear, tbinary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
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COMMAND
IC_DEVICE_REV
Default Value
See below
Device Identifier Code default:
• 0000b
8.6.50 MFR_SPECIFIC_00 (D0h)
The MFR_SPECIFIC_00 register is dedicated as a user scratch pad. Only the lower 8 bits are writeable for
users. This is a read word command, with only the lower 8 bits accessible. Note it's NOT a read byte command.
The contents of this register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
COMMAND
MFR_SPECIFIC_00
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
r/wE
0
0
0
0
0
0
Function
User scratch pad
Default Value
0
0
0
0
0
0
0
0
0
0
8.6.51 OPTIONS (MFR_SPECIFIC_21) (E5h)
The OPTIONS register can be used for setting user selectable options, as shown below. The contents of this
register can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
COMMAND
OPTIONS
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r/wE
r/wE
r/wE
r/wE
r/w
r/w
r/wE
r/wE
r/wE
Function
X
X
X
X
X
X
X
SS_DET_
DIS
EN_AUTO
_ARA
DLO
VSM
EN_ADC_C
NTL
Default
Value
0
0
0
0
0
0
0
0
1
0
0
1
AVG_PROG[1:0]
1
0
PMB_VT PMB_HI_
H
LO
1
1
8.6.51.1 PMB_HI_LO
This bit forces PMB rail logic levels.
• 0: Force 3V/5V logic thresholds.
• 1: Force 1.8V logic thresholds.
8.6.51.2 PMB_VTH
This bit configures automatic PMBus logic level detection.
• 0: No automatic bus detection occurs.
• 1: Allow the automatic bus detection to occur – VTH can result in 3V/5V or 1.8V depending upon comparator
output.
74
PMB_VTH
PMB_HI_LO
BUS DETECTION
COMPARATOR ( < 2.4 V)
VSET_USED
FINAL VTH
0
0
X
X
3V/5V
0
1
X
X
1.8V
1
X
0
0
3V/5V
1
X
0
1
1.8V
1
X
1
X
1.8V
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8.6.51.3 EN_ADC_CNTL
This bit enables ADC operation used for voltage, current and temperature monitoring.
• 0: Disable ADC operation.
• 1: Enable ADC operation.
NOTE
The EN_ADC_CNTL bit must be set in order to enable output voltage, current and
temperature telemetry. When the EN_ADC_CNTL bit is zero, the READ_VOUT,
READ_IOUT and READ_TEMPERATURE_2 registers do not update continuously, and
retain their previous values from the last time EN_ADC_CNTL was set.
8.6.51.4 VSM
This bit configures the measurement system for fast, vout-only measurement mode. Setting this bit disables
READ_IOUT, and READ_TEMPERATURE_2, and insteasd allows the device to update READ_VOUT more
frequently. This bit does not have EEPROM backup.
• 0: Measure Vout, Temperature, and Iout.
• 1: Measure only Vout.
8.6.51.5 DLO
This bit allows bypassing the normal valid data checks on register writes. This feature is included for flexibility
during debug to quickly generate fault conditions and/or possibly work around any data limit protection
mechanisms prohibiting output voltage programming. This bit does not have EEPROM backup.
• 0: Normal PMBus data write restrictions.
• 1: Data write restrictions are overridden for the following registers: SMBALERT_MASK, VOUT_COMMAND,
VOUT_SCALE_LOOP, VOUT_OV_FAULT_LIMIT, VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT,
VOUT_UV_FAULT_LIMIT,
IOUT_OC_FAULT_LIMIT,
IOUT_OC_WARN_LIMIT,
OT_FAULT_LIMIT,
OT_WARN_LIMIT, TON_MAX_FAULT_LIMIT, TON_RISE, TOFF_FALL, MFR_VOUT_MIN, VOUT_MAX,
VIN_ON, VIN_OFF, and OPERATION.
NOTE
CAUTION: Users should use this bit with extreme caution. Setting this bit allows invalid
data conditions to be programmed into the device which can lead to damage. Invalid data
written into any register when DLO is enabled does NOT set the IVD bit; nor trigger
SMBALERT. The invalid data is simply allowed to be programmed. Furthermore, invalid
data programmed into a command/status register while DLO is enabled, does not trigger
SMBALERT upon de-assertion of DLO. So, it is possible to exit DLO mode with invalid
data in command/status registers. Use with extreme caution.
8.6.51.6 AVG_PROG[1:0]
These bits configure programmable digital measurement averaging. Bits provide programmable averaging for
current (READ_IOUT), temperature (READ_TEMPERATURE_2), and voltage (READ_VOUT). The default (10b)
yields 8x averaging for all three parameters; however, this default can be changed and stored in EEPROM, if
necessary. Programming options are:
AVG_PROG[1:0]
ACCUMULATING AVERAGING
00b
16x
01b
0x – this ‘bypasses’ the averagers – every sample from measurement system updates
corresponding READ_XXX CSR.
10b
8x
11b
32x
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8.6.51.7 EN_AUTO_ARA
This bit Enables auto Alert Response Address response. When this feature is enabled, and after the device has
successfully responded to an ARA transaction, the hardware automatically masks any fault source currently set
from re-asserting SMBALERT. This prevents PMBus “bus hogging” in the case of a persistent fault in a device
that consistently wins ARA arbitration due to its device address. In contrast, when this bit is cleared, immediate
re-assertion of SMBALERT is allowed in the event of a persistent fault and the responsibility is upon the host to
mask each source individually.
8.6.51.8 SS_DET_DIS
This bit Disables Soft Start Detection when set. The READ_TEMPERATURE_2 value remains at 25°C when
OPTIONS (MFR_SPECIFIC_21) (E5h) is set to 0 since the TSNS/SS pin is configured to set TON_RISE time
and not used for external temperature sensing.
8.6.52 MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h)
This user-accessible register is used for miscellaneous options, as shown below. The contents of this register
can be stored to non-volatile memory using the STORE_DEFAULT_ALL command.
COMMAND
MISC_CONFIG_OPTIONS
Format
Unsigned binary
Bit Position
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r/wE
r/wE
r/wE
r/wE
Function
X
X
X
X
X
X
X
X
X
X
X
X
FORCE_SYNC
Default
Value
0
0
0
0
0
0
0
0
1
1
0
0
0
HSOC_USER_TRIM[1:0]
0
1
OV_RESP_SEL
1
8.6.52.1 OV_RESP_SEL
This bit selects between two options for low-side FET behavior after an output overvoltage fault condition.
Regardless of the setting of this bit, the low-side FET latches on when an output OV fault is detected (if the
OV_FAULT_RESPONSE is not programmed to “ignore”).
• 0: the low-side FET remains on until either the part initiates a new startup of the output voltage or the
CLEAR_FAULTS command is given while the part is in the “DISABLE” operational state
• 1: the low-side FET turns off as soon as the sensed output (at DIFFO pin) drops below the
VOUT_UV_FAULT_LIMIT.
8.6.52.2 HSOC_USER_TRIM[1:0]
This trim is provided so that the customers can adjust the high-side overcurrent (HSOC) threshold in order to
account for their application specific Vin sensing parasitics and component current handling spec requirements.
HSOC_USER_TRIM[1:0]
HSOC Change from Default
00b
0
01b
+12.5%
10b
–25%
11b
–12.5%
8.6.52.3 FORCE_SYNC
This bit configures the SYNC/RESET_B pin functions in conjunction with VSET detection.
• 0: the pin operates as RESET_B if VSET detection is valid, and SYNC otherwise.
• 1: the SYNC/RESET_B pin operates as a SYNC pin regardless of the outcome of the VSET detection.
76
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9 Applications and Implementation
9.1 Application Information
The TPS544x25 devices are highly-integrated synchronous step-down DC-DC converters. These devices are
used to convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 20 A
or 30 A. Use the following design procedure to select key component values for this family of devices, and set
the appropriate behavioral options via the PMBus™ interface.
9.2 Typical Applications
9.2.1 TPS544C25 4.5-V to 18-V Input, 0.95-V Output, 30-A Converter
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Typical Applications (continued)
S1
TP12
U2
1
8
7
6
VNC
NC
NC
LM334SM/NOPB
100k
33pF
R2
R20
R21
38.3k
C3
10.5k
Q2
2N7002E-T1-E3
21.5
3
R1
BP3
C1
Q1
MMBT3904
C2
1000pF
1200pF
R3
BP3
TP3
R5
31
40
37
38
39
22
VIN
SW
11
VIN
SW
14
GND
51.1k
R12
51.1k
JP2
GND
DATA
TP9
CLK
TP4
SMBALERT
R13
VOUTS+
49.9
C5
R14
0
330pF
C9
TP1
0.1µF
L1
TP5
R15
VOUTS-
VOUT = 0.95V @ 30A MAX ("C" version)
49.9
TP6
J3
12
470nH
744301047
C10
1000pF
GND
C18
6800pF
BOTTOM
RT
SW
GND
VIN
TP13
C11
C12
C21
100µF 100µF 100µF
C22
C23
C19
100µF 100µF 22µF
C20
C27
22µF
C25
DNP
R16
1
13
C17
6800pF
TOP
R11
9
10
GND
C16
22µF
SW
GND
C15
22µF
SW
VIN
16
C14
22µF
VIN
8
20
C13
22µF
7
23
21
PMBus
R10
10.0k
6
BOOT
PGND
15
GND
AGND
SMBALERT
24
GND
TSNS/SS
BP3
J1
C24
100µF
35
5
GND
GND
36
CLK
GND
VIN = 4.5V - 18V
COMP
BP6
18
C8
2.2µF
C7
4.7µF
PGOOD
28
25
R17
0
3
4
26
JP1
ADDR0
DATA
27
BP3
VSET
VDD
2
4
6
8
10
CNTL
2
29
GND
DNP
40.2k
1
CNTL
ADDR1
17
C6
1µF
30
DNP
VOUTSVOUTS+
PGND
R19
GND
SYNC/RESET_B
32
VOUTSVOUTS+
TP8
34
33
BP3
R18
10.0k
10.0k
R4
R7
U1
TPS544C25RVF
300
FB
1200pF
R8
DIFFO
R9
DNP
GND
GND
TP2
R6
49.9
19
10.0k
C4
GND
D1
Pink
J2
1
3
5
7
9
TP7
SMBALERT
DATA
V+
R
NC
NC
CLK
CNTL
3
2
4
5
2
1
TP11
C28
C26 100µF 100µF
DNP
J4
TP10
TP14
FSW = 500KHz
GND
Figure 44. Typical Application Schematic
9.2.2 Design Requirements
For this design example, use the following input parameters.
Table 16. Design Example Specifications
PARAMETER
VIN
Input voltage
VIN(ripple)
Input ripple voltage
VOUT
Output voltage
TEST CONDITION
MIN
TYP
MAX
UNIT
4.5
12.0
18.0
V
0.4
V
IOUT = 30 A
0.95
V
Line regulation
4.5 V ≤ VIN ≤ 18 V
Load regulation
0 V ≤ IOUT ≤ 30 A
VPP
Output ripple voltage
IOUT = 30 A
20
mV
VOVER
Transient response overshoot
ISTEP = 10 A
90
mV
VUNDER
Transient response undershoot
ISTEP = 10 A
IOUT
Output current
4.5 V ≤ VIN ≤ 18 V
tSS
Soft-start time
VIN = 12 V
IOC
Overcurrent trip point
η
Peak Efficiency
fSW
Switching frequency
78
0.5%
0.5%
90
0
20
5
36
IOUT = 13 A, VIN = 12 V
A
ms
40
A
88%
500
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mV
30
kHz
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9.2.3 Design Procedure
9.2.3.1 Switching Frequency Selection
Select a switching frequency for the regulator. There is a trade off between higher and lower switching
frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and
smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher
switching frequency causes extra switching losses, which decrease efficiency and impact thermal performance.
In this design, a moderate switching frequency of 500 kHz achieves both a small solution size and a highefficiency operation With the frequency selected, the timing resistor is calculated using Equation 11
RT =
2.01 × 1010 2.01 × 1010
=
= 40.2 k3
fSW
500 kHz
(11)
9.2.3.2 Inductor Selection
To calculate the value of the output inductor, use Equation 12. The coefficient KIND represents the amount of
inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple
current. Therefore, choosing a high inductor ripple current impacts the selection of the output capacitor since the
output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. Generally,
KIND coefficient should be kept between 0.2 and 0.4 for balanced performance. Using this target ripple current,
the required inductor size can be calculated as shown in Equation 12
L1 =
VOUT
kVIN :max ; × fSW o
×
VIN F VOUT
kIOUT :max ; × K IND o
=
0.95 V × (18 V F 0.95 V)
= 0.tJH
:18 V × 500 kHz × 30 A × 0.3;
(12)
Selecting KIND = 0.3, the target inductance L1 = 200 nH. Using the next standard value, the 470 nH is chosen in
this application for its high current rating, low DCR, and small size. The inductor ripple current, RMS current, and
peak current can be calculated using Equation 13, Equation 14 and Equation 15. These values should be used
to select an inductor with approximately the target inductance value, and current ratings that allow normal
operation with some margin.
IRIPPLE =
VOUT
kVIN :max ; × fSW o
IL(rms ) = ¨(IOUT )² +
×
VIN (max ) F VOUT
0.95 V × (18 V F 0.95 V)
=
= 3.83 A
:18 V × 500 kHz × 470 nH;
L1
1
1
(IRIPPLE )² = ¨(30 A)² +
× (3.83 A)² = 30.02 A
12
12
1
1
IL(peak ) = (IOUT ) + :IRIPPLE ; = 30 A + :3.83 A; = 31.95 A
2
2
(13)
(14)
(15)
The Pulse PG077.401NL is rated for 45 ARMS current, and 48-A saturation. Using this inductor, the ripple current
IRIPPLE= 3.85 A, the RMS inductor current IL(rms)= 30.02 A, and peak inductor current IL(peak)= 31.92 A.
9.2.3.3 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
affects three criteria:
• how the regulator responds to a change in load current or load transient
• the output voltage ripple
• the amount of capacitance on the output voltage bus
The last of these three considerations is important when designing regulators that must operate where the
electrical conditions are unpredictable. The output capacitance needs to be selected based on the most stringent
of these three criteria.
9.2.3.3.1 Response to a Load Transient
The desired response to a load transient is the first criterion. The output capacitor needs to supply the load with
the required current when not immediately provided by the regulator. When the output capacitor supplies load
current, the impedance of the capacitor greatly affects the magnitude of voltage deviation during the transient.
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In order to meet the requirements for control loop stability, the TPS544C25 requires the addition of compensation
components in the design of the error amplifier. While these compensation components provide for a stable
control loop, they often also reduce the speed with which the regulator can respond to load transients. The delay
in the regulator response to load changes can be two or more clock cycles before the control loop reacts to the
change. During that time the difference between the old and the new load current must be supplied (or absorbed)
by the output capacitance. The output capacitor impedance must be designed to be able to supply or absorb the
delta current while maintaining the output voltage within acceptable limits. Equation 16 and Equation 17 show the
relationship between the transient response overshoot, VOVER, the transient response undershoot, VUNDER, and
the required output capacitance, COUT.
VOVER <
VUNDER
:ITRAN ;2 × L1
VOUT × COUT
(16)
:ITRAN ;2 × L1
<
(VIN F VOUT ) × COUT
If
•
•
VIN(min) > 2 × VOUT, use overshoot to calculate minimum output capacitance.
VIN(min) < 2 × VOUT, use undershoot to calculate minimum output capacitance.
(17)
In this case, the minimum designed input voltage VIN(min) is greater than 2 × VOUT, so VOVER dictates the minimum
output capacitance. Therefore, using Equation 18, the minimum output capacitance required to meet the
transient requirement is 285 µF.
COUT (min ) =
:10 A;2 × 470 nH
(ITRAN )² × L1
=
= 550 JF
:VOUT × VOVER ; :0.95 V × 90 mV;
(18)
9.2.3.3.2 Output Voltage Ripple
The output voltage ripple is the second criterion. Equation 19 calculates the minimum output capacitance
required to meet the output voltage ripple specification. This criterion is the requirement when the impedance of
the output capacitance is dominated by ESR.
COUT (min ) =
IRIPPLE
k8 × fSW × VOUT (ripple ) o
=
3.83 A
= 48 JF
:8 × 500 kHz × 20 mV;
(19)
In this case, the maximum output voltage ripple is 20 mV. Under this requirement, the minimum output
capacitance for ripple (as calculated in Equation 19) yields 48 μF. Because this capacitance value is smaller than
the output capacitance required to meet the transient response, select the output capacitance value based on the
transient requirement. For this application, seven 100-µF low-ESR ceramic capacitors, and two 22-µF ceramic
capacitors were selected to meet the transient specification with sufficient margin. Therefore COUT = 744 µF.
With the target output capacitance value chosen, Equation 20 calculates the maximum ESR the output capacitor
bank can have to meet the output voltage ripple specification. Equation 20 indicates the ESR should be less than
4.9 mΩ. The ceramic capacitors each contribute approximately 3 mΩ, making the effective ESR of the output
capacitor bank approximately 0.3 mΩ, meeting the specification with sufficient margin.
VOUT(ripple) ESR MAX =
IRIPPLE
:8×fSW×COUT ;
IRIPPLE
20mV F
=
3.83 A
:8 × 500 kHz × 744 JF;
= 4.9 •À
3.83 A
(20)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in, which increases the
minimum required capacitance value. Capacitors generally have limits to the amount of ripple current they can
handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current
must be specified. Some capacitor data sheets specify the RMS (root mean square) value of the maximum ripple
current. Equation 21 can be used to calculate the RMS ripple current the output capacitor needs to support. For
this application, Equation 21 yields 1.11 A.
IC(rms ) =
80
VOUT × (VIN :max ; F VOUT )
¾12 × VIN :max ; × fSW × L1
=
0.95 V × (18 V F 0.95 V)
¾12 × 18 V × 500 kHz × 470 nH
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= 1.11 A
(21)
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9.2.3.3.3 Bus Capacitance
The amount of bus capacitance is the third criterion. This requirement is optional. However, extra output bus
capacitance should be considered in systems where the electrical environment is unpredictable, or not fully
defined, or can be subject to severe events such as hot-plug events or even electrostatic discharge (ESD)
events.
During a hot-plug event, when a discharged load capacitor is plugged into the output of the regulator, the
instantaneous current demand required to charge this load capacitance is be far too rapid to be supplied by the
control loop. Often the peak charging current can be multiple times higher than the current limit of the regulator.
Additional output capacitance helps maintain the bus voltage within acceptable limits. For hot-plug events, the
amount of required bus capacitance can be calculated if the load capacitance is known, based on the concept of
conservation of charge.
An ESD event, or even non-direct lightning surges at the primary circuit level can cause glitches at this converter
system level. A glitch of sufficient amplitude to falsely trip OVP or UVLO can cause several clock cycles of
disturbance. In such cases it is beneficial to design in more bus capacitance than is required by the simpler load
transient and ripple requirements. The amount of extra bus capacitance can be calculated based on maintaining
the output voltage within acceptable limits during the disturbance. This capacitance can be as much as required
to fully support the load for the duration of the interrupted converter operation.
9.2.3.4 Input Capacitor Selection
The TPS544x25 devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a
value of at least 0.1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input
decoupling capacitance (effective capacitance at the VIN and GND pins) must be sufficient to supply the high
switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage
ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input
capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating
greater than the maximum input current ripple to the device during full load. The input ripple current can be
calculated using Equation 22.
kVIN :min ; F VOUT o
VOUT
0.95 V (4.5 V F 0.95 V)
ICIN :rms ; = IOUT :max ; × ¨
×
= 30 A × ¨
×
VIN :min ;
VIN :min ;
4.5 V
4.5 V
= 12.2 Arms
(22)
The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are
shown in Equation 23 and Equation 24. The input ripple is composed of a capacitive portion, VRIPPLE(cap), and a
resistive portion, VRIPPLE(esr).
CIN (min ) =
IOUT :max ; × VOUT
30 A × 0.95 V
=
= 32 JF
VRIPPLE :cap ; × VIN :max ; × fSW 100 mV × 18 V × 500 KHz
(23)
V RIPPLE (ESR )
0.3 V
=
= 9.4 •À
1
1
:I
;
:3.83
30
A
+
+
A;
(max )
2
2 RIPPLE
(24)
ESR CIN (max ) =
IOUT
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at
least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input
ripple for VRIPPLE(cap), and 0.3-V input ripple for VRIPPLE(esr). Using Equation 23 and Equation 24, the minimum
input capacitance for this design is 32 µF, and the maximum ESR is 9.4 mΩ. For this example, four 22-μF, 25-V
ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for the
power stage. For the VDD pin, one 1-μF, 25-V ceramic capacitor was selected. The input voltage (VDD) and
power input voltage (VIN) pins must be tied together.
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9.2.3.5 Bootstrap Capacitor Selection
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper
operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor
should have voltage rating of 25 V or higher.
9.2.3.6 BP6 and BP3
According to the recommendations in , BP3 is bypassed to AGND with 2.2 μF of capacitance, and BP6 is
bypassed to PGND with 4.7-µF of capacitance. In order for the regulator to function properly, it is important that
these capacitors be localized to the TPS544x25 , with low-impedance return paths. See for more information.
9.2.3.7 R-C Snubber and VIN Pin High-Frequency Bypass
Though it is possible to operate the TPS544x25 within absolute maximum ratings without ringing reduction
techniques, some designs may require external components to further reduce ringing levels. This example uses
two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between
the SW area and GND.
The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the
outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and
discharge once the high-side MOSFET is turned on. For this example two 6.8-nF, 25-V, 0402 sized highfrequency capacitors are used. The placement of these capacitors is critical to its effectiveness. Its ideal
placement is shown in .
Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF
capacitor and a 1-Ω resistor are chosen. In this example a 1206 resistor is chosen, which is rated for 0.25 W,
nearly twice the estimated power dissipation. See SLUP100 for more information about snubber circuits.
9.2.3.8 Temperature Sensor
This application design uses a surface-mount MMBT3904 for the temperature sensor, Q1. In this example, the
sensor monitors the PCB temperature where it is generally the highest, next to the power inductor. Placement of
the temperature sensor and routing back to the TSNS pin are critical design features to reduce noise its
temperature measurements. In this example, the temperature sensor is placed on the VOUT side of the power
inductor to avoid switching noise from the SW plane, and routed back to the TSNS and AGND pin. Additionally, a
1-nF capacitor, C2, is placed from TSNS to AGND near the TSNS pin. The READ_TEMPERATURE_2 (8Eh)
register is continually updated with the digitized temperature measurement, enabling temperature telemetry.
Disable external temperature sensing by terminating TSNS to AGND with a 0 Ω resistor. This termination forces
the temperature readings to –40 °C, and prevents external over-temperature fault trips.
The switch S1 in this example can be used to switch between temperature sensor and SS resistor. Note that the
READ_TEMPERATURE_2 value will be kept at 25°C when SS_DET_DIS in (E5h) MFR_SPECIFIC_21 is set to
0 since the TSNS/SS pin is configured to set TON_RISE time and not used for external temperature sensing.
9.2.3.9 Key PMBus™ Parameter Selection
Several of the key design parameters for the TPS544x25 device can be configured via the PMBus interface, and
stored to its non-volatile memory (NVM) for future use.
9.2.3.9.1 Enable, UVLO and Sequencing
The ON_OFF_CONFIG (02h) command is used to select the turn-on behavior of the converter. For this example,
the CNTL pin was used to enable or disable the converter, regardless of the state of OPERATION (01h), as long
as input voltage is present, and above the UVLO threshold.
The minimum input voltage, VIN(min) , for this example is 4.5 V. The VIN_ON command was set to 4.5 V, and the
VIN_OFF command was set to 4.0 V, giving 500 mV of hysteresis. If VIN falls below VIN_OFF, power conversion
stops, until it is raised above VIN_ON.
The turn-on or turn-off delay time can be set by TON_DELAY and TOFF_DELAY. Accounting for the time during
which the COMP signal rises to the valley of the PWM ramp, the delay between enabling power conversion, and
the rise of the output voltage is approximately 200 µs. See Soft-Start and TON_RISE Command for more
information.
82
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9.2.3.9.2 Soft-Start Time
The TON_RISE command sets the soft-start time. When selecting the soft-start time, consider the charging
current for the output capacitors. In some applications (e.g., those with large amounts of output capacitance) this
current can lead to problems with nuisance tripping of the overcurrent protection circuitry. To avoid nuisance
tripping, the output capacitor charging current should be included when choosing a soft-start time, and
overcurrent threshold. The capacitor charging current can be calculated using Equation 25
ICAP =
V OUT × C OUT
0.95 V × 744 JF
=
= 141.36 mA
5 ms
t SS
(25)
With the charging current calculated, the overcurrent threshold can then be calibrated to the sum of the
maximum load current and the output capacitor charging current plus some margin.
In this example, the soft-start time is arbitrarily selected to be 5 ms. In this case, the charging current, ICAP =
141.36 mA.
9.2.3.9.3 Overcurrent Threshold and Response
The IOUT_OC_FAULT_LIMIT command sets the overcurrent threshold. The current limit should be set to the
maximum load current, plus the output capacitor charging current during start-up, plus some margin for load
transients and component variation. The amount of margin required depends on the individual application, but a
suggested starting point is between 25% and 30%. More or less may be required. For this application, the
maximum load current is 30 A, the output capacitor charging current is 141 mA. This design allows some extra
margin, so an overcurrent threshold of 36 A was selected.
The IOUT_OC_FAULT_RESPONSE command sets the desired response to an overcurrent event, which can be
hiccup (continuously restart waiting for a 7 x soft-start time-out between re-trials) in the event of an overcurrent,
latch-off, or continue without interruption (i.e. ignore the fault).
9.2.3.9.4 Power Good, Output Overvoltage and Undervoltage Protection
The VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT commands configure the PGOOD window, and
VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT commands configure the output voltage fault limits.
The VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE command sets the desired response
to an output overvoltage and undervoltage event respectively, which can be hiccup (continuously restart waiting
for a 7 x soft-start time-out between re-trials) in the event of a fault, latch-off, or continue without interruption (i.e.
ignore the fault).
Note that the VOUT_UV_FAULT_LIMIT is masked until the unit reaches the programmed output voltage. If the
output voltage did not reach the programmed value during the soft start time UPPER limit required by
TON_MAX_FAULT_LIMIT, the device will assert a TON_MAX fault and reponse according to
TON_MAX_FAULT_RESPONSE.
9.2.3.10 Output Voltage Setting and Frequency Compensation Selection
The output voltage can be set by the resistor connected from VSET to AGND with 8 possible options to set initial
boot-up output voltage ranging from 0.80 V to 1.20 V with VOUT_SCALE_LOOP = 1. The output voltage can
also be set by VOUT_COMMAND through the PMBus interface .
It is required that the user program VOUT_SCALE_LOOP prior to any VOUT related commands in order for the
proper range checking to work and to avoid Invalid Data scenarios. VOUT_SCALE_LOOP is equal to the
feedback resistor ratio of (R9/(R5+R9)). It is limited to only 3 possible options/ratios: 1 (default, no bottom
resistor required), 0.5, and 0.25.
In this design, the VSET pin is pulled up to BP3, so the VOUT_COMMAND goes to the default value of 0.95V
stored in the EEPROM. No bottom feedback resistor is needed for the output voltage range of 0.5 V to 1.5V.
The TPS544x25 device uses voltage mode control, with input feedforward. See SLUP206 for an in-depth
discussion of voltage-mode feedback and control. Frequency compensation can be accomplished using standard
techniques. TI also provides a compensation calculator tool to streamline compensation design. Using the
TPS40k Loop Compensation Tool, with 50 kHz of bandwidth, and 60 degrees of phase margin and optimizing
based on measured results yields the following:
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Table 17. Design Example Frequency Compensation Values
RESISTOR
VALUE (kΩ)
CAPACITOR
VALUE (pF)
R5
10.0
C4
1200
R8
0.3
C3
1200
R2
10.5
C1
33
RBias
Not Used
The tool provides the recommended compensation components, and approximate bode plots. As a starting point,
the crossover frequency should be set to 1/10 fSW, and the phase margin at crossover should be greater than
45°. The resulting plots should be reviewed for a few common issues. The error amplifier gain should not hit the
error amplifier gain bandwidth product (GBWP), nor should its mid-band gain, AMID, be greater than
approximately 20 dB in general. Use the tool to calculate the system bode plot at different loading conditions to
ensure that the phase does not drop below zero prior to crossover, as this condition is known as conditional
stability.
Application Curves
100
100
95
95
90
90
Efficiency (%)
85
80
75
70
85
80
75
65
65
60
60
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32
Load Current (A)
D001
VIN = 5 V
L = 470 nH
fSW = 500 kHz
No snubber
0
RBOOT = 0 Ω
RDCR = 0.3 mΩ
VIN = 5 V
VIN = 12 V
VIN = 18 V
0.9525
Gain (dB)
Output Voltage (V)
0.955
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32
Load Current (A)
D001
fSW = 500 kHz
No snubber
RBOOT = 0 Ω
RDCR = 0.3 mΩ
Figure 46. Efficiency vs. Load Current
0.96
0.9575
2
VIN = 12 V
L = 470 nH
Figure 45. Efficiency vs. Load Current
0.95
0.9475
0.945
75
400
60
320
45
240
30
160
15
80
0
0
-15
0.9425
-30
0.94
0.9375
0
3
6
9
12
15
18
21
Output Current (A)
24
27
30
-45
100
-80
-160
Gain
Phase
1000
D001
VIN = 12 V
VOUT = 0.95 V
Figure 47. Load Regulation
84
VOUT = 0.5 V
VOUT = 1.0 V
VOUT = 1.5 V
VOUT = 2.5 V
VOUT = 3.3 V
70
VOUT = 0.5 V
VOUT = 1.0 V
VOUT = 1.5 V
VOUT = 2.5 V
Phase (°)
Efficiency (%)
9.2.4
10000
Frequency (Hz)
100000
VOUT = 0.95 V
-240
1000000
D001
D008
D002
IOUT = 20 A
Figure 48. System Bode Plot
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VIN = 12 V
VOUT = 0.95 V
IOUT = 20 A
Figure 49. Startup from CNTL
VIN = 12 V
VOUT = 0.95 V
IOUT = 0 A to 20A , 2.5 A/µs
VIN = 12 V
VOUT = 0.95 V
IOUT = 20 A
Figure 50. Shutdown from CNTL
VIN = 12 V
Figure 51. Transient Load
VOUT = 0.95 V
IOUT = 20 A
Figure 52. DC Ripple
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VIN = 12 V
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IOUT = 0 A
VPRE-BIAS= 0.5 V
VIN = 12 V
Figure 53. 50% Pre-Biased Start-Up
Natural Convection
IOUT = 20 A
VOUT = 0.95 V
fSW = 500 kHz
Figure 54. Thermal Image
10 Power Supply Recommendations
These devices are designed to operate from an input voltage supply between 4.5 V and 18 V. This supply must
be well regulated. These devices are not designed for split-rail operation. The VIN and VDD pins must be the
same potential for accurate high-side short circuit protection. Proper bypassing of input supplies and internal
regulators is also critical for noise performance, as is PCB layout and grounding scheme. See the
recommendations in the Layout section.
86
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11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. Figure 55 shows the recommended PCB layout
configuration. A list of PCB layout considerations using these devices are listed below.
•
•
•
•
•
•
•
•
•
•
•
As with any switching regulator, there are several signal paths that conduct fast switching voltages or
currents. Minimize the loop area formed by these paths and their bypass connections.
Bypass the VIN pins to GND with a low-impedance path. Power-stage input bypass capacitors should be as
close as physically possible to the VIN and GND pins. Additionally, a high-frequency bypass capacitor in 0402
package on the VIN pins can help to reduce switching spikes, which can be tucked right underneath the IC on
the other side of the PCB to keep a minimum loop.
BP6 bypass capacitor carries large switching current for gate driver. Bypassing the BP6 pin to GND with a
low-impedance path is very critical to the stable operation of the TPS544x25 devices. Place BP6 highfrequency bypass capacitors as close as possible to the device pins, with a minimum return loop back to
ground.
The VDD and BP3 also require good local bypassing. Place bypass capacitors as close as possible to the
device pins, with a minimum return loop back to ground and this return loop should be kept away from fast
switching voltage and main current path, as well as BP6 current path. Poor bypassing on VDD and BP3 can
degrade the performance of the regulator.
Keep signal components local to the device, and place them as close as possible to the pins to which they
are connected. These components include the feedback resistors, the RT resistor, the VSET resistor, the SS
resistor, as well as ADDR0 and ADDR1 resistors. These components should also be kept away from fast
switching voltage and current paths. Those components can be terminated to GND with minimum return loop
or bypassed to a separate low impedance analog ground (AGND) copper area, which is isolated from fast
switching voltage and current paths and has single connection to PGND on the thermal tab via AGND pin.
See Figure 55 for placement recommendation.
The PGND pin (pin 26) must be directly connected to the thermal pad of the device on the PCB, with a lownoise, low-impedance path to ensure accurate current monitoring.
Minimize the SW copper area for best noise performance. Route sensitive traces away from SW and BOOT,
as these nets contain fast switching voltages, and lend easily to capacitive coupling.
Snubber component placement is critical to its effectiveness of ringing reduction. These components should
be on the same layer as the TPS544x25 devices, and be kept as close as possible to the SW and GND
copper areas.
The VIN and VDD pins must be the same potential for accurate short circuit protection, but high frequency
switching noise on the VDD pin can degrade performance. VDD should be connected to VIN through a trace
from the input copper area. Optionally form a small low-pass R-C between VIN and VDD, with the VDD
bypass capacitor (1 µF) and a 0-2 Ω resistor between VIN and VDD. See Figure 55.
Route the VOUTS+ and VOUTS– lines from the output capacitor bank at the load back to the device pins as
a tightly coupled differential pair. It is critical that these traces be kept away from switching or noisy areas
which can add differential-mode noise.
Routing of the temperature sensor traces is critical to the noise performance of temperature monitoring. Keep
these traces away from switching areas or high current paths on the layout. It is also recommended to use a
small 1-nF capacitor from TSNS/SS to AGND to improve the noise performance of temperature readings.
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11.2 Layout Example
(A)
(C)
(B)
(Not to scale)
VIN
RBOT
GND
VIN
VIN
VIN
VIN
VIN
BP3
PGND
BP6
VDD
VSET
VOUTS-
CCOMP2
RCOMP1
VOUTS+
(L)
(K)
RTOP
DIFFO
RCOMP2
CCOMP2
CCOMP3
GND
COMP
GND
Thermal Pad
PGOOD
RPG
(J)
GND
(N)
FB
GND
TSNS/SS
RSYNC
(I)
(D)
GND
(M)
AGND
VOUTS±
GND
GND
SYNC/RESET_B
RT
RSNS±
GND
AGND
SW
SW
SW
SW
SW
BOOT
SMBALERT
CLK
DATA
ADDR0
CNTL
ADDR1
RRT
(H)
CBOOT
TSNS
RBOOT
Optional
RC
Snubber
Address
Resistors
(G)
CNTL
PMBus
Signal Communication
L1
RSNS+
QTSNS
AGND
VOUTS+
VOUT
(E)
(F)
(A) Connect to AGND with setting resistor or pull up to BP3 if not used.
(B) Bypass for internal regulators BP3, BP6, VDD. Use multiple vias to reduce parasitic inductance
(C) Place VIN bypass capacitors as close as possible to device, with best high frequency capacitor closest to VIN and
GND pins
(D) Kelvin connect to TPS544C25 VOUTS– and VOUTS+ pins
(E) Sense point should be directly at the load
(F) For best efficiency, use a heavy weight copper and place these planes on multiple PCB layers
(G) Minimize SW area for least noise. Keep sensitive traces away from SW and BOOT on all layers
(H) AGND and PGND are only connected together on Thermal Pad.
(I) Optional SYNC/RESET_B Signal. Pull up to BP3 if not used.
(J) Pull up to BP6 or external voltage to use PGOOD.
(K) Maintain feedback and compensation network components localized to the device.
(L) Internal AGND Plane to reduce the BP3 and VDD bypass parasitics.
(M) Connect AGND to Thermal Pad
(N) Connect PGND to Thermal Pad
Figure 55. PCB Layout Recommendation
11.2.1 Mounting and Thermal Profile Recommendation
Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the
reflow process can affect electrical performance. Figure 56 shows the recommended reflow oven thermal profile.
Proper post-assembly cleaning is also critical to device performance. See SLUA271 for more information.
88
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Layout Example (continued)
tP
Temperature (°C)
TP
TL
TS(max)
tL
TS(min)
rRAMP(up)
tS
rRAMP(down)
t25P
25
Time (s)
Figure 56. Recommended Reflow Oven Thermal Profile
Table 18. Recommended Thermal Profile Parameters
PARAMETER
MIN
TYP
MAX
UNIT
RAMP UP AND RAMP DOWN
rRAMP(up)
Average ramp-up rate, TS(max) to TP
3
°C/s
rRAMP(down)
Average ramp-down rate, TP to TS(max)
6
°C/s
PRE-HEAT
TS
Pre-heat temperature
tS
Pre-heat time, TS(min) to TS(max)
150
200
°C
60
180
s
REFLOW
TL
Liquidus temperature
TP
Peak temperature
217
tL
Time maintained above liquidus temperature, TL
tP
Time maintained within 5 °C of peak temperature, TP
t25P
Total time from 25 °C to peak temperature, TP
°C
260
°C
60
150
s
20
40
s
480
s
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Texas Instruments Fusion Digital Power Designer
The TPS544x25 devices are fully supported by Texas Instruments Digital Power Designer. Fusion Digital Power
Designer is a graphical user interface (GUI) which can be used to configure and monitor the devices via PMBus
using a Texas Instruments USB-to-GPIO adapter.
Click this link to download the Texas Instruments Fusion Digital Power Designer software package.
Figure 57. Device Monitoring with Fusion Digital Power Designer
90
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Device Support (continued)
Figure 58. Device Configuration with Fusion Digital Power Designer
12.1.1.2 TPS40k Loop Compensation Tool
The TPS544x25 devices are supported by the Texas Instruments TPS40k Loop Compensation Tool. This
spreadsheet tool can be used to calculate frequency compensation components for devices with voltage mode
control.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 19. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS544C25
Click here
Click here
Click here
Click here
Click here
TPS544B25
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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12.4 Trademarks
SWIFT, NexFET, E2E are trademarks of Texas Instruments.
PMBus is a trademark of SMIF, Inc..
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. These data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
92
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS544B25RVFR
ACTIVE
LQFN-CLIP
RVF
40
2500
RoHS-Exempt
& Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS544B25
TPS544B25RVFT
ACTIVE
LQFN-CLIP
RVF
40
250
RoHS-Exempt
& Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS544B25
TPS544C25RVFR
ACTIVE
LQFN-CLIP
RVF
40
2500
RoHS-Exempt
& Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS544C25
TPS544C25RVFT
ACTIVE
LQFN-CLIP
RVF
40
250
RoHS-Exempt
& Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS544C25
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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