TPS54J061
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
TPS54J061 4-VIN to 16-VIN, 6-A, Synchronous Step-Down Converter with D-CAP3™
Control and 0.6-V Reference
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Server and cloud-computing POLs
Broadband, networking, and optical
Wireless infrastructure
Industrial PC
IP network camera
3 Description
The TPS54J061 device is a high-efficiency, smallsized, synchronous buck converter with an adaptive
on-time D-CAP3™ control mode. The device offers
ease-of-use and low external-component count for
space-conscious power systems.
This device features high-performance integrated
MOSFETs, accurate ±1% 600-mV reference
with an junction temperature range between –
40°C and +125°C. Competitive features include
very-low external-component count, fast loadtransient response, accurate load regulation
and line regulation, auto-skip or FCCM mode
operation, adjustable soft-start control, and external
compensation is not needed to support all ceramic
capacitor design .
TPS54J061 is available in a 14-pin QFN package.
Device Information(1)
PART NUMBER
PACKAGE
TPS54J061
(1)
QFN (14)
BODY SIZE (NOM)
2.00 mm × 3.00 mm
For available package, see the addendum at the end of the
data sheet.
100
95
90
Efficiency (%)
•
•
2.7-V to 16-V input range with external bias
ranging from 3.3 V to 3.6 V
4-V to 16-V input range without external bias
Integrated MOSFETs support 6-A continuous
output current
D-CAP3™ control mode with fast load-step
response
Supports all ceramic output capacitors
Reference voltage 600 mV ±1% tolerance from
–40°C to +125°C junction temperature
Output voltage range: 0.6 V to 5.5 V
Auto-skipping Eco-mode™ for high light-load
efficiency
Programmable current limit through external
resistor
Selectable frequency settings (600 kHz, 1100 kHz,
2200 kHz)
Internal fixed, external adjustable soft start
Safe pre-biased start-up capability
Built-in circuit allows slow output discharge
Open-drain power-good output
Self restarting hiccup mode for OC, UV faults
Fully RoHS compliant
2-mm × 3-mm, 14-Pin Hotrod™ package with 0.5mm pitch
85
80
75
70
VIN = 5 V
VIN = 8 V
VIN = 12 V
VIN = 16 V
65
60
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
4.5
5
5.5
6
Typical Efficiency (VOUT = 1.8 V, fSW = 600 kHz)
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................ 8
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................17
8 Application and Implementation.................................. 18
8.1 Application Information............................................. 18
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................31
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 33
11 Device and Documentation Support..........................35
11.1 Documentation Support.......................................... 35
11.2 Support Resources................................................. 35
11.3 Receiving Notification of Documentation Updates.. 35
11.4 Trademarks............................................................. 35
11.5 Glossary.................................................................. 35
11.6 Electrostatic Discharge Caution.............................. 35
12 Mechanical, Packaging, and Ordering Information..36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2020) to Revision A (June 2021)
Page
• Changed VIN – SW transient < 20 ns min value to –4....................................................................................... 4
• Updated Section 7.3.4 for soft-start capacitor clarification............................................................................... 12
• Updated Section 8.2.2.7 for soft-start capacitor clarification............................................................................ 23
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
5 Pin Configuration and Functions
Figure 5-1. 14-Pin QFN RPG Package (Top View)
Figure 5-2. 14-Pin QFN RPG Package (Bottom
View)
Table 5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
1, 14
PGND
G
Power ground of internal low-side MOSFET
2., 11
SW
O
Output switching terminal of the power converter. Connect this pin to the output inductor.
3
VIN
I
Power-supply input pins for both integrated power MOSFET pair and the internal regulator.
Place the decoupling input capacitors as close as possible to VIN pins.
4
TRIP
I/O
Current limit setting pin. Connect a resistor to ground to set the current limit trip point. See
Section 7.3.7 for detailed OCP setting.
5
EN
I
Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating the EN pin
is not recommended.
6
FB
I
Output feedback input. A resistor divider from the VOUT to AGND (tapped to FB pin) sets the
output voltage.
7
AGND
G
Analog ground pin, reference point for internal control circuits
8
SS/REFIN
I/O
Internal reference voltage can be overridden by an external voltage source on this pin for
tracking application. Connecting a capacitor to AGND increases soft-start time.
9
PGOOD
O
Open-drain power-good status signal. A high voltage indicates the FB voltage has moved
inside the specified limits.
10
BOOT
I/O
Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from
this pin to SW node.
12
MODE
I
The MODE pin sets the forced continuous-conduction mode (FCCM) or skip-mode operation. It
also selects the operating frequency.
I/O
Internal 3-V LDO output. An external bias with 3.3-V ±5% voltage can be connected to this pin
to save the power losses on the internal LDO. The voltage source on this pin powers both the
internal circuitry and gate driver. For the decoupling, a 1-µF ceramic capacitor as close to VCC
pin as possible is suggested.
13
(1)
VCC
I = Input, O = Output, P = Supply, G = Ground
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
3
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted)(1)
MIN
MAX
VIN
–0.3
18
V
VIN – SW
–0.3
18
V
–0.3
18
V
–4.0
25
V
SW – PGND
VIN – SW
Transient < 20 ns
–5.0
21.5
V
BOOT – SW
–0.3
6
V
BOOT – PGND
–0.3
24
V
EN, PGOOD
–0.3
6
V
TRIP, MODE, SS/REFIN, FB
–0.3
6
V
VCC
–0.3
6
V
AGND - PGND
–0.3
0.3
V
Operating Junction Temperature Range, TJ
–40
150
°C
Storage Temperature Range, Tstg
–55
150
°C
Pin voltage(2)
Pin voltage
differential
(1)
(2)
SW – PGND
DC
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
VIN with up to 3.6V external bias on VCC (1)
VIN
VIN with internal bias
VIN to enable the converter with internal bias
Pin voltage
MAX
2.7
16
V
4
16
V
3.3
UNIT
V
SW – PGND
–0.1
16
V
BOOT – SW
–0.1
5.3
V
TRIP, SS/REFIN, FB
–0.1
1.5
V
MODE
–0.1
VCC
V
EN, PGOOD
–0.1
5.5
V
3.0
3.6
V
VCC
Pin voltage differential
AGND - PGND
–0.1
0.1
V
Junction temperature, TJ
Operating junction temperature
–40
125
°C
(1)
4
MIN
Ensure that under any combination of the conditions listed above that stresses on the device do not exceed those specified in the
Absolute Maximum Ratings.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
6.4 Thermal Information
TPS54J060
THERMAL METRIC(1)
RPG (QFN)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance (JEDEC)
RθJC(top)
Junction-to-case (top) thermal resistance (JEDEC)
RθJC(bot)
Junction-to-case (bottom) thermal resistance (JEDEC)
RθJB
Junction-to-board thermal resistance (JEDEC)
16.2
°C/W
RθJA(EVM)
Junction-to-ambient thermal resistance (EVM)
43.5
°C/W
ψJT
Junction-to-top characterization parameter (EVM)
1.7
°C/W
ψJB
Junction-to-board characterization parameter (EVM)
21
°C/W
(1)
64
°C/W
40
°C/W
16.2
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
6.5 Electrical Characteristics
TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
750
900
µA
SUPPLY
IQ(VIN)
IQ(VCC)
ISD_VIN
VINUVLO
VIN operating non-switching supply
current
External VCC bias current(1)
VIN shutdown supply current
VIN UVLO rising threshold voltage
VEN = 2 V, VFB = VINTREF + 50mV, VIN = 12 V, no
external bias on VCC pin
3.3 V external bias on VCC pin, fSW(FCCM) =
600kHz
3
mA
3.3 V external bias on VCC pin, fSW(FCCM) =
1100kHz
5.5
mA
3.3 V external bias on VCC pin, fSW(FCCM) =
2200kHz
10
mA
VEN = 0 V, VIN =12 V, no external bias on VCC pin
10
µA
VCC = external 3.3V
2.1
2.4
2.7
V
VCC = external 3.3V
1.55
1.85
2.15
V
ENABLE
VENH
EN enable threshold voltage (rising)
1.17
1.22
1.27
V
VENL
EN disable threshold voltage (falling)
0.97
1.02
1.07
V
VENHYST
EN hysteresis voltage
VENLEAK
EN input leakage current
VEN = 3.3 V
5
µA
EN internal pull-down resistance
EN pin to AGND.
0.2
–5
0
V
6500
kΩ
INTERNAL LDO
VCC
Internal LDO output voltage
VIN = 12 V, IVCC(LOAD) = 5 mA
2.90
3.00
3.10
V
VCCUVLO
VCC undervoltage-lockout (UVLO)
threshold voltage
VCC rising
2.80
2.85
2.90
V
VCC falling
2.65
2.70
2.75
V
VCCUVLO
VCC undervoltage-lockout (UVLO)
threshold voltage
VCC hysteresis
VCCDO
LDO low-droop dropout voltage
VIN = 3.3 V, IVCC(LOAD) = 20 mA, TJ = 25°C
LDO overcurrent limit
All VINs, all temps
Internal REF voltage
TJ = 25°C
Internal REF voltage tolerance
TJ = 0°C to 70°C
597
603
mV
Internal REF voltage tolerance
TJ = –40°C to 125°C
594
606
mV
FB input current
VFB = VINTREF
100
nA
0.15
V
310
30
60
mV
mA
REFERENCE
VINTREF
IFB
600
mV
SWITCHING FREQUENCY
fSW(FCCM)
VO switching frequency, FCCM
operation(1)
VIN = 12 V, VOUT=1.2V, RMODE = 0 Ω to AGND, No
Load
935
1100
1265
kHz
fSW(FCCM)
VO switching frequency, FCCM
operation(1)
VIN = 12 V, VOUT=2.5V, RMODE = 30.1 kΩ to AGND,
No Load
1870
2200
2530
kHz
fSW(FCCM)
VO switching frequency, FCCM operation
VIN = 12 V, VOUT=1.2V, RMODE = 60.4 kΩ to AGND,
No Load
536
630
724
kHz
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
5
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tON(min)
Minimum on-time
VIN=12V VOUT=1V, first pulse
tOFF(min)
Minimum off-time
TJ = 25°C, HS FET Gate falling to rising
EN to first switching delay, internal LDO
The delay from EN goes high to the first SW rising
edge with internal 3.0V LDO. VCC bypass cap =
1uF for typical value, VCC bypass cap = 2.2uF for
max value. CSS/REFIN = 1nF
EN to first switching delay, external VCC
bias
The delay from EN goes high to the first SW rising
edge with external 3.3V VCC bias. CSS/REFIN = 1nF
MIN
TYP
70
MAX
UNIT
95
ns
220
ns
0.85
2
ms
500
700
µs
STARTUP
tSS
Internal soft-start time
VO rising from 0 V to 95% of final setpoint, CSS/
= 1nF
REFIN
1
1.5
ms
SS/REFIN sourcing current
VSS/REFIN = 0 V
9
µA
SS/REFIN sinking current
VSS/REFIN = 1 V
3
µA
SSREFIN Detection Threshold
VIN=4V-16V, VCC=3.0V – 5.3V, -40C- 125C,
TPS54J061
800
mV
SS/REFIN to FB matching
VSS/REFIN = 0.5 V
-5
0
5
mV
POWER STAGE
RDS(on)HS
High-side MOSFET on-resistance
TJ = 25°C, BOOT-SW = 3 V, IO = 3 A
22
mΩ
RDS(on)LS
Low-side MOSFET on-resistance
TJ = 25°C, VCC = 3 V, IO = 3 A
8.5
mΩ
BOOT CIRCUIT
IVBST-SW
VBST-SW leakage current
TJ = 25°C, VVBST-SW = 3.3 V
28
µA
BOOT UVLO(1)
TJ = 25°C, Voltage rising
2.35
V
BOOT UVLO Hysteresis(1)
TJ = 25°C
0.32
V
CURRENT DETECTION
Current limit clamp
RTRIP
TRIP pin resistance range
IOCL
Current limit threshold
KOCL
KOCL constant for RTRIP equation
Valley current on LS FET, 0-Ω ≤ RTRIP ≤ 3.16-kΩ
8.1
9.5
3.74
Valley current on LS FET, RTRIP = 4.99 kΩ
A
30.1
kΩ
6.9
A
-10
10
%
-16.5
16.5
%
5.1
6.0
30000
KOCL tolerance
3.74-kΩ ≤ RTRIP ≤ 4.99-kΩ
KOCL tolerance
10-kΩ = RTRIP
INOCL
Negative current limit threshold
All VINs
IZC
Zero-cross detection current threshold,
open loop
VIN = 12 V, VCC = 3 V
-4.3
–3.5
-2.8
A
0
200
730
mA
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Overvoltage-protection (OVP) threshold
voltage
113
116
119
%
VUVP
Undervoltage-protection (UVP) threshold
voltage
77
80
83
%
tdelay(OVP)
OVP response delay
tdelay(UVP)
UVP filter delay
tdelay(hiccup)
Hiccup delay time
With 100-mV overdrive
VIN=12V, VCC=3V
300
ns
64
µs
14
ms
POWER GOOD
VPGTH
6
PGOOD threshold
FB rising, PGOOD transition low to high
89
92.5
95
FB rising, PGOOD transition high to low
113
116
119
FB falling, PGOOD transition high to low
77
80
83
102.5
105
107.5
VOOB
PGOOD & Out-of-bounds threshold
FB rising
IPG
PGOOD sink current
VPGOOD = 0.4 V, VIN = 12 V, VCC = 3 V
IPG
PGOOD low-level output voltage
IPGOOD = 5.5 mA, VIN = 12 V, VCC = 3 V
%
%
5.5
mA
400
mV
Delay for PGOOD from low to high
1
1.25
ms
Delay for PGOOD from high to low
2
5
µs
5
µA
tdelay(PG)
PGOOD delay time
Ilkg(PG)
PGOOD leakage current when pulled high TJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER
PGOOD clamp low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up
to 3.3 V through a 100-kΩ resistor
750
1100
mV
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up
to 3.3 V through a 10-kΩ resistor
950
1250
mV
Min VCC for valid PGOOD output
1.5
V
OUTPUT DISCHARGE
RDischg
Output discharge resistance
VIN = 12 V, VCC = 3 V, power conversion disabled
80
Ω
170
°C
38
°C
THERMAL SHUTDOWN
TSDN
(1)
Thermal shutdown threshold(1)
Temperature rising
Thermal shutdown hysteresis(1)
155
Specified by design. Not production tested.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
7
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
6.6 Typical Characteristics
30
28
26
RdsON (m:)
RdsON (m:)
24
22
20
18
16
14
12
HS Resistance at VCC = 3V
10
-50
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
150
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-50
Figure 6-1. High-Side FET RdsON
6.8
Negative Overcurrent Threshold (A)
LS FET Valley Current (A)
6.4
6.2
6
5.8
5.6
5.4
5.2
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
10
30
50
70
90
Junction Temperature (°C)
110
130
150
130
150
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
-50
150
Figure 6-3. Overcurrent Limit
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
Figure 6-4. Negative Overcurrent Limit
1.5
0.606
Enable Voltage Rising (V)
Enable Voltage Falling (V)
1.44
0.6045
1.38
0.603
1.32
VREF (V)
Enable Voltage (V)
-10
4
RTRIP = 4.99k:
-30
-30
Figure 6-2. Low-Side FET RdsON
6.6
5
-50
LS Resistance at VCC = 3V
1.26
1.2
1.14
1.08
0.6015
0.6
0.5985
0.597
1.02
0.5955
0.96
0.9
-50
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
150
0.594
-50
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
150
Figure 6-6. Vref
Figure 6-5. Enable Voltage
8
-30
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
3
4
2.7
3.8
2.4
3.6
2.1
3.4
1.8
3.2
VCC (V)
VIN (V)
www.ti.com
1.5
1.2
0.9
3
2.8
2.6
0.6
2.4
VIN Rising (V)
VIN Falling (V)
0.3
0
-50
Vcc Rising (V)
Vcc Falling (V)
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
2.2
2
-50
150
-30
120
115
110
105
100
95
90
85
80
75
70
65
60
55
50
-50
130
150
VIN = 12V, VCC = Internal LDO
16
FB Rising PGOOD rising
FB falling PGOOD falling
FB Rising PGOOD falling
Out of Bounds
15.2
14.4
13.6
12.8
12
11.2
10.4
9.6
8.8
8
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
0
150
10
20
30
40
50
60
70
Junction Temperature (°C)
80
90
100
130
150
Figure 6-10. PGOOD Sink Current
0.8
10
VIN = 12V, VCC = Internal LDO
9.8
Soft Start Sourcing Current (PA)
0.72
0.64
0.56
Current (A)
110
16.8
Figure 6-9. PGOOD Thresholds
0.48
0.4
0.32
0.24
0.16
0.08
0
-50
10
30
50
70
90
Junction Temperature (°C)
Figure 6-8. VCC UVLO
PGOOD Sink Current (mA)
PGOOD Threshold (% of VREF)
Figure 6-7. VIN UVLO
-10
9.6
9.4
9.2
9
8.8
8.6
8.4
8.2
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
Figure 6-11. Zero Crossing Threshold
150
8
-50
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
Figure 6-12. Soft-Start Sourcing Current
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
9
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
20
800
18
Shutdoen Supply Current (PA)
900
Supply Current (PA)
700
600
500
400
300
200
VIN = 12V, VCC = Internal LDO
VEN = 2V, VFB = VINTREF+50mV
100
0
-50
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
12
10
8
6
4
-30
-10
10
30
50
70
90
Junction Temperature (°C)
110
130
150
Figure 6-14. Shutdown Supply Current
1300
1250
675
Switching Frequency (kHz)
Switching Frequency (kHz)
14
0
-50
150
700
650
625
600
VIN = 5 V
VIN = 12 V
VIN = 16 V
575
1200
1150
1100
1050
1000
VIN = 5 V
VIN = 12 V
VIN = 16 V
950
900
550
0
0.5
1
1.5
2
2.5 3 3.5 4
Output Current (A)
VOUT = 1.2 V
L = 1 µH
4.5
5
5.5
0
6
MODE = FCCM
0.5
1
1.5
2
VOUT = 1.2 V
Figure 6-15. 600-kHz Switching Frequency vs Load
Current
2.5 3 3.5 4
Output Current (A)
L = 1 µH
4.5
5
5.5
6
MODE = FCCM
Figure 6-16. 1100 kHz Switching Frequency vs
Load Current
2600
1400
VIN = 5 V
VIN = 12 V
VIN = 16 V
VIN = 8 V
2400
1200
Switching Frequency (kHz)
2500
Switching Frequency (kHz)
16
2
Figure 6-13. Non-Switching Supply Current
2300
2200
2100
2000
1000
800
600
400
VIN = 5 V
VIN = 12 V
VIN = 16 V
200
1900
1800
0
0
0.5
1
VOUT = 2.5 V
1.5
2
2.5 3 3.5 4
Output Current (A)
L = 0.47 µH
4.5
5
5.5
6
MODE = FCCM
Figure 6-17. 2200 kHz Switching Frequency vs
Load Current
10
VIN = 12V, VCC = Internal LDO, VEN = 0V
0
0.5
1
VOUT = 1.2 V
1.5
2
2.5 3 3.5 4
Output Current (A)
L = 1 µH
4.5
5
5.5
6
MODE = DCM
Figure 6-18. 1100 kHz Switching Frequency vs
Load Current – DCM
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
7 Detailed Description
7.1 Overview
The TPS54J061 device is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The
device suits low output voltage point-of-load applications with up to 6-A output current in server, storage, and
similar computing applications. The TPS54J061 features proprietary D-CAP3™ control combined with adaptive
on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC
converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage
ranges from 2.7 V to 16 V, and the VCC input voltage ranges from 3 V to 3.6 V. The D-CAP3 control uses
emulated current information to control the modulation. An advantage of this control scheme is that it does
not require a phase-compensation network outside, which makes the device easy-to-use and also allows low
external component count. Further advantage of this control scheme is that it supports stable operation with all
ceramic output capacitors. Adaptive on-time control tracks the preset switching frequency over a wide range of
input and output voltage while increasing switching frequency as needed during load-step transient.
7.2 Functional Block Diagram
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
11
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
7.3 Feature Description
7.3.1 Enable and Internal LDO
The TPS54J061 has an internal 3-V LDO feature using input from VIN and output to VCC. When the VIN voltage
rises above VINUVLO rising threshold (typically 2.4 V), and the EN voltage rises above the enable threshold
(typically 1.22 V), the internal LDO is enabled and outputs voltage to the VCC pin. The VCC voltage provides
the bias voltage for the internal analog circuitry. The VCC voltage also provides the supply voltage for the gate
drives.
When the EN pin voltage rises above the enable threshold voltage, and VCC rises above the VCCUVLO rising
threshold (typically 2.85 V), the device enters its start-up sequence. The device then uses the first 400-μs to
calibrate the MODE setting resistance attached to the MODE pin and sets the switching frequency internally.
During this period, the MODE pin resistance determines the operation mode too. The device remains in the
disabled state when the EN pin floats due to an internal pulldown resistance with a nominal value of 6.5 MΩ.
There is an internal 2-µs filter to filter noise on the EN pin. If the pin is held low longer than the filter, then the IC
shuts down. If the EN pin is taken high again after shutdown, then the sequence begins as if EN is taken high for
the first time.
7.3.2 Split Rail and External LDO
The TPS54J061 can also operate with an externally-supplied VCC. It is important that the external VCC voltage
(3.3 V ±5%) be applied and ready before at least one of the VIN or EN signals are applied. This avoids the
possibility of sinking current out of the internal LDO and thus ensures a smooth power-up sequence.
A good power-up sequence is where least one of VINUVLO rising threshold or EN rising threshold is satisfied later
than the VCCUVLO rising threshold. A practical example is: VIN applied first, then the external bias applied, and
then EN signal goes high. When the EN pin voltage rises above the enable threshold voltage, the device enters
its start-up sequence as above. A good power-down sequence is the reverse, where either the VINUVLO falling
threshold or EN falling threshold is satisfied before the VCCUVLO falling threshold.
7.3.3 Output Voltage Setting
The output voltage is programmed by the voltage-divider resistors, RFB_HS and RFB_LS, shown in Equation 1.
Connect RFB_HS between the FB pin and the positive node of the load, and connect RFB_LS between the FB pin
and AGND. TI recommends a RFB_LS value between 1 kΩ to 20 kΩ. Determine RFB_HS by using Equation 1.
RFB _ HS
VO VINTREF
u RFB _ LS
VINTREF
(1)
RFB_HS and RFB_LS should be as close to the device as possible.
7.3.4 Soft Start and Output-Voltage Tracking
The TPS54J061 implements a circuit to allow both internal fixed soft start and external adjustable soft start. The
internal soft-start time is typically 1.5 ms and has a 1-ms minimum value. The internal soft-start time can be
increased by adding a SS capacitor between SS/REFIN and AGND. The SS capacitor value can be determined
by Equation 2. Note, any CSS calculation that uses a soft-start time of less than 1.5 ms will be ignored by the
internal soft-start time circuit. Therefore, selecting a capacitor less than or equal to 22 nF will result in the internal
default 1.5 ms soft-start time (Section 8.2.2.7).
CSS
ISS u tSS
VINTREF
(2)
The SS/REFIN pin can also be used as an analog input to accept an external reference. When an external
voltage signal is applied to SS/REFIN pin, it acts as the reference voltage, thus FB voltage follows this external
voltage signal. Apply the external reference to the SS/REFIN pin before soft start. The external reference voltage
must be equal to or higher than the internal reference level to ensure correct Power Good thresholds during soft
start. With an external reference applied, the internal fixed soft start controls output voltage ramp during start-up.
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
After soft start, the external reference voltage signal can be in a range of 0.5 V to 1.2 V.
When driving the SS/REFIN pin with an external resistor divider, the resistance should be low enough so that the
external voltage source can overdrive the internal current source. Note that the internal current source remains
active.
When the TPS54J061 is enabled, an internal discharge resistance turns on to discharge external capacitance on
the SS/REFIN pin and ensure soft-start from 0 V. When the device is enabled with both VIN and EN above their
rising thresholds, 100 Ω of resistance is connected from the SS/REFIN pin to ground. After the device detects
the VCC pin is in regulation, the discharge resistance is increased to 300 Ω. The 300-Ω discharge resistance
is connected to the SS/REFIN until the MODE detection time is completed. After the MODE detection time is
completed, the TPS54J061 detects if an external reference is connected.
7.3.5 Frequency and Operation Mode Selection
The TPS54J061 provides forced CCM operation for tight output ripple application and auto-skipping Eco-Mode
for high light-load efficiency. The device allows users to select the switching frequency and operation mode by
using the MODE pin. Table 7-1 lists the resistor values for the switching frequency and operation mode selection.
TI recommends 1% tolerance resistors with a typical temperature coefficient of ±100 ppm/°C.
The MODE status is set and latched during the MODE pin calibration time. Changing the MODE pin resistance
after the calibration time will not change the status of the device.
To make sure internal circuit detects the desired setting correctly, do not place any capacitor on the MODE pin.
Table 7-1. MODE Pin Selection
MODE PIN
CONNECTIONS
OPERATION MODE UNDER LIGHT
LOAD
SWITCHING FREQUENCY
(fSW) (kHz)
Short to VCC
Skip mode
1100
243 kΩ ± 10% to AGND
Skip mode
2200
121 kΩ ± 10% to AGND
Skip mode
600
60.4 kΩ ±10% to AGND
Forced CCM
600
30.1 kΩ ±10% to AGND
Forced CCM
2200
Short to AGND
Forced CCM
1100
7.3.6 D-CAP3™ Control
The TPS54J061 uses D-CAP3 control to achieve fast load transient while maintaining ease-of-use. The D-CAP3
control architecture includes an internal ripple generation network enabling the use of very low-ESR output
capacitors such as multi-layered ceramic capacitors (MLCC). No external current sensing network or voltage
compensators are required with D-CAP3 control architecture. The role of the internal ripple generation network
is to emulate the ripple component of the inductor current information and then combine it with the voltage
feedback signal to regulate the loop. The amplitude of the ramp is determined by the R-C time-constant of
the internal circuit. At different switching frequencies (fSW), the R-C time-constant varies to maintain relatively
constant amplitude of the internally generated ripple. Also, the device uses an internal circuit to cancel the dc
offset caused by the injected ramp, which significantly reduces the DC offset caused by the output ripple voltage.
For any control topologies supporting no external compensation design, there is a minimum range or maximum
range (or both) of the output filter it can support. The output filter used with TPS54J061 is a low-pass L-C circuit.
This L-C filter has double pole that is described in Equation 3.
fP =
1
2 ´ p ´ LOUT ´ COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54J061. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade and the phase drops rapidly. The internal ripple generation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
13
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and
increases the phase by 90 degrees a decade above the zero frequency.
The inductor and capacitor selected for the output filter must be such that the double pole of Equation 3 is
located below the internal zero so that the phase boost provided by the internal zero provides adequate phase
margin to meet the loop stability requirement.
Table 7-2. Internal Zero Frequency
SWITCHING FREQUENCIES
(fSW) (kHz)
ZERO (fZ) FREQUENCY (kHz)
600
10
1100
20
2200
50
After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 20% and 40% of the maximum output current. Use Table
7-2 to help locate the internal zero based on the selected switching frequency. In general, where reasonable (or
smaller) output capacitance is desired, set the L-C double pole frequency below the internal zero frequency to
determine the necessary output capacitance for stable operation.
If MLCC output capacitors are used, derating characteristics must be accounted for to determine the final output
capacitance for the design. For example, when using an MLCC with specifications of 10-µF, X5R, and 6.3 V, the
deratings by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these
two factors, which in this case is 40% and 4 µF. Consult with capacitor manufacturers for specific characteristics
of the capacitors used
For higher output voltage at or above 2 V, additional phase boost can be required for sufficient phase margin
due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed-on-time topology based
operation.
A feedforward capacitor placed in parallel with RFB_HS is found to be very effective to boost the phase margin
at loop crossover. Refer to the Optimizing Transient Response of Internally Compensated dc-dc Converters With
Feedforward Capacitor application report for details.
7.3.7 Current Sense and Positive Overcurrent Protection
For a buck converter, during the on-time of the high-side FET, the switch current increases at a linear rate
determined by input voltage, output voltage, and the output inductor value. During the on-time of the low-side
FET, this current decreases at a linear rate determined by the output voltage and the output inductor value. The
average value of the inductor current equals to the load current, IOUT.
The output overcurrent limit (OCL) in the TPS54J061 is implemented using a cycle-by-cycle valley current
detect control circuit. The inductor current is monitored during the OFF state by measuring the low-side FET
drain-to-source current. If the measured drain-to-source current of the low-side FET is above the current limit,
the low-side FET stays ON until the current level becomes lower than the OCL level. This type of behavior
reduces the average output current sourced by the device. During an overcurrent condition, the current to the
load exceeds the current to the output capacitors and the output voltage tends to decrease. Eventually, when
the output voltage falls below the undervoltage-protection threshold (80%), the UVP comparator shuts down
the device after a wait time of 64 µs. The device will latch in the OFF state (both high-side and low-side FETs
are latched off) and then restart after an approximate 14-ms delay. If the fault condition persists, the sensing
detection, shut down and restart cycle repeats until the fault condition is removed.
If an OCL condition happens during start-up, then the device completes the charging of the soft-start capacitor,
then trips UV when soft start is complete. Delay and attempted restart function follows as above.
The resistor, RTRIP connected from the TRIP pin to AGND sets the valley current limit threshold. Equation 4
calculates the RTRIP for a given current limit threshold.
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
RTRIP
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
30000
ILIM _ VALLEY
(4)
where
•
•
ILIM_VALLEY is the valley current limit threshold in A
RTRIP is TRIP resistor value in Ω
If an RTRIP value less than 3.74 kΩ is used, the TPS54J061 will default to an internally determined current limit
clamp value.
7.3.8 Low-side FET Negative Current Limit
The device has a fixed, cycle-by-cycle negative current limit. Similar with the positive overcurrent limit, the
inductor current is monitored during the OFF state. To prevent too large negative current flowing through
low-side FET, when the low-side FET detects –3.5-A current (typical threshold), the device turns off the low-side
FET and turns on the high-side FET for the on-time determined by VIN, VOUT, and fSW. After the high-side FET
on-time expires, the low-side FET turns on again.
7.3.9 Power Good
The device has a power-good output that indicates high when the converter output is within the target. The
power-good output is an open-drain output and must be pulled up externally through a pullup resistor (usually
10 kΩ). The recommended power-good pullup resistor value is 1 kΩ to 100 kΩ. The power-good function is
activated after the soft-start operation is complete.
During start-up, PGOOD transitions HIGH after soft start is complete and the output is between the UV and OV
thresholds. If the FB voltage drops to 80% of the VINTREF voltage or exceeds 116% of the VINTREF voltage, the
power-good signal latches low after a 5-µs internal delay. When using an external reference, the power-good
thresholds are based on the external reference voltage. The power-good signal can only be pulled high again
after re-toggling EN or a reset of VCC.
If the input supply fails to power up the device, the power-good signal clamps low by itself when PGOOD is
pulled up through an external resistor.
7.3.10 Overvoltage and Undervoltage Protection
The TPS54J061 monitors the FB voltage to detect overvoltage and undervoltage. When the FB voltage becomes
lower than 80% of the VINTREF voltage, the UVP comparator detects and an internal UVP delay counter begins
counting. After the 64-µs UVP delay time, the device latches OFF both high-side and low-side FETs drivers. The
UVP function enables after the soft-start period is complete.
When the FB voltage becomes higher than 116% of the VINTREF voltage, the OVP comparator detects and the
circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative
current limit INOCL. Upon reaching the negative current limit, the low-side FET is turned off, and the high-side
FET is turned on again for the on-time determined by VIN, VOUT and fSW. The device operates in this cycle until
the output voltage is pulled down under the UVP threshold voltage for 64 µs. After the 64-µs UVP delay time,
both high-side and low-side FET latch off. The fault is cleared with a reset of the input voltage or by re-toggling
the EN pin.
During the UVP delay time, if output voltage becomes higher than UV threshold, thus is not qualified for UV
event, the timer will be reset to zero. When the output voltage triggers UV threshold again, the UVP delay timer
restarts.
7.3.11 Out-Of-Bounds Operation (OOB)
The TPS54J061 has an out-of-bounds (OOB) overvoltage protection circuit that protects the output load at
an overvoltage threshold of 5% above the VINTREF voltage. OOB protection does not trigger an overvoltage
fault, so the device is on non-latch mode after an OOB event. OOB protection operates as an early no-fault
overvoltage-protection mechanism. During the OOB operation, the controller operates in forced CCM mode. The
low-side FET turns ON, discharging the inductor current below the zero current threshold, discharging the output
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
15
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
capacitor and pulling the output voltage to the set point. During the operation, the cycle-by-cycle negative current
limit is also activated to ensure the safe operation of the internal FETs.
7.3.12 Output Voltage Discharge
When the device is disabled through EN, it enables the output voltage discharge mode. This mode forces both
high-side and low-side FETs to latch off, and turns on the approximate 80-Ω discharge FET, which is connected
from SW to PGND, to discharge the output voltage. Once the FB voltage drops below 100 mV, the internal LDO
is turned off and the discharge FET is turned off.
The output voltage discharge mode is activated by any of the following fault events:
1. EN pin goes low to disable the converter.
2. Thermal shutdown (OTP) is triggered.
3. VCC UVLO (falling) is triggered.
4. VIN UVLO (falling) is triggered.
The discharge FET will remain ON for 128 μs after leaving any of the above states.
7.3.13 UVLO Protection
The device monitors the voltage on both the VIN and the VCC pins. If the VCC pin voltage is lower than
the VCCUVLO off-threshold voltage, the device shuts off. If the VCC voltage increases beyond the VCCUVLO
on-threshold voltage, the device turns back on. VCC UVLO is a non-latch protection.
If the VIN pin voltage is lower than the VINUVLO falling-threshold voltage but VCC pin voltage is still higher
than VCCUVLO on-threshold voltage, the device stops switching and discharges SS. If the VIN voltage increases
beyond the VINUVLO rising-threshold voltage, the device initiates the soft start and switches again. VIN UVLO is
a non-latch protection.
7.3.14 Thermal Shutdown
If the internal junction temperature exceeds the threshold value (typically 170°C), the device stops switching and
discharges SS. When the temperature falls approximately 38°C below the threshold value, the device turns back
on with a initiated soft start. Thermal shutdown is a non-latch protection.
16
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
7.4 Device Functional Modes
7.4.1 Auto-Skip Eco-Mode Light Load Operation
While the MODE pin is pulled to VCC directly or connected to AGND pin through a resistor larger than 121 kΩ,
the device automatically reduces the switching frequency at light-load conditions to maintain high efficiency. This
section describes the operation in detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches IZC, the zero-cross detection current threshold. IZC is the boundary
between the continuous-conduction and discontinuous-conduction modes. The synchronous MOSFET turns
off when this zero inductor current is detected. As the load current decreases further, the converter runs into
discontinuous-conduction mode (DCM). After 16 consecutive detections of zero crossings, the TPS54J061
enters Eco-Mode and the switching frequency begins to decrease. The on-time is maintained to a level
approximately the same as during continuous-conduction mode operation so that discharging the output
capacitor with a smaller load current to the level of the reference voltage requires more time. The transition
point to the light-load operation IOUT(LL) (for example, the threshold between continuous- and discontinuousconduction mode) is calculated as shown in Equation 5.
IOUT(LL ) =
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
(5)
where
•
fSW is the PWM switching frequency
Only using ceramic capacitors is recommended for auto-skip mode.
7.4.2 Forced Continuous-Conduction Mode
When the MODE pin is tied to the AGND pin through a resistor less than 60.4 kΩ, the controller operates
in continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency is
maintained to an almost constant level over the entire load range which is suitable for applications requiring tight
control of the switching frequency at the cost of lower efficiency.
7.4.3 Pre-Bias Start-up
When the TPS54J061 begins soft start, internal circuitry detects if there is a voltage already present on the
output. This can be due to a leakage current path in a multi-rail system charging the output capacitors. If the
pre-biased voltage is greater than the output voltage commanded by the soft-start voltage, the TPS54J061
operates in Pulse-skip mode during the rise of soft start. When the soft-start voltage reaches a point where the
commanded output voltage is greater than the pre-bias voltage, normal switching occurs.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
17
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS54J061 is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The device
suits low output voltage point-of-load applications with 6-A or lower output current in server, storage, and
similar computing applications. The device features proprietary D-CAP3 control combined with adaptive on-time
architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC converters
in an ideal fashion. The output voltage ranges from 0.9 V to 5.5 V. The conversion input voltage ranges from
2.7 V to 16 V and the VCC input voltage ranges from 3.0 V to 3.6 V. The D-CAP3 control uses emulated
current information to control the modulation. An advantage of this control scheme is that it does not require
a phase-compensation network outside which makes the device easy-to-use and also allows low external
component count. Further advantage of this control scheme is that it supports stable operation with all ceramic
output capacitors. Adaptive on-time control tracks the preset switching frequency over a wide range of input and
output voltage while increasing switching frequency as needed during a load-step transient.
8.2 Typical Application
This design example describes a D-CAP3 type, 6-A synchronous buck converter with integrated MOSFETs. The
device provides a fixed 1.8-V output at up to 6 A from a 12-V input bus.
Input Voltage: 12 V Nominal
J1
VIN
2
1
CBULK
100uF
INPUT
CI1
1206
25V
10uF
CI2
1206
25V
10uF
CI3
0603
25V
4.7uF
CI4
0603
25V
4.7uF
CI5
0.1uF
0402
25V
U1
3
5
PGND
REN_T
499k
J3
VCC
RVCC
0
3.3k
9
PGOOD
MODE 12
EN
EN_OFF
ILIM
4
8
REN_B
100k
BOOT
EN
SW
SW
TP1
RPG
TP2
2
1
VCC
VIN
RMODE RTRIP
DNP
4.99k
0
PGOOD
FB
VCC
AGND
0
11
2
TRIP
PGND
PGND
SS/REFIN
TPS54J061RPGR
Output Voltage: 1.8 V at 6 A
LO
CBOOT
OUTPUT
VOUT
1uH
220nF
CO1
0402
6.3V
0.1uF
SW
6
FB
13
VCC
CO2
0805
6.3V
47uF
CO3
0805
6.3V
47uF
CO4
0805
6.3V
47uF
CO5
0805
6.3V
47uF
CO6
0805
6.3V
47uF
CO7
0805
6.3V
47uF
1
2
J2
PGND
PGND
MODE
AGND
CSS
22nF
RBOOT
10
RFB_T
1
14
7
CVCC
4.7µF
CFF
NT1
Net-Tie
AGND
PGND
RBODE
1.00k
RFB_B
499
4.7nF
10.0
TP3
BODE-
TP4
BODE+
RBODE for testing purposes only
AGND
Figure 8-1. Application Circuit Diagram
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
8.2.1 Design Requirements
This design uses the parameters listed in Table 8-1.
Table 8-1. Design Example Specifications
DESIGN PARAMETER
CONDITIONS
MIN
TYP
MAX
8
12
16
UNIT
VIN
Voltage range
VOUT
Output voltage
ILOAD
Output load current
VRIPPLE
Output voltage DC ripple
10
mVPP
VTRANS
Output voltage undershoot and IOUT = 25% to 75% step, 1 A/µs slew rate
overshoot after load step
18
mV
IOUT_LIM
Output over current limit
6.6
A
tSS
Soft-start time
1.5
ms
fSW
Switching frequency
1100
kHz
1.8
V
6
VIN = 12 V, IOUT = 6 A (CCM)
VIN = 8 V
V
A
8.2.2 Detailed Design Procedure
The external components selection is a simple process using D-CAP3 control mode. Select the external
components using the following steps.
8.2.2.1 Choose the Switching Frequency and Operation Mode (MODE Pin)
The switching frequency and light load mode of operation are configured by the resistor on the MODE pin.
From Table 7-1, the MODE pin is connected to VCC to set a 1100-kHz switching frequency with discontinuous
conduction mode and skip mode enabled at light loads.
When selecting the switching frequency of a buck converter, the minimum on-time and minimum off-time must
be considered. Equation 6 calculates the maximum fSW before being limited by the minimum on-time. When
hitting the minimum on-time limits of a converter with D-CAP3 control, the effective switching frequency will
change to keep the output voltage regulated. This calculation ignores resistive drops in the converter to give a
worst case estimation.
fSW max
VOUT
1
u
VIN max t ON _ MIN max
1.8 V
1
u
16 V 95 ns
1180 kHz
(6)
Equation 7 calculates the maximum fSW before being limited by the minimum off-time. When hitting the minimum
off-time limits of a converter with D-CAP3 control, the operating duty cycle will max out and the output voltage
will begin to drop with the input voltage. This equation requires the DC resistance of the inductor, RDCR,
selected in the following step so this preliminary calculation assumes a resistance of 10 mΩ. If operating near
the maximum fSW limited by the minimum off-time, the variation in resistance across temperature must be
considered when using Equation 7. The selected fSW of 1100 kHz is below the two calculated maximum values.
fSW max
fSW max
VIN min
VOUT
t OFF _ MIN max u VIN min
8 V 1.8 V
220 ns u 8 V
IOUT max u RDCR
RDS ON
IOUT max u RDS ON
6 A u 10 m : 25 m :
6 A u 25 m: 9.2 m:
_ HS
_ HS
RDS ON
_ LS
3360 kHz
(7)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
19
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
8.2.2.2 Choose the Output Inductor (L)
Calculate the inductance value to set the ripple current at approximately 0.3 times the output current using
Equation 8. Larger ripple current improves transient response and improves signal-to-noise ratio with the tradeoff
of increased steady state output voltage ripple. Smaller ripple current reduces steady state output voltage ripple
with the tradeoff of slower transient response and can increase jitter. The target ripple current must be between
0.6 A and 3 A. Based on the result of Equation 8, a standard inductance value of 1 µH was selected.
L
VIN max
VOUT u VOUT
16 V 1.8 V u 1.8 V
IRIPPLE u VIN max u fSW
0.3 u 6 A u 16 V u 1100 kHz
0.81 +
(8)
Equation 9 calculates the ripple current with the selected inductance. Equation 10 calculates the peak current in
the inductor and the saturation current rating of the inductor should be greater than this. The saturation behavior
of the inductor at the peak inductor current at current limit must also be considered when choosing the inductor.
Equation 11 calculates the RMS current in the inductor and the heat current rating of the inductor should be
greater than this.
IRIPPLE
VIN max
VOUT u VOUT
L u VIN max u fSW
IL PEAK
IOUT
IL RMS
IOUT 2
IRIPPLE
2
6A
IRIPPLE2
16 V 1.8 V u 1.8 V
1 +u
1.45 A
2
6 A2
9u
1.45 A
N+]
(9)
6.73 A
1.45 A 2
(10)
6.17 A
(11)
The selected inductance is a CMLE063T-1R0. This has a saturation current rating of 14 A, RMS current rating of
16 A and a DCR of 6.5 mΩ max. This inductor was selected for its low DCR to get high efficiency.
8.2.2.3 Set the Current Limit (TRIP)
The RTRIP resistor sets the valley current limit. Equation 12 calculates the recommended current limit target.
This includes the tolerance of the inductor and a factor of 0.85 for the tolerance of the current limit threshold.
Equation 13 calculates the RTRIP resistor to set the current limit. The typical valley current limit target is 6 A and
the closest standard value for RTRIP is 4.99 kΩ.
ILIM _ VALLEY
ILIM _ VALLEY
RTRIP
§
VIN min VOUT u VOUT ·
1
1
¨ IOUT
¸u
u
¨
¸
2 L u 1 L TOL u VIN min u fSW ¹ 0.85
©
§
·
8 V 1.8 V u 1.8 V
1
1
u
¨¨ 6 A
¸¸ u
2 1 µH u 1 0.2 u 8 V u 1100 kHz ¹ 0.85
©
30000
ILIM _ VALLEY
30000
6A
6.44 A
(12)
5.0 k:
(13)
With the current limit set, Equation 14 calculates the typical maximum output current at current limit. Equation 15
calculates the typical peak current at current limit. As mentioned in Section 8.2.2.2, the saturation behavior of the
inductor at the peak current during current limit must be considered. For worst case calculations, the tolerance of
the inductance and the current limit must be included.
IOUT _ LIM min
20
ILIM _ VALLEY
1 VIN min VOUT u VOUT
u
2
L u VIN min u fSW
6A
Submit Document Feedback
8 V 1.8 V u 1.8 V
1
u
2 1 µH u 8 V u 1100 kHz
6.6 A
(14)
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
IL PEAK
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
ILIM _ VALLEY
VIN max
VOUT u VOUT
6A
L u VIN max u fSW
16 V 1.8 V u 1.8 V
1 µH u 16 V u 1100 kHz
7.45 A
(15)
8.2.2.4 Choose the Output Capacitors (COUT)
There are three considerations for selecting the value of the output capacitor:
1. Stability
2. Steady state output voltage ripple
3. Regulator transient response to a change load current
First, the minimum output capacitance should be calculated based on these three requirements. Equation
16 calculates the minimum capacitance to keep the LC double pole below 1/30th the fSW to meet stability
requirements. This requirement helps to keep the LC double pole close to the internal zero. See Table 7-2 for the
location of the internal zero. Equation 17 calculates the minimum capacitance to meet the steady state output
voltage ripple requirement of 10 mV. This calculation is for CCM operation and does not include the portion of
the output voltage ripple caused by the ESR or ESL of the output capacitors.
2
§ 15 ·
1
COUT _ STABILITY ! ¨
¸ u
© S u fSW ¹ L
COUT _ RIPPLE !
IRIPPLE
8 u VRIPPLE u fSW
2
15
1
§
·
¨ S u 1100 kHz ¸ u 1 µH
©
¹
1.45 A
8 u 10 mV u 1100 kHz
19 µF
(16)
16.5 µF
(17)
Equation 18 and Equation 19 calculate the minimum capacitance to meet the transient response requirement of
18 mV with a 3-A step. These equations calculate the necessary output capacitance to hold the output voltage
steady while the inductor current ramps up or ramps down after a load step.
COUT _ UNDERSHOOT
COUT _ UNDERSHOOT
§
·
VOUT
L u ISTEP2 u ¨
tOFF _ MIN max ¸
¨ V min u f
¸
SW
© IN
¹
!
§ VIN min VOUT
·
2 u VTRANS u VOUT u ¨
t OFF _ MIN max ¸
¨ V min u f
¸
SW
© IN
¹
1.8 V
§
·
1 µH u 3 A 2 u ¨
220 ns ¸
8
V
1100
kHz
u
©
¹
!
122 µF
§ 8 V 1.8 V
·
2 u 18 mV u 1.8 V u ¨
220 ns ¸
© 8 V u 1100 kHz
¹
COUT _ OVERSHOOT !
L u ISTEP2
2 u VTRANS u VOUT
1 µH u 3 A 2
2 u 18 mV u 1.8 V
(18)
139 µF
(19)
The output capacitance needed to meet the overshoot requirement is the highest value so this sets the
required minimum output capacitance for this example. Stability requirements can also limit the maximum output
capacitance and Equation 20 calculates the recommended maximum output capacitance. This calculation keeps
the LC double pole above 1/100th the fSW. It can be possible to use more output capacitance but the stability
must be checked through a bode plot or transient response measurement. The selected output capacitance is
6x 47-µF 0805 6.3-V ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due
to DC and AC bias effects. The selected capacitors derate to 60% their nominal value giving an effective total
capacitance of 169 µF. This effective capacitance meets the minimum and maximum requirements.
2
COUT _ STABILITY
§ 50 · 1
¨
¸ u
© S u fSW ¹ L
2
50
1
§
·
¨ S u 1100 kHz ¸ u 1 µH
©
¹
209 µF
(20)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
21
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If
using non-ceramic capacitors, as a starting point, the ESR should be below the values calculated in Equation
21 to meet the ripple requirement and Equation 22 to meet the transient requirement. For more accurate
calculations or if you are using mixed output capacitors, the impedance of the output capacitors should be used
to determine if the ripple and transient requirements can be met.
RESR _ RIPPLE
VRIPPLE
IRIPPLE
10 mV
1.45 A
6.9 m:
RESR _ TRANS
VTRANS
ISTEP
18 mV
3A
6.0 m:
(21)
(22)
8.2.2.5 Choose the Input Capacitors (CIN)
The TPS54J061 requires input bypass capacitors between the VIN and PGND pins to bypass the power-stage.
The bypass capacitors must be placed as close as possible to the pins of the IC as the layout will allow. At least
10-µF of ceramic capacitance and a 0.01-µF to 0.1-µF high frequency ceramic bypass capacitor is required.
The high frequency bypass capacitor minimizes high frequency voltage overshoot across the power-stage. The
ceramic capacitors must be high-quality dielectric of X5R or X7R for their high capacitance-to-volume ratio and
stable characteristics across temperature. In addition to this, more bulk capacitance can be needed on the input
depending on the application to minimize variations on the input voltage during transient conditions.
The input capacitance required to meet a specific input ripple target can be calculated with Equation 23.
A recommended target input voltage ripple is 5% the minimum input voltage, 400-mV in this example. The
calculated input capacitance is 2.4 µF and the minimum input capacitance of 10 µF exceeds this. This example
meets these two requirements with two 4.7-µF 0603 25-V ceramic capacitors and two 10-µF 1206 25-V ceramic
capacitors.
CIN
§
VOUT ·
VOUT u IOUT u ¨ 1
¸
¨
VIN min ¸¹
©
!
fSW u VIN min u VIN _ RIPPLE
§ 1.8 V ·
1.8 V u 6 A u ¨ 1
8 V ¸¹
©
1100 kHz u 8 V u 400 mV
2.4 )
(23)
The capacitor must also have an RMS current rating greater than the maximum input RMS current in the
application. The input RMS current the input capacitors must support is calculated by Equation 24 and is 2.5 A in
this example. The ceramic input capacitors have a current rating much greater than this.
ICIN RMS
IOUT u
VIN min VOUT
VOUT
u
VIN min
VIN min
6 Au
1.8 V 8 V 1.8 V
u
8V
8V
2.5 A
(24)
For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current,
the selection process in this article is recommended.
8.2.2.6 Feedback Network (FB Pin)
The output voltage is programmed by the voltage-divider resistors, RFB_T and RFB_B, shown in Equation 25.
Connect RFB_T between the FB pin and the output, and connect RFB_B between the FB pin and AGND. The
recommended RFB_B value is from 499 Ω to 20 kΩ. Determine RFB_T using Equation 25.
RFB _ T
22
§V
RFB _ B u ¨ OUT
© VREF
·
1¸
¹
§ 1.8 V
·
499 : u ¨
1¸
0.6
V
©
¹
1.00 k:
Submit Document Feedback
(25)
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
In most applications, a feedforward capacitor (CFF) in parallel with RFB_T is recommended. CFF can improve the
transient response and increase the phase margin. CFF can be required for sufficient phase margin if the output
voltage is greater than 1.8 V or if the LC double pole frequency is below fSW/60. The frequency of the LC double
pole for this application is calculated with Equation 26 to be 12.2 kHz. This is less than fSW / 60 so CFF is used.
fLC
1
1
2S u L u COUT
2S u 1 µH u 169 µF
12.2 kHz
(26)
The recommended value for CFF is calculated with Equation 27. This equation selects CFF to put a zero at fLC ×
3. In this example, the calculated value is 4340 pF and a standard value of 4700 pF is used. For higher output
voltages, the zero from CFF should be closer to the LC double pole. For example, for a 5-V application, the zero
from CFF should be placed at or even below the LC double pole.
CFF
1
1
2S u 1.00 k: u 3 u 12.2 kHz
2S u RFB _ T u 3 u fLC
4340 pF
(27)
8.2.2.7 Soft Start Capacitor (SS/REFIN Pin)
The capacitor placed on the SS/REFIN pin can be used to extend the soft-start time past the internal 1.5-ms soft
start. This example uses a 1.5-ms soft-start time and the required external capacitance can be calculated with
Equation 28. In this example, a 22-nF capacitor is used.
CSS
ISS u tSS
VREF
9 µA u 1.5 ms
0.6 V
22.5 nF
(28)
Note
A minimum capacitor value of 1 nF is required at the SS/REFIN pin to help bypass noise. Also, the
SS/REFIN capacitor must use the AGND pin for its ground. Note, any CSS calculation that uses a
soft-start time of less than 1.5 ms will be ignored by the internal soft-start time circuit. Therefore,
selecting a capacitor less than or equal to 22 nF will result in the internal default 1.5 ms soft-start time.
8.2.2.8 EN Pin Resistor Divider
A resistor divider on the EN pin can be used to increase the input voltage and the converter begins its
start-up sequence. Increasing the input voltage the converter starts up at can be useful in high output voltage
applications. The resistor divider can be selected so the converter starts switching after the input voltage is
greater than the output voltage. If the output voltage comes up before the input voltage is sufficient, UVP can be
tripped and cause the converter to latch off.
To set the start voltage, first select the bottom resistor (REN_B). The recommended value is between 1 kΩ and
100 kΩ. There is an internal pulldown resistance with a nominal value of 6 MΩ, which must be included for the
most accurate calculations. This is especially important when the bottom resistor is a higher value, near 100
kΩ. This example uses a 100-kΩ resistor and this combined with the internal resistance in parallel results in
an equivalent bottom resistance of 98.4 kΩ. The top resistor value for the target start voltage is calculated with
Equation 29. In this example, the nearest standard value of 499 kΩ is selected for REN_T.
REN _ T
REN _ B u VSTART
VENH
REN _ B
98.4 k: u 7.4 V
1.22 V
98.4 k:
498 k:
(29)
The start and stop voltages with the selected EN resistor divider can be calculated with Equation 28 and
Equation 31.
VSTART
VENH u
REN _ B
REN _ T
REN _ B
1.22 V u
98.4 k: 499 k:
98.4 k:
7.41 V
(30)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
23
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
VSTOP
VENL u
REN _ B
REN _ T
REN _ B
1.02 V u
98.4 k: 499 k:
98.4 k:
6.19 V
(31)
8.2.2.9 VCC Bypass Capacitor
At a minimum, a 1-µF ceramic bypass capacitor is needed on the VCC pin located as close to the pin as the
layout will allow.
8.2.2.10 BOOT Capacitor
At a minimum, a 0.1-µF ceramic bypass capacitor is needed between the BOOT and SW pins located as close
to the pin as the layout will allow.
8.2.2.11 Series BOOT Resistor and RC Snubber
A series BOOT resistor can help reduce the overshoot at the SW pin. As a best practice, include a 0-Ω series
BOOT resistor in the design for 12-V or higher input applications. The BOOT resistor can be used to reduce the
voltage overshoot on the SW pin to within the Absolute Maximum Ratings in case the overshoot is higher than
normal due to parasitic inductance in PCB layout. Including a 0-Ω BOOT resistor is recommended with external
VCC as the SW node overshoot is increased. The recommended BOOT resistor value to decrease the SW pin
overshoot is 4.7 Ω.
An RC snubber on the SW pin can also help reduce the high frequency voltage spikes and ringing at the SW
pin. Recommended snubber values are 6.8 Ω and 220 pF. The best value for these components can vary
with different layouts but these recommended values should provide a good starting point. In order for the RC
snubber to be as effective as possible, it should be placed on the same side as the IC and be as close as
possible to the SW pins with a very low impedance return to PGND pins.
8.2.2.12 PGOOD Pullup Resistor
The PGOOD pin is open-drain so a pullup resistor is required when using this pin. The recommended value is
between 1 kΩ and 100 kΩ.
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
8.2.3 Application Curves
100
100
95
90
80
90
Efficiency (%)
Efficiency (%)
70
85
80
75
60
50
40
30
70
VIN = 5 V
VIN = 8 V
VIN = 12 V
VIN = 16 V
65
10
0
0.001
60
0
0.5
1
VOUT = 1.8 V
VCC = Int 3.0 V
1.5
2
2.5 3 3.5 4
Output Current (A)
fSW = 1100 kHz
4.5
5
5.5
6
MODE = FCCM
Figure 8-2. Efficiency – 1100 kHz, FCCM
100
95
95
90
90
80
75
fSW = 1100 kHz
1
2 3 4 5 7 10
MODE = DCM
Figure 8-3. Efficiency – 1100 kHz, DCM
100
85
0.01 0.02 0.05 0.1 0.2 0.5
Output Current (A)
VOUT = 1.8 V
VCC = Int 3.0 V
Efficiency (%)
Efficiency (%)
VIN = 5 V
VIN = 8 V
VIN = 12 V
VIN = 16 V
20
70
85
80
75
70
VIN = 8 V
VIN = 12 V
VIN = 16 V
65
VIN = 3.3 V
VIN = 5 V
VIN = 8 V
65
60
60
0
0.5
VOUT = 1.8 V
VCC = Ext 3.3 V
1
1.5
2
2.5 3 3.5 4
Output Current (A)
fSW = 1100 kHz
RBOOT = 4.7 Ω
4.5
5
5.5
6
MODE = FCCM
Figure 8-4. Efficiency – 1100 kHz, FCCM, External
3.3-V VCC, 4.7-Ω RBOOT
0
0.5
VOUT = 1.8 V
VCC = Ext 3.3 V
1
1.5
2
2.5 3 3.5 4
Output Current (A)
fSW = 1100 kHz
RBOOT = 0 Ω
4.5
5
5.5
6
MODE = FCCM
Figure 8-5. Efficiency – 1100 kHz, FCCM, External
3.3-V VCC, 0-Ω RBOOT
100
90
80
Efficiency (%)
70
60
50
40
30
20
VIN = 3.3 V
VIN = 5 V
VIN = 8 V
10
0
0.001
VOUT = 1.8 V
VCC = Ext 3.3 V
fSW = 1100 kHz
RBOOT = 4.7 Ω
MODE = DCM
Figure 8-6. Efficiency – 1100 kHz, DCM, External
3.3-V VCC, 4.7-Ω RBOOT
VOUT = 1.8 V
VCC = Ext 3.3 V
0.01 0.02 0.05 0.1 0.2 0.5
Output Current (A)
fSW = 1100 kHz
RBOOT = 0 Ω
1
2 3 4 5 7 10
MODE = DCM
Figure 8-7. Efficiency – 1100 kHz, DCM, External
3.3-V VCC, 0-Ω RBOOT
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
25
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
100
100
95
90
80
90
Efficiency (%)
Efficiency (%)
70
85
80
75
60
50
40
30
70
VIN = 5 V
VIN = 8 V
VIN = 12 V
VIN = 16 V
65
10
60
0
0.5
1
VOUT = 1.8 V
VCC = Int 3.0 V
1.5
2
2.5 3 3.5 4
Output Current (A)
fSW = 600 kHz
4.5
5
5.5
0
0.001
6
MODE = FCCM
VOUT = 1.8 V
VCC = Int 3.0 V
Figure 8-8. Efficiency – 600 kHz, FCCM
0.01 0.02 0.05 0.1 0.2 0.5
Output Current (A)
fSW = 600 kHz
1
2 3 4 5 7 10
MODE = DCM
Figure 8-9. Efficiency – 600 kHz, DCM
1.82
1.82
VIN = 8 V
VIN = 12 V
VIN = 16 V
VIN = 5 V
1.816
1.812
1.812
1.808
1.804
1.8
1.796
1.792
1.808
1.804
1.8
1.796
1.792
1.788
1.788
1.784
1.784
1.78
0
0.5
1
VOUT = 1.8 V
1.5
2
2.5 3 3.5 4
Output Current (A)
fSW = 1100 kHz
4.5
5
5.5
VIN = 8 V
VIN = 12 V
VIN = 16 V
VIN = 5 V
1.816
Output Voltage (V)
Output Voltage (V)
VIN = 5 V
VIN = 8 V
VIN = 12 V
VIN = 16 V
20
6
MODE = FCCM
Figure 8-10. Output Voltage vs Output Current –
FCCM
1.78
0.001
VOUT = 1.8 V
0.01 0.02 0.05 0.1 0.2 0.5
Output Current (A)
fSW = 1100 kHz
1
2 3 4 5 7 10
MODE = DCM
Figure 8-11. Output Voltage vs Output Current –
DCM
1.82
IOUT = 0 A, DCM
IOUT = 0 A, FCCM
IOUT = 3 A
IOUT = 6 A
1.816
Output Voltage (V)
1.812
1.808
1.804
1.8
1.796
1.792
1.788
1.784
1.78
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Input Voltage (V)
VOUT = 1.8 V
fSW = 1100 kHz
Figure 8-12. Output Voltage vs Input Voltage
26
VOUT = 1.8 V
fSW = 1100 kHz
MODE = FCCM
Figure 8-13. Switching Frequency vs Output
Current – 1100 kHz
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
VOUT = 1.8 V
fSW = 600 kHz
MODE = FCCM
Figure 8-14. Switching Frequency vs Output
Current – 600 kHz
VIN = 12 V
RLOAD = 0.3 Ω
Figure 8-16. EN Start-Up
VIN = 12 V
RLOAD = 0.3 Ω
Figure 8-15. EN Start-Up
VIN = 12 V
IOUT = 0 A
MODE = DCM
Figure 8-17. EN Start-Up – DCM
VOUT (1 V/div)
IOUT (5 A/div)
EN (2 V/div)
PGOOD (2 V/div)
Time (100 µs/div)
VIN = 12 V
RLOAD = 0.3 Ω
Figure 8-18. EN Shutdown
RLOAD = 0.3 Ω
Figure 8-19. VIN Start-Up
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
27
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
VOUT (1 V/div)
SW (5 V/div)
VIN (10 V/div)
VOUT AC (20 mV/div)
IOUT (5 A/div)
IOUT (2 A/div)
EN (1 V/div)
Time (20 µs/div)
Time (4 ms/div)
VIN = 12 V
MODE = FCCM
RLOAD = 0.3 Ω
Figure 8-20. VIN Shutdown
0.1 A to 3.1 A step
1 A/µsec
Figure 8-21. Load Transient – FCCM
Gain (dB)
SW (5 V/div)
VOUT AC (20 mV/div)
60
180
40
120
20
60
0
0
-20
-40
IOUT (2 A/div)
-60
-60
1000 2000
Time (20 µs/div)
VIN = 12 V
MODE = DCM
0.1 A to 3.1 A step
1 A /µsec
-120
Gain
Phase
5000 10000
100000
Frequency (Hz)
VIN = 12 V
-180
1000000
IOUT = 6 A
Figure 8-23. Bode Plot
Figure 8-22. Load Transient – DCM
SW (5 V/div)
SW (5 V/div)
VOUT AC (20 mV/div)
VOUT AC (20 mV/div)
Time (1 µs/div)
VIN = 12 V
ILOAD = 0.1 A
Time (4 µs/div)
MODE = FCCM
Figure 8-24. Output Voltage Ripple
28
VIN = 12 V
ILOAD = 0.1 A
MODE = DCM
Figure 8-25. Output Voltage Ripple – DCM
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
SW (5 V/div)
VOUT AC (20 mV/div)
Time (1 µs/div)
VIN = 12 V
ILOAD = 6 A
Figure 8-26. Output Voltage Ripple
VIN = 12 V
IOUT = 0 A
Prebias = 1.0 V
Figure 8-27. EN Start-Up With Prebias
SW (10 V/div)
VOUT (500 mV/div)
VOUT (1 V/div)
IOUT (5 A/div)
IL (2 A/div)
PGOOD (2 V/div)
Time (100 µs/div)
VIN = 12 V
Time (100 µs/div)
IOUT = 7.5-A Constant Current
Figure 8-28. Overcurrent Response
VIN = 12 V
IOUT = 7.5-A Constant Current
Figure 8-29. Overcurrent Response
SW (5 V/div)
SW (5 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
IL (5 A/div)
IOUT (5 A/div)
Time (20 µs/div)
VIN = 12 V
Time (4 ms/div)
IOUT = Short
Figure 8-30. Short Circuit Response
VIN = 12 V
IOUT = 7.5-A Constant Current
Figure 8-31. Overcurrent Enter Hiccup
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
29
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
SW (5 V/div)
VOUT (1 V/div)
IOUT (5 A/div)
Time (4 ms/div)
VIN = 12 V
IOUT = 7.5-A Constant Current
Figure 8-32. Overcurrent Exit Hiccup
30
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.7 V and 16 V. If you are
using an input voltage below 4.0 V, the VCC pin requires external bias. Proper bypassing of input supplies (VIN)
and internal LDO (VCC) is also critical for noise performance, as is PCB layout and grounding scheme. See the
recommendations in Section 10.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
31
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
10 Layout
10.1 Layout Guidelines
Before beginning a design using the device, consider the following:
• A 0402 sized 0.01-µF to 0.1-µF decoupling capacitor should be placed as close as possible to the VIN and
PGND pins to decouple high frequency noise and help reduce switch node ringing. Larger VIN decoupling
capacitors should be placed as close as possible to VIN and PGND pins behind this capacitor to further
minimize the input AC-current loop.
• Place the power components (including input and output capacitors, the inductor, and the IC) on the solder
side of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert and
connect at least one inner plane to ground.
• All sensitive analog traces and components such as FB, PGOOD, TRIP, MODE, and SS/REFIN must be
placed away from high-voltage switching nodes such as SW and BOOT to avoid coupling. Use internal layers
as ground planes and shield the feedback trace from power traces and components.
• Place the feedback resistor near the device to minimize the FB trace distance.
• Place the OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE) close to the device. Use the
common AGND via to connect the resistors to the VCC PGND plane if applicable.
• Place the VCC decoupling capacitors as close as possible to the device. If multiple capacitors are used,
provide PGND vias for each decoupling capacitor and ensure the return path is as small as possible.
• Keep the switch node connections from pins 2 and 11 to the inductor as short and wide as possible.
• Use separate traces to connect SW node to the bootstrap capacitor and RC snubber, if used, instead of
combining them into one connection. Keep both the BOOT and snubber paths short for low inductance and
the best possible performance. Also, to minimize inductance, avoid using vias for the RC snubber routing and
use very wide traces. To be most effective, the RC snubber should be connected between a large SW copper
shape and large PGND copper shape on the same side of the PCB as the TPS54J061.
• Avoid connecting AGND to the PCB ground plane (PGND) in a high current path where significant IR and
L*dI/dt drops can occur.
32
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
10.2 Layout Example
Vias to PGND
Figure 10-1. Top Layer Layout
PGND Plane
Figure 10-2. Signal Layer 1 Layout
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
33
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
PGND Plane
VCC Trace
MODE Trace
EN Trace
Trace from FB divider to VOUT
Avoid routing near noise
Figure 10-3. Signal Layer 2 Layout
PGND Plane
VOUT Plane
Trace to EN input
Trace to PGOOD output
Figure 10-4. Bottom Layer Layout (Viewed from Top)
34
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Trademarks
D-CAP3™ and Eco-mode™, are trademarks of TI.
Hotrod™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
35
TPS54J061
www.ti.com
SLVSFQ0A – OCTOBER 2020 – REVISED JUNE 2021
12 Mechanical, Packaging, and Ordering Information
The following pages include mechanical, packaging, and ordering information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54J061
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54J061RPGR
ACTIVE
VQFN-HR
RPG
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
54J061
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
