TPS55340QRTERQ1

TPS55340-Q1 SLVSBV5C – JUNE 2014 – REVISED SEPTEMBER 2021 TPS55340-Q1 Integrated 5-A, Wide Input Range Boost, SEPIC, or Flyback DC/DC Converter 1 Features 3 Description • • The TPS55340-Q1 device is a monolithic nonsynchronous switching converter with an integrated 5-A, 40-V power switch. The device can be configured in several standard switching regulator topologies, including boost, SEPIC, and isolated flyback. The device has a wide input voltage range to support applications with input voltage from 2.9 V to 38 V. • • • • • • • The TPS55340-Q1 device regulates the output voltage with current mode PWM (pulse width modulation) control, and has an internal oscillator. The switching frequency of PWM is set by either an external resistor or by synchronizing to an external clock signal. The user can program the switching frequency from 100 kHz to 2.5 MHz. The device features a programmable soft-start function to limit inrush current during start-up and has other built-in protection features including cycleby-cycle overcurrent limit and thermal shutdown. The TPS55340-Q1 device is available in a small 3mm × 3-mm 16-pin WQFN package with PowerPad for enhanced thermal performance. Device Information 2 Applications • • • • PART NUMBER Boost, SEPIC, and flyback topologies Automotive pre-boost applications to support startstop requirements USB power delivery Industrial power systems L VI D TPS55340-Q1 (1) PACKAGE(1) BODY SIZE (NOM) WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. 100 VO 95 CI TPS55340-Q1 VIN SW EN SW FREQ SW SS R(FREQ) CSS R(C) 85 R(SH) FB COMP PGND SYNC PGND AGND PGND 90 CO Efficiency (%) • • • • • • • Qualified for automotive applications AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to 125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C6 Internal 5-A, 40-V low-side MOSFET switch 2.9 to 38-V input voltage range ±0.7% reference voltage 0.5-mA operating quiescent current 2.7-µA shutdown supply current Fixed-frequency current mode PWM control Frequency adjustable from 100 kHz to 2.5 MHz (see Section 7.3.2) Synchronization capability to external clock Adjustable soft-start time Pulse-skipping for higher efficiency at light loads Cycle-by-cycle current-limit, thermal shutdown, and UVLO protection WQFN-16 (3 mm × 3 mm) package with PowerPad™ Wide –40°C to +150°C operating TJ range Create a custom design using the TPS55340-Q1 with the WEBENCH Power Designer 80 75 70 65 R(SL) C(C) 60 55 VO = 24 V VI VI = =5 5V V VI 12 V V VI == 12 ƒS = 600 kHz VI == 15 VI 15 V V 50 0.0 Typical Application for Boost 0.4 0.8 1.2 1.6 2.0 Output Current (A) 2.4 C021 Efficiency Versus Output Current An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS55340-Q1 www.ti.com SLVSBV5C – JUNE 2014 – REVISED SEPTEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Typical Characteristics................................................ 6 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Feature Description.....................................................9 7.4 Device Functional Modes..........................................12 8 Application and Implementation.................................. 14 8.1 Application Information............................................. 14 8.2 Typical Applications.................................................. 14 9 Power Supply Recommendations................................29 10 Layout...........................................................................30 10.1 Layout Guidelines................................................... 30 10.2 Layout Example...................................................... 30 11 Device and Documentation Support..........................31 11.1 Device Support........................................................31 11.2 Receiving Notification of Documentation Updates.. 31 11.3 Support Resources................................................. 31 11.4 Trademarks............................................................. 31 11.5 Electrostatic Discharge Caution.............................. 31 11.6 Glossary.................................................................. 31 12 Mechanical, Packaging, and Orderable Information.................................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2019) to Revision C (September 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document. ................1 Changes from Revision A (July 2016) to Revision B (January 2019) Page • Added links for Webench ...................................................................................................................................1 • Added text note under pin configuration diagram. ............................................................................................. 3 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-Q1 TPS55340-Q1 www.ti.com SLVSBV5C – JUNE 2014 – REVISED SEPTEMBER 2021 SW SW NC PGND 5 Pin Configuration and Functions 16 15 14 13 SW 1 12 PGND VIN 2 11 PGND EN 3 10 NC SS 4 PowerPAD 5 6 7 8 SYNC AGND COMP FB 9 FREQ TI recommends connecting NC with AGND. Figure 5-1. 16-Pin QFN With PowerPAD RTE Package (Top View) Table 5-1. Pin Functions PIN NAME DESCRIPTION NO. AGND 6 Signal ground of the IC COMP 7 Output of the transconductance error amplifier. An external RC network connected to this pin compensates the regulator feedback loop. EN 3 Enable pin. When the voltage of this pin falls below the enable threshold for more than 1 ms, the IC turns off. FB 8 Error amplifier input and feedback pin for positive voltage regulation. Connect the FB pin to the center tap of a resistor divider to program the output voltage. FREQ 9 Switching frequency program pin. An external resistor connected between the FREQ pin and the AGND pin sets the switching frequency. NC 10 14 This pin is reserved and must be connected to ground. 11 PGND 12 Power ground of the IC. The PGND pin is connected to the source of the internal power MOSFET switch. 13 SS 4 Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start timing. 1 SW 15 SW is the drain of the internal power MOSFET. Connect the SW pin to the switched side of the boost or SEPIC inductor or the flyback transformer. 16 SYNC 5 Switching frequency synchronization pin. An external clock signal can set the switching frequency between 200 kHz and 1 MHz. If this pin is not used, it must be tied to AGND. VIN 2 The input supply pin to the IC. Connect the VIN pin to a supply voltage between 2.9 V and 32 V. The voltage on the VIN pin can be different from the boost power stage input. PowerPAD The PowerPAD must be soldered to AGND. If possible, use thermal vias to connect the PowerPAD to PCB ground plane layers for improved power dissipation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-Q1 3 TPS55340-Q1 www.ti.com SLVSBV5C – JUNE 2014 – REVISED SEPTEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN(2) –0.3 40 V EN(2) –0.3 40 V FB, FREQ, and COMP(2) –0.3 3 V SS(2) –0.3 5 V SYNC(2) –0.3 7 V SW(2) –0.3 40 V –5 40 V Operating junction temperature –40 150 °C Storage temperature, Tstg –65 150 °C Input voltage Output voltage (1) (2) SW ( VI (4) 7.3.3 Overcurrent Protection and Frequency Foldback The TPS55340-Q1 device provides cycle-by-cycle overcurrent protection that turns off the power switch when the inductor current reaches the overcurrent limit threshold. The PWM circuitry resets at the beginning of the next switch cycle. During an overcurrent event, the output voltage begins to droop as a function of the load on the output. When the FB voltage through the feedback resistors, drops lower than 0.9 V, the switching frequency is automatically reduced to 1/4 of the normal value. Figure 6-9 shows the non-foldback frequency with an 80-kΩ timing resistor and the corresponding foldback frequency. The switching frequency does not return to normal 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-Q1 TPS55340-Q1 www.ti.com SLVSBV5C – JUNE 2014 – REVISED SEPTEMBER 2021 until the overcurrent condition is removed and the FB voltage increases above 0.9 V. The frequency foldback feature is disabled during soft start. 7.3.3.1 Minimum On Time and Pulse Skipping The TPS55340-Q1 PWM control system has a minimum PWM pulse width of 77 ns (typical). This minimum on-time determines the minimum duty cycle of the PWM, for any set switching frequency. When the voltage regulation loop of the TPS55340-Q1 device requires a minimum on-time pulse width less than 77 ns, the IC enters pulse-skipping mode. In this mode, the device power switches off for several switching cycles to prevent the output voltage from rising above the desired regulated voltage. This operation typically occurs in light load conditions when the PWM operates in discontinuous conduction mode. Pulse skipping increases the output ripple as shown in Figure 8-7. 7.3.4 Voltage Reference and Setting Output Voltage An internal voltage reference provides a precise 1.229-V voltage reference at the error amplifier non-inverting input. To set the output voltage, select the FB pin resistor R(SH) and R(SL) as shown in Equation 5. æ R(SH) ö VO = 1.229 V ´ ç + 1÷ ç R(SL ) ÷ è ø (5) 7.3.5 Soft Start The TPS55340-Q1 device has a built-in soft-start circuit that significantly reduces the start-up current spike and output voltage overshoot. When the IC is enabled, an internal bias current source (6 µA typical) charges a capacitor (C(SS)) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the peak current and duty cycle of the PWM controller. Limiting the peak switch current during start-up with a slow ramp on the SS pin reduces in-rush current and output voltage overshoot. When the capacitor reaches 1.8 V, the soft-start cycle is complete and the soft-start voltage no longer clamps the error amplifier output. When the EN is pulled low for at least 1 ms, the IC enters Shutdown mode and the SS capacitor is discharged through a 5-kΩ resistor to prepare for the next soft-start sequence. 7.3.6 Slope Compensation To prevent subharmonic oscillations, the TPS55340-Q1 device uses internal slope compensation. Use Equation 6 to calculate the sensed current slope of boost converter. V = I ´R (n ) L (SENSE ) S (6) Use Equation 7 to calculate the slope compensation dv/dt. æ ö ç 0.32 V ÷ çR ÷ ç (FREQ ) ÷ 0.5 µA è ø S (e ) = 16 ´ (1 - D) ´ 6 pF + 6 pF (7) In a converter with current mode control, in addition to the output voltage feedback loop, the inner current loop including the inductor current sampling effect and the slope compensation on the small-signal response must be taken into account as calculated in Equation 8. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340-Q1 11 TPS55340-Q1 www.ti.com SLVSBV5C – JUNE 2014 – REVISED SEPTEMBER 2021 He (s) = 1 éæ ù S(e ) ö ÷ ´ (1 - D) - 0.5 ú s ´ êç 1 + êç ú S(n ) ÷ ø ëè û+ 1+ ƒS s2 (p ´ ƒS ) 2 (8) where • • • R(SENSE) (15 mΩ) is the equivalent current-sense resistor. R(FREQ) is the timing resistor used to set frequency. D is the duty cycle. Note If S(n)