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TPS61045
SLVS440C – JANUARY 2003 – REVISED DECEMBER 2014
TPS61045 Digitally Adjustable Boost Converter
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TPS61045 device is a high-frequency boost
converter with digitally-programmable output voltage
and true shutdown. During shutdown, the output is
disconnected from the input by opening the internal
input switch. This allows a controlled power-up and
power-down sequencing of the display. The output
voltage can be increased or decreased in digital
steps by applying a logic signal to the CTRL pin. The
output voltage range, as well as the output voltage
step size, can be programmed with the feedback
divider network. With a high switching frequency of
up to 1 MHz, the TPS61045 device allows the use of
small external components, and together, with the
small 8-pin VSON package, a minimum system
solution size is achieved.
1
Input Voltage Range from 1.8 to 6 V
Output Voltage of up to 28 V Possible
Up to 85% Efficiency
Digitally Adjustable Output Voltage Control
Disconnects Output From Input During Shutdown
Switching Frequency up to 1 MHz
No Load Quiescent Current 40 μA Typical
Thermal Shutdown Mode
Shutdown Current 0.1 μA Typical
Available in Small 3-mm × 3-mm VSON Package
2 Applications
•
•
LCD Bias Supply for Small to Medium LCD
Displays
OLED Display Power Supply
– PDA, Pocket PC, Smart Phones
– Handheld Devices
– Cellular Phones
Device Information(1)
PART NUMBER
TPS61045
PACKAGE
BODY SIZE (NOM)
VSON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
D1
MBR0530
L1
4.7 mH
VO
16.2 V to 18.9 V/ 10 mA
C2
4.7mF
1
VIN = 1.8 V to 6 V
2
R1
2.2 MW
L
SW 8
DO 3
4
FB
CTRL
6
7
GND PGND
R3
1 MW
Cff
22 pF
C3
1 mF
VIN
5
C1
100 nF
TPS61045
R2
180 kW
Enable / LCD bias control
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61045
SLVS440C – JANUARY 2003 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Dissipation Rating .....................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
10.3 Thermal Considerations ........................................ 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
Changes from Revision B (March 2009) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Updated Equation 10 ........................................................................................................................................................... 12
•
Updated Equation 11 ........................................................................................................................................................... 13
2
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SLVS440C – JANUARY 2003 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
DRB PACKAGE
(TOP VIEW)
8 SW
L 1
VIN 2
DO 3
Exposed
Thermal
Pad
7 PGND
6 GND
FB 4
(1)
5 CTRL
The exposed thermal pad is connected to PGND. Connect this pad directly with the GND pin.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CTRL
5
I
Combined enable and digital output voltage programming pin. Pulling CTRL constantly high enables the
device. When CTRL is pulled to GND, the device is disabled and the input is disconnected from the output
by opening the integrated switch Q1. Pulsing CTRL low increases or decreases the output voltage. Refer to
Application and Implementation for further information.
DO
3
O
Internal DAC output. DO programs the output voltage through the CTRL pin. Refer to Application and
Implementation for further information.
FB
4
I
Feedback. FB must be connected to the output voltage-feedback divider.
GND
6
—
Analog ground. GND must be directly connected to the PGND pin. Refer to Application and Implementation
for further information.
L
1
O
Drain of the internal input switch (Q1). Connect L to the inductor.
PGND
7
—
Power ground
SW
8
I
Drain of the integrated main switch Q2. SW is connected to the inductor and anode of the Schottky rectifier
diode.
VIN
2
I
Input supply pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
Supply voltage VVIN
(2)
Voltage
VCTRL, V(FB), VL, VDO
Voltage
VSW
(2)
(2)
MIN
MAX
UNIT
–0.3
7
V
–0.3
VIN + 0.3
V
30
V
Continuous power dissipation
See Dissipation Rating
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1500
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VVIN
Input voltage range
VSW
Switch voltage
L
Inductor
ƒ
Switching frequency (1)
CI(C2)
Input capacitor (C2)
TYP
1.8
MAX
UNIT
6
V
30
(1)
V
μH
4.7
1
(1)
MHz
μF
4.7
(1)
μF
CO(C3)
Output capacitor (C3)
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
1
See application section for further information.
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS61045
THERMAL METRIC (1)
RΘJA (2)
(1)
(2)
VSON (8 PINS)
Junction-to-ambient thermal resistance
270
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Standard 2-layer PCB without vias for the thermal pad. See the application section on how to improve the thermal resistance RΘJA.
6.5 Dissipation Rating
PACKAGE
8-pin VSON (DRB)
(1)
4
(1)
TA ≤ 25°C
POWER RATING
DERATING FACTOR ABOVE
TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
370 mW
3.7 mW/°C
204 mW
148 mW
See Thermal Information for the junction-to-ambient thermal resistance.
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6.6 Electrical Characteristics
VIN = 2.4 V, CTRL = VIN, VO = 18 V, IO = 10 mA, TA = –40°C to 85°C, typical values are at TA = 25° C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6
V
65
μA
SUPPLY CURRENT
VIN
Input voltage range
IQ
Operating quiescent current
IO = 0 mA, not switching
1.8
40
IO(SD)
Shutdown current
CTRL = GND
0.1
1
μA
UVLO
Undervoltage lockout (UVLO) threshold
VIN falling
1.5
1.7
V
CTRL AND DAC OUTPUT
VIH
CTRL high-level input voltage
VIL
CTRL low-level input voltage
Ilkg
CTRL input leakage current
VO(DO)
DAC output voltage range
1.3
V
CTRL = GND or VIN
0
0.3
V
0.1
μA
1.233
V
DAC resolution
6 bit
19.6
mV
VO(DO)
DAC center output voltage
CTRL = high
607
IO(SINK)
Maximum DAC sink current
tUP
Increase output voltage one step
CTRL = High to low to high
tDWN
Decrease the output voltage one step
CTRL = High to low to high
td1
Delay time between up and down steps
CTRL = Low to high to low
1
μs
tOFF
Shutdown
CTRL = High to low to high
560
μs
mV
30
μA
1
60
μs
140
240
μs
INPUT SWITCH (Q1), MAIN SWITCH (Q2), AND CURRENT LIMIT
VSW(Q2)
Main switch maximum voltage (Q2)
30
V
rDS(on)
Main switch MOSFET on-resistance
VIN = 2.4 V; IS = 200 mA
400
800
mΩ
Ilkg
Main switch MOSFET leakage current
VS = 28 V
0.1
10
μA
ILIM
Main switch MOSFET current limit
375
450
mA
rDS(on)
Input switch MOSFET on-resistance
VIN = 2.4 V; IS = 200 mA
1
2
Ω
Ilkg
Input switch MOSFET leakage current
VL = GND, VIN = 6 V
0.1
10
μA
28
V
30
100
nA
300
OUTPUT
VO
Output voltage range
Vref
Internal voltage reference
IFB
Feedback input bias current
V(FB) = 1.3 V
Feedback trip point voltage
1.8 V ≤ VIN ≤ 6 V; VO = 18 V, ILOAD = 10 mA
1.208
1.233
1.258
V
Feedback trip point voltage
1.8 V ≤ VIN≤ 3.6 V; VO = 18 V,
ILOAD = 10 mA , TA = 0°C to 85°C
1.214
1.233
1.251
V
VFB
VIN
1.233
V
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6.7 Typical Characteristics
Table 1. Table of Graphs
Graph Title
Figure
Efficiency vs Load Current
Figure 1
Efficiency vs Input Voltage
Figure 2
IDD(Q)
Quiescent Current vs Input Voltage
Figure 3
VFB
Feedback Voltage vs Temperature
Figure 4
IFB
Feedback Current vs Temperature
Figure 5
rDS(on) Main Switch Q2 vs Temperature
Figure 6
rDS(on) Main Switch Q2 vs Input Voltage
Figure 7
rDS(on) Input Switch Q1 vs Temperature
Figure 8
η
rDS(on)
VDO
rDS(on) Input Switch Q1 vs Input Voltage
Figure 9
VDO Voltage vs CTRL Input Step
Figure 10
Line Transient Response
Figure 13
Load Transient Response
Figure 14
PFM Operation
Figure 15
Softstart
Figure 16
88
90
VIN = 5 V
86
84
84
VIN = 3.6 V
82
Efficiency - %
Efficiency - %
L = 4.7 mF
VO = 18 V
87
80
VIN = 2.4 V
78
76
L = 4.7 mH
VO = 18 V
74
IO = 10 mA
81
78
75
72
69
IO = 5 mA
66
72
63
70
60
0.1
1
10
1
100
2
3
IO - Output Current - mA
Figure 1. Efficiency vs Load Current
6
Figure 2. Efficiency vs Input Voltage
1.238
VIN = 2.4 V
o
TA = 85 C
50
V(fb) - Feedback Voltage - V
IDD(Q) - Quiescent Current - mA
5
VIN - Input Voltage - V
60
o
TA = 25 C
40
TA = - 40oC
30
20
10
1.237
1.236
1.235
1.234
1.233
0
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
- 40
- 15
10
35
60
85
o
TA - Free-Air Temperature - C
VIN - Input Voltage - V
Figure 3. Quiescent Current vs Input Voltage
6
4
Figure 4. Feedback Voltage vs Temperature
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700
rDS(on) - On-State Resistance - mW
100
I(fb) - Feedback Current - nA
90
80
VIN = 3.6 V
70
60
50
40
30
20
VIN = 2.4 V
10
VIN = 5 V
VIN = 2.4 V
600
500
400
300
200
100
0
0
- 40
- 15
10
35
60
- 40
85
- 15
Figure 5. Feedback Current vs Temperature
60
85
Figure 6. rDS(on) Main Switch Q2 vs Temperature
1.6
rDS(on) - On-State Resistance - W
rDS(on) - On-State Resistance - mW
35
TA - Free-Air Temperature - C
600
TA = 25°C
500
400
300
200
100
0
VIN = 2.4 V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
- 40
- 15
10
35
60
85
o
VIN - Input Voltage - V
TA - Free-Air Temperature - C
Figure 7. rDS(on) Main Switch Q2 vs Input Voltage
Figure 8. rDS(on) Input Switch Q1 vs Temperature
1.8
1.4
o
TA = 25 C
1.6
V(DO) – Drop-Out Voltage – V
rDS(on) - On-State Resistance - W
10
o
o
TA - Free-Air Temperature - C
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VIN = 2.4 V
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
0
VIN - Input Voltage - V
8
16
24
32
40
48
56
64
Input Step Number
Figure 9. rDS(on) Input Switch Q1 vs Input Voltage
Figure 10. V(DO) Voltage vs CTRL Input Step
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Detailed Description
7.1 Overview
The TPS61045 device operates with an input voltage range of 1.8 to 6 V and generates output voltages up to 28
V. The device operates in a pulse frequency modulation (PFM) scheme with constant peak current control. This
control scheme maintains high efficiency over the entire load current range, and with a switching frequency of up
to 1 MHz, the device enables the use of small external components.
The converter monitors the output voltage. When the feedback voltage falls below the reference voltage of
1.233 V (typical), the main switch turns on and the current ramps up. The main switch turns off when the inductor
current reaches the internally set peak current of 375 mA (typical). See Peak Current Control for more
information. The second criteria that turns off the main switch is the maximum on-time of 6 μs (typical). This limits
the maximum on-time of the converter in extreme conditions. As the switch is turned off, the external Schottky
diode is forward biased delivering the current to the output. The main switch remains off until the minimum off
time of 400 ns (typical) has passed and the feedback voltage is below the reference voltage again. Using this
PFM peak current control scheme, the converter operates in discontinuous conduction mode (DCM) where the
switching frequency depends on the input voltage, output voltage, and output current. This gives a high efficiency
over the entire load current range. This regulation scheme is inherently stable, which allows a wider range for the
selection of the inductor and output capacitor.
7.2 Functional Block Diagram
L
VIN
SW
Q1
Input switch
400 ns Min
Off T ime
UVLO
Bias Supply
Gate
Driver
CTRL
Q2
Main Switch
Error Comparator
S
–
FB
+
Vref = 1.233 V
Gate
Driver
RS Latch
Logic
6 µs Max
On Time
R
Current Limit
CTRL
Digital
Interface
+
6-Bit DAC
Rsense
–
Soft
Start
DO
GND
PGND
7.3 Feature Description
7.3.1 Peak Current Control
The internal switch is turned on until the inductor current reaches the typical dc current limit (ILIM) of 375 mA. Due
to the internal current limit delay of 100 ns (typical), the actual current exceeds the dc current limit threshold by a
small amount. The typical peak current limit can be calculated:
V
IP(typ) = I(LIM) + IN x 100 ns
L
(1)
IP(typ) = 375 m A +
VIN
x 100 ns
L
(2)
The higher the input voltage and the lower the inductor value, the greater the current limit overshoot.
8
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Feature Description (continued)
7.3.2 Softstart
If no special precautions are taken, all inductive step-up converters exhibit high inrush current during start up.
This can cause voltage drops at the input rail during start-up, which may result in an unwanted or premature
system shutdown.
When the device is enabled, the internal input switch (Q1) is slowly turned on to reduce the inrush current
charging the capacitor (C2) connected to pin L. Furthermore, the TPS61045 device limits this inrush current
during start-up by increasing the current limit in two steps starting from ILIM / 4 for 256 switch cycles to ILIM / 2 for
the next 256 switch cycles.
7.3.3 Enable (CTRL Pin)
The CTRL pin serves two functions. One function is the enable and disable of the device. The other function is
the output voltage programming of the device. If the digital interface is not required, the CTRL pin is used as a
standard enable pin for the device.
Pulling the CTRL pin high enables the device beginning with the softstart cycle.
Pulling the CTRL pin to ground for a period of ≥560 μs shuts down the device, reducing the shutdown current to
0.1 μA (typical). During shutdown, the internal input switch (Q1) remains open and disconnects the load from the
input supply of the device.
The user must terminate this pin. For more details on how to use the interface function, see Digital Interface
(CTRL).
7.3.4 DAC Output (DO)
The TPS61045 device allows digital adjustment of the output voltage using the digital CTRL interface, as
described in Digital Interface (CTRL). The DAC output pin (DO) drives an external resistor (R3) connected to the
external feedback divider. The DO output has a typical output voltage range from 0 V to Vref (1.233 V). If the DO
output voltage is set to 0 V, the external resistor (R3) is more or less in parallel with the lower feedback resistor
(R2), giving the highest output voltage. Programming the DO output to Vref gives the lowest output voltage.
Internally, a 6-bit DAC is used with 64 steps and 0 as the first step. This gives a typical voltage step of 19.6 mV,
which is calculated as:
ǒ
V
V
O(DO)
+
ref
Ǔ
26–1
(3)
See Setting the Output Voltage for further information.
After start-up, when the CTRL pin is pulled high, the DO output voltage is set to its center voltage, which is the
32nd step of typical V(DO) = 607 mV.
7.3.5 Digital Interface (CTRL)
When the CTRL pin is pulled high, the device starts up with softstart and the DAC output voltage (DO) sets to its
center voltage with a typical output voltage of 607 mV.
The output voltage can be programmed by pulling the CTRL pin low for a certain period of time. Depending on
this time period, the internal DAC voltage increases or decreases one digital step, as outlined in Table 2 and
Figure 11. Programming the DAC output V(DO) to 0 V places R3 in parallel to R2, which gives the maximum
output voltage. If the DAC is programmed to its maximum output voltage equal to the internal reference voltage,
typically V(DO) = 1.233 V, then the output has its minimum output voltage.
Table 2. Timing Table
DAC OUTPUT DO
TIME
LOGIC LEVEL
Increase one step
tUP = 1 to 60 μs
Low
Decrease one step
tDWN = 140 to 240 μs
Low
Shutdown
tOFF ≥ 560 μs
Low
Delay between steps
td1 = 1 μs
High
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td1
High
EN
Low
t(UP)
td1
t(DWN)
t(OFF)
Device Enabled
Device Disabled
Figure 11. CTRL Timing Diagram
7.3.6 UVLO
An UVLO feature prevents misoperation of the device at input voltages below 1.5 V (typical). As long as the input
voltage is below the undervoltage threshold, the device remains off, with the input switch (Q1) and the main
switch (Q2) open.
7.3.7 Thermal Shutdown
An internal thermal shutdown is implemented in the TPS61045 device that shuts down the device if the typical
junction temperature of 160°C is exceeded. If the device is in thermal shutdown mode, the input switch (Q1) and
the main switch (Q2) are open.
7.4 Device Functional Modes
The device operates in a pulse frequency modulation (PFM) scheme with constant peak current control. This
control scheme maintains high efficiency over the entire load current range, and with a switching frequency of up
to 1 MHz, the device enables the use of small external components. The converter monitors the output voltage.
When the feedback voltage falls below the reference voltage of 1.233 V (typical), the main switch turns on and
the current ramps up. The main switch turns off when the inductor current reaches the internally set peak current
of 375 mA (typical).
10
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Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS61045 device is a high-frequency boost converter with digitally-programmable output voltage and true
shutdown. The TPS61045 device operates with an input voltage range of 1.8 to 6 V and generates output
voltages up to 28 V. The device operates in a constant peak current control, which maintains high efficiency over
the entire load current range, and with a typical switching frequency of up to 1 MHz.
8.2 Typical Application
The following section provides a step-by-step design approach for configuring the TPS61045 as a voltage
regulating boost converter, as shown in Figure 12.
8.2.1 Analog Adjusted Output Voltage
L1
4.7 mH
LQH32CN4R7M11
D1
Zetex ZHZS400
C2
4.7 mF
VCC = 1.8 V to 6 V
C1
100 nF
VO
15 V to 18 V
Adjustable / 10 mA
Cff
22 pF
R1
2.2 MΩ
L
SW
VIN
DO
CTRL
FB
GND PGND
TPS61045
R3
390 kΩ
C3
1 mF
DAC or Analog Voltage
0 V = 25 V
1.233 V = 18 V
R2
180 kW
Enable
Figure 12. Typical Application With Analog Adjusted Output Voltage
8.2.1.1 Design Requirements
Table 3. Design Parameters
PARAMETERS
Output voltage
Input voltage
Output current
VALUES
18 V
1.8 to 6 V
10 mA
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Inductor Selection, Maximum Load Current
Because the PFM peak current control scheme is inherently stable, the inductor and capacitor value does not
affect the stability of the regulator. The selection of the inductor together with the nominal load current, input, and
output voltage of the application determines the switching frequency of the converter. Depending on the
application, TI recommends inductor values between 2.2 to 47 μH. The maximum inductor value is determined
by the maximum switch on-time of 6 μs (typical). The peak current limit of 375 mA (typical) must be reached
within 6 μs for proper operation.
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The inductor value determines the maximum switching frequency of the converter. Therefore, the user must
select the inductor value for the maximum switching frequency at maximum load current of the converter and
should not be exceeded. A good inductor value to start with is 4.7 μH. The maximum switching frequency is
calculated as:
9IN u 9O ± 9IN
¦s(max)
IP u L u VO
where
•
IP(typ)
IP = Peak current as described in Peak Current Control
V
= 375 m A + IN ´100 ns
L
(4)
where
L = Selected inductor value; TI recommends inductor values between 2.2 to 47 μH
•
(5)
If the selected inductor does not exceed the maximum switching frequency of the converter, as a next step, the
switching frequency at the nominal load current is estimated as follows:
u ,LOAD u 9O ± 9IN 9F
¦S(ILOAD)
IP2 u L
where
•
IP(typ)
IP = Peak current as described in Peak Current Control
V
= 375 m A + IN ´100 ns
L
(6)
where
•
•
•
L = Selected inductor value
I(LOAD) = Nominal load current
VF = Rectifier diode forward voltage (typically 0.3 V)
(7)
The smaller the inductor value, the higher the switching frequency of the converter, but the lower the efficiency.
The maximum load current of the converter is determined at the operation point where the converter starts to
enter continuous conduction mode. The converter must always operate in DCM to maintain regulation.
Two conditions exist for determining the maximum output current of the converter. One condition is when the
inductor current fall time is 400 ns.
One way to calculate the maximum available load current for certain operation conditions is to estimate the
expected converter efficiency at the maximum load current. Find this number in the efficiency graphs shown in
Figure 1 and Figure 2. Then, the maximum load current can be estimated:
Inductor fall time:
I ´L
t fall = P
VO - VIN
(8)
For tf ≥ 400 ns:
Iload max = h
IP ´ VIN
2 ´ VO
(9)
For tf ≤ 400 ns:
Iload max
K
IP2 u L u VIN
VO VIN u 2 u IP u L 2 u 400 ns u VIN
where
•
•
•
12
L = Selected inductor value
η = Expected converter efficiency (typically between 70% to 85%)
IP = Peak current as described in Peak Current Control
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IP
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VIN
u 100 ns
L
300 mA
(11)
Equation 10 contains the expected converter efficiency that allows calculating the expected maximum load
current the converter can support. Find the efficiency in the efficiency graphs shown in Figure 1 and Figure 2, or
80% can be used as a good estimation.
The selected inductor must have a saturation current which meets the maximum peak current of the converter as
calculated in Peak Current Control. Use the maximum value for ILim (450 mA) for this calculation.
Another important inductor parameter is the dc resistance. The lower the dc resistance, the higher the efficiency
of the converter. See Table 4 and Inductor Selection, Maximum Load Current.
Table 4. Possible Inductor Selection
Inductor Value
Component Supplier
Comments
10 μH
Sumida CR32-100
High efficiency
10 μH
Sumida CDRH3D16-100
High efficiency
10 μH
Murata LQH43CN100K01
4.7 μH
Sumida CDRH3D16-4R7
Small solution size
4.7 μH
Murata LQH32CN4R7M51
Small solution size
8.2.1.2.2 Setting the Output Voltage
See Simplified Schematic. When the converter is programmed to the minimum output voltage, the DAC output
(DO) equals the reference voltage of 1.233 V (typical). Therefore, only the feedback resistor network (R1) and
(R2) determines the output voltage under these conditions. This gives the minimum output voltage possible and
can be calculated as:
V
O(min)
+V
(FB)
ǒR1
) 1Ǔ
R2
(12)
The maximum output voltage is determined as the DAC output (DO) is set to 0 V:
V
O(max)
+V
(FB)
R1 ) V
(FB)
R3
ǒR1
) 1Ǔ
R2
(13)
The output voltage can be digitally programmed by pulling the CTRL pin low for a certain period of time as
described in Digital Interface (CTRL). Pulling the signal applied to the CTRL pin low and high again (for related
timing see Electrical Characteristics) increases or decreases the DAC output DO (pin 3) one step where one step
is typically 19.6 mV. A voltage step on DO of 19.6 mV (typical) changes the output voltage by one step and is
calculated as:
V
+ 19.6 mV R1
O(step)
R3
(14)
The possible output voltage range is determined by selecting R1, R2, and R3. A possible larger output voltage
range gives a larger output voltage step size. The smaller the possible output voltage range, the smaller the
output voltage step size.
To reduce the overall operating quiescent current in battery-powered applications a high-impedance voltage
divider must be used with a typical value for R2 of ≤200 kΩ and a maximum value for R1 of 2.2 MΩ.
Some applications may not need the digital interface to program the output voltage. In this case, the output DO
can be left open as shown in Figure 12, and the output voltage is calculated as for any standard boost converter:
V
O
+ 1.233 V
Ǔ
ǒ1 ) R1
R2
(15)
In such a configuration, a high-impedance voltage divider must also be used to minimize ground current, and TI
recommends a typical value for R2 of ≤200 kΩ and a maximum value for R1 of 2.2 MΩ.
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A feed-forward capacitor (C(FF)), across the upper feedback resistor (R1), is required to provide sufficient
overdrive for the error comparator. Without a feed-forward capacitor or with a too-small feed-forward capacitor
value, the device shows double pulses or a pulse burst instead of single pulses at the switch node (SW). This
can cause higher output voltage ripple. If a higher output voltage ripple is acceptable, the feed-forward capacitor
can be left out also.
The lower the switching frequency of the converter, the larger the feed-forward capacitor value needs to be. A
good starting point is to use a 10-pF feed-forward capacitor. As a first estimation, the required value for the feedforward capacitor can be calculated at the operation point:
1
C(FF) |
¦
2 u S u S u R1
20
where
•
•
R1 = Upper resistor of voltage divider
ƒS = Switching frequency of the converter at the nominal load current. (For the calculation of the switching
frequency, see Inductor Selection, Maximum Load Current.)
(16)
For C(FF), choose a value which comes closest to the calculation result.
The larger the feed-forward capacitor, the worse the line regulation of the device. Therefore, select the feedforward capacitor as small as possible if good line regulation is of concern.
8.2.1.2.3 Output Capacitor Selection
For better output voltage filtering, TI recommends a low-ESR output capacitor. Ceramic capacitors have low-ESR
values, but depending on the application, tantalum capacitors can also be used. For the selection of the output
capacitor, see Table 5.
Assuming the converter does not show double pulses or pulse bursts on the switch node (SW), the output
voltage ripple is calculated as:
§
·
IO
IP u L
1
±
u¨
¸ ,P u (65
&O ¨© ¦S(ILOAD)
9O 9F 9IN ¸¹
'9O
where
•
IP = Peak current as described in Peak Current Control
V
IP = 375 m A + IN x 100 ns
L
(17)
where
•
•
•
•
•
•
8.2.1.2.4
L = Selected inductor value
IO(LOAD)= Nominal load current
ƒS(ILoad) = Switching frequency at the nominal load current as calculated previously.
VF = Rectifier diode forward voltage (typically 0.3 V)
CO = Selected output capacitor
ESR = Output capacitor ESR value
(18)
Input Capacitor Selection
The input capacitor (C1) filters the high-frequency noise to the control circuit and must be directly connected to
the input pin (VIN) of the device. The capacitor (C2) connected to the L pin of the device is the input capacitor for
the power stage.
The main purpose of the capacitor (C2), that is connected directly to the L pin, is to smooth the inductor current.
A larger capacitor reduces the inductor ripple current present at the L pin. The smaller the ripple current at the L
pin, the higher the efficiency of the converter. If a sufficiently large capacitor is used, the input switch must carry
only the dc current, filtered by the capacitor (C2), and not the high switching currents of the converter. A 4.7- or
10-μF ceramic capacitor (C2) is sufficient for most applications. For better filtering, this value can be increased
without limit. See Table 5 for input capacitor recommendations.
14
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Table 5. Possible Input and Output Capacitor Selection
Capacitor
Voltage Rating
Component Supplier
Comments
4.7 F/X5R/0805
6.3 V
Tayo Yuden JMK212BY475MG
CI / CO
10 μF/X5R/0805
6.3 V
Tayo Yuden JMK212BJ106MG
CI / CO
1 μF/X7R/1206
25 V
Tayo Yuden TMK316BJ105KL
CO
1 μF/X7R/1206
35 V
Tayo Yuden GMK316BJ105KL
CO
4.7 μF/X5R/1210
25 V
Tayo Yuden TMK325BJ475MG
CO
8.2.1.2.5
Diode Selection
To achieve high efficiency, use a Schottky diode. The current rating of the diode must meet the peak current
rating of the converter as it is calculated in Peak Current Control. Use the maximum value for I(LIM) (450 mA) for
this calculation. For the selection of the Schottky diode, see Table 6.
Table 6. Possible Schottky Diode Selection
Component Supplier
Reverse Voltage
ON Semiconductor MBR0530
30 V
ON Semiconductor MBR0520
20 V
ON Semiconductor MBRM120L
20 V
Toshiba CRS02
30 V
Zetex ZHZS400
40 V
8.2.1.3 Application Curves
VIN = 2.4 V to 3.4 V Step
VO = 50 mV/Div
VO = 100 mV/Div
I(Load) = 1 mA to 11 mA Step
50 µs/Div
250 ms/Div
Figure 13. Line Transient Response
Figure 14. Load Transient Response
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V(SW) = 10 V/Div
VO = 5 V/Div
VO = 50 mV/Div
CTRL 2 V/Div
II = 50 mA/Div
IL = 200 mA/Div
500 µs/Div
1 ms/Div
Figure 15. PFM Operation
Figure 16. Softstart
8.2.2 OLED Supply with Higher Output Current
L1
4.7 mH
LQH32CN4R7M23
C2
4.7 mF
VIN = 2.7 V to 6 V
C1
100 nF
D1
Zetex ZHZS400
R1
2.2 MΩ
L
SW
VIN
DO
CTRL
FB
GND PGND
TPS61045
VO
16.2 V to 18.9 V/
20 mA
Cff
22 pF
C3
1 mF
R3
1 MΩ
R2
180 kW
Enable / LCD
Bias Control
Figure 17. OLED Supply Providing Higher Output Current
8.2.2.1 Design Requirements
Table 7. Design Parameters
PARAMETERS
Output voltage
Input voltage
Output current
VALUES
16.2 to 18.9 V
2.7 to 6 V
20 mA
8.2.2.2 Detailed Design Procedure
Refer to the prior Detailed Design Procedure.
8.2.2.3 Application Curves
Refer to waveforms in the prior Application Curves.
16
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 1.8 to 6 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and switching frequencies. If the layout is not carefully implemented, the regulator can show noise problems and
duty cycle jitter.
The inductor and diode must be placed as close as possible to the switch pin (SW) to minimize noise coupling
into other circuits. Because the feedback pin and network is a high-impedance circuit, the feedback network must
be routed away from the inductor. Also, the input capacitor must be placed as close as possible to the input pin
for good input-voltage filtering. If space is critical and these guidelines can not be followed completely, the user
must give the highest priority to the close placement of the diode to the switch pin (SW).
10.2 Layout Example
Figure 18. Board Layout Example
10.3 Thermal Considerations
The TPS61045 device is available in a thermally-enhanced VSON package. The package includes a thermal
pad, improving the thermal capabilities of the package. See VSON PCB attachment application note (SLUA271).
The thermal resistance junction to ambient (RΘJA) of the VSON package depends on the PCB layout. Use
thermal vias and wide PCB traces to improve thermal resistance (RΘJA). Under normal operation conditions, no
PCB vias are required for the thermal pad. However, the thermal pad must be soldered to the PCB.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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19-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS61045DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BHT
Samples
TPS61045DRBRG4
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BHT
Samples
TPS61045DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BHT
Samples
TPS61045DRBTG4
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BHT
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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