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TPS61093-Q1
SLVSCO6 – JANUARY 2015
TPS61093-Q1 Low Input Boost Converter
With Integrated Power Diode and Input/Output Isolation
1 Features
3 Description
•
The TPS61093-Q1 is a 1.2-MHz, fixed-frequency
boost converter designed for high integration and
high reliability. The IC integrates a 20-V power
switch, input/output isolation switch, and power diode.
When the output current exceeds the overload limit,
the isolation switch of the IC opens up to disconnect
the output from the input. This disconnection protects
the IC and the input supply. The isolation switch also
disconnects the output from the input during shut
down to minimize leakage current. When the IC is
shutdown, the output capacitor is discharged to a low
voltage level by internal diodes. Other protection
features include 1.1-A peak overcurrent protection
(OCP) at each cycle, output overvoltage protection
(OVP), thermal shutdown, and undervoltage lockout
(UVLO).
1
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: -40°C to 125°C
Junction Operating Temperature Range
Input Range: 1.6-V to 6-V
Integrated Power Diode and Isolation FET
20-V Internal Switch FET With 1.1-A Current
Fixed 1.2-MHz Switching Frequency
Efficiency at 15-V Output up to 88%
Overload and Overvoltage Protection
Programmable Soft Start-up
Load Discharge Path After IC Shutdown
2.5 × 2.5 × 0.8 mm SON Package
2 Applications
•
•
With its 1.6-V minimum input voltage, the IC can be
powered by two alkaline batteries, a single Li-ion
battery, or 3.3-V and 5-V regulated supply. The
output can be boosted up to 17-V. The TPS61093-Q1
is available in 2.5 mm × 2.5 mm SON package with
thermal pad.
OLED Power Supply
3.3-V to 12-V, 5-V to 12-V Boost Converter
Device Information (1)
PART NUMBER
TPS61093-Q1
(1)
PACKAGE
SON (10)
BODY SIZE (NOM)
2.50 mm x 2.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
VI 1.6 V to 6 V
L1
10 mH
C1
4.7 mF
C3
R3
200 kW
TPS61093
VIN
SW
CP1
VO
CP2
OUT
100 nF
C5
1 mF
EN
FB
SS
GND
C2
0.1 mF
VO 15 V/50 mA
R1
294 kW
C4
1 mF
R2
10.2 kW
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61093-Q1
SLVSCO6 – JANUARY 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Applications ................................................ 10
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
11.3 Thermal Considerations ........................................ 18
12 Device and Documentation Support ................. 19
12.1 Trademarks ........................................................... 19
12.2 Electrostatic Discharge Caution ............................ 19
12.3 Glossary ................................................................ 19
Detailed Description .............................................. 8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
8.1 Overview ................................................................... 8
5 Revision History
2
DATE
REVISION
NOTES
January 2015
*
Initial Release
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6 Pin Configuration and Functions
2.5 mm x 2.5 mm QFN
10 PIN
TOP VIEW
GND
1
10
VIN
CP2
VO
SW
Thermal
Pad
OUT
CP1
FB
EN 5
6
SS
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VIN
2
I
IC Supply voltage input.
VO
10
O
Output of the boost converter. When the output voltage exceeds the over voltage protection (OVP)
threshold, the power switch turns off until VO drops below the over voltage protection hysteresis.
OUT
8
O
Isolation switch is between this pin and VO pin. Connect load to this pin for input/output isolation during
IC shutdown. See Without Isolation FET for the tradeoff between isolation and efficiency.
1
–
Ground of the IC.
GND
CP1, CP2
3, 4
Connect to flying capacitor for internal charge pump.
EN
5
I
Enable pin (HIGH = enable). When the pin is pulled low for 1 ms, the IC turns off and consumes less
than 1-μA current.
SS
6
I
Soft start pin. A RC network connecting to the SS pin programs soft start timing. See Start Up
FB
7
I
Voltage feedback pin for output regulation, 0.5-V regulated voltage. An external resistor divider
connected to this pin programs the regulated output voltage.
SW
9
I
Switching node of the IC where the internal PWM switch operates.
Thermal Pad
–
–
It should be soldered to the ground plane. If possible, use thermal via to connect to ground plane for
ideal power dissipation.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage on pin VIN (2)
Voltage on pins CP2, EN, and SS
(2)
MIN
MAX
UNIT
–0.3
7
V
–0.3
7
V
Voltage on pin CP1 and FB (2)
–0.3
3
V
Voltage on pin SW, VO, and OUT (2)
–0.3
20
V
Operating Junction Temperature Range
-40
150
°C
Tstg, Storage temperature range
-55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
UNIT
±2000
Corner pins (1, 5, 6, and 10)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Vi
Input voltage range
Vo
Output voltage range at VO pin
NOM
1.6
(1)
4.7
UNIT
6
V
17
V
10
μH
L
Inductor
Cin
Input capacitor
Co
Output capacitor at OUT pin (1)
Cfly
Flying capacitor at CP1 and CP2 pins
TJ
Operating junction temperature
–40
125
°C
TA
Operating ambient temperature
–40
125
°C
(1)
2.2
MAX
μF
4.7
1
10
10
μF
nF
These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in
other applications but should be fully tested by the user.
7.4 Thermal Information
TPS60193-Q1
THERMAL METRIC
(1)
DSK
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
49.2
RθJC(top)
Junction-to-case (top) thermal resistance
63.3
RθJB
Junction-to-board thermal resistance
23.4
ψJT
Junction-to-top characterization parameter
1.1
ψJB
Junction-to-board characterization parameter
23.0
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.7
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
VIN = 3.6 V, EN = VIN, TA = TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.9
1.5
mA
5
μA
SUPPLY CURRENT
VIN
Input voltage range, VIN
IQ
Operating quiescent current into VIN
Device PWM switching no load
1.6
ISD
Shutdown current
EN = GND, VIN = 6 V
UVLO
Undervoltage lockout threshold
VIN falling
Vhys
Undervoltage lockout hysterisis
6
1.5
V
1.55
V
50
mV
ENABLE AND PWM CONTROL
VENH
EN logic high voltage
VIN = 1.6 V to 6 V
VENL
EN logic low voltage
VIN = 1.6 V to 6 V
REN
EN pull down resistor
1.2
V
0.3
V
400
800
1600
kΩ
0.49
0.5
0.51
V
100
nA
1.4
MHz
VOLTAGE CONTROL
VREF
Voltage feedback regulation voltage
IFB
Voltage feedback input bias current
fS
Oscillator frequency
Dmax
Maximum duty cycle
VFB = 0.1 V
1.0
1.2
90%
93%
POWER SWITCH, ISOLATION FET
RDS(ON)N
N-channel MOSFET on-resistance
VIN = 3 V
0.25
0.4
Ω
RDS(ON)iso
Isolation FET on-resistance
VO = 5 V
2.5
4
Ω
VO = 3.5 V
4.5
3
μA
1
μA
ILN_N
N-channel leakage current
VDS = 20 V
ILN_iso
Isolation FET leakage current
VDS = 20 V
VF
Power diode forward voltage
Current = 500 mA
0.8
V
OC, ILIM, OVP SC AND SS
ILIM
N-Channel MOSFET current limit
Vovp
Over voltage protection threshold
Vovp_hys
Over voltage protection hysteresis
IOL
Over load protection
0.9
Measured on the VO pin
1.1
18
1.6
A
19
200
V
0.6
V
300
mA
THERMAL SHUTDOWN
Tshutdown
Thermal shutdown threshold
150
°C
Thysteresis
Thermal shutdown hysteresis
15
°C
7.6 Timing Requirements
VIN = 3.6 V, EN = VIN, TA = TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
Toff
EN pulse width to shutdown
Tmin_on
Minimum on pulse width
TEST CONDITIONS
MIN
TYP
EN high to low
MAX
UNIT
1
65
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5
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7.7 Typical Characteristics
Table 1. Table Of Graphs
Figure 1, L = TOKO #A915_Y-100M, unless otherwise noted
FIGURE
η
Efficiency
vs Load current at OUT = 15 V
Figure 1
η
Efficiency
vs Load current at OUT = 10 V
Figure 2
VFB
FB voltage
vs Free-air temperature
Figure 3
Figure 4
VFB
FB voltage
vs Input voltage
ILIM
Switch current limit
vs Free-air temperature
Figure 5
Line transient response
VIN = 3.3 V to 3.6 V; Load = 50 mA
Figure 10
Load transient response
VIN = 2.5 V; Load = 10 mA to 50 mA; Cff = 100 pF
Figure 11
PWM control in CCM
VIN = 3.6 V; Load = 50 mA
Figure 12
PWM control in DCM
VIN = 3.6 V; Load = 1 mA
Figure 13
Pulse skip mode
VIN = 4.5 V; OUT = 10 V; No load
Figure 14
Soft start-up
VIN = 3.6 V; Load = 50 mA
Figure 15
100
100
95
90
VI = 3.3 V
85
85
80
80
75
VI = 2.5 V
70
VI =1.8 V
65
70
60
55
50
50
45
45
100
40
1
1000
VI = 2.5 V
VI =1.8 V
65
55
10
VI = 3.3 V
75
60
40
1
VI = 4.2 V
90
Efficiency - %
Efficiency - %
95
VI = 4.2 V
10
Load - mA
100
1000
Load - mA
OUT = 15V
OUT = 10V
Figure 1. Efficiency vs. Load
Figure 2. Efficiency vs. Load
502
0.502
501.5
0.501
VFB - mV
VFB - V
501
0.5
500.5
500
0.499
499.5
0.498
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - ºC
100
120
Figure 3. FB Voltage vs. Free-Air Temperature
6
499
1.6
2
2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6
VI - Input Voltage - V
6
Figure 4. FB Voltage vs. Input Voltage
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1.3
ILIM - A
1.2
1.1
1
0.9
0.8
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - ºC
100
120
Figure 5. Switch Current Limit vs. Free-Air Temperature
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8 Detailed Description
8.1 Overview
The TPS61093-Q1 is a highly integrated boost regulator for up to 17-V output. In addition to the on-chip 1-A
PWM switch and power diode, this IC also integrates an output-side isolation switch as shown in the functional
block diagram. One common issue with conventional boost regulators is the conduction path from input to output
even when the PWM switch is turned off. It creates three problems, which are inrush current during start-up,
output leakage current during shutdown, and excessive over load current. In the TPS61093-Q1, the isolation
switch turns off under shutdown-mode and over load conditions, thereby opening the current path. However,
shorting the VO and OUT pins bypasses the isolation switch and enhances efficiency. Because the isolation
switch is on the output side, the IC's VIN pin and power stage input power (up to 10 V) can be separated.
The TPS61093-Q1 adopts current-mode control with constant pulse-width-modulation (PWM) frequency. The
switching frequency is fixed at 1.2-MHz typical. PWM operation turns on the PWM switch at the beginning of
each switching cycle. The input voltage is applied across the inductor and the inductor current ramps up. In this
mode, the output capacitor is discharged by the load current. When the inductor current hits the threshold set by
the error amplifier output, the PWM switch is turned off, and the power diode is forward-biased. The inductor
transfers its stored energy to replenish the output capacitor. This operation repeats in the next switching cycle.
The error amplifier compares the FB-pin voltage with an internal reference, and its output determines the duty
cycle of the PWM switching. This closed-loop system requires frequency compensation for stable operation. The
device has a built-in compensation circuit that can accommodate a wide range of input and output voltages. To
avoid the sub-harmonic oscillation intrinsic to current-mode control, the IC also integrates slope compensation,
which adds an artificial slope to the current ramp.
8.2 Functional Block Diagram
FB
EN
CP2
CP1
SW
OUT
VO
Soft
Startup
Ref.
C/P
EA
Gate
Driver
PWM Control
Gate
Driver
EN
Precharge
On/off control
Oscillator
Ramp
Generator
SS
8
+
Current Sensor
GND
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8.3 Feature Description
8.3.1 Shutdown And Load Discharge
When the EN pin is pulled low for 1-ms, the IC stops the PWM switch and turns off the isolation switch, providing
isolation between input and output. The internal current path consisting of the isolation switch’s body diode and
several parasitic diodes quickly discharges the output voltage to less than 3.3-V. Afterwards, the voltage is slowly
discharged to zero by the leakage current. This protects the IC and the external components from high voltage in
shutdown mode.
In shutdown mode, less than 5-μA of input current is consumed by the IC.
8.3.2 Over Load And Over Voltage Protection
If the over load current passing through the isolation switch is above the over load limit (IOL) for 3-μs (typ), the
TPS61093-Q1 is switched off until the fault is cleared and the EN pin toggles. The function only is triggered 52ms after the IC is enabled.
To prevent the PWM switch and the output capacitor from exceeding maximum voltage ratings, an over voltage
protection circuit turns off the boost switch as soon as the output voltage at the VO pin exceeds the OVP
threshold. Simultaneously, the IC opens the isolation switch. The regulator resumes PWM switching after the VO
pin voltage falls 0.6-V below the threshold.
8.3.3 Under Voltage Lockout (UVLO)
An under voltage lockout prevents improper operation of the device for input voltages below 1.55-V. When the
input voltage is below the under voltage threshold, the entire device, including the PWM and isolation switches,
remains off.
8.3.4 Thermal Shutdown
An internal thermal shutdown turns off the isolation and PWM switches when the typical junction temperature of
150°C is exceeded. The thermal shutdown has a hysteresis of 15°C, typical.
8.4 Device Functional Modes
The converter operates in continuous conduction mode (CCM) as soon as the input current increases above half
the ripple current in the inductor, for lower load currents it switches into discontinuous conduction mode (DCM). If
the load is further reduced, the part starts to skip pulses to maintain the output voltage.
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9 Application and Implementation
9.1 Application Information
The following section provides a step-by-step design approach for configuring the TPS61093-Q1 as a voltage
regulating boost converter, as shown in Figure 6.
9.2 Typical Applications
9.2.1 15V Output Boost Converter
Vin 1.8V to 6V
L1
10mH
C1
TPS61093
4.7mF
C3 100nF
R3
200kW
C5
1 mF
VIN
SW
CP1
VO
CP2
OUT
EN
FB
SS
GND
C2 0.1mF
Vo 15V/50mA
R1
294kW
C6
10nF
C4
100mF
R2
10.2kW
Figure 6. 15V Boost Converter with 100µF Output Capacitor
9.2.1.1 Design Requirements
Table 2. Design Parameters
10
PARAMETERS
VALUES
Input voltage
4.2 V
Output voltage
15 V
Operating frequency
1.2 MHz
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Output Program
To program the output voltage, select the values of R1 and R2 (see Figure 7) according to Equation 1.
æ R1 ö
Vout = 0.5 V ´ ç
+1÷
è R2 ø
æ Vout
ö
R1 = R2 ´ ç
- 1÷
0.5
V
è
ø
(1)
A recommended value for R2 is approximately 10-kΩ which sets the current in the resistor divider chain to
0.5V/10kΩ = 50-μA. The output voltage tolerance depends on the VFB accuracy and the resistor divider.
C2
C2
VO
OUT
VO
TPS61093
Cff
Option
R1
C4
OUT
R1
TPS61093
FB
Cff
Option
FB
R2
R2
(a) With isolation FET
(b) Without isolation FET
Figure 7. Resistor Divider to Program Output Voltage
9.2.1.2.2 Without Isolation FET
The efficiency of the TPS61093-Q1 can be improved by connecting the load to the VO pin instead of the OUT
pin. The power loss in the isolation FET is then negligible, as shown in Figure 8. The tradeoffs when bypassing
the isolation FET are:
• Leakage path between input and output causes the output to be a diode drop below the input voltage when
the IC is in shutdown
• No overload circuit protection
When the load is connected to the VO pin, the output capacitor on the VO pin should be above 1-μF.
100
95
90
Without isolation
85
Efficiency - %
80
With isolation
75
70
65
60
55
50
45
40
0
50
100
150
200
Load - mA
250
300
Figure 8. Efficiency vs. Load
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9.2.1.2.3 Start Up
The TPS61093-Q1 turns on the isolation FET and PWM switch when the EN pin is pulled high. During the soft
start period, the R and C network on the SS pin is charged by an internal bias current of 5-μA (typ). The RC
network sets the reference voltage ramp up slope. Since the output voltage follows the reference voltage via the
FB pin, the output voltage rise time follows the SS pin voltage until the SS pin voltage reaches 0.5-V. The soft
start time is given by Equation 2.
0.5 V ´ C5
tSS =
5 mA
where
•
C5 is the capacitor connected to the SS pin
(2)
When the EN pin is pulled low to switch the IC off, the SS pin voltage is discharged to zero by the resistor R3.
The discharge period depends on the RC time constant. Note that if the SS pin voltage is not discharged to zero
before the IC is enabled again, the soft start circuit may not slow the output voltage startup and may not reduce
the startup inrush current.
9.2.1.2.4 Switch Duty Cycle
The maximum switch duty cycle (D) of the TPS61093-Q1 is 90% (minimum). The duty cycle of a boost converter
under continuous conduction mode (CCM) is given by:
Vout + 0.8 V - Vin
D=
Vout + 0.8 V
(3)
The duty cycle must be lower than the specification in the application; otherwise the output voltage cannot be
regulated.
The TPS61093-Q1 has a minimum ON pulse width once the PWM switch is turned on. As the output current
drops, the device enters discontinuous conduction mode (DCM). If the output current drops extremely low,
causing the ON time to be reduced to the minimum ON time, the TPS61093-Q1 enters pulse-skipping mode. In
this mode, the device keeps the power switch off for several switching cycles to keep the output voltage in
regulation. See Figure 14. The output current when the IC enters skipping mode is calculated with Equation 4.
Iout_skip =
2
Vin2 ´ Tmin_on
´ fSW
2 ´ (Vout + 0.8V - Vin) ´ L
where
•
•
•
12
Tmin_on = Minimum ON pulse width specification (typically 65-ns);
L = Selected inductor value;
fSW = Converter switching frequency (typically 1.2-MHz)
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9.2.1.2.5 Inductor Selection
Because the selection of the inductor affects steady state operation, transient behavior, and loop stability, the
inductor is the most important component in power regulator design. There are three important inductor
specifications, inductor value, saturation current, and dc resistance. Considering inductor value alone is not
enough.
The saturation current of the inductor should be higher than the peak switch current as calculated in Equation 5.
DI
IL_peak = IL_DC + L
2
Vout ´ Iout
IL_DC =
Vin ´ h
1
DIL =
é
1
1 öù
æ
êL ´ ¦ SW ´ ç Vout + 0.8 V - VIN + VIN ÷ ú
è
øû
ë
where
•
•
•
•
IL_peak = Peak switch current
IL_DC = Inductor average current
ΔIL = Inductor peak to peak current
η = Estimated converter efficiency
(5)
Normally, it is advisable to work with an inductor peak-to-peak current of less than 30% of the average inductor
current. A smaller ripple from a larger valued inductor reduces the magnetic hysteresis losses in the inductor and
EMI. But in the same way, load transient response time is increased. Also, the inductor value should not be
outside the 2.2-μH to 10-μH range in the recommended operating conditions table. Otherwise, the internal slope
compensation and loop compensation components are unable to maintain small signal control loop stability over
the entire load range. Table 3 lists the recommended inductor for the TPS61093-Q1.
Table 3. Recommended Inductors for the TPS61093-Q1
Part Number
L (μH)
DCR Max (mΩ)
Saturation Current (A)
Size (L×W×H mm)
Vendor
#A915_Y-4R7M
4.7
45
1.5
5.2x5.2x3.0
Toko
#A915_Y-100M
10
90
1.09
5.2x5.2x3.0
Toko
VLS4012-4R7M
4.7
132
1.1
4.0x4.0x1.2
TDK
VLS4012-100M
10
240
0.82
4.0x4.0x1.2
TDK
CDRH3D23/HP
10
198
1.02
4.0x4.0x2.5
Sumida
LPS5030-103ML
10
127
1.4
5.0x5.0x3.0
Coilcraft
9.2.1.2.6 Input And Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. This ripple
voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a ceramic
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by:
D ´ Iout
Cout =
Fs ´ Vripple
where
•
Vripple = peak to peak output ripple
(6)
The ESR impact on the output ripple must be considered if tantalum or electrolytic capacitors are used.
Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging, and ac signal. For
example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the
switching frequency. So the effective capacitance is significantly lower. The dc bias can also significantly reduce
capacitance. A ceramic capacitor can lose as much as 50% of its capacitance at its rated voltage. Therefore,
always leave margin on the voltage rating to ensure adequate capacitance at the required output voltage.
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Product Folder Links: TPS61093-Q1
13
TPS61093-Q1
SLVSCO6 – JANUARY 2015
www.ti.com
A 4.7-μF (minimum) input capacitor is recommended. The output requires a capacitor in the range of 1 μF to 10
μF. The output capacitor affects the small signal control loop stability of the boost regulator. If the output
capacitor is below the range, the boost regulator can potentially become unstable.
The popular vendors for high value ceramic capacitors are:
• TDK (http://www.component.tdk.com/components.php)
• Murata (http://www.murata.com/cap/index.html)
9.2.1.2.7 Small Signal Stability
The TPS61093-Q1 integrates slope compensation and the RC compensation network for the internal error
amplifier. Most applications will be control loop stable if the recommended inductor and input/output capacitors
are used. For those few applications that require components outside the recommended values, the internal error
amplifier’s gain and phase are presented in Figure 9.
80
180
VFB
VEA
135
Phase
60
90
Gain - dB
45
20
Gain
0
fzea
0
fp-ea
-45
Phase - deg
40
-90
-20
-135
-40
10
100
1k
10k
f - Frequency - Hz
100k
-180
1M
Figure 9. Bode Plot of Error Amplifier Gain and Phase
The RC compensation network generates a pole fp-ea of 57-kHz and a zero fz-ea of 1.9-kHz, shown in Figure 9.
Use Equation 7 to calculate the output pole, fP, of the boost converter. If fP
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