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TPS61280D
SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
TPS6128xD Low-IQ, Wide-Voltage Battery Front-End DC/DC Converter for
Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications
1 Features
3 Description
•
•
The TPS6128xD device provides a power supply
solution for products powered by either by a Li-Ion,
Nickel-Rich, Silicon Anode, Li-Ion or LiFePO4 battery.
The voltage range is optimized for single-cell portable
applications like in smart-phones or tablet PCs.
1
•
•
•
•
•
•
•
•
•
•
•
95% Efficiency at 2.3 MHz Operation
3-µA Quiescent Current in Low IQ Pass-Through
Mode
Wide VIN Range From 2.3 V To 4.8 V
IOUT ≥ 4A (Peak) at VOUT = 3.35 V, VIN ≥ 2.65 V
Integrated Pass-Through Mode (35 mΩ)
Programmable Valley Inductor Current Limit and
Output Voltage
True Pass-Through Mode During Shutdown
Best-in-Class Line and Load Transient
Low-Ripple Light-Load PFM Mode
In-Situ Customization with On-Chip E2PROM
(Write Protection)
Two Interface Options:
– I2C Compatible I/F up to 3.4 Mbps
(TPS61280D)
– Simple I/O Logic Control Interface
Thermal Shutdown and Overload Protection
Total Solution Size < 20 mm2, Sub 1-mm Profile
Used as a high-power pre-regulator, the TPS6128xD
extends the battery run-time and overcomes input
current- and voltage limitations of the powered
system.
While in shutdown, the TPS6128xD operates in a true
pass-through mode with only 3-µA quiescent
consumption for longest battery shelf life.
During operation, when the battery is at a good stateof-charge, a low-ohmic, high-efficient integrated passthrough path connects the battery to the powered
system.
If the battery gets to a lower state of charge and its
voltage becomes lower than the desired minimum
system voltage, the device seamlessly transits into
boost mode to uses the full battery capacity.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
PACKAGE
BODY SIZE (NOM)
TPS61280D
Single-Cell Ni-Rich, Si-Anode, Li-Ion, LiFePO4
Smart-Phones or Tablet PCs
2.5G, 3G, 4G Mini-Module Data Cards
Current Limited Applications Featuring High Peak
Power Loads
TPS61281D
DSBGA (16)
1.66 mm x 1.66 mm
TPS61282D
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
TPS61280D
SW
VOUT
SW
VOUT
VBAT’
L
0.47μH
VIN
Battery
2.5V .. 4.35V
CO (x2)
10µF X5R 6.3V (0603)
VIN
CI
1.5µF X5R 6.3V (0402)
Voltage Select
Enable
Forced Bypass / Auto
VSEL
EN
1.8V
BYP
SCL
2
I C Bus
SDA
GPIO
Interrupt
PGND
PGND
PGND
AGND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61280D
SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9
1
1
1
2
3
3
4
6
Absolute Maximum Ratings ..................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 7
I2C Interface Timing Characteristics ........................ 9
I2C Timing Diagrams............................................... 11
Typical Characteristics ............................................ 12
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 17
9.5 Programming........................................................... 22
9.6 Register Maps ......................................................... 25
10 Application and Implementation........................ 33
10.1 Application Information.......................................... 33
10.2 Typical Application ................................................ 34
11 Power Supply Recommendations ..................... 46
12 Layout................................................................... 46
12.1 Layout Guidelines ................................................. 46
12.2 Layout Example .................................................... 46
12.3 Thermal Information .............................................. 47
13 Device and Documentation Support ................. 48
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
48
14 Mechanical, Packaging, and Orderable
Information ........................................................... 49
14.1 Package Summary................................................ 49
4 Revision History
Changes from Original (January 2018) to Revision A
Page
•
Changed devices TPS61281D and TPS61282D From: Product Preview To: Production data ............................................. 1
•
Changed the TPS61280D pin configuration ........................................................................................................................... 4
•
Changed the TPS6128xD pin configuration ........................................................................................................................... 5
2
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SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
5 Description (continued)
TPS6128xD device supports more than 4 A pulsed load current even from a deeply discharged battery. In this
mode of operation, the TPS6128xD enables the use of the full battery capacity: A high battery-cut-off voltage
originated by powered components with a high minimum input voltage is overcome; new battery chemistries can
be fully discharged; high current pulses forcing the system into shutdown are buffered by the device seamlessly
transitioning between boost and by-pass mode back and forth.
This has significant impact on the battery on-time and translates into either a longer use-time and better userexperience at an equal battery capacity or into reduced battery costs at similar use-times.
The TPS6128xD offers a small solution size (< 20 mm2) due to minimum amount of external components,
enabling the use of small inductors and input capacitors, available as a 16-pin chip-scale package (CSP).
The TPS6128xD operates in synchronous, 2.3 MHz boost mode and enters power-save mode operation (PFM)
at light load currents to maintain high efficiency over the entire load current range.
6 Device Comparison Table
DEVICE
SPECIFIC FEATURES
PART NUMBER
TPS61280D
DC/DC boost / bypass threshold = 3.15 V (VSEL = L)
I2C Control Interface
User Prog. E2PROM Settings
DC/DC boost / bypass threshold = 3.35 V (VSEL = H)
Valley inductor current limit = 3 A
DC/DC boost / bypass threshold = 3.15 V (VSEL = L)
TPS61281D
Simple Logic Control Interface
DC/DC boost / bypass threshold = 3.35 V (VSEL = H)
Valley inductor current limit = 3 A
DC/DC boost / bypass threshold = 3.3 V (VSEL = L)
TPS61282D
Simple Logic Control Interface
DC/DC boost / bypass threshold = 3.5 V (VSEL = H)
Valley inductor current limit = 4 A
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7 Pin Configuration and Functions
TPS61280D YFF Package
16-Bump DSBGA
Top View
1
A
2
EN
B
GPIO
VSEL
VOUT
SDA
AGND
D
VIN
SCL
nBYP
C
3
SW
PGND
PGND
TPS61280D YFF Package
16-Bump DSBGA
Bottom View
4
1
2
3
4
D
AGND
PGND
PGND
PGND
C
nBYP
SDA
SW
SW
B
VSEL
SCL
VOUT
VOUT
A
EN
GPIO
VIN
VIN
VIN
VOUT
SW
PGND
Not to scale
Not to scale
Pin Functions, TPS61280D
PIN
NAME
NO.
I/O
DESCRIPTION
VIN
A3, A4
I
Power supply input.
VOUT
B3, B4
O
Boost converter output.
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN
A1
I
EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the
logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be
regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current
consumption is reduced to a few µA. For more details, refer to Table 2.
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For
more details, refer to Table 2.
This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/FAULT )
pin. Per default, the pin is configured as RST/FAULT input/output. The input must not be left floating and must be
terminated.
Manual Reset Input: Drive RST/FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a
falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output
followed by a start-up phase.
GPIO
A2
I/O
Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output
voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling edgetriggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state.
Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at
high-load currents and in pulse frequency modulation mode (PFM) at light load currents.
Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced.
VSEL
B1
I
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
nBYP
C1
I
A logic low level on the BYP input forces the device in pass-through mode. This pin must not be left floating and
must be terminated.
Serial interface clock line. This pin must not be left floating and must be terminated.
SCL
B2
I
SDA
C2
I/O
Serial interface address/data line. This pin must not be left floating and must be terminated.
SW
C3, C4
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
PGND
D2, D3, D4
AGND
D1
4
Power ground pin.
Analog ground pin. This is the signal ground reference for the IC.
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TPS6128xD YFF Package
16-Bump DSBGA
Top View
1
A
2
EN
B
PG
VSEL
VOUT
AGND
AGND
D
VIN
MODE
nBYP
C
3
SW
PGND
PGND
TPS6128xD YFF Package
16-Bump DSBGA
Bottom View
4
1
2
3
4
D
AGND
PGND
PGND
PGND
C
nBYP
AGND
SW
SW
B
VSEL
MODE
VOUT
VOUT
A
EN
PG
VIN
VIN
VIN
VOUT
SW
PGND
Not to scale
Not to scale
Pin Functions, TPS6128xD
PIN
NAME
NO.
I/O
DESCRIPTION
VIN
A3, A4
I
Power supply input.
VOUT
B3, B4
O
Boost converter output.
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN
A1
I
EN = Low: The device is forced into shutdown mode. Depending on the logic level applied to the nBYP input, the
converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit
the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For
more details, refer to Table 2.
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For
more details, refer to Table 2.
PG
A2
O
Power-Good Output (open-drain output to host): A logic high on the PG output indicates that the converter's output
voltage is within its regulation limits. A logic low indicates a fault has occurred (e.g. thermal shutdown, output voltage
out of limits, current limit triggered, and so on). The PG signal is de-asserted automatically once the IC resumes
proper operation.
VSEL
B1
I
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
nBYP
C1
I
A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to Table 2. This
pin must not be left floating and must be terminated.
This is the mode selection pin of the device. This pin must not be left floating, must be terminated and can be
connected to AGND. During start-up this pin must be held low. Once the output voltage settled and PG pin indicates
that the converter's output voltage is within its regulation limits the device can be forced in PWM mode operation by
applying a high level on this pin.
MODE
B2
I
C3, C4
I/O
MODE = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load
currents and in pulse frequency modulation mode (PFM) at light load currents. This pin must be held low during
device start-up.
MODE = High: Low-noise mode enabled, regulated frequency PWM operation forced.
SW
PGND
D2, D3, D4
AGND
C2, D1
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
Power ground pin.
Analog ground pin. This is the signal ground reference for the IC.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage at VOUT (2)
Voltage at VIN
GPIO (2)
(2)
(2)
(2)
, EN , VSEL , BYP
(2)
, PG ,
Voltage at SW (2)
Differential voltage between VIN and VOUT
Continuous average current into SW
Input current
Peak current into SW
MAX
UNIT
–0.3
4.7
V
DC
–0.3
5.2
V
DC
–0.3
3.6
V
DC
–0.3
4.7
V
Transient: 2 ns, 2.3
MHz
–0.3
5.5
V
DC
–0.3
4
V
1.8
A
5.5
A
(2)
Voltage at SCL (2), SDA (2)MODE (2)
Input voltage
MIN
DC
(3)
(4)
Power dissipation
Temperature range
Tstg
(1)
(2)
(3)
(4)
(5)
Internally limited
Operating temperature range, TA
(5)
–40
85
°C
Operating virtual junction, TJ
–40
150
°C
Storage temperature range
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
Limit the junction temperature to 105°C for continuous operation at maximum output power.
Limit the junction temperature to 105°C for 15% duty cycle operation.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
8.2 ESD Ratings
VALUE
UNIT
±2000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±1000
V
Machine Model - (MM)
±200
V
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins
VESD
(1)
(2)
Electrostatic discharge
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
VI
Input voltage range
NOM
2.30
MAX
UNIT
4.85
V
Input voltage range for in-situ customization by E2PROM write operation
3.4
3.5
3.6
V
L
Inductance
200
470
800
nH
CO
Output capacitance
9
13
100
IL
Maximum load current during start-up
250
TA
Ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
6
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µF
mA
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8.4 Thermal Information
TPS6128xD
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
78
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
0.6
°C/W
RθJB
Junction-to-board thermal resistance
13
°C/W
ψJT
Junction-to-top characterization parameter
2.4
°C/W
ψJB
Junction-to-board characterization parameter
13
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Minimum and maximum values are at VIN = 2.3 V to 4.85 V, VOUT = 3.4 V (or VIN, whichever is higher), EN = 1.8 V, VSEL =
1.8 V, nBYP = 1.8 V, –40°C ≤ TJ ≤ 125°C; Circuit of Parameter Measurement Information section (unless otherwise noted).
Typical values are at VIN = 3.2 V, VOUT = 3.4 V, EN = 1.8 V, TJ = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC/DC boost mode. Device not
switching
IOUT = 0 mA, VIN = 3.2 V, VOUT = 3.4 V
47.4
65.6
µA
Pass-through mode (auto)
EN = 1.8 V, BYP = 1.8 V, VIN = 3.6 V
27.4
42.6
µA
15.4
25.6
µA
8.9
19.6
µA
SUPPLY CURRENT
Operating quiescent current
into VIN
IQ
TPS6128xD
VUVLO
Shutdown current
Under-voltage lockout threshold
–40°C ≤ TJ ≤
85°C
DC/DC boost mode. Device not
switching
IOUT = 0 mA, VIN = 3.2 V, VOUT = 3.4 V
Operating quiescent current
into VOUT
ISD
Pass-through mode (forced)
EN = 1.8 V, BYP = AGND, VOUT = 3.6 V
TPS6128xD
TPS6128xD
EN = 0 V, BYP = 0 V, VIN = 3.6 V
EN = 0 V, BYP = 1.8 V, VIN = 3.6 V
Falling
Hysteresis
3
6.6
μA
8.9
20.6
μA
2
2.1
V
0.1
V
EN, VSEL, nBYP, MODE, SDA, SCL, GPIO, PG
VIL
Low-level input voltage
VIH
High-level input voltage
Low-level output voltage (SDA)
VOL
RPD
CIN
VTHPG
Ilkg
Low-level output voltage (GPIO)
0.4
TPS6128xD
TPS61280D
1.2
V
V
IOL = 8 mA
0.3
V
IOL = 8 mA, GPIOCFG = 0
0.3
V
0.3
V
Low-level output voltage (PG)
TPS6128xD
IOL = 8 mA
EN, VSEL, BYP,
pull-down resistance
TPS6128xD
Input ≤ 0.4 V
EN, VSEL, BYP, MODE, PG
input capacitance
TPS6128xD
SDA, SCL, GPIO input
capacitance
TPS61280D
Power good threshold
TPS6128xD
300
kΩ
9
pF
9
pF
Input connected to AGND or VIN
Input leakage current
TPS6128xD
Threshold DC voltage accuracy
TPS6128xD
Rising VOUT
0.95 x VOUT
Falling VOUT
0.9 x VOUT
Input connected to AGND
Input connected VIN
0
–40°C ≤ TJ ≤
85°C
µA
0.5
µA
OUTPUT
VOUT(TH)
VOUT
Regulated DC voltage accuracy
TPS6128xD
No load. Open loop
-1.5%
1.5%
2.65 V ≤ VIN ≤ VOUT_TH - 150 mV
IOUT = 0mA
PWM operation.
-2%
2%
2.65 V ≤ VIN ≤ VOUT_TH - 150 mV
IOUT = 0 mA
PFM/PWM operation
-2%
4%
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Electrical Characteristics (continued)
Minimum and maximum values are at VIN = 2.3 V to 4.85 V, VOUT = 3.4 V (or VIN, whichever is higher), EN = 1.8 V, VSEL =
1.8 V, nBYP = 1.8 V, –40°C ≤ TJ ≤ 125°C; Circuit of Parameter Measurement Information section (unless otherwise noted).
Typical values are at VIN = 3.2 V, VOUT = 3.4 V, EN = 1.8 V, TJ = 25°C (unless otherwise noted).
PARAMETER
ΔVOUT
Power-save mode
output ripple voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PFM operation, IOUT = 1 mA
30
mVpk
PWM operation, IOUT = 500 mA
15
mVpk
VIN = 3.2 V, VOUT = 3.5 V
45
80
mΩ
VIN = 3.2 V, VOUT = 3.5 V
40
70
mΩ
High-side pass-through MOSFET
on resistance
VIN = 3.2 V
35
60
mΩ
Reverse leakage current into SW
EN = AGND, VIN = VOUT = SW = 3.5 V
–40°C ≤ TJ ≤ 85°C
0.1
2
µA
0.11
2
µA
0.3
V
TPS6128xD
PWM mode output ripple voltage
POWER SWITCH
Low-side switch MOSFET
on resistance
rDS(on)
Ilkg
High-side rectifier MOSFET
on resistance
Reverse leakage current into
VOUT
ISINK
TPS6128xD
TPS6128xD
EN = BYP = VIN, VIN = 2.9 V, VOUT = 4.4 V, VSW = 0 V
device not switching
–40°C ≤ TJ ≤ 85°C
EN = AGND, VOUT ≤ 3.6 V,IOUT = -10 mA
VOUT sink capability
TPS6128xD
Valley inductor current limit
TPS61280D VIN = 2.9 V, VOUT = 3.5 V, –40°C ≤ TJ ≤ 125°C, auto
TPS61281D PFM/PWM
2475
3000
3525
mA
Valley inductor current limit
TPS61282D
VIN = 2.9 V, VOUT = 3.5 V, –40°C ≤ TJ ≤ 125°C, auto
PFM/PWM
3300
4000
4700
mA
Pass through mode current limit
TPS6128xD
Pre-charge mode current limit
(linear mode, phase 1)
Pre-charge mode current limit
(linear mode, phase 2)
TPS6128xD
EN = BYP = GND, VIN = 3.2 V
5000
EN = VIN, BYP = don't care , VIN = 3.2 V
mA
5600
7400
9100
mA
500
650
mA
2000
mA
2.3
MHz
VIN - VOUT >= 300 mV
OSCILLATOR
fOSC
Oscillator frequency
TPS6128xD
VIN = 2.7 V, VOUT = 3.5 V
THERMAL SHUTDOWN, HOT DIE DETECTOR
Thermal shutdown (1)
TPS6128xD
140
160
Hot die detector accuracy (1)
TPS61280D
-10
105
Start-up time
TPS6128xD
°C
10
°C
TIMING
GPIO rise time
(1)
8
(1)
VIN = 3.2 V, VOUT_TH = 01011 (3.4 V), RLOAD = 50 Ω
Time from active VIN to VOUT settled
TPS61280D
500
µs
200
ns
Specified by characterization. Not tested in production.
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8.6 I2C Interface Timing Characteristics (1)
PARAMETER
TEST CONDITIONS
MAX
UNIT
Standard mode
MIN
100
kHz
Fast mode
400
kHz
1
MHz
High-speed mode (write operation), CB – 100 pF max
3.4
MHz
High-speed mode (read operation), CB – 100 pF max
3.4
MHz
High-speed mode (write operation), CB – 400 pF max
1.7
MHz
High-speed mode (read operation), CB – 400 pF max
1.7
MHz
Fast mode plus
f(SCL)
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
tBUF
tHD, tSTA
tLOW
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
Standard mode
4.7
μs
Fast mode
1.3
μs
Fast mode plus
0.5
μs
Standard mode
4
μs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode
160
ns
Standard mode
4.7
μs
Fast mode
1.3
μs
Fast mode plus
0.5
μs
High-speed mode, CB – 100 pF max
160
ns
High-speed mode, CB – 400 pF max
320
ns
Standard mode
tHIGH
HIGH Period of the SCL Clock
tSU, tSTA
tSU, tDAT
tHD, tDAT
Setup Time for a Repeated START
Condition
Data Setup Time
Data Hold Time
4
μs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode, CB – 100 pF max
60
ns
High-speed mode, CB – 400 pF max
120
ns
Standard mode
4.7
μs
Fast mode
600
ns
Fast mode plus
260
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
Fast mode plus
50
ns
High-speed mode
10
Standard mode
0
3.45
μs
Fast mode
0
0.9
μs
Fast mode plus
0
High-speed mode, CB – 100 pF max
0
70
ns
High-speed mode, CB – 400 pF max
0
Standard mode
Fast mode
tRCL
tRCL1
(1)
Rise Time of SCL Signal
Rise Time of SCL Signal After a Repeated
START Condition and After an
Acknowledge BIT
20 + 0.1 CB
Fast mode plus
ns
μs
150
ns
1000
ns
300
ns
120
ns
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
120
ns
Fast mode plus
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
Specified by design. Not tested in production.
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I2C Interface Timing Characteristics(1) (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
20 + 0.1 CB
300
ns
Fast mode
300
ns
Fast mode plus
120
ns
Standard mode
tFCL
Fall Time of SCL Signal
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
1000
ns
300
ns
120
ns
Standard mode
Fast mode
tRDA
Rise Time of SDA Signal
20 + 0.1 CB
Fast mode plus
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
300
ns
300
ns
120
ns
Standard mode
Fast mode
tFDA
tSU, tSTO
CB
10
Fall Time of SDA Signal
Setup Time of STOP Condition
Capacitive Load for SDA and SCL
20 + 0.1 CB
Fast mode plus
High-speed mode, CB – 100 pF max
10
80
ns
High-speed mode, CB – 400 pF max
20
160
ns
Standard mode
4
μs
Fast mode
600
ns
Fast mode plus
260
ns
High-Speed mode
160
ns
Standard mode
400
pF
Fast mode
400
pF
Fast mode plus
550
pF
High-Speed mode
400
pF
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8.7 I2C Timing Diagrams
SDA
tf
tLOW
tf
tsu;DAT
tr
tBUF
tr
thd;STA
SCL
S
thd;STA
thd;DAT
tsu;STA
tsu;STO
HIGH
Sr
P
S
Figure 1. Serial Interface Timing Diagram for Standard-, Fast-, Fast-Mode Plus
Sr
Sr P
tfDA
trDA
SDAH
tsu;STA
thd;DAT
thd;STA
tsu;STO
tsu;DAT
SCLH
tfCL
trCL1
See Note A
trCL1
trCL
tHIGH
tLOW
tLOW
tHIGH
See Note A
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 2. Serial Interface Timing Diagram for H/S-Mode
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50
70
48
65
46
LS FET On Resistance (m
HS FET On Resistance (m
8.8 Typical Characteristics
44
42
40
38
36
34
60
55
50
45
40
35
32
30
30
-40
-20
0
20
40
60
80
100
Junction Temperature (ƒC)
VIN = 3.2 V
VOUT = 3.5 V
-40
120
-20
0
20
40
60
80
100
120
Junction Temperature (ƒC)
C001
TJ = –40 to 125°C
VIN = 3.2 V
Figure 3. High side Rds(on) vs Junction Temperature
VOUT = 3.5 V
C002
TJ = –40 to 125°C
Figure 4. Low side Rds(on) vs Junction Temperature
50
60
Quiescent Current_Boost (µA)
LS FET On Resistance (m
48
46
44
42
40
38
36
34
50
40
Tj=25C
T
J = 30°C
Tj=-40
T
J = -40°C
32
30
-20
0
20
40
60
80
100
120
Junction Temperature (ƒC)
VIN = 3.2 V
Bypass
2.3
TJ = –40 to 125°C
VIN = 2.3 - 3.4 V
EN = High
2.7
2.9
3.1
VOUT = 3.4 V
Bypass = High
C004
IOUT = 0 mA
Figure 6. Quiescent Current at Boost Mode vs Input Voltage
35
Quiescent Current_Auto Bypass (µA)
20
Quiescent Current_Force Bypass (µA)
2.5
Input Voltage (V)
C003
Figure 5. Bypass FET Rds(on) vs Junction Temperature
18
16
14
T
Tj=25C
J = 30°C
12
Tj=-40
T
J = -40°C
T
TjJ = 85°
85 C
C
10
3.5
VIN = 3.5 - 4.4 V
EN = High
VOUT = 3.4 V
Bypass = Low
33
31
29
27
25
23
21
T
Tj=25C
J = 30°C
19
Tj=-40
T
J = -40°C
17
T
TjJ = 85°
85 C
C
15
4.5
Input Voltage (V)
3.5
IOUT = 0 mA
4.5
Input Voltage (V)
C005
Figure 7. Quiescent Current at Forced Bypass Mode vs
Input Voltage
12
T
85°C
TjJ = 85
30
-40
VIN = 3.6 - 4.4 V
EN = High
VOUT = 3.4 V
Bypass = High
C006
IOUT = 0 mA
Figure 8. Quiescent Current at Auto Bypass Mode vs Input
Voltage
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Typical Characteristics (continued)
5
13
Leakage Current_Low Iq (µA)
Leakage Current_Low Iq (µA)
12
4
3
2
Tj=25C
T
J = 30°C
1
Tj=-40
T
J = -40°C
2.3
3.3
9
8
7
6
TJ = -40
-40°C
Tj
TJ = 85
85°C
Tj
3
2.3
3.3
VOUT = 4.4 V
Bypass = Low
VSW = 0 V
4.3
Input Voltage (V)
C007
VIN = 2.3 - 4.4 V
EN = Low
Figure 9. Shutdown Current at Low IQ mode vs Input
Voltage
C008
VOUT = 4.4 V
Bypass = High
VSW = 0 V
Figure 10. Shutdown Current vs Input Voltage
4.5
2.20
4.0
Vin UVLO Threshold (V)
Switch Valley Current Limit (A)
Tj
TJ = 25C
30°C
5
4.3
Input Voltage (V)
VIN = 2.3 - 4.4 V
EN = Low
10
4
TjJ = 85°
85 C
C
T
0
11
3.5
3.0
2.5
TPS61281D
2.00
Vin
VIN Rising
TPS61282D
2.0
VIN Falling
Vin
Falling
1.80
-40
10
60
110
O
Temperature ( C)
VIN = 3.2 V
EN = High
-40
-20
0
VOUT = 3.5 V
Bypass = High
TJ = –40 to 125°C
Figure 11. Switch Valley Current Limit: TPS61281D,
TPS61282D vs Input Voltage
20
40
60
80
VIN = 3.2 V
120
VOUT = 3.5 V
C010
TJ = –40 to 125°C
Figure 12. VIN UVLO Threshold Rising/Falling vs Junction
Temperature
1.10
1.10
EN Rising
nBYP Rising
EN Falling
nBYP Falling
1.00
EN Logic Threshold (V)
1.00
EN Logic Threshold (V)
100
Junction Temperature (ƒC)
C009
0.90
0.80
0.70
0.60
0.90
0.80
0.70
0.60
0.50
0.50
-40
-20
0
20
40
60
80
Junction Temperature (ƒC)
VIN = 3.2 V
VOUT = 3.5 V
100
120
-40
-20
TJ = –40 to 125°C
Figure 13. EN Logic High Threshold Rising/Falling vs
Junction Temperature
0
20
40
60
80
100
120
Junction Temperature (ƒC)
C011
VIN = 3.2 V
C012
TJ = –40 to 125°C
Figure 14. BYP Logic High Threshold Rising/Falling vs
Junction Temperature
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9 Detailed Description
9.1 Overview
The TPS6128xD is a high-efficiency step-up converter featuring pass-through mode optimized to provide lownoise voltage supply for 2G RF power amplifiers (PAs) in mobile phones and/or to pre-regulate voltage for
supplying subsystem like eMMC memory, audio codec, LCD bias, antenna switches, RF engine PMIC and so on.
It is designed to allow the system to operate at maximum efficiency for a wide range of power consumption levels
from a low-, wide- voltage battery cell.
The capability of the TPS6128xD to step-up the voltage as well as to pass-through the input battery voltage
when its level is high enough allow systems to operate at maximum performance over a wide range of battery
voltages, thereby extending the battery life between charging. The device also addresses brownouts caused by
the peak currents drawn by the APU and GPU which can cause the battery rail to droop momentarily. Using the
TPS6128xD device as a pre-regulator eliminates system brownout condition while maintaining a stable supply
rail for critical sub-system to function properly.
The TPS6128xD synchronous step-up converter typically operates at a quasi-constant 2.3-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6128xD converter
operates in power-save mode with pulse frequency modulation (PFM).
In general, a dc/dc step-up converter can only operate in "true" boost mode, that is the output “boosted” by a
certain amount above the input voltage. The TPS6128xD device operates differently as it can smoothly transition
in and out of zero duty cycle operation. Depending upon the input voltage, output voltage threshold and load
current, the integrated bypass switch automatically transitions the converter into pass-through mode to maintain
low-dropout and high-efficiency. The device exits pass-through mode (0% duty cycle operation) if the total
dropout resistance in bypass mode is insufficient to maintain the output voltage at it's nominal level. Refer to the
typical characteristics section (DC Output Voltage vs. Input Voltage) for further details.
During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to
achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on
the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the lowside N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the ontime and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the
inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on
timer again and activating the low-side N-MOS switch.
The current mode architecture provides excellent transient load response, requiring minimal output filtering.
Internal soft-start and loop compensation simplifies the design process while minimizing the number of external
components.
The TPS6128xD directly and accurately controls the average input current through intelligent adjustment of the
valley current limit, allowing an accuracy of ±17.5%. Together with an external bulk capacitor, the TPS6128xD
allows an application to be interfaced directly to its load, without overloading the input source due to appropriate
set average input current limit. An open-drain output (PG or GPIO/nFAULT) provides a signal to issue an
interrupt to the system if any fault is detected on the device (thermal shutdown, output voltage out-of limits, and
so on).
The output voltage can be dynamically adjusted between two values (floor and roof voltages) by toggling a logic
control input (VSEL) without the need for external feedback resistors. This features can either be used to raise
the output voltage in anticipation of a positive load transient or to dynamically change the PA supply voltage
depending on its mode of operation and/or transmitting power.
The TPS61280D integrates an I2C compatible interface allowing transfers up to 3.4Mbps. This communication
interface can be used to set the output voltage threshold at which the converter transitions between boost and
pass-through mode, for reprogramming the mode of operation (PFM/PWM or forced PWM), for settings the
average input current limit or resetting the output voltage for instance.
Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The
I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the
E2PROMCTRL Register [reset = 0xFF], it is possible to store the active configuration in non-volatile E2PROM;
during power-up, the contents of the E2PROM are copied into the I2C registers and used to configure the device.
14
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9.2 Functional Block Diagram
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9.3 Feature Description
9.3.1 Voltage Scaling Management (VSEL)
In order to maintain a certain minimum output voltage under heavy load transients, the output voltage set point
can be dynamically increased by asserting the VSEL input. The functionality also helps to mitigate undershoot
during severe line transients, while minimizing the output voltage during more benign operating conditions to
save power.
The output voltage ramps up (floor to roof transition) at pre-defined rate defined by the average input current limit
setting. The required time to ramp down the voltage (roof to floor transition) largely depends on the amount of
capacitance present at the converter's output as well as on the load current. Table 1 shows the ramp rate control
when transitioning to a lower voltage.
Table 1. Ramp Down Rate vs. Target Mode
Mode Associated with Floor Voltage
Output Voltage Ramp Rate
Forced PWM
Output capacitance is being discharged at a rate of approx. 50mA (or higher) constant current
in addition to the load current drawn
PFM
Output capacitance is being discharged (solely) by the load current drawn
9.3.2 Spread Spectrum, PWM Frequency Dithering
The goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar
to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to
comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in
cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that
is focused on specific frequencies.
Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or regulated, based on the output load. This method of conversion
creates large components of noise at the frequency of operation (fundamental) and multiples of the operating
frequency (harmonics).
The spread spectrum architecture varies the switching frequency by ca. ±15% of the nominal switching frequency
thereby significantly reducing the peak radiated and conducting noise on both the input and output supplies. The
frequency dithering scheme is modulated with a triangle profile and a modulation frequency fm.
0 dBV
FENV,PEAK
Dfc
Dfc
Non-modulated harmonic
F1
Side-band harmonics
window after modulation
0 dBVref
B = 2 × fm × (1 + mf ) = 2 × ( Dfc + fm )
Bh = 2 × fm × (1 + mf × h )
B = 2 × fm × (1 + mf ) = 2 × ( Dfc + fm )
Figure 15. Spectrum of a Frequency Modulated
Sin. Wave with Sinusoidal Variation in Time
Figure 16. Spread Bands of Harmonics in
Modulated Square Signals (1)
The above figures show that after modulation the sideband harmonic is attenuated compared to the nonmodulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the
modulation index (mf) the larger the attenuation.
(1)
16
Spectrum illustrations and formulae (Figure 15 and Figure 16) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC
COMPATIBILITY, VOL. 47, NO.3, AUGUST 2005.
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mƒ =
δ ´ ƒc
ƒm
where
•
•
•
d=
fc is the carrier frequency (approx. 2.3MHz)
fm is the modulating frequency (approx. 40kHz)
δ is the modulation ratio (approx 0.15)
(1)
D ƒc
ƒc
(2)
The maximum switching frequency fc is limited by the process and finally the parameter modulation ratio (δ),
together with fm , which is the side-band harmonics bandwidth around the carrier frequency fc. The bandwidth of
a frequency modulated waveform is approximately given by the Carson’s rule and can be summarized as:
(
B = 2 ´ ¦m ´ 1 + m ¦
)=2
´
(D ¦c
+ ¦m )
(3)
fm < RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are
added in the input filter and the measured value is higher than expected in theoretical calculations.
fm > RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the
measurements match with the theoretical calculations.
9.4 Device Functional Modes
9.4.1 Power-Save Mode
The TPS6128xD integrates a power-save mode to improve efficiency at light load. In power save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold
voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in
PFM mode.
Figure 17. Power-Save Mode Ripple
9.4.2 Pass-Through Mode
The TPS6128xD contains an internal switch for bypassing the dc/dc boost converter during pass-through mode.
When the input voltage is larger than the preset output voltage, the converter seamlessly transitions into 0% duty
cycle operation and the bypass FET is fully enhanced. Entry in pass-through mode is triggered by condition
where VOUT >(1+2%)* VOUT_NORM and no switching has occurred during past 8µs.
In this mode of operation, the load (2G RF PA for instance) is directly supplied from the battery for maximum RF
output power, highest efficiency and lowest possible input-to-output voltage difference. The device consumes
only a standby current of 15µA (typ). In pass-through mode, the device is short-circuit protected by a very fast
current limit detection scheme.
During this operation, the output voltage follows the input voltage and will not fall below the programmed output
voltage threshold as the input voltage decreases. The output voltage drop during pass-through mode depends on
the load current and input voltage, the resulting output voltage is calculated as:
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Device Functional Modes (continued)
VOUT = VIN - (R DSON(BP) x IOUT )
(4)
Conversely, the efficiency in pass-through mode is defined as:
η = 1 - R DSON(BP)
•
IOUT
VIN
in which RDSON(BP) is the typical on-resistance of the bypass FET
(5)
4.5
4.4
4.3
4.2
Output Voltage (V)
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
Vout_nom = 3.15V
Vout_nom = 3.35V
Vout_nom = 3.3V
Vout_nom = 3.5V
3.2
3.1
3
2.5
2.7
2.9
3.1
3.3 3.5 3.7 3.9
Input Voltage (V)
4.1
4.3
4.5
G000
Figure 18. DC Output Voltage vs. Input Voltage
Pass-through mode exit is triggered when the output voltage reaches the pre-defined threshold (that is, 3.4V).
During pass-through mode, the TPS6128xD device is short-circuit protected by a fast current limit detection
scheme. If the current in the pass-through FET exceeds approximately 7.3 Amps a fault is declared and the
device cycles through a start-up procedure.
9.4.3 Mode Selection
Depending on the settings of CONFIG Register [reset = 0x01] the device can be operated at a quasi-constant
2.3-MHz frequency PWM mode or in automatic PFM/PWM mode. In this mode, the converter operates in
pseudo-fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which
maintains high efficiency over a wide load current range. For more details, see the CONFIG Register [reset =
0x01] description.
The quasi-constant frequency PWM mode has the tightest regulation and the best line/load transient
performance. In forced PWM mode, the device features a unique RDS(ON) management function to maintain high
broadband efficiency as well as low resistance in pass-through mode.
In the TPS61280D device, the GPIO pin can be configured (via the CONFIG Register [reset = 0x01] ) to select
the operating mode of the device. In the other TPS6128xD devices, the MODE pin is used to select the operating
mode. Pulling this pin high forces the converter to operate in the PWM mode even at light load currents. The
advantage is that the converter modulates its switching frequency according to a spread spectrum PWM
modulation technique allowing simple filtering of the switching harmonics in noise-sensitive applications.
For additional flexibility, it is possible to switch from power-save mode (GPIO or MODE input = L) to PWM mode
(GPIO or MODE input = H) during operation. This allows efficient power management by adjusting the operation
of the converter to the specific system requirements (that is, 2G RF PA Rx/Tx operation).
Entry to forced pass-through mode (nBYP = L) initiates with a current limited transition followed by a true bypass
state. To prevent reverse current to the battery, the devices waits until the output discharges below the input
voltage level before entering forced pass-through mode. Care should be taken to prohibit the output voltage from
collapsing whilst transitioning into forced pass-through mode under heavy load conditions and/or limited output
capacitance. This can be easily done by adding capacitance to the output of the converter. In forced passthrough mode, the output follows the input below the preset output threshold voltage (VOUT_TH).
18
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Device Functional Modes (continued)
9.4.4 Current Limit Operation
The TPS6128xD device features a valley inductor current limit scheme.
In dc/dc boost mode, the TPS6128xD device employs a current limit detection scheme in which the voltage drop
across the synchronous rectifier is sensed during the off-time. In the TPS61280D the current limit threshold can
be set via an I2C register. TPS6128xD devices have a fixed current limit threshold. See Device Comparison
Table for detailed information.
The output voltage is reduced as the power stage of the device operates in a constant current mode. The
maximum continuous output current (IOUT(MAX)), before entering current limit (CL) operation, can be defined by
Equation 6.
I O U T (M A X _ D C ) = I
L IM IT
V IN
´h
VOUT
´
where
•
•
η is the efficiency
The inductor peak-to-peak current ripple (ΔIL) is calculated by Equation 7
(6)
V
D
DI L = IN ´
L
f
(7)
The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is
increased such that the trough is above the current limit threshold, the off-time is increased to allow the current to
decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). When the
current limit is reached the output voltage decreases during further load increase.
Figure 19 illustrates the inductor and rectifier current waveforms during current limit operation.
IL
Current Limit
Threshold
Rectifier
Current
IPEAK
IVALLEY
IOUT
DIL
IOUT(DC)
Increased
Load Current
IIN(DC)
f
Inductor
Current
IIN(DC)
DIL
ΔI L =
V IN D
×
L f
Figure 19. Inductor/Rectifier Currents in Current Limit Operation (DC/DC Boost Mode)
During pass-through mode, the TPS6128xD device is short-circuit protected by a very fast current limit detection
scheme. If the current in the bypass FET exceeds approximately 7.5Amps a fault is declared and the device
cycles through a start-up procedure.
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Device Functional Modes (continued)
9.4.5 Start-Up and Shutdown Mode
The TPS6128xD automatically powers-up as soon as the input voltage is applied. The device has an internal
soft-start circuit that limits the inrush current during start-up. The first phase in the start-up procedure is to bias
the output node close to the input level (so called pre-charge phase).
In this operating mode, the device limits its output current to ca. 500mA. Should the output voltage not have
reached the input level within a maximum duration of 750µs, the device automatically increases its pre-charge
current to ca. 2000mA. If the output voltage still fails to reach its target after 1.5ms, a fault condition is declared.
After waiting 1ms, a restart is attempted.
When output voltage being close to Vout, the device enters into boost startup mode (for Auto Mode only). The
device provides a reduced current limit of ~1.25A (I2C programable for TPS61280D to set it back to normal
current limit) when the output voltage is below pre-set voltage to avoid the high inrush current from battery.
During start-up, it is recommended to keep DC load current draw below 250mA.
The TPS6128xD device contains a thermal regulation loop that monitors the die temperature during the precharge phase. If the die temperature rises to high values of about 110°C, the device automatically reduces the
current to prevent the die temperature from increasing further. Once the die temperature drops about 10°C below
the threshold, the device will automatically increase the current to the target value. This function also reduces the
current during a short-circuit condition.
When the EN and nBYP pins are set high, the device enters normal operation (that is, automatic dc/dc boost,
pass-through mode) and ensures that the output voltage remains above a pre-defined threshold (that is, 3.3 V).
Setting the EN pin low (nBYP = 1) forces the TPS6128xD device in shutdown mode with a current consumption
of 115ºC.
5
DCDCMODE
R
0
DC/DC mode of operation status bit.
1: Device operates in PFM mode.
0: Device operates in PWM mode.
4
OPMODE
R
0
Device mode of operation status bit.
0: Device operates in pass-through mode.
1: Device operates in dc/dc mode.
0
Current limit status bit (pass-through mode).
0: Normal operation.
1: Indicates that the bypass FET current limit has triggered. This
flag is reset after readout.
0
Current limit status bit (dc/dc boost mode).
0: Normal operation.
1: Indicates that the average input current limit has triggered for
1.5ms in dc/dc boost mode. This flag is reset after readout.
0
FAULT status bit.
0: Normal operation.
1: Indicates that a fault condition has occurred. This flag is reset
after readout.
0
Power Good status bit.
0: Indicates the output voltage is out of regulation.
1: Indicates the output voltage is within its nominal range. This
bit is set if the converter is forced in pass-through mode.
3
2
1
0
ILIMPT
ILIMBST
FAULT
PGOOD
R
R
R
R
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9.6.10 E2PROMCTRL Register [reset = 0xFF]
Memory location: 0xFF
Figure 33. E2PROMCTRL Register
7
WEN
R/W
Stored in E2
N
6
WP
R/W
5
ISE2PROMWP
R
4
3
1
0
R/W
2
RESERVED
R/W
R/W
R/W
R/W
Y
N
N
N
N
N
N
Table 9. E2PROMCTRL Register Field Descriptions
Bit
7
6
5
4:0
32
Field
WEN
WP
ISE2PROMWP
RESERVED
Type
R/W
R/W
R
R/W
Reset
Description
0
E2PROM Write Enable bit.
0: No operation.
1: Forces the contents of selected I2C register bits to be copied
into E2PROM, thereby making them the default values during
power-up. When the contents of all the I2C register bits have
been written to the E2PROM, the device automatically resets this
bit.
0
E2PROM Write Protect bit.
0: Normal operation.
1: Forces the E2PROM content to be locked following a write
sequence (WEN = 1). This protects the E2PROM content from
undesirable write actions making it virus safe. This process is
non reversible.
0
E2PROM Write Protect Status bit.
0: E2PROM content is not write protected. E2PROM content can
still be updated.
1: E2PROM content is write protected. E2PROM content is
permanently locked.
0
Reserved bit.
This bits is reserved for future use. During write operations data
intended for this bit is ignored, and during read operations 0 is
returned.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The devices are step up dc/dc converters with true bypass function integrated. They are typically used as
preregulators with input voltage ranges from 2.3V to 4.8V, extend the battery run time and overcome input
current and input voltage limitations of the system being powered.
While the input voltage higher than boost/bypass threshold, the high-efficient integrated pass-through path
connects the battery to the powered system directly.
If the input voltage becomes lower than boost/bypass threshold, the device seamlessly transitions into boost
mode operation with a maximum available output current of 3 A.
The following design procedure can be used to select component values for the TPS61281D and TPS61282D
(also applicable for TPS61280D just by I2C program).
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10.2 Typical Application
10.2.1 TPS61281D with 2.5V-4.35 VIN, 1500 mA Output Current (TPS61280D with default I2C
Configuration)
LM3242
SuPA
BUCK / BYPASS
CIN
10 µF
3G PA
CIN
4.7 µF
2G PA
WL8PM27
SuPA
BUCK
CIN
4.7 µF
WIFI PA
PMIC
CDECOUPLING
10 µF
TPS61281D
SW
VOUT
SW
VOUT
SMPS
Vcore1, 1.05V
SMPS
Vcore2, 1.15V
LDO
eMMC, 2.95V
LDO
LCD, 2.80V
LDO
Antenna switches
2.60V
VBAT’
L
0.47 μH
200 to 600mV
2.7V
VIN
Battery
2.7V .. 4.35V
CO (x2)
10µF X5R 6.3V (0603)
CDECOUPLING
10 µF
VIN
CI
1.5µF X5R 6.3V (0402)
Voltage Select
Enable
Forced Bypass / Auto
PFM/FPWM
Note: Resistive load equivalent
for the measurement result.
VSEL
1.8V
EN
BYP
MODE
PG
Interrupt
PGND
PGND
AGND
PGND
AGND
Copyright © 2016, Texas Instruments Incorporated
Figure 34. TPS61281D Application Circuit with 1500mA Output Current
10.2.1.1 Design Requirement
Table 10. Design Parameters
34
REFERENCE
DESCRIPTION
VIN
Input voltage range
SAMPLE VALUES
2.5V-4.35V
VOUT
Output voltage range at VSEL = Low
VOUT = 3.15 V if VIN ≤ 3.15 V, VOUT = VIN if VIN > 3.15 V
VOUT
Output voltage range VSEL = High
VOUT= 3.35 V if VIN ≤ 3.35 V, VOUT = VIN if VIN > 3.35 V
IOUT
Output current
1500mA
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10.2.1.2 Detailed Design Parameters
10.2.1.2.1 Inductor Selection
A boost converter normally requires two main passive components for storing energy during the conversion, an
inductor and an output capacitor are required. It is advisable to select an inductor with a saturation current rating
higher than the possible peak current flowing through the power switches.
The inductor peak current varies as a function of the load, the input and output voltages and can be estimated
using Equation 8.
IOUT
VIN x D
VIN
IL(PEAK) =
+
with D = 1 2xfxL
(1 - D) x h
VOUT
(8)
Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the
converter. This could eventually harm the device and reduce it's reliability.
When selecting the inductor, as well as the inductance, parameters of importance are: maximum current rating,
series resistance, and operating temperature. The inductor DC current rating should be greater than the
maximum input average current, refer to Equation 9 and the Current Limit Operation section for more details.
V
1
IL(DC) = OUT x
x IOUT
VIN
h
(9)
The TPS6128xD series of step-up converters have been optimized to operate with a effective inductance in the
range of 200 nH to 800 nH. Larger or smaller inductor values can be used to optimize the performance of the
device for specific operating conditions. For more details, see the Checking Loop Stability section.
In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (that
is, quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care
should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing
the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor
size, increased inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance, R(DC) , and the following frequencydependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
For good efficiency, the inductor DC resistance should be less than 30 mΩ. The following inductor series from
different suppliers have been used with the TPS6128xD converters.
Table 11. List of Inductors
SERIES
DIMENSIONS (in mm)
DC INPUT CURRENT LIMIT SETTING
DFE252010C
2.5 x 2.0 x 1.0 max. height
≤3000 mA
DFE252012C
2.5 x 2.0 x 1.2 max. height
≤3500 mA
DFR252010C
2.5 x 2.0 x 1.0 max. height
≤3000 mA
DFE252012C
2.5 x 2.0 x 1.2 max. height
≤3500 mA
DFE252012P
2.5 x 2.0 x 1.2 max. height
≤3500 mA
DFE201610C
2.0 x 1.6 x 1.0 max. height
≤2000 mA
DFE201612C
2.0 x 1.6 x 1.2 max. height
≤3000 mA
DFE201612P
2.0 x 1.6 x 1.2 max. height
≤3000 mA
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10.2.1.2.2 Output Capacitor
For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the
VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can
not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly
recommended. This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC.
To get an estimate of the recommended minimum output capacitance, Equation 10 can be used.
CMIN =
IOUT x (VOUT - VIN )
f x DV x VOUT
where
•
f is the switching frequency which is 2.3 MHz (typ.) and ΔV is the maximum allowed output ripple.
(10)
With a chosen ripple voltage of 20 mV, a minimum effective capacitance of 10 μF is needed. The total ripple is
larger due to the ESR and ESL of the output capacitor. This additional component of the ripple can be calculated
using Equation 11
ΔI ö
æI
ΔVOUT(ESR) = ESR x ç OUT + L ÷
è1 - D 2 ø
ΔI
1
æI
ö
ΔVOUT(ESL) = ESL x ç OUT + L - IOUT ÷ x
2
è1 - D
ø t SW(RISE)
(11)
(12)
ΔI
1
æI
ö
ΔVOUT(ESL) = ESL x ç OUT - L - IOUT ÷ x
2
è1 - D
ø t SW(FALL)
where
•
•
•
•
•
•
•
IOUT = output current of the application
D = duty cycle
ΔIL = inductor ripple current
tSW(RISE) = switch node rise time
tSW(FALL) = switch node fall time
ESR = equivalent series resistance of the used output capacitor
ESL = equivalent series inductance of the used output capacitor
(13)
An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This
is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V
and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive
at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause
lower output voltage ripple as well as lower output voltage drop during load transients.
In applications featuring high (pulsed) load currents (e.g. ≥ 2 Amps), it is recommended to run the converter with
a reasonable amount of effective output capacitance and low-ESL device, for instance x2 22 µF X5R 6.3V (0603)
MLCC capacitors connected in parallel with a 1 µF X5R 6.3 V (0306-2T) MLCC LL capacitor.
DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the
device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size
and voltage rating in combination with material are responsible for differences between the rated capacitor value
and it's effective capacitance. For instance, a 10 µF X5R 6.3 V (0603) MLCC capacitor would typically show an
effective capacitance of less than 5 µF (under 3.5 V bias condition, high temperature).
For RF Power Amplifier applications, the output capacitor loading is combined between the dc/dc converter and
the RF Power Amplifier (x2 10 µF X5R 6.3 V (0603) + PA input cap 4.7 µF X5R 6.3 V (0402)) are recommended.
36
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High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall
series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and therefore
the regulation circuit has no voltage drop to react on. Nevertheless, for accurate output voltage regulation even
with low ESR, the regulation loop can switch to a pure comparator regulation scheme.
10.2.1.2.3 Input Capacitor
Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have
extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible
to the device. While a 4.7-μF input capacitor is sufficient for most applications, larger values may be used to
reduce input current ripple without limitations.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed
between CI and the power source lead to reduce ringing than can occur between the inductance of the power
source leads and CI.
10.2.1.2.4 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted
when the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (that is, MOSFET rDS(on)) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
The TPS6128xD series of step-up converters have been optimized to operate with a effective inductance in the
range of 200 nH to 800 nH and with output capacitors in the range of 8 µF to 100 µF. The internal compensation
is optimized for an output filter of L = 0.5 µH and CO = 15 µF.
Table 12. Component List
REFERENCE
(1)
DESCRIPTION
PART NUMBER, MANUFACTURER (1)
CIN
1.5μF, 6.3V, 0402, X5R ceramic
GRM155R60J155ME80D
COUT
2 x 10μF, 6.3V, 0603, X5R ceramic
2 x GRM188R60J106ME84
L
470nH, 47mΩ, 2.5mm x 2.0mm x 1.2mm
DFE252012CR470
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10.2.1.3 Application Performance Curves
100.0
100.0
Efficiency (%)
Efficiency (%)
90.0
80.0
95.0
90.0
70.0
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
60.0
0.0001
0.001
VOUT = 3.15 V
0.01
Current (A)
0.1
VSEL = Low
1
VIN = 3.6V
VIN = 4.3V
VIN = 3.0V
VIN = 2.7V
VIN = 2.5V
VIN = 3.6V
VIN = 4.3V
85.0
0.1
2
Mode = Low
0.3
0.5
0.7
VOUT = 3.15 V
Figure 35. TPS61281D Efficiency vs Output Current
0.9 1.1 1.3
Current (A)
1.5
VSEL = Low
1.7
1.9
Mode = Low
Figure 36. TPS61281D Efficiency vs Output Current
100.0
100.0
Efficiency (%)
Efficiency (%)
90.0
80.0
95.0
90.0
70.0
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
60.0
0.0001
0.001
VOUT = 3.35 V
0.01
Current (A)
VIN = 3.6V
VIN = 4.3V
0.1
VSEL = High
1
85.0
0.1
2
Mode = Low
0.3
0.5
0.7
VOUT = 3.35 V
Figure 37. TPS61281D Efficiency vs Output Current
VIN = 3.6V
VIN = 4.3V
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
0.9 1.1 1.3
Current (A)
VSEL = High
1.5
1.7
1.9
Mode = Low
Figure 38. TPS61281D Efficiency vs Output Current
3.276
3.213
3.244
Output Voltage (V)
Output Voltage (V)
3.181
3.213
3.181
3.15
3.118
3.087
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
3.055
0.0001
VOUT = 3.15 V
0.001
3.118
3.087
0.01
Current (A)
0.1
1
2
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.0V
3.055
1.5
VOUT = 3.15 V
Mode = Low
Figure 39. TPS61281D DC Output Voltage vs Output
Current
38
3.15
1.9
2.3
Current (A)
2.7
Mode = Low
Figure 40. TPS61281D DC Output Voltage vs Output
Current
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3.417
3.484
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
VIN = 3.2V
3.451
Output Voltage (V)
Output Voltage (V)
3.384
3.417
3.384
3.35
3.317
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
3.284
3.25
0.0001
0.001
3.35
3.317
3.284
0.01
0.1
1
3.25
1.6
2
2
VOUT = 3.35 V
VOUT = 3.35 V
Mode = Low
Output Voltage (V)
Output Voltage (V)
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
IOUT = 1mA
IOUT = 100mA
IOUT = 1000mA
IOUT = 1500mA
2.7
2.9
3.1
VOUT = 3.15 V
2.8
3.3 3.5 3.7 3.9
Input Voltage (V)
4.1
4.3
4.5
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
2.5
IOUT = 1mA
IOUT = 100mA
IOUT = 1000mA
IOUT = 1500mA
2.7
2.9
VOUT = 3.35 V
VSEL = Low
Figure 43. TPS61281D DC Output Voltage vs Input Voltage
Mode = Low
Figure 42. TPS61281D DC Output Voltage vs Output
Current
Figure 41. TPS61281D DC Output Voltage vs Output
Current
3
2.5
2.4
Current (A)
Current (A)
3.1
3.3 3.5 3.7 3.9
Input Voltage (V)
VSEL = High
4.1
4.3
4.5
Mode = Low
Figure 44. TPS61281D DC Output Voltage vs Input Voltage
3.1
3
Output Current (A)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.5
2.6
VOUT = 3.35 V
2.7
2.8
2.9
Input Voltage (V)
TA = 85°C
3
3.1
3.2
Mode = Low
Figure 45. TPS61281D Maximum Output Current vs Input
Voltage
Figure 46. Boost to Pass-Through Mode Exit / Entry
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Figure 47. TPS61281D Dynamic Voltage Management
(VSEL) Load Current 50 mA
Figure 48. TPS61281D Dynamic Voltage Management
(VSEL) Load Current 500 mA
Figure 49. TPS61281D Forced Pass-Through to Boost
Mode Transition
Figure 50. TPS61280D, 81A Load Transient Response In
PFM/PWM Operation
Figure 51. TPS61280D, 81A Load Transient Response In
PFM/PWM Operation
Figure 52. Start-Up at No Load
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Figure 53. Start-Up at 30-Ω Load
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10.2.2 TPS61282D with 2.5V-4.35 VIN, 2000 mA Output Current (TPS61280D with I2C Programmable)
LM3242
CIN
10 µF
SuPA
BUCK/BYPASS
3G PA
Note: Resistive load equivalent
for the measurement result.
CIN
4.7 µF
2G PA
WL8PM27
SuPA
BUCK
CIN
4.7 µF
WIFI PA
PMIC
CDECOUPLING
10 µF
TPS61282D
SW
VOUT
SW
VOUT
SMPS
Vcore1, 1.05V
SMPS
Vcore2, 1.15V
LDO
eMMC, 2.95V
LDO
LCD, 2.80V
LDO
Antenna switches
2.60V
VBAT’
L
200 to 600mV
0.47 μH
CDECOUPLING
10 µF
2.7V
VIN
Battery
2.7V .. 4.35V
CO (x4)
10µF X5R 6.3V (0603)
VIN
CI
1.5µF X5R 6.3V (0402)
Note: Resistive load equivalent
for the measurement result.
Voltage Select
Enable
Forced Bypass / Auto
PFM/FPWM
VSEL
1.8V
EN
BYP
MODE
PG
Interrupt
PGND
PGND
AGND
PGND
AGND
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Figure 54. TPS61282D Application Circuit with 2000 mA Output Current
10.2.2.1 Design Requirements
Table 13. Design Parameters
REFERENCE
DESCRIPTION
PART NUMBER, MANUFACTURER
VIN
Input voltage range
2.5 V to 4.35 V
VOUT
Output voltage range at VSEL=Low
VOUT = 3.3 V if VIN ≤ 3.3 V, VOUT= VIN if VIN > 3.3 V
VOUT
Output voltage range VSEL=High
VOUT = 3.5 V if VIN ≤ 3.5 V, VOUT= VIN if VIN > 3. 5V
IOUT
Output Current
2000 mA
Table 14. Component List
REFERENCE
(1)
DESCRIPTION
PART NUMBER, MANUFACTURER (1)
CI
1.5 μF, 6.3 V, 0402, X5R ceramic
GRM155R60J155ME80D
CO
4 x 10 μF, 6.3 V, 0603, X5R ceramic
4 x GRM188R60J106ME84
L
470 nH, 47 mΩ, 2.5 mm x 2.0 mm x 1.2 mm
DFE252012CR470
See Third-Party Products Disclaimer
10.2.2.2 Detailed Design Procedures
See TPS61281D with 2.5V-4.35 VIN, 1500 mA Output Current (TPS61280D with default I2C Configuration) for all
Detailed Design Procedures.
42
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10.2.2.3 Application Performance Curves
100.0
100.0
Efficiency (%)
Efficiency (%)
90.0
80.0
70.0
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
60.0
0.0001
0.001
VOUT = 3.3 V
0.01
Current (A)
95.0
90.0
VIN = 3.6V
VIN = 4.3V
0.1
VSEL = Low
1
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
85.0
0.1
2
Mode = Low
0.3
0.5
0.7
VOUT = 3.3 V
Figure 55. TPS61282D Efficiency vs Output Current
VIN = 3.3V
VIN = 4.3V
0.9 1.1 1.3
Current (A)
1.5
VSEL = Low
1.7
1.9
Mode = Low
Figure 56. TPS61282D Efficiency vs Output Current
100.0
100.0
Efficiency (%)
Efficiency (%)
90.0
80.0
95.0
90.0
70.0
VIN = 3.3V
VIN = 4.3V
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
60.0
0.0001
0.001
0.01
0.1
1
85.0
0.1
2
VIN = 2.5V
VIN = 2.7V
VIN = 3.0V
0.3
0.5
0.7
Current (A)
VOUT = 3.5 V
VSEL = High
Mode = Low
VOUT = 3.5 V
Figure 57. TPS61282D Efficiency vs Output Current
VIN = 3.3V
VIN = 4.3V
0.9 1.1 1.3
Current (A)
VSEL = High
1.5
1.7
1.9
Mode = Low
Figure 58. TPS61282D Efficiency vs Output Current
3.333
3.432
3.366
Output Voltage (V)
Output Voltage (V)
3.399
3.333
3.3
3.267
3.234
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
3.201
0.0001
3.3
3.267
3.201
0.001
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
VIN = 3.2V
3.234
0.01
0.1
1
2
2
VOUT = 3.3 V
2.4
2.8
3.2
3.6
4
Current (A)
Current (A)
VOUT = 3.3 V
Mode = Low
Figure 59. TPS61282D DC Output Voltage vs Output
Current
Mode = Low
Figure 60. TPS61282D DC Output Voltage vs Output
Current
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3.57
3.64
3.535
3.57
Output Voltage (V)
Output Voltage (V)
3.605
3.535
3.5
3.465
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
3.43
3.395
0.0001
0.001
VOUT = 3.5 V
3.5
3.465
3.43
0.01
Current (A)
0.1
1
2
3.395
1.8
IOUT = 1mA
IOUT = 100mA
IOUT = 1000mA
IOUT = 2000mA
2.9
VOUT = 3.3 V
44
3.1
3.3 3.5 3.7
Input Voltage (V)
VSEL = Low
2.6
3
Current (A)
3.9
4.1
4.3
4.5
3.8
Mode = Low
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
IOUT
= 1mA
Iout=1mA
IOUT
= 100mA
Iout=100mA
IOUT
= 1000mA
Iout=1000mA
IOUT
= 2000mA
Iout=2000mA
2.5
2.7
2.9
3.1
3.3
3.5
3.7
Input Voltage(V)
Mode = Low
3.4
Figure 62. TPS61282D DC Output Voltage vs Output
Current
Output Voltage(V)
Output Voltage (V)
4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
2.7
2.2
VOUT = 3.5 V
Mode = Low
Figure 61. TPS61282D DC Output Voltage vs Output
Current
3
2.5
VIN = 2.5V
VIN = 2.7V
VIN = 2.9V
VIN = 3.1V
VIN = 3.2V
VIN = 3.4V
VOUT = 3.5 V
VSEL = High
3.9
4.1
4.3
4.5
C013
Mode = Low
Figure 63. TPS61282D DC Output Voltage vs Input Voltage
Figure 64. TPS61282D DC Output Voltage vs Input Voltage
Figure 65. Boost to Pass-Through Mode Exit / Entry
Figure 66. TPS61282D Dynamic Voltage Management
(VSEL) Load Current 50mA
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Figure 67. TPS61282D Dynamic Voltage Management
(VSEL) Load Current 500mA
Figure 68. TPS61282D Line Transient
Figure 69. TPS61282D Load Transient Response In PWM
Operation
Figure 70. TPS61282D Load Transient Response In
PFM/PWM Operation
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11 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.3 V and 4.8 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the TPS61280D,
TPS61281D or TPS61282D converter additional bulk capacitance may be required in addition to the ceramic
bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 μF is a typical choice.
12 Layout
12.1 Layout Guidelines
•
•
•
•
For all switching power supplies, the layout is an important step in the design, especially at high peak
currents and high switching frequencies.
If the layout is not carefully done, the regulator could show stability problems as well as EMI problems.
Therefore, use wide and short traces for the main current path and for the power ground tracks.
To minimize voltage spikes at the converter's output:
– Place the output capacitor(s) as close as possible to GND and VOUT, as shown in Figure 71.
– The input capacitor and inductor should also be placed as close as possible to the IC.
– Use a common ground node for power ground and a different one for control ground to minimize the
effects of ground noise.
– Connect these ground nodes at any place close to the ground pins of the IC.
– Junction-to-ambient thermal resistance is highly application and board-layout dependent.
– It is suggested to maximize the pour area for all planes other than SW. Especially the ground pour should
be set to fill available PWB surface area and tied to internal layers with a cluster of thermal vias.
12.2 Layout Example
L
Vin
Cout
Cin
Cout
Vout
GND
Figure 71. Suggested Layout (Top)
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12.3 Thermal Information
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
As power demand in portable designs is more and more important, designers must figure the best trade-off
between efficiency, power dissipation and solution size. Due to integration and miniaturization, junction
temperature can increase significantly which could lead to bad application behaviors (that is, premature thermal
shutdown or worst case reduce device reliability).
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where
high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.
The device operating junction temperature (TJ) should be kept below 125°C.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14.1 Package Summary
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C1
D4
D3
D2
D1
YMLLLLS
TPS6128xD
D
A1
E
Figure 72. Chip Scale Package
(Bottom View)
Figure 73. Chip Scale Package
(Top View)
Code:
• YM — Year Month date code
• LLLL — Lot trace code
• S — Assembly site code
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS61280DYFFR
ACTIVE
DSBGA
YFF
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
61280D
TPS61280DYFFT
ACTIVE
DSBGA
YFF
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
61280D
TPS61281DYFFR
ACTIVE
DSBGA
YFF
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
61281D
TPS61281DYFFT
ACTIVE
DSBGA
YFF
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
61281D
TPS61282DYFFR
ACTIVE
DSBGA
YFF
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
61282D
TPS61282DYFFT
ACTIVE
DSBGA
YFF
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
61282D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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