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TPS61310, TPS61311
SLVS978D – MARCH 2010 – REVISED SEPTEMBER 2016
TPS6131x 1.5-A Multiple LED Camera Flash and Video Light Driver
With I2C Compatible Interface
1 Features
3 Description
•
The TPS6131x family is an integrated solution with a
wide feature set for driving up to three LEDs for stillcamera flash strobe and video-camera lighting
applications. It is based on a high efficiency
synchronous boost topology with combinable current
sinks to drive up to three white LEDs in parallel. The
2-MHz switching frequency allows the use of small
and low-profile 2.2-µH inductors. To optimize overall
efficiency, the device operates with a low LEDfeedback voltage and regulated output-voltage
adaptation.
1
•
•
•
•
•
•
•
•
•
•
•
Operational Modes:
– Video Light and Flash Strobe
– Voltage Regulated Converter: 3.8 V to 5.7 V
With Down Mode
– Standby: 2 µA (Typical)
LED VF Measurement
Power-Save Mode for Improved Efficiency at Low
Output Power, Up to 95% Efficiency
I2C Compatible Interface up to 3.4 Mbps
Dual Wire Camera Module Interface
Zero Latency Tx-Masking Input
Hardware Reset Input
Privacy Indicator LED Output
GPIO and Power Good Output
Various Safe Operation and Robust Handling
Features:
– LED Temperature Monitoring
– Open and Shorted LED Detection and
Protection
– Integrated LED Safety Timer
– Automatic Battery Voltage Droop Monitoring
and Protection
– Smooth LED Current Ramp-Up and RampDown
– Undervoltage Lockout
Total Solution Size of Less Than 25 mm2
Available in a 20-Pin NanoFree™ DSBGA
Package
The device integrates a control scheme that
automatically optimizes the LED current flash budget
as a function of the battery voltage condition.
The TPS6131x not only operates as a regulated
current source, but also as a standard voltage boost
regulator. The device enters power-save mode
operation at light load currents to maintain high
efficiency over the entire load current range. These
operating modes can be useful to supply other high
power devices in the system (for example, a handsfree audio PA).
To simplify video light and flash synchronization with
the camera module, the device offers a dedicated
control interface (STRB0, STRB1) for zero latency
LED turnon time.
Device Information(1)
PART NUMBER
DSBGA (20)
•
•
•
Single, Dual, or Triple White LED Flash Supply for
Cell Phones and Smart-Phones
Video Lighting for Digital Video Applications
General Lighting Applications
Audio Amplifier Power Supply
BODY SIZE (NOM)
2.20 mm × 1.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
PACKAGE
TPS61310,
TPS61311
Typical Application
L
2.2 mH
2.5 V to
5.5 V
SW
SW
VOUT
AVIN
CO
10 mF
CI
4.7 mF
NRESET
SCL
SDA
INDLED
Privacy
Indicator
Tx-MASK
TS
NTC
AGND
AGND
D2
LED1
LED2
LED3
STRB0
STRB1
I2C I/F
D1
GPIO/PG
PGND
PGND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61310, TPS61311
SLVS978D – MARCH 2010 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Interface Timing Requirements...........................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 13
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 25
9.5 Register Maps ......................................................... 30
10 Application and Implementation........................ 38
10.1 Application Information.......................................... 38
10.2 Typical Applications .............................................. 38
11 Power Supply Recommendations ..................... 45
12 Layout................................................................... 45
12.1 Layout Guidelines ................................................. 45
12.2 Layout Example .................................................... 46
12.3 Thermal Considerations ........................................ 46
13 Device and Documentation Support ................. 48
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
48
48
14 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2012) to Revision D
Page
•
Added Device Information table,ESD Ratings table,Recommended Operating Conditions table,Thermal Information
table,Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section........... 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
Changes from Revision B (September 2011) to Revision C
Page
•
Added revision letter C to literature number........................................................................................................................... 1
•
Added TPS61311 to ordering table ........................................................................................................................................ 3
•
Added Current Limit Setting for TPS61311 .......................................................................................................................... 21
•
Added current limit setting for TPS61311 in register map.................................................................................................... 34
Changes from Revision A (October 2010) to Revision B
Page
•
Changed VUVLO to max value from 2.35 V to 2.4 V. ............................................................................................................... 5
•
Updated LED forward voltage calibration description. ......................................................................................................... 24
•
Updated SFT bit description ................................................................................................................................................. 33
2
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS61310 TPS61311
TPS61310, TPS61311
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SLVS978D – MARCH 2010 – REVISED SEPTEMBER 2016
5 Device Comparison Table
DEVICE SPECIFIC FEATURES (1)
PACKAGE
TPS61310
up to 1750-mA (typical) input valley current
TPS61311
up to 2480-mA (typical) input valley current
(1)
For more details, see Detailed Description and Application and Implementation.
6 Pin Configuration and Functions
YFF Package
20-Pin DSBGA
Top View
A
B
C
D
E
4
AGND
STRB0
TS
GPIO/PG
AVIN
3
AGND
NRESET
Tx-MASK
STRB1
LED3
2
VOUT
SCL
SW
PGND
LED1
1
INDLED
SDA
SW
PGND
LED2
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
A1
INDLED
O
This pin provides a constant current source to drive low VF LEDs. Connect to LED anode.
A2
VOUT
O
This is the output voltage pin of the converter.
A3, A4
AGND
—
Analog ground.
B1
SDA
I/O
Serial interface address and data line. This pin must not be left floating and must be terminated.
B2
SCL
I
Serial interface clock line. This pin must not be left floating and must be terminated.
B3
NRESET
I
Master hardware reset input.
NRESET = LOW: The device is forced in shutdown mode and the I2C control I/F and all internal control
registers are reset.
NRESET = HIGH: The device is operating normally under the control of the I2C interface.
STRB0
I
LED1, LED2, and LED3 enable logic input. This pin can be used to enable or disable the high-power
LEDs connected to the device.
STRB0 = LOW: LED1, LED2 and LED3 current regulators are turned off.
STRB0 = HIGH: LED2, LED2 and LED3 current regulators are active. The LED current level (video light
or flash current) is defined according to the STRB1 logic level.
SW
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
SW is high impedance during shutdown.
Tx-MASK
I
B4
C1, C2
C3
RF PA synchronization control input. Pulling this pin high turns the LED from flash to video light
operation, thereby reducing almost instantaneously the peak current loading from the battery.
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Pin Functions (continued)
PIN
I/O
NO.
NAME
C4
TS
I
D1, D2
PGND
—
D3
STRB1
I
D4
GPIO/PG
I/O
E1
LED2
I
E2
LED1
I
E3
LED3
I
E4
AVIN
I
DESCRIPTION
NTC resistor connection. This pin can be used to monitor the LED temperature. Connect a 220-kΩ NTC
resistor from the TS input to ground. In case this functionality is not desired, the TS input must be tied to
AVIN or left floating.
Power ground. Connect to AGND underneath IC.
LED current level selection input. Pulling this input high disables the video light watchdog timer.
STRB1 = LOW: flash mode is enabled.
STRB1 = HIGH: video light mode is enabled.
This pin can either be configured as a general purpose I/O pin (GPIO) or either as an open-drain or a
push-pull output to signal when the converters output voltage is within the regulation limits (PG). Per
default, the pin is configured as an open-drain Power Good output.
LED return input (current sinks). This feedback pin regulates the LED current through the internal sense
resistor by regulating the voltage across it. Connect to the cathode of the white LEDs.
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
7 Specifications
7.1 Absolute Maximum Ratings
see
(1)
AVIN, VOUT, SW, LED1, LED2, LED3, SCL, SDA, STRB0, STRB1, NRESET,
GPIO/PG, Tx-MASK, TS
Voltage
MIN
MAX
UNIT
–0.3
7
V
±25
mA
Current on GPIO/PG
Power dissipation
Internally limited
Operating ambient temperature, TA (2)
–40
Maximum operating junction temperature, TJ (2)
Storage temperature, Tstg
(1)
(2)
–65
85
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
In applications where high power dissipation or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part in the
application (RθJA), as given by: TA(max) = TJ(max) – (RθJA × PD(max))
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
TJ
4
Operating junction temperature
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MIN
MAX
UNIT
–40
125
°C
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS61310 TPS61311
TPS61310, TPS61311
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SLVS978D – MARCH 2010 – REVISED SEPTEMBER 2016
7.4 Thermal Information
TPS6131x
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
71
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.4
°C/W
RθJB
Junction-to-board thermal resistance
21
°C/W
ψJT
Junction-to-top characterization parameter
1.9
°C/W
ψJB
Junction-to-board characterization parameter
11.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Specification applies for VIN = 3.6 V over an operating junction temperature TJ = –40°C to 125°C; see Figure 24 (unless
otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage
IQ
2.5
Operating quiescent current into AVIN
IOUT = 0 mA, device not switching (Power Safe
Mode), –40°C ≤ TJ ≤ 85°C
590
IOUT(DC) = 0 mA, PWM operation VOUT = 4.95 V,
voltage regulation mode
11.3
ISD
Shutdown current
–40°C ≤ TJ ≤ 85°C
VUVLO
Undervoltage lockout threshold
(analog circuitry)
VIN falling
5.5
V
700
µA
mA
1
5
µA
2.3
2.4
V
OUTPUT
Output voltage
VOUT
VIN
5.5
Voltage regulation mode
3.825
5.7
–2%
2%
Internal feedback voltage accuracy
2.5 V ≤ VIN ≤ 4.8 V, –20°C ≤ TJ ≤ 125°C, Boost
mode, PWM voltage regulation
Power-save mode ripple voltage
IOUT = 10 mA
0.015 × VOUT
VOUT rising, 0000 ≤ OV[3:0] ≤ 0100
4.5
VOUT rising, 0101 ≤ OV[3:0] ≤ 1111
5.8
Output overvoltage protection
OVP
Current regulation mode
Output overvoltage protection hysteresis
VOUT falling
V
VP–P
4.65
4.8
6
6.2
V
0.15
POWER SWITCH
rDS(on)
Ilkg(SW)
Ilim
Switch MOSFET ON-resistance
VOUT = VGS = 3.6 V
90
Rectifier MOSFET ON-resistance
VOUT = VGS = 3.6 V
135
Leakage into SW
VOUT = 0 V, SW = 3.6 V, –40°C ≤ TJ ≤ 85°C
0.3
Rectifier valley current limit (open loop)
VOUT = 4.95 V, –20°C ≤ TJ ≤ 85°C,
PWM operation, relative to selected ILIM
–15%
mΩ
mΩ
4
µA
15%
OSCILLATOR
fOSC
Oscillator frequency
fACC
Oscillator frequency
1.92
–10%
MHz
7%
THERMAL SHUTDOWN, HOT DIE DETECTOR
Thermal shutdown (1)
140
Thermal shutdown hysteresis (1)
Hot die detector accuracy
(1)
160
°C
20
°C
–8
8
0.4 V ≤ VLED[1,3] ≤ 2 V,
0 mA ≤ ILED[1,3] ≤ 100 mA, TJ = 85°C
–10%
10%
0.4 V ≤ VLED[1,3] ≤ 2 V,
100 mA < ILED[1,3] ≤ 400 mA, TJ = 85°C
–7.5%
7.5%
°C
LED CURRENT REGULATOR
LED1 and LED3 current accuracy (2)
(1)
(2)
Verified by characterization. Not tested in production.
Verified by characterization. Not tested in production.
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Electrical Characteristics (continued)
Specification applies for VIN = 3.6 V over an operating junction temperature TJ = –40°C to 125°C; see Figure 24 (unless
otherwise noted). Typical values are for TJ = 25°C.
PARAMETER
TEST CONDITIONS
LED2 current accuracy (2)
LED1 and LED3 current matching
MIN
MAX
–10%
10%
0.4 V ≤ VLED2 ≤ 2 V,
250 mA ≤ ILED2 ≤ 800 mA, TJ = 85°C
–7.5%
7.5%
–10%
10%
(2)
LED1, LED2, and LED3 current temperature
coefficient
0.05
1.5 V ≤ (VIN – VINDLED) ≤ 2.5 V
2.6 mA ≤ IINDLED ≤ 15.8 mA, TJ = 25°C
INDLED current accuracy
–20%
INDLED current temperature coefficient
VDO
TYP
0.4 V ≤ VLED2 ≤ 2 V,
0 mA ≤ ILED2 ≤ 250 mA, TJ = 85°C
%/°C
20%
0.05
LED1, LED2, and LED3 sense voltage
ILED[1,2,3] = full-scale current
VOUT dropout voltage
IOUT = –15.8 mA, TJ = 25°C, device not switching
LED1, LED2, and LED3 input leakage current
VLED[1,2,3] = VOUT = 5 V, –40°C ≤ TJ ≤ 85°C
INDLED input leakage current
VINDLED = 0 V, –40°C ≤ TJ ≤ 85°C
UNIT
%/°C
400
mV
250
mV
0.1
4
µA
0.1
1
µA
LED TEMPERATURE MONITORING
IO(TS)
Temperature Sense Current Source
Thermistor bias current
TS Resistance (Warning Temperature)
LEDWARN bit = 1
TS Resistance (Hot Temperature)
LEDHOT bit = 1
23.8
µA
39
44.5
50
kΩ
12.5
14.5
16.5
kΩ
SDA, SCL, GPIO/PG, Tx-MASK, STRB0, STRB1, NRESET
V(IH)
High-level input voltage
V(IL)
Low-level input voltage
1.2
V
0.4
Low-level output voltage (SDA)
IOL = 8 mA
0.3
Low-level output voltage (GPIO)
DIR = 1, IOL = 5 mA
0.3
V(OH)
High-level output voltage (GPIO)
DIR = 1, GPIOTYPE = 0, IOH = 8 mA
I(LKG)
Logic input leakage current
Input connected to VIN or GND, –40°C ≤ TJ ≤ 85°C
0.01
STRB0, STRB1 pulldown resistance
STRB0, STRB1 ≤ 0.4 V
400
NRESET pulldown resistance
NRESET ≤ 0.4 V
400
Tx-MASK pulldown resistance
Tx-MASK ≤ 0.4 V
400
SDA Input Capacitance
SDA = VIN or GND
9
SCL Input Capacitance
SCL = VIN or GND
4
GPIO/PG Input Capacitance
DIR = 0, GPIO/PG = VIN or GND
9
STRB0 Input Capacitance
STRB0 = VIN or GND
3
STRB1 Input Capacitance
STRB1 = VIN or GND
3
NRESET Input Capacitance
NRESET = VIN or GND
3.5
Tx-MASK Input Capacitance
Tx-MASK = VIN or GND
4
V(OL)
RPD
C(IN)
VIN – 0.4
V
V
V
0.1
µA
kΩ
pF
TIMING
tNRESET
Reset pulse width
10
Start-up time
LED current settling time
edge on STRB0
(3)
triggered by a rising
LED current settling time (3) triggered by Tx-MASK
(3)
6
µs
From shutdown into video light mode
ILED = 150 mA
1.2
ms
MODE_CTRL[1:0] = 10, ILED2 = from 0 mA to
950 mA
500
µs
20
µs
MODE_CTRL[1:0] = 10, ILED2 = from 950 mA to
150 mA
Settling time to ±15% of the target value.
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SLVS978D – MARCH 2010 – REVISED SEPTEMBER 2016
7.6 I2C Interface Timing Requirements
see
(1)
MIN
f(SCL)
SCL Clock Frequency
Standard mode
100
Fast mode
400
High-speed mode (write operation), CB – 100 pF max
3.4
High-speed mode (read operation), CB – 100 pF max
3.4
High-speed mode (write operation), CB – 400 pF max
1.7
High-speed mode (read operation), CB – 400 pF max
tBUF
Bus Free Time Between a STOP
and START Condition
tHD, tSTA
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
4.7
Fast mode
1.3
600
High-speed mode
160
Standard mode
4.7
Fast mode
1.3
High-speed mode, CB – 100 pF max
160
High-speed mode, CB – 400 pF max
320
tHIGH
tSU, tSTA
tSU, tDAT
Fast mode
HIGH Period of the SCL Clock
Setup Time for a Repeated START
Condition
Data Setup Time
tHD, tDAT
tRCL
Data Hold Time
Rise Time of SCL Signal
60
120
Standard mode
4.7
Fast mode
600
High-speed mode
160
Standard mode
250
Fast mode
100
tFCL
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge BIT
Fall Time of SCL Signal
(1)
ns
µs
ns
µs
ns
ns
10
0
3.45
0
0.9
High-speed mode, CB – 100 pF max
0
70
High-speed mode, CB – 400 pF max
0
150
Standard mode
20 + 0.1 × CB
1000
Fast mode
20 + 0.1 × CB
300
10
40
20
80
Standard mode
20 + 0.1 × CB
1000
Fast mode
20 + 0.1 × CB
300
High-speed mode, CB – 100 pF max
10
80
High-speed mode, CB – 400 pF max
20
160
Standard mode
20 + 0.1 × CB
300
Fast mode
20 + 0.1 × CB
300
10
40
High-speed mode, CB – 100 pF max
Rise Time of SDA Signal
µs
Fast mode
High-speed mode, CB – 400 pF max
tRDA
ns
Standard mode
High-speed mode, CB – 400 pF max
tRCL1
µs
4
High-speed mode, CB – 400 pF max
High-speed mode, CB – 100 pF max
MHz
600
High-speed mode, CB – 100 pF max
High-speed mode
kHz
µs
4
Fast mode
Standard mode
UNIT
1.7
Standard mode
Standard mode
tLOW
MAX
20
80
Standard mode
20 + 0.1 × CB
1000
Fast mode
20 + 0.1 × CB
300
High-speed mode, CB – 100 pF max
10
80
High-speed mode, CB – 400 pF max
20
160
µs
ns
ns
ns
ns
ns
Specified by design. Not tested in production.
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I2C Interface Timing Requirements (continued)
see (1)
tFDA
Fall Time of SDA Signal
MIN
MAX
Standard mode
20 + 0.1 × CB
300
Fast mode
20 + 0.1 × CB
300
High-speed mode, CB – 100 pF max
10
80
High-speed mode, CB – 400 pF max
20
160
Standard mode
tSU, tSTO
CB
Setup Time for STOP Condition
4
Fast mode
600
High-speed mode
160
Capacitive Load for SDA and SCL
UNIT
ns
µs
ns
400
pF
7.7 Dissipation Ratings
(1)
PACKAGE
POWER RATING (TA = 25°C)
DERATING FACTOR ABOVE TA = 25°C (1)
YFF
1.4 W
14 mW/°C
Maximum power dissipation is a function of TJ(max), RθJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / RθJA.
SDA
tf
tLOW
tsu;DAT
tr
tf
tBUF
tr
thd;STA
SCL
thd;STA
thd;DAT
S
tsu;STA
tsu;STO
HIGH
Sr
P
S
Figure 1. Serial Interface Timing For F/S-Mode
Sr
Sr P
tfDA
trDA
SDAH
thd;DAT
thd;STA
tsu;STA
tsu;STO
tsu;DAT
SCLH
tfCL
trCL1
See Note A
trCL1
trCL
tHIGH
tLOW
tLOW
tHIGH
See Note A
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 2. Serial Interface Timing For H/S-Mode
8
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7.8 Typical Characteristics
Table 1. Table of Graphs
CAPTION
FIGURE
LED Power Efficiency
Input Voltage
DC Input Current
Input Voltage
Figure 3, Figure 4
LED Current
LED Pin Headroom Voltage
LED Current
LED Current Digital Code
INDLED Current
INDLED Pin Headroom Voltage
Efficiency
Output Current
Figure 13, Figure 14
DC Output Voltage
Load Current
Figure 15, Figure 16
Maximum Output Current
Input Voltage
DC Precharge Current
Differential I/O Voltage
Supply Current
Input Voltage
Figure 5
Figure 6, Figure 7
Figure 8, Figure 9, Figure 10, Figure 11
Figure 12
Figure 17
Figure 18, Figure 19
Figure 20
Temperature Detection Threshold
Figure 21, Figure 22
Port Voltage
Figure 23
100
100
90
90
LED Power Efficiency (PLED/PIN) - %
LED Power Efficiency (PLED/PIN) - %
Junction Temperature
80
70
ILED2 = 75 mA
60
ILED2 = 100 mA
ILED2 = 150 mA
50
ILED2 = 225 mA
40
30
20
ILIM = 1750 mA,
Tx-MASK = Low
LED2 Channel
10
0
2.5
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
60
ILED1 = ILED3 = 75 mA
ILED2 = 150 mA
ILED1 = ILED3 = 100 mA
ILED2 = 200 mA
ILED1 = ILED3 = 250 mA
ILED2 = 450 mA
ILED1 = ILED3 = 250 mA
ILED2 = 550 mA
50
40
30
20
ILIM = 1750 mA,
Tx-MASK = Low
10
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
ILED2 = 800 mA
800
ILED2 = 700 mA
700
LED2 Current - mA
1500
DC Input Current - mA
ILED1 = ILED3 = 50 mA
ILED2 = 100 mA
900
ILED1 = ILED3 = 350 mA
ILED2 = 600 mA
1750
1250
1000
ILED1 = ILED3 = 250 mA
ILED2 = 550 mA
ILED1 = ILED3 = 250 mA
ILED2 = 450 mA
500
0
2.5
70
Figure 4. LED Power Efficiency vs Input Voltage
2000
250
80
0
2.5
5.3
Figure 3. LED Power Efficiency vs Input Voltage
750
ILED1 = ILED3 = 350 mA
ILED2 = 600 mA
500
400
300
ILED2 = 550 mA
ILED2 = 450 mA
ILED2 = 350 mA
ILED2 = 300 mA
200
ILED1 = ILED3 = 250 mA
ILED2 = 275 mA
100
ILIM = 1750 mA,
Tx-MASK = Low
2.9
600
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
Figure 5. DC Input Current vs Input Voltage
ILIM = 1750 mA
0
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED2 Pin Headroom Voltage - mV
Figure 6. LED2 Current vs LED2 Pin Headroom Voltage
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Typical Characteristics (continued)
900
300
ILED1 = ILED3 = 400 mA
250
ILED1 = ILED3 = 300 mA
225
LED2 Current - mA
LED1 + LED3 Current - mA
ILED1 = ILED3 = 350 mA
700
600
ILIM = 1750 mA
275
800
ILED1 = ILED3 = 250 mA
500
400
300
VIN = 2.5 V
200
VIN = 4.5 V
175
150
VIN = 3.6 V
125
100
75
200
50
ILIM = 1750 mA
100
25
0
400 500 600 700 800 900 1000 1100 1200 1300 1400
LED1, LED3 Pin Headroom Voltage - mV
Figure 7. LED1 + LED3 Current vs
LED1 + LED3 Pin Headroom Voltage
0
0 25 50 75 100 125 150 175 200 225 250 275 300
LED2 Current Digital Code - mA
Figure 8. LED2 Current vs LED2 Current Digital Code
900
125
850
ILIM = 1750 mA
ILIM = 1750 mA
VIN = 2.5 V
750
VIN = 3.6 V
100
700
VIN = 4.5 V
75
LED2 Current - mA
LED1, LED3 Current - mA
800
VIN = 2.5 V
50
650
VIN = 4.5 V
VIN = 3.6 V
600
550
500
450
400
350
300
250
25
25
50
75
100
LED1, LED3 Current Digital Code - mA
125
Figure 9. LED1, LED3 Current vs
LED1, LED3 Current Digital Code
200
200
400
500
600
700
800
LED2 Current Digital Code - mA
900
Figure 10. LED2 Current vs LED2 Current Digital Code
450
425
300
9
ILIM = 1750 mA
8
VIN = 2.5 V
INDLED = 0011
TA = 85°C
TA = 25°C
TA = -40°C
7
375
350
VIN = 3.6 V
VIN = 4.5 V
325
300
275
6
TA = 25°C
5
4
3
2
225
1
200
200 225 250 275 300 325 350 375 400 425 450
LED1, LED3 Current Digital Code - mA
0
0.5
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INDLED = 0010
250
Figure 11. LED1, LED3 Current vs
LED1, LED3 Current Digital Code
10
INDLED Current - mA
LED1, LED3 Current - mA
400
INDLED = 0001
VIN = 3.6 V
0.7
TA = 85°C
TA = 25°C
TA = -40°C
TA = -40°C
0.9
1.1
1.3
1.5
1.7
INDLED Pin Headroom Voltage - V
1.9
Figure 12. INDLED Current vs
INDLED Pin Headroom Voltage
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Typical Characteristics (continued)
100
100
VIN = 4.2 V
80
Efficiency - %
70
Forced PWM Operation
VIN = 3 V
70
PFM/PWM Operation
60
50
40
Forced PWM Operation
VIN = 4.2 V
60
50
PFM/PWM Operation
40
30
30
20
VOUT = 3.825 V
ILIM = 1750 mA
Voltage Mode Regulation
20
VOUT = 4.95 V
ILIM = 1750 mA
Voltage Mode Regulation
10
10
0
1
10
100
1000
IO - Output Current - mA
1
10000
10
100
1000
IO - Output Current - mA
Figure 13. Efficiency vs Output Current
4.016
Voltage Mode Regulation
5.15
VOUT = 4.95 V,
ILIM = 1750 mA
Voltage Mode Regulation
IOUT = 0 mA
3.978
PFM/PWM Operation
5.1
5.05
5
VIN = 4.2 V
4.95
Forced PWM Operation
4.9
VIN = 3.6 V
VO - Output Voltage (DC) - V
VO - Output Voltage (DC) - V
10000
Figure 14. Efficiency vs Output Current
5.2
4.85
4.8
1
10
100
1000
IO - Output Current - mA
3.825
IOUT = 1000 mA
3.787
VOUT = 3.825 V
ILIM = 1750 mA
2.9
3.3
3.7
4.1
4.5
4.9
IO - Output Current - mA
5.3
400
Voltage Mode Regulation
350
VOUT = 4.95 V,
ILIM = 1250 mA
VOUT = 5.7 V,
ILIM = 1250 mA
1000
900
800
700
600
500
400
DC Pre-Charge Current - mA
1100
IOUT = 100 mA
3.863
Figure 16. DC Output Voltage vs Load Current
1300
1200
3.902
3.71
2.5
10000
Figure 15. DC Output Voltage vs Load Current
1500
1400
3.94
3.749
VIN = 2.5 V
IO - Output Current (max) - mA
VIN = 3 V
VIN = 2.5 V
80
VIN = 3.6 V
Efficiency - %
VIN = 2.5 V
0
VIN = 3.6 V
90
90
VIN = 3.6 V, TA = 25°C
300
VIN = 4.2 V, TA = 25°C
250
200
VIN = 2.5 V, TA = 25°C
150
100
300
50
200
100
0
2.5
0
2.9
3.3
3.7
4.1
4.5
VI - Input Voltage - V
4.9
5.3
Figure 17. Maximum Output Current vs Input Voltage
0
0.6
1.2
1.8
2.4
3
3.6
Differential Input - Output Voltage - V
4.2
Figure 18. DC Precharge Current vs
Differential I/O Voltage
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Typical Characteristics (continued)
400
1500
IOUT = 0 mA
ENPSM bit = ENVM bit = 1
1400
VIN = 3.6 V, TA = -40°C
1300
300
ICC - Supply Current - mA
DC Pre-Charge Current - mA
350
250
200
VIN = 3.6 V, TA = 85°C
150
VIN = 3.6 V, TA = 25°C
100
1200
VOUT = 4.95 V, TA = 85°C
1100
VOUT = 5.7 V, TA = 25°C
1000
900
800
VOUT = 4.95 V,
TA = -40°C V
OUT = 4.95 V,
TA = 25°C
700
50
0
600
0
0.6
1.2
1.8
2.4
3
3.6
Differential Input - Output Voltage - V
500
2.5
4.2
26
24
20
22
Sample Percentage - %
Sample Percentage - %
26
22
18
16
14
12
10
Sample Size = 76
6
4.9
5.3
VIN = 3.6 V
20
18
16
14
12
Sample Size = 76
10
8
6
4
4
2
0
3.7
4.1
4.5
VI - Input Voltage - V
28
VIN = 3.6 V
8
3.3
Figure 20. Supply Current vs Input Voltage
Figure 19. DC Precharge Current vs
Differential I/O Voltage
24
2.9
VOUT = 3.825 V,
TA = 25°C
2
50
51 52 53 54 55 56 57 58 59
Temperature Detection (55°C Threshold)
0
60
Figure 21. Temperature Detection Threshold
64 65 66 67 68 69 70 71 72 73 74 75
Temperature Detection (70°C Threshold)
Figure 22. Temperature Detection Threshold
200
150
Tx-MASK Input
IPORT = -100 mA
STRB1 Input
125
100
75
50
25
Port
Input Buffer
0
-25
VPORT
TJ - Junction Temperature - °C
175
100 mA
-50
-0.6 -0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1
Port Voltage - V
Figure 23. Junction Temperature vs Port Voltage
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8 Parameter Measurement Information
TPS61310
L
SW
SW
VOUT
2 . 2 mH
AVIN
CO
2 . 5 V .. 5 . 5 V
CI
10 mF
4.7 mF
D1
D2
NRESET
LED 1
STRB0
LED 2
STRB1
LED 3
SCL
2
I C I /F
SDA
INDLED
Privacy
Indicator
Tx -MASK
TS
GPIO
/PG
NTC
AGND
PGND
AGND
PGND
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L = 2.2-µH
CI, CO = 10-µF, 6.3-V X5R 0603
NTC = 220-kΩ
Figure 24. TPS61310 Typical Application Circuit
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9 Detailed Description
9.1 Overview
The TPS6131x family is an integrated solution with a wide feature set for driving up to three LEDs for still-camera
flash and video-camera lighting applications. It employs a 2-MHz fixed on-time, PWM current-mode converter to
generate the output voltage required to drive up to three high-power LEDs in parallel. The device integrates an
NMOS-switch power stage and a synchronous PMOS rectifier. The device also implements a set of linear lowside current regulators to control the LED current when the battery voltage is higher than the diode forward
voltage.
The high-efficiency boost converter stage and LED forward voltage adoption ensure lowest device input current
for a given LED output current.
A special circuit disconnects the load from the battery during shutdown of the converter. In conventional
synchronous-rectifier circuits, the back-gate diode of the high-side PMOS is forward biased in shutdown, allowing
current to flow from the battery to the output. The TPS6131x prevents this by disconnecting the cathode of the
back-gate diode of the high-side PMOS from the source when the regulator is in shutdown.
The TPS6131x device not only operates as a regulated current source, but also as a standard voltage-boost
regulator featuring a power-save mode for improved efficiency at light loads. If the input voltage is higher than
the programmed output voltage, a down mode is implemented that acts similarly to an LDO.
The power stage is capable of supplying a maximum total current of roughly 1500 mA. The TPS6131x provides
three constant-current sinks, capable of sinking up to 2 × 400 mA (LED1 and LED3) and 800 mA (LED2) in flash
mode.
Figure 25. TPS6131x States
Special effort is taken for safe operation and robust system integration. The battery voltage can be monitored so
that the flash current is not increased if the battery voltage drops by a programmable threshold. Internal timers
limit the flash ON time to prevent potential camera-engine software errors, and a video light watchdog acts in a
similar fashion. Multiple monitoring features (LED and die temperature, input voltage droop and so forth) keep
the device and LEDs operating properly.
The TPS6131x integrates an I2C compatible interface allowing transfers up to 3.4 Mbps for controlling the device,
featuring low-speed mode, standard mode and high-speed mode compatible operation. Additionally, basic
functions can be triggered by dedicated hardware input signals, such as STRB0 and STRB1 for triggering the
flash or video lighting with zero latency.
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9.2 Functional Block Diagram
SW
AVIN
Undervoltage
Lockout
Bias Supply
Bandgap
OVP
COMPARATOR
VREF = 1.238V
REF
Backgate
Control
VOUT
Hot Die
Indicator
VBAT DROOP
COMPARATOR
TON
Control
ERROR
AMPLIFIER
VREF
Digital
Filter
S
Q
R
Q
CONTROL LOGIC
P
COMPARATOR
BATTERY DROOP
THRESHOLD
VOLTAGE
REGULATION
CURRENT
REGULATION
VLED Sense
SENSE FB
LED2
ON/OFF
Max tON Timer
SCL
I2C I/F
CURRENT
CONTROL
DAC
P
SDA
SENSE FB
LED Current Ramp
(STOP)
Slew-Rate
Controller
LED1
ON/OFF
Oscillator
CURRENT
CONTROL
DAC
P
STRB1
SENSE FB
LED3
STRB0
Tx-MASK
P
NRESET
Low-Side LED Current Regulator
Control
Logic
350 kΩ
AVIN
INDLED
INDC[1:0]
AVIN
High-Side LED Current Regulator
23µA
TS
WARNING
VREF = 1.05V
HOT
VREF = 0.345V
AGND
PGND
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Figure 26. TPS6131x
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Functional Block Diagram (continued)
(GPIO Bit)
Tx-MASK
350 kW
Port Direction
(DIR)
CURRENT REGULATOR MODE – DC LIGHT / FLASH ACTIVE
MODE 0 = LOW
MODE 0 MODE 1 = HIGH
Port Type
(PG)
MODE 1
STRB1
GPIO/PG
0
STRB0
1
1
(GPIO Bit)
350 kW
Safety Timer Trigger
(STT)
Edge Detect
PWROK
Start
Flash/Timer
(SFT)
MODE 0
MODE 1
DC Light
Safety Timer
(11.2s)
0: NORMAL OPERATION
1: DISABLE CURRENT SINK
Start
LED1-3 CURRENT CONTROL
CLOCK
16-bit Prescaler
Safety Timer
0: DC LIGHT CURRENT LEVEL
1: FLASH CURRENT LEVEL
tPULSE
Time-Out (TO)
Dimming
(DIM)
Timer
Value
(STIM)
Duty-Cycle Generator (5% ... 67%)
LED1-3 ON/OFF CONTROL
0: LED1-3 OFF
1: DC LIGHT CURRENT LEVEL
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Figure 27. Timer Block
9.3 Feature Description
9.3.1 Privacy Indicator
The privacy indicator functionality can be used to indicate when a person is being photographed or filmed. The
TPS6131x device offers two options of privacy indication: A dedicated pin driving an additional privacy indicator
LED or using the white LEDs with pulse width modulation.
9.3.1.1 Dedicated LED Privacy Indicator
The TPS6131x device provides a high-side linear constant current source to drive low VF LEDs. The LED current
is directly regulated off the battery and can be controlled through the INDC[3:0] bits, from 2.6 mA to 15.8 mA in 7
programable current steps.
The device can drive two possible hardware configurations shown in Figure 28 and Figure 29. In Figure 28 the
TPS6131x device drives a privacy indicator LED towards ground.
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Feature Description (continued)
VOUT
VOUT
COUT
COUT
LED1
LED1
TPS6131x
TPS6131x
LED2
LED2
LED3
LED3
INDLED
INDLED
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Figure 28. Configuration 1
Figure 29. Configuration 2
The TPS6131x device also allows a path for driving a privacy indicator LED that is reverse biased to the white
flash LED, see Figure 29. To do so, the output of the converter (VOUT) is pulled to ground thus allowing a
reverse current to flow. This mode of operation is only possible when the converter’s power stage is in shutdown
(MODE_CTRL[1:0] = 00, ENVM = 0).
9.3.1.2 White LED Privacy Indicator
The TPS6131x device features white LED drive capability at very low light intensity. To generate a reduced LED
average current, the device employs a 30-kHz fixed-frequency PWM modulation scheme. The PWM timer uses
the internal oscillator as reference clock, therefore the PWM modulating frequency shows the same accuracy as
the internal reference clock. Operation is shown in Figure 27.
The video light current is modulated with a duty cycle defined by the INDC[3:0] bits. The low light dimming mode
can only be activated in the software-controlled video-light-only mode (MODE_CTRL[1:0] = 01, ENVM = 1), and
applies to the LEDs selected through ENLED[3:1] bits. In this mode, the video light safety-timeout feature is
disabled.
PWM Dimming Steps
5%, 11%, 17%, 23%, 30%, 36%, 48%, 67%
I DCLIGHT
t1
I LED (DC ) = I DCLIGHT x PWM Dimming Step
0
T PWM
Figure 30. PWM Dimming Principle
9.3.2 Safe Operation and Protection Features
9.3.2.1 LED Temperature Monitoring (Finger-Burn Protection)
The TPS6131x device optionally monitors the LED temperature. Critical temperatures are handled in two stages
reflected by two bits: LEDWARN provides an early warning to the camera engine, LEDHOT immediately
suspends the flash operation.
The LED temperature is sensed by measuring the voltage drop of a negative-temperature-coefficient resistor
connected between the TS and AGND pins. An internal current source provides the bias (approximately 24 µA)
for the NTC, and the TS pin voltage is compared to internal thresholds (1.05 V and 0.345 V) to protect the LEDs
against overheating. See NTC Selection.
The temperature-monitoring blocks are explicitly active in video light or flash modes. In voltage-mode operation
[MODE_CTRL[1:0] = 11], the device only activates the TS input when the ENTS bit is set high.
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Feature Description (continued)
The LEDWARN and LEDHOT bits reflect the LED temperature. The LEDWARN bit is set when the voltage at the
TS pin is lower than 1.05 V. This threshold corresponds to an LED warning temperature value; device operation
is still permitted. While regulating LED current, video light or flash modes, the LEDHOT bit is latched when the
voltage at the TS pin is lower than 0.345 V. This threshold corresponds to an excessive LED temperature value;
device operation is immediately suspended, (MODE_CTRL[1:0] bits are reset, and the HOTDIE[1:0] bits are set).
9.3.2.2 LED Failure Modes (Open and Short Detection) and Overvoltage Protection
The TPS6131x devices incorporate protection features to indicate if the connected LEDs are failing. These
protections cover overvoltage conditions, which are caused by a failing LED showing open circuit behavior, as
well as short-circuit conditions caused by a failing LED or further reasons causing a short-circuit condition. If such
failure conditions occur, these are indicated by setting a failure detection flag. Furthermore, the maximum current
drawn from the output is limited and can be programmed by the current-limit setting.
9.3.2.2.1 LED Open Circuit Detection and Overvoltage Protection
If the connected LED(s) fail showing an open circuit behavior or are disconnected, the VOUT output voltage must
be limited to prevent the step-up converter from exceeding critical values. An overvoltage protection is
implemented to avoid the output voltage exceeding critical values for the device and possibly for the system it is
supplying. For this protection the TPS6131x output voltage is monitored internally. The TPS6131x device limits
VOUT according to the overvoltage protection settings (see Table 2). In this failure mode, VOUT is either limited to
4.65 V (typical) or 6 V (typical) and the HIGH-POWER LED FAILURE (HPLF) flag is set. The OVP threshold
depends on the programmed output voltage (OV).
Table 2. OVP Specification
OVP THRESHOLD
OPERATING CONDITIONS
4.65 V typical
0000 ≤ OV[3:0] ≤ 0100
6 V typical
0101 ≤ OV[3:0] ≤ 1111
9.3.2.2.2 Short-Circuit Protection
The TPS6131x devices incorporate double protection to protect the device and application circuit from shortcircuit conditions occurring between VOUT and the current sinks LED1, LED2, and LED3.
If a short-circuit condition occurs while the LEDs are operated, the low side current sinks LED1, LED2, LED3 limit
the maximum output current as programmed for the video-light mode or flash mode respectively. If a short-circuit
condition occurs, the current sinks increase their input resistance to prevent excessive current to be drawn.
Furthermore, the HIGH-POWER LED FAILURE flag (HPLF) is set to indicate the short circuit condition. (HPLF) is
triggered if the LED forward voltage drops below 1.23 V typically. The second protection is the current limit,
which generally limits the current drawn from VOUT. See Current Limit.
9.3.2.3 LED Current Ramp-Up and Ramp-Down
To achieve smooth LED current waveforms and avoid excessive battery voltage drop, the TPS6131x device
actively controls the LED current ramp-up and ramp-down sequence.
Table 3. LED Current Ramp-Up and Ramp-Down
Control vs Operating Mode
LED CURRENT
OPERATING MODE
ISTEP = 25 mA
Ramp-up
tRISE = 12 µs
Slew rate × 2.1 mA/µs
ISTEP = 25 mA
Ramp-down
tFALL = 0.5 µs
Slew rate × 50 mA/µs
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LED
CURRENT
ISTEP
Time
t RISE
t FALL
Figure 31. LED Current Slew Rate Control
9.3.2.4 Battery Voltage Droop Monitoring and Protection
During a high-power flash strobe, the battery voltage usually drops by a few hundred millivolts. To prevent the
battery voltage from collapsing too much, the TPS6131x devices integrates a battery voltage droop monitoring
feature to automatically limit the flash current if the battery voltage drops more than a programmable threshold.
The battery voltage droop monitoring feature can be enabled or disabled through the ENBATMON bit.
At the very beginning of the flash strobe, the device measures the battery voltage and sets a minimum battery
voltage threshold based on the tolerable droop (see REGISTER7 (address = 0x07) for BATDROOP[2:0] bits).
While the LED current is increasing to the target flash current (see REGISTER1 (address = 0x01) and
REGISTER2 (address = 0x02) for FC13[4:0] and FC2[5:0] bits), a comparator monitors the actual battery voltage
and stops the ramp-up sequence when the droop exceeds the limit. See Functional Block Diagram and
Figure 32.
The battery voltage droop monitor feature is automatically disabled during a Tx-MASK event.
ILED
Target Flash
Current (950mA)
Actual Flash
Current (700mA)
DC light
VBAT
maximum allowed
Battery Droop
(BATDROOP[2:0])
LED current is
stopped from
ramping further
Battery droop
threshold
exceeded
STRB0
Figure 32. Battery Voltage Droop Monitoring and LED Current Control Principle (STRB1 = 0, Tx-Base = 1)
9.3.2.5 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from error conditions at low input voltages. It prevents the
converter from turning on the switch MOSFET, or rectifier MOSFET for battery voltages below 2.3 V. The I2C
compatible interface is fully functional down to 2.1-V input voltage.
9.3.2.6 Hot Die Detection and Thermal Shutdown
The TPS6131x device offers two levels of die temperature monitoring and protection, which are hot die detection
and thermal shutdown functionality. The hot die detector (HOTDIE[1:0] bits) reflects the instantaneous junction
temperature. This functionality is always enabled except when the device is in shutdown mode.
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The hot die detector monitors the junction temperature but does not shut down the device. It provides an early
warning to the camera engine to avoid excessive power dissipation thus preventing from thermal shutdown
during the next high-power flash strobe.
As soon as the junction temperature TJ exceeds 160°C typical, the device goes into thermal shutdown. In this
mode, the power stage and the low-side current regulators are turned off, the HOTDIE[1:0] bits are set and can
only be reset by a read access. In the voltage mode operation (MODE_CTRL[1:0] = 11 or ENVM = 1), the device
continues its operation when the junction temperature falls below 140°C typical again. In the current regulation
mode, video light or flash modes, device operation is suspended.
Table 4. Die Temperature Bits
HOTDIE[1:0]
JUNCTION TEMPERATURE
00
70°C
11
Thermal shutdown tripped. The bit is reset after read access
9.3.2.7 Current Limit
The TPS6131x devices employ a programmable inductor current limit. This allows choosing inductors with
different saturation current ratings. Furthermore, this provides protection against a shorted inductor, or if the
inductance value dramatically drops. This protects the battery from excessively high current drain.
The current limit circuit employs a valley current sensing scheme. The detection threshold is user selectable
through the ILIM bit. The ILIM bit can only be set before entering operation, during initial shutdown state.
Figure 33 illustrates the inductor and rectifier current waveforms during current limit operation. The output
current, IOUT, is the average of the rectifier ripple current waveform. When the load current is increased such
that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease
to this threshold before the next ON time begins (so called frequency foldback mechanism).
Both the output voltage and the switching frequency are reduced as the power stage of the device operates in a
constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit operation,
can be defined as:
V
V
- VIN
1
D
IOUT(CL) = (1 - D) ´ (IVALLEY + DIL ) with DIL = IN ´
and D » OUT
2
L
f
VOUT
(1)
The TPS6131x device also provides a negative current limit (≈ 300 mA) to prevent an excessive reverse inductor
current when the power stage sinks current from the output in the forced continuous conduction mode.
IPEAK
DIL
Current Limit
Threshold
Rectifier
Current
IVALLEY = ILIM
IOUT (CL)
DIL
IOUT(DC) (= ILED)
Increased
Load Current
IIN (DC)
f
Inductor
Current
IIN (DC)
DIL
ΔI L =
V IN D
×
L f
Figure 33. Inductor and Rectifier Currents in Current Limit Operation
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Table 5. Inductor Current Limit Operation
CURRENT LIMIT SETTING
ILIM BIT
TPS61310
TPS61311
1250 mA
1800 mA
Low
1750 mA
2480 mA
High
9.3.2.8 Flash Blanking (Tx-Mask) for Instantaneous Flash Current Reduction
The TPS6131x devices offer a dedicated hardware signal input (Tx-Mask) that can be used to reduce the flash
current to the programmed video light level instantaneously.
This feature can be used to reduce the overall current drawn from the battery if other system components require
high energy simultaneously, such as during a RF PA transmission pulse.
The Tx-MASK function has no influence on the safety timer duration.
FLASH
LED CURRENT
DC LIGHT
Tx- MASK
STRB0
Figure 34. Synchronized Flash With Blanking Periods (STRB1 = 0)
9.3.3 Start-Up Sequence
To avoid high inrush current during start-up, control the inrush current. When the device enables, the internal
start-up cycle starts with the first step, the precharge phase.
During precharge, the rectifying switch is turned on until the output capacitor is either charged to a value close to
the input voltage or ≈ 3.3 V, whichever occurs first. The rectifying switch is current limited during that phase. The
current limit increases with decreasing input-to-output voltage difference. This circuit also limits the output current
under output short-circuit conditions.
After precharging the output capacitor, the device starts switching, and increases its current limit in three steps of
typically 25 mA, 250 mA and full current limit (ILIM setting). The current limit transition from the first to the
second step occurs after 1 ms of operation. Full current limit operation is set once the output voltage reaches its
regulation limits. In this mode, the active balancing circuit is disabled.
9.3.4 NRESET Input: Hardware Enable or Disable
The TPS6131x family features a hardware reset pin (NRESET). This reset pin allows the device to be disabled
by an external controller without requiring an I2C write command. Under normal operation, the NRESET pin must
be held high to prevent an unwanted reset. When the NRESET is driven low, the I2C control interface and all
internal control registers are reset to the default states and the part enters shutdown mode.
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9.3.5 Serial Interface Description
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors [1]. The bus
consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives or transmits data on the
bus under control of the master device.
The TPS6131x device works as a slave and supports these data transfer modes, as defined in the I2C Bus
Specification: standard mode (100 kbps) and fast mode (400 kbps), and high-speed mode (3.4 Mbps). The
interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values
depending on the instantaneous application requirements. Register contents remain intact as long as supply
voltage remains above 2.1 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/Smode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as H/Smode. The TPS6131x device supports 7-bit addressing; 10-bit addressing and general call address are not
supported. The device 7-bit address is defined as 011 0011.
9.3.5.1 F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 35. All I2C-compatible devices must
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 35. Start and Stop Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read or write direction bit
(R/W) on the SDA line. During all transmissions, the master checks for valid data. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 36). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 37) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 36. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver must to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
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To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 35). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
Figure 37. Acknowledge on the I2C Bus
Figure 38. Bus Protocol
9.3.5.2 H/S-Mode Protocol
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in H/S-mode.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
9.3.5.3 TPS6131x I2C Update Sequence
The TPS6131x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS6131x device acknowledges by pulling the SDA line low during
the high period of a single clock pulse. A valid I2C address selects the TPS6131x. TPS6131x performs an update
on the falling edge of the acknowledge signal that follows the LSB byte.
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1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A
P
“0” Write
A
S
Sr
P
From Master to TPS6131x
From TPS6131x to Master
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 39. : Write Data Transfer Format in F/S-Mode
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
“0” Write
“1” Read
From Master to TPS6131x
A
S
Sr
P
From TPS6131x to Master
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 40. Read Data Transfer Format in F/S-Mode
F/S Mode
HS Mode
F/S Mode
1
8
1
1
7
1
1
8
1
8
1
1
S
HS-Master Code
A
Sr
Slave Address
R/W
A
Register Address
A
Data
A/A
P
Data Transferred
(n x Bytes + Acknowledge)
HS Mode Continues
Sr
A
A
S
Sr
P
From Master to TPS6131x
From TPS6131x to Master
Slave Address
= Acknowledge
= Acknowledge
= START condition
= REPEATED START condition
= STOP condition
Figure 41. Data Transfer Format in H/S-Mode
9.3.5.4 Slave Address Byte
MSB
X
LSB
X
X
X
X
X
A1
A0
The slave address byte is the first byte received following the START condition from the master device.
9.3.5.5 Register Address Byte
MSB
0
LSB
0
0
0
00
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TPS6131x,
which contains the address of the register to be accessed.
9.3.6 LED Forward Voltage Calibration
High-power LEDs tend to exhibit a wide forward voltage distribution. The TPS6131x device integrates a selfcalibration procedure that can be used to determine the actually LED forward voltage. The LED forward voltage
in situ characterization can be performed at camera engine production test. This data can help to estimate more
precisely the actual LED electrical power versus flash current.
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This calibration procedure is meant to start at a minimum output voltage, and can be initiated by writing the
SELFCAL bit (preferably with MODE_CTRL[1:0] = 00, ENVM = 0). The calibration procedure monitors the sense
voltage across the low-side current regulators (according to ENLED[3:1] bits setting) and registers the worst case
LED, the LED featuring the largest forward voltage. The TPS6131x device automatically sweeps through its
output voltage range and performs a short duration flash strobe for each step (see REGISTER1 (address = 0x01)
and REGISTER2 (address = 0x02) for FC13[4:0] and FC2[5:0] bits settings).
The sequence is stopped as soon as the device detects that each of the low-side current regulators have enough
headroom voltage (400 mV typical). The device returns the according output voltage in the register OV[3:0] and
sets the SELFCAL bit. This bit is only being reset at the start or restart of a calibration cycle. In other words,
when SELFCAL is asserted the output voltage register (OV[3:0]) returns the result of the last calibration
sequence.
Output Voltage, VOUT
~200 ms
ESR x ILED
Feedback Sense
Comparator Information
VBAT
Power Good, PG
~200 ms
LED Flash Current, IFLASH
Feedback Sense Comparator Output
VLED > 400 mV
OV[3:0]
0000
0001
0010
0011
0100
0101
Self-Calibration,
SELFCAL bit (write)
Self-Calibration,
SELFCAL bit (read)
X
Figure 42. LED Forward Voltage Calibration Principle
9.4 Device Functional Modes
9.4.1 Video Light and Flash Strobe Operation
The TPS6131x devices drive one, two or three LEDs for video light and flash application. The video light and
flash operation can either be triggered by an I2C software command or by means of dedicated, zero latency
hardware signals.
9.4.1.1 LED Hardware Setup
The TPS6131x device uses LED forward-voltage sensing circuitry on LED1, LED2, and LED3 pins to optimize
the power-stage boost ratio for maximum efficiency. Due to the nature of the sensing circuitry, TI does not
recommend leaving any of the LED1, LED2, and LED3 pins unused if the operation is selected through
ENLED[3:1] bits. Leaving LED1, LED2, and LED3 pins unconnected, while the respective ENLEDx bits have
been set, forces the control loop into high gain, and eventually trips the output overvoltage protection. Figure 43
shows the recommended LED setup for a single, dual or triple-LED application.
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Device Functional Modes (continued)
VOUT
TPS6131x
VOUT
COUT
TPS6131x
LED1
LED2
LED3
VOUT
COUT
TPS6131x
LED1
LED2
LED3
Dual LED
Single LED
COUT
LED1
LED2
LED3
Tripple LED
Figure 43. White LED Hardware Setup Options
The LED1, LED2, and LED3 inputs may be connected together to drive one or two LEDs at higher currents.
Connecting the current sink inputs in parallel does not affect the internal operation of the TPS6131x. For best
operation, TI recommends disabling the LED inputs that are not connected. (see the ENLED[3:1] bits description
in REGISTER5 (address = 0x05)).
The video light currents are individually programmed through the video light control bits DCL13[2:0] and
DCL2[2:0] , the flash currents through FC2[5:0] and FC13[4:0] bits accordingly. If, for single or dual LED
application as shown in Figure 43, current sinks are connected to each other and enabled, the resulting video or
flash current is the sum of the programmed currents.
9.4.1.2 Triggering Video Light and Flash
For most flexible system integration, the TPS6131x offers several options for activating the video light and flash.
Depending on the settings of the MODE_CTRL[1:0] bits, the device can enter different modes of operation. It
offers the option of triggering the video light and flash through hardware signals (STRB0, STRB1) or software I2C
command. The flash-signal hardware trigger can be on the leading-edge, turning on for the programmed flash on
time, or level sensitive, turning on for as long as the signal is logic high.
The TPS6131x flash timer is programmed through the STIM[2:0] and SELSTIM bits. If the flash is fired by a
rising-edge trigger or by an I2C command, the timer defines the flash duration. If the flash is fired by a levelsensitive trigger, the timer defines the maximum flash ON duration, and overrides the hardware signal if the
programmed on-time is exceeded.
For video lighting, a watchdog timer is implemented; this must be refreshed within 13 seconds. This function can
be disabled, as described in Table 6.
Table 6. Mode Operations for Video Light and Flash
MODE_CTRL SETTING
DESCRIPTION
MODE_CTRL[1:0] = 01
The STRB0, STRB1 inputs are disabled. The device regulates the LED current in video light mode
(DCLC bits) regardless of the STRB0, STRB1 inputs and the START_FLASH/TIMER (SFT) bit. To avoid
device shutdown because of the video light safety timeout, MODE_CTRL[1:0] must be refreshed within
less than 13 seconds (STRB1 = 0). The video light watchdog timer can be disabled by pulling the
STRB1 signal high.
MODE_CTRL[1:0] = 10
The STRB0, STRB1 inputs are enabled. The flash pulse can be triggered by these synchronization
signals, or by a software command (START_FLASH/TIMER (SFT) bit). The LEDs are enabled or
disabled according to the STRB0, STRB1 input. The flash safety timer is activated, and the video light
watchdog timer is disabled.
The dual-wire camera-module interface STRB0 and STRB1 inputs are used for selecting the video light
(STRB1 = 1) or flash (STRB1 = 0) mode. The STRB0 signal then triggers the video light or flash, depending on
the state of STRB1. The STT bit defines if the flash trigger is level sensitive (STT = 0), or fired on the rising edge
(STT = 1).
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9.4.1.3 Level-Sensitive Flash Trigger (STT = 0)
In this mode, the high-power LEDs are driven at the flash current level and the safety timer (STIM) is running.
The maximum duration of the flash pulse is defined in the STIM[2:0] register.
The safety timer is triggered on rising edge and stopped by a negative logic on the synchronization source
(STRB0, STRB1 = 0) or by a timeout event (TO bit).
AF ASSIST LIGHT
STROBE
STRB0
STRB1
DURATION < STIM
TIMER
LED CONTROL
LED OFF
LED OFF
DC LIGHT
LED OFF
FLASH
Figure 44. Hardware Synchronized Video Light and Flash Strobe
9.4.1.4 Rising-Edge Flash Trigger (STT = 1)
In this mode, the high-power LEDs are driven at the flash current level and the safety timer (STIM) is running.
The duration of the flash pulse is defined in the STIM[2:0] register.
The flash strobe is started either by a rising edge on the synchronization source (STRB0 = 1, STRB1 = 0) or by a
positive transition on the START-FLASH/TIMER (SFT) bit (STRB0 = 1, STRB1 = 0). Once running, the timer
ignores all kind of triggering signals and only stops after a timeout (TO). START-FLASH/TIMER (SFT) bit is being
reset by the timeout (TO) signal.
AF ASSIST LIGHT
STROBE
STRB0
STRB1
DURATION = STIM
TIMER
LED CONTROL
LED OFF
LED OFF
DC LIGHT
LED OFF
FLASH
Figure 45. Edge Sensitive Timer (Single Trigger Event)
9.4.2 Voltage Mode
In this mode, the TPS6131x operates as a standard voltage-boost regulator, featuring power-save mode for
improved efficiency under light loads. The voltage-mode operation is enabled by software control by setting the
mode-control bit MODE_CTRL[1:0] = 11. The device regulates a constant output voltage according to the
OV[3:0] bit settings (from 3.825 V to 5.7 V in 125-mV steps). In voltage mode, the LED current sinks LED1,
LED2, and LED3 are turned off.
The TPS6131x integrates a software control bit (ENVM bit) that can be used to force the converter to run in
voltage mode. This enables the converter to operate at a fixed programmed output voltage (according to the
OV[3:0] settings) while operating the LEDs.
Table 7 provides an overview of the different voltage mode variations.
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Table 7. Voltage Mode Description
INTERNAL REGISTER
SETTINGS MODE_CTRL[1:0]
ENVM
BIT
11
0
00
1
01
1
The converter operates in voltage-regulation mode (VM); the output voltage is set through the
register OV[3:0]. The LEDs are turned on for video light operation and the energy is being
directly transferred from the battery to the output. The LED currents are regulated by the means
of the low-side current sinks.
10
1
The converter operates in the voltage-regulation mode (VM); the output voltage is set through
the register OV[3:0]. The LED currents are regulated by the low-side current sinks. The LEDs
are ready for flash operation.
11
1
LEDs are turned off and the converter operates in the voltage regulation mode (VM); the output
voltage is set through the register OV[3:0].
OPERATING MODES
LEDs are turned off and the converter operate in voltage-regulation mode (VM); the output
voltage is set through register OV[3:0].
9.4.2.1 Down Mode in Voltage Mode Operation
In general, a boost converter only regulates output voltages which are higher than the input voltage. The
TPS6131x can regulate 4.2 V at the output with an input voltage as high as 5.5 V. To control these applications
properly, a down-conversion mode is implemented.
In voltage-regulation mode, if the input voltage reaches or exceeds the output voltage, the converter changes to
down-conversion mode. In this mode, the control circuit changes the behavior of the rectifying PMOS. It sets the
voltage drop across the PMOS as high as required to regulate the output voltage. This increases the power
losses in the converter, and must be considered for thermal design. The down-conversion mode is automatically
turned off as soon as the input voltage falls to approximately 200 mV below the output voltage.
For proper operation in down-conversion mode the output voltage must not be programmed higher than
approximately 5.3 V. Take care not to violate the absolute maximum ratings at the SW pins.
9.4.2.2 Power Good Indication
The TPS6131x integrates a Power Good circuit that is activated when the device operates in voltage-regulation
mode (MODE_CTRL[1:0] = 11 or ENVM = 1). In shutdown mode (MODE_CTRL[1:0] = 00, ENVM = 0), the
GPIO/PG pin state is defined below, according to the GPIOTYPE bit:
Table 8. GPIO/PG State in Shutdown
GPIOTYPE
GPIO/PG SHUTDOWN STATE
0
Reset or pulled to ground
1
Open-drain
Depending on the GPIO/PG output stage type selection, push-pull or open-drain, the polarity of the Power Good
output signal (PG) can be inverted or not. The Power Good software bit and hardware signal polarity is defined
below:
Table 9. Power Good Signal Polarity
GPIOTYPE
PG BIT
GPIO/PG OUTPUT PORT
0
0
1
1
0
Open-drain
1
Low
0: push-pull output
1: open-drain output
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COMMENTS
Output is active-high
Output is active-low
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The Power Good signal is true when the output voltage is from –1.5% to 2.5% of its nominal value. Conversely, it
is false when the voltage-mode operation is suspended (MODE_CTRL[1:0] ≠ 11 and ENVM = 0).
Forced PWM mode operation
Output Voltage
Down Regulation
Voltage Mode Request
1.025 VOUT (NOM )
Nom. Voltage
Output Voltage, VOUT
VOUT (NOM )
Start-up phase
0.985 VOUT (NOM )
Output Voltage
Up Regulation
Power Good Bit, (PG)
Power Good Output,
GPIO/PG
Hi-Z
Hi-Z
Forced PWM mode operation
(PG) Bit
Figure 46. Power Good Operation (DIR = 1, GPIOTYPE = 1)
The TPS6131x device uses a control architecture that recycles excess energy that might be stored in the output
capacitor. By reversing the operation of the boost power stage, the converter is capable of transferring energy
from its output back into the input source. In this case, the Power Good signal is deasserted while the output
voltage is decreasing towards its target value, the closest fit voltage the converter can support.
9.4.3 Power-Save Mode Operation, Efficiency
The TPS6131x integrates a power-save mode to improve efficiency under light loads. In power-save mode the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with one to several pulses and returns to power-save mode once the output voltage exceeds the set
threshold voltage.
Output
Voltage
PFM mode at light load
PFM ripple about 0.015 x VOUT
1.013 x VOUT NOM.
VOUT NOM.
PWM mode at heavy load
Figure 47. Operation in PFM Mode and Transfer to PWM Mode
The power-save mode can be enabled and disabled through the ENPSM bit. In down conversion mode, powersave mode is always active and the device cannot be forced into fixed frequency operation at light loads.
The LED sense voltage has a direct effect on converter efficiency. Because the voltage across the low-side
current regulator does not contribute to the output power (LED brightness), the lower the sense voltage the
higher the efficiency is.
The integrated current control loop automatically selects the minimum boost ratio to maintain regulation based on
the LED forward voltage and current requirements. The low-side current regulators drop the voltage difference
between
the
input
voltage
and
the
LEDs
forward
voltage
(VF(LED) < VIN). When running in boost mode (VF(LED) > VIN), the voltage present at the LED1, LED2, and LED3
pins of the low-side current regulators is typically 400 mV, leading to high power conversion efficiency.
Depending on the input voltage and the LEDs forward voltage characteristic the converter efficiency is
approximately 75% to 90%.
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9.4.4 Shutdown
Writing 00 to MODE_CTRL[1:0] bits forces the device into shutdown. The shutdown state can only be entered
when the voltage regulation (ENVM = 0) and light modes are both turned off.
In the shutdown state:
• The regulator stops switching.
• The high-side PMOS disconnects the load from the input.
• The LEDx pins are high impedance thus eliminating any DC conduction path.
• The TPS6131x device actively discharges the output capacitor when it turns off.
9.5 Register Maps
9.5.1 REGISTER0 (address = 0x00)
Figure 48. REGISTER0 Fields
D7
RESET
R/W-0
D6
—
R/W-0
D5
R/W-0
D4
DCLC13[2:0]
R/W-0
D3
D2
R/W-1
R/W-0
D1
DCLC2[2:0]
R/W-1
D0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. REGISTER0 Field Descriptions
BIT
DESCRIPTION
RESET
Register Reset bit
0: Normal operation.
1: Default values are set to all internal registers.
DCLC13[2:0]
Video Light Current Control bits (LED1 and LED3)
000: 0 mA (1) (2)
001: 25 mA
010: 50 mA
011: 75 mA
100: 100 mA
101: 125 mA
110: 150 mA
111: 175 mA
DCLC2[2:0]
Video Light Current Control bits (LED2)
000: 0 mA (1) (2)
001: 25 mA
010: 50 mA
011: 75 mA
100: 100 mA
101: 125 mA
110: 150 mA, 225 mA current level can be activated simultaneously with Tx-MASK = 1
111: 175 mA, 325 mA current level can be activated simultaneously with Tx-MASK = 1
(1)
(2)
30
LEDs are off, VOUT set according to OV[3:0].
When DCLC2[2:0] and DCLC13[2:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according
to OV[3:0].
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9.5.2 REGISTER1 (address = 0x01)
Figure 49. REGISTER1 Fields
D7
D6
MODE_CTRL[1:0]
R/W-0
R/W-0
D5
D4
D3
D2
D1
D0
R/W-0
R/W-0
R/W-0
FC2[5:0]
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. REGISTER1 Field Descriptions
BIT
DESCRIPTION
MODE_CTRL[1:0]
Mode Control bits
00: Device in shutdown mode.
01: Device operates in video light mode.
10: Device operates in flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by video light safety timeout, MODE_CTRL[1:0] bits must be refreshed within less than
13 s.
Writing to REGISTER1[7:6] automatically updates REGISTER2[7:6].
FC2[5:0]
Flash Current Control bits (LED2)
000000: 0 mA (1) (2)
000001: 25 mA
000010: 50 mA
000011: 75 mA
000100: 100 mA
000101: 125 mA
000110: 150 mA
000111: 175 mA
001000: 200 mA
001001: 225 mA
001010: 250 mA
001011: 275 mA
001100: 300 mA
001101: 325 mA
001110: 350 mA
001111: 375 mA
010000: 400 mA
010001: 425 mA
010010: 450 mA
010011: 475 mA
010100: 500 mA
010101: 525 mA
010110: 550 mA
010111: 575 mA
011000: 600 mA
011001: 625 mA
011010: 650 mA
011011: 675 mA
011100: 700 mA
011101: 725 mA
011110: 750 mA
011111: 775 mA
100000 to 111111: 800 mA
(1)
(2)
LEDs are off, VOUT set according to OV[3:0].
When FC13[4:0] and FC2[5:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according to
OV[3:0].
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9.5.3 REGISTER2 (address = 0x02)
Figure 50. REGISTER2 Fields
D7
D6
MODE_CTRL[1:0]
R/W-0
R/W-0
D5
ENVM
R/W-0
D4
D3
R/W-0
R/W-1
D2
FC13[4:0]
R/W-0
D1
D0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. REGISTER2 Field Descriptions
BIT
DESCRIPTION
MODE_CTRL[1:0]
Mode Control bits
00: Device in shutdown mode.
01: Device operates in video light mode.
10: Device operates in flash mode.
11: Device operates as constant voltage source.
To avoid device shutdown by video light safety timeout, MODE_CTRL[1:0] bits must be refreshed within less than
13 s.
Writing to REGISTER2[6:5] automatically updates REGISTER1[6:5].
ENVM
Enable Voltage Mode bit.
0: Normal operation.
1: Forces the device into a constant voltage source.
In read mode, the ENVM bit is automatically updated to reflect the logic state of the ENVM input pin.
FC13[4:0]
Flash Current Control bits (LED1 and LED3)
00000: 0 mA (1) (2)
00001: 25 mA
00010: 50 mA
00011: 75 mA
00100: 100 mA
00101: 125 mA
00110: 150 mA
00111: 175 mA
01000: 200 mA
01001: 225 mA
01010: 250 mA
01011: 275 mA
01100: 300 mA
01101: 325 mA
01110: 350 mA
01111: 375 mA
10000 to 11111: 400 mA
(1)
(2)
32
LEDs are off, VOUT set according to OV[3:0].
When FC13[4:0] and FC2[5:0] are both reset, the device operates in voltage regulation mode. The output voltage is set according to
OV[3:0].
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9.5.4 REGISTER3 (address = 0x03)
Figure 51. REGISTER3 Fields
D7
D6
D5
D4
STIM[2:0]
R/W-1
R/W-1
HPFL
R/W-0
R-0
D3
SELSTIM (W)
TO (R)
R-0
D2
D1
D0
STT
SFT
Tx-MASK
R/W-0
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. REGISTER3 Field Descriptions
BIT
DESCRIPTION
Safety Timer bits
STIM[2:0]
STIM[2:0]
000
001
010
011
100
101
110
111
RANGE 0
68.2 ms
102.2 ms
136.3 ms
170.4 ms
204.5 ms
340.8 ms
579.3 ms
852 ms
RANGE 1
5.3 ms
10.7 ms
16 ms
21.3 ms
26.6 ms
32 ms
37.3 ms
71.5 ms
HPFL
High-Power LED Failure flag
0: Proper LED operation.
1: LED failed (open or shorted).
High-power LED failure flag is reset after readout
SELSTIM
Safety Timer Selection Range (Write Only)
0: Safety timer range 0.
1: Safety timer range 1.
TO
Time-Out Flag (Read Only)
0: No time-out event occurred.
1: Time-out event occurred. Time-out flag is reset at restart of the safety timer.
STT
Safety Timer Trigger bit
0: LED safety timer is level sensitive.
1: LED safety timer is rising edge sensitive.
This bit is only valid for MODE_CTRL[1:0] = 10.
SFT
Start/Flash Timer bit
In write mode, this bit initiates a flash strobe sequence. Notice that this bit is only active when STRB0 input is high.
0: No change in the high-power LED current.
1: High-power LED current ramps to the flash current level.
In read mode, this bit indicates the high-power LED status.
0: High-power LEDs are idle.
1: Ongoing high-power LED flash strobe.
Tx-MASK
Flash Blanking Control bit
In write mode, this bit enables and disables the flash blanking and LED current reduction function.
0: Flash blanking disabled.
1: LED current is reduced to video light level when Tx-MASK input is high.
In read mode, this flag indicates whether or not the flash masking input is activated. Tx-MASK flag is reset after
readout of the flag.
0: No flash blanking event occurred.
1: Tx-MASK input triggered.
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9.5.5 REGISTER4 (address = 0x04)
Figure 52. REGISTER4 Fields
D7
PG
R/W-0
D6
D5
D4
ILIM
R/W-0
HOTDIE[1:0]
R-0
R-0
D3
D2
D1
D0
R/W-0
R/W-0
INDC[3:0]
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. REGISTER4 Field Descriptions
Bit
Description
PG
Power Good bit
In write mode, this bit selects the functionality of the GPIO/PG output.
0: PG signal is routed to the GPIO port.
1: GPIO PORT VALUE bit is routed to the GPIO port.
In read mode, this bit indicates the output voltage conditions.
0: The converter is not operating within the voltage regulation limits.
1: The output voltage is within its nominal value.
HOTDIE[1:0]
Instantaneous Die Temperature bits
00: TJ < 55°C
01: 55°C < TJ < 70°C
10: TJ > 70°C
11: Thermal shutdown tripped. Indicator flag is reset after readout.
Inductor Valley Current Limit bit
The ILIM bit can only be set before the device enters operation, during initial shutdown state.
ILIM
VALLEY CURRENT LIMIT SETTING
ILIM BIT SETTING
TPS61310
1250 mA
1750 mA
Low
High
TPS61311
1800 mA
2480 mA
Indicator Light Control bits
INDC[3:0]
(1)
(2)
34
INDC[3:0]: PRIVACY INDICATOR INDLED CHANNEL
_
0000: Privacy indicator turned off
0001: INDLED current = 2.6 mA (1)
0010: INDLED current = 5.2 mA (1)
0011: INDLED current = 7.9 mA (1)
0100: Privacy indicator turned off
0101: INDLED current = 5.2 mA (1)
0110: INDLED current = 10.4 mA (1)
0111: INDLED current = 15.8 mA (1)
INDC[3:0]: PRIVACY INDICATOR LED1, LED2, and
LED3 CHANNELS (2)
1000: 5% PWM dimming ratio
1001: 11% PWM dimming ratio
1010: 17% PWM dimming ratio
1011: 23% PWM dimming ratio
1100: 30% PWM dimming ratio
1101: 36% PWM dimming ratio
1110: 48% PWM dimming ratio
1111: 67% PWM dimming ratio
The output node (VOUT) is internally pulled to ground.
This mode of operation can only be activated for MODE_CTRL[1:0] = 01 and ENVM = 1.
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9.5.6 REGISTER5 (address = 0x05)
Figure 53. REGISTER5 Fields
D7
D6
SELFCAL
ENPSM
R/W-0
R/W-1
D5
DIR (W)
STSTRB1 (R)
R/W-1
D4
D3
D2
D1
D0
GPIO
GPIOTYPE
ENLED3
ENLED2
ENLED1
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. REGISTER5 Field Descriptions
Bit
Description
SELFCAL
High-Current LED Forward Voltage Self-Calibration Start bit
In write mode, this bit enables and disables the output voltage versus LED forward voltage and current selfcalibration procedure.
0: Self-calibration disabled.
1: Self-calibration enabled.
In read mode, this bit returns the status of the self-calibration procedure.
0: Self-calibration ongoing
1: Self-calibration done. This bit is only reset at the start or restart of a calibration cycle.
ENPSM
Enable and Disable Power-Save Mode bit
0: Power-save mode disabled.
1: Power-save mode enabled.
STSTRB1
STRB1 Input Status bit (Read Only)
This bit indicates the logic state on the STRB1 state.
DIR
GPIO Direction bit
0: GPIO configured as input.
1: GPIO configured as output.
GPIO
GPIO Port Value
This bit contains the GPIO port value.
GPIOTYPE
GPIO Port Type
0: GPIO is configured as push-pull output.
1: GPIO is configured as open-drain output.
ENLED3
Enable and Disable High-Current LED3 bit
0: LED3 input is disabled.
1: LED3 input is enabled.
ENLED2
Enable and Disable High-Current LED2 bit
0: LED2 input is disabled.
1: LED2 input is enabled.
ENLED1
Enable and Disable High-Current LED1 bit
0: LED1 input is disabled.
1: LED1 input is enabled.
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9.5.7 REGISTER6 (address = 0x06)
Figure 54. REGISTER6 Fields
D7
ENTS
R/W-0
D6
LEDHOT
R/W-0
D5
LEDWARN
R-0
D4
LEDHDR
R-0
D3
D2
D1
D0
R/W-0
R/W-1
0V[3:0]
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. REGISTER6 Field Descriptions
Bit
Description
ENTS
Enable and Disable LED Temperature Monitoring
0: LED temperature monitoring disabled.
1: LED temperature monitoring enabled.
LEDHOT
LED Excessive Temperature Flag
This bit can be reset by writing a logic level zero.
0: TS input voltage > 0.345 V.
1: TS input voltage < 0.345 V.
LEDWARN
LED Temperature Warning Flag (Read Only)
This flag is reset after readout.
0: TS input voltage > 1.05 V.
1: TS input voltage < 1.05 V.
LEDHDR
LED High-Current Regulator Headroom Voltage Monitoring bit
This bit returns the headroom voltage status of the LED high-current regulators. This value is being updated at the
end of a flash strobe, before the LED current ramp-down phase.
0: Low headroom voltage.
1: Sufficient headroom voltage.
0V[3:0]
Output Voltage Selection bits
In read mode, these bits return the result of the high-current LED forward voltage self-calibration procedure.
In write mode, these bits are used to set the target output voltage (see Down Mode in Voltage Mode Operation
voltage regulation mode). In applications requiring dynamic voltage control, take care to set the new target code
after voltage mode operation is enabled (MODE_CTRL[1:0] = 11 or ENVM bit = 1).
OV[3:0]: Target Output Voltage
0000: 3.825 V
0001: 3.95 V
0010: 4.075 V
0011: 4.2 V
0100: 4.325 V
0101: 4.45 V
0110: 4.575 V
0111: 4.7 V
1000: 4.825 V
1001: 4.95 V
1010: 5.075 V
1011: 5.2 V
1100: 5.325 V
1101: 5.45 V
1110: 5.575 V
1111: 5.7 V
36
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9.5.8 REGISTER7 (address = 0x07)
Figure 55. REGISTER7 Fields
D7
ENBATMON
R/W-0
D6
R/W-1
D5
BATDROOP[2:0]
R/W-0
D4
R/W-0
D3
—
R/W-0
D2
R-1
D1
REVID[2:0]
R-1
D0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. REGISTER7 Field Descriptions
Bit
Description
ENBATMON
Enable and Disable Battery Voltage Droop Monitoring Bit
0: Battery voltage droop monitoring disabled.
1: Battery voltage droop monitoring enabled.
BATDROOP[2:0]
Battery Voltage Droop
000: 50 mV
001: 75 mV
010: 100 mV
011: 125 mV
100: 150 mV
101: 175 mV
110: 200 mV
111: 225 mV
REVID[2:0]
Silicon Revision ID
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
TPS6131x family is based on a high-efficiency synchronous boost topology, which can drive up to three LEDs in
parallel. The power stage is capable of supplying a maximum total current up to 1750 mA for TPS61310 and
2480 mA for TPS61311. The 2-MHz switching frequency allows the use of small and low passive components.
10.2 Typical Applications
10.2.1 2x 600-mA High Power White LED Solution Featuring Privacy Indicator
TPS
61310
L
SW
SW
VOUT
2.2 mH
CO
AVIN
2 .5 V .. 5 .5 V
10 mF
CI
CAMERA ENGINE
FLASH SYNCHRONIZATION
D2
LED 1
NRESET
HARDWARE RESET
D1
LED 2
STRB0
LED 3
STRB1
INDLED
2
I C I /F
RF PA TX ACTIVE
SCL
Privacy
SDA
Indicator
Tx -MASK
NTC
TS
GPIO
/PG
220 k
PGND
AGND
PGND
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Figure 56. 2x 600-mA High Power White LED Solution Featuring Privacy Indicator
10.2.1.1 Design Requirements
In this design example, different LED current limit is set through I2C interface, the input voltage is 2.5 V to 5.5 V,
output voltage is 4.94 V, operating frequency of 2 MHz.
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Typical Applications (continued)
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Inductor Selection
A boost converter requires two main passive components for storing energy during the conversion. A boost
inductor and a storage capacitor at the output are required.
The TPS6131x device integrates current-limit protection circuitry. The valley current of the PMOS rectifier is
sensed to limit the maximum current flowing through the synchronous rectifier and the inductor. The valley peak
current limit (1250 mA or 1750 mA) is user selectable through the I2C interface.
To optimize solution size the TPS6131x device is designed to operate with inductance values from a minimum of
1.3 µH to a maximum of 2.9 µH. TI recommends a 2.2-µH inductance in typical high-current white LED
applications.
The highest peak current through the inductor and the power switch depends on the output load, the input and
output voltages. The maximum average inductor current and the maximum inductor peak current can be
estimated using Equation 2 and Equation 3:
VOUT
IL » IOUT ´
η ´ VIN
(2)
IL(PEAK) =
VIN ´ D
2 ´ f ´ L
+
IOUT
(1 - D) ´ h
with D =
VOUT - VIN
VOUT
where
•
•
•
f = switching frequency (2 MHz)
L = inductance value (2.2 µH)
η = estimated efficiency (85%)
(3)
The losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter for
total circuit efficiency.
10.2.1.2.2 Input Capacitor
For good input-voltage filtering, TI recommends low ESR ceramic capacitors. TI recommends a 10-µF input
capacitor to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. The
input capacitor must be placed as close as possible to the input pin of the converter.
10.2.1.2.3 Output Capacitor
The major parameter necessary to define the output capacitor is the maximum allowed output-voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance required for the defined ripple, supposing that the ESR is zero, by
using Equation 4:
IOUT × (V OUT - VIN)
Cmin »
f ´ DV ´ V OUT
where
•
•
f is the switching frequency
ΔV is the maximum allowed ripple
(4)
With a chosen ripple voltage of 10 mV, a minimum capacitance of 10 µF is required. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 5:
DVERR = IOUT ´ RESR
(5)
The total ripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the
capacitor. Additional ripple is caused by load transients. This means that the output capacitor must completely
supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends
on the speed of the load transients and the load current during the load change.
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Typical Applications (continued)
For the standard current white LED application, a minimum of 3-µF effective output capacitance is usually
required when operating with 2.2-µH (typical) inductors. For solution size reasons, this is usually one or more
X5R or X7R ceramic capacitors.
Depending on the material, size and therefore margin to the rated voltage of the used output capacitor,
degradation on the effective capacitance can be observed. This loss of capacitance is related to the DC bias
voltage applied. Therefore, TI recommends checking that the selected capacitors show enough effective
capacitance under real operating conditions.
10.2.1.2.4 NTC Selection
The TPS6131x requires a negative thermistor (NTC) for sensing the LED temperature. Once the temperature
monitoring feature is activated, a regulated bias current (approximately 24 µA) is driven out of the TS port to
produce a voltage across the thermistor.
If the temperature of the NTC-thermistor rises due to the heat dissipated by the LED, the voltage on the TS input
pin decreases. When this voltage goes below the warning threshold, the LEDWARN bit in REGISTER6 is set.
This flag is cleared by reading the register.
If the voltage on the TS input decreases further and falls below hot threshold, the LEDHOT bit in REGISTER6 is
set and the device goes automatically in shutdown mode to avoid damaging the LED. This status is latched until
the LEDHOT flag gets cleared by software.
The selection of the NTC-thermistor value strongly depends on the power dissipated by the LED and all
components surrounding the temperature sensor and on the cooling capabilities of each specific application. With
a 220-kΩ (at 25°C) thermistor, the valid temperature window is set from 60°C to 90°C. The temperature window
can be enlarged by adding external resistors to the TS pin application circuit. To obtain proper triggering of the
LEDWARN and LEDHOT flags in noisy environments, the TS signal may require additional filtering capacitance.
80
Minimum NTC
Maximum NTC
Typical NTC
TS Input Resistance (k:)
70
60
50
40
30
20
10
0
25
35
45
55
65
75
85
Temperature (°C)
95
105
115
125
D001
Figure 57. Temperature Monitoring Characteristic
10.2.1.2.5 Checking Loop Stability
The first step of circuit and stability evaluation is to examine these signals from a steady-state perspective:
• Switching node (SW)
• Inductor current (IL)
• Output ripple voltage (VOUT(AC))
These are the basic signals that must be measured when evaluating a switching converter. If the switching
waveform shows large duty-cycle jitter or the output voltage or inductor current shows oscillations, the regulation
loop may be unstable. This is often a result of improper board layout or L-C combination.
As a next step in the evaluation of the regulation loop, test the load transient response. VOUT can be monitored
for settling time, overshoot or ringing that helps judge the converter's stability. With no ringing, the loop usually
has more than 45° of phase margin.
40
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Typical Applications (continued)
Because the damping factor of the circuitry is directly related to several resistive parameters (MOSFET rDS(ON))
that are temperature dependant, the loop stability must be analyzed over the input voltage range, output current
range, and temperature range.
10.2.1.2.6 LED Flash Current Level Optimization Versus Battery Droop
In cell phone applications, the camera engine is normally specified over an operating temperature down to 0°C or
–10°C. To achieve a reliable system operation, the LED flash current must be rated according to the maximum
tolerable battery voltage drop, highest battery impedance and lowest ambient temperature.
To dynamically optimize the LED flash current (light output) versus battery state-of-charge and temperature, we
could consider the self-adjustment procedure in Figure 58. This algorithm could be embedded into the autoexposure, auto white-balance, or red-eye reduction pre-flash algorithms.
Base-band processor to compute battery ESR
~
~
Battery Voltage
~
~
Battery Voltage
Measurement
tCRITICAL
Pre-Flash
Flash (Capture)
(3 ms)
(133 ms)
~
~
IFLASH
(Optimum)
LED Current
~
~
~
~
Flash Synchronization
(Camera ISP)
Figure 58. Image Capture Sequence
•
•
Phase 1: Pre-Flash, Battery Impedance Estimation
The battery voltage usually drops by a few hundreds of millivolts during a high-power flash strobe. For short
durations, this voltage droop should not be subject to the battery intrinsic capacitance (relaxation effect) but
rather to its cell impedance.
Based on the state of the Tx-MASK input, the battery voltage drop, during pre-flash, and the LED current
level, the base-band processor can compute an estimated cell-impedance value (ESR).
Depending on the ambient temperature, the battery state-of-charge (SoC), the flash (capture) duration and
the actual status of the various RF interfaces, the base-band processor can determine a safe battery voltage
droop, to be tolerated during the forthcoming strobe sequence, as well as a maximum flash current rating.
The maximum flash current setting can be estimated by considering nominal LEDs and approximately 85%
power efficiency in the driver.
Phase 2: Battery Loading Monitoring Before Image Capture
For a reliable system operation, the base-band processor must make sure that no 'parasitic' high-current load
suddenly impacts the budgeted battery voltage sag. The most critical timing is referenced as tCRITICAL.
The interrupt subroutine, running on the base-band processor, must be ready to detect any 'parasitic' battery
load event that could occur before the image capture (see REGISTER3 (address = 0x03) for SFT bit
description). In such a situation, the battery voltage droop budget and the maximum LED current settings
would need to be revised.
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Typical Applications (continued)
Figure 59. 900-mAh, Li-Ion Battery Transient Response vs SoC and Temperature
10.2.1.3 Application Curves
STRB0
(2V/div)
STRB0
(2V/div)
ILED2
(500mA/div)
LED2 Channel Only
DCLC2[2:0] = 000
FC2[5:0] = 100000
Tx-MASK
(2V/div)
DCLC13[2:0] = 000
FC13[4:0] = 01100
ILED1 + ILED3
(200mA/div)
VOUT
(1V/div - 3.6V Offset)
LED2 Pin Headroom Voltage
(1V/div)
ILED2
(200mA/div)
VIN = 3.6V, VOUT = 4.95V, ILIM = 1750mA
VIN = 3.6V, VOUT = 4.95V, ILIM = 1750mA
t - Time = 500 µs/div
t - Time = 1 ms/div
STRB1 = 0
STRB1 = 0
Figure 60. Flash Sequence
42
DCLC2[2:0] = 000
FC2[5:0] = 011000
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Figure 61. Tx-Masking Operation
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Typical Applications (continued)
Tx-MASK
(2V/div)
Tx-MASK
(2V/div)
ILED2
(200mA/div)
ILED2
(200mA/div)
IL
(200mA/div)
IL
(500mA/div)
LED2 Channel Only
DCLC2[2:0] = 111
FC2[5:0] = 100000
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
LED2 Channel Only
DCLC2[2:0] = 010
FC2[5:0] = 100000
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
t - Time = 5 µs/div
t - Time = 100 µs/div
STRB1 = 0
STRB1 = 0
Figure 62. Tx-Masking Operation
Figure 63. Tx-Masking Operation
VOUT
(20mV/div - 4.95V Offset)
ILED2
(20 mA/div)
IL
(200mA/div)
SW
(2V/div)
Frequency = 30 kHz
Duty Cycle = 23 %
VIN = 3.6V, VOUT = 4.95V
IOUT = 300mA, ILIM = 1750mA
t - Time = 10 µs/div
Forced PWM Operation
ENPSM bit = 0
t - Time = 125 ns/div
Figure 64. Low-Light Dimming Mode Operation
Figure 65. PWM Operation
MODE_CTRL[1:0] = 01
DC Light Turn-On
VOUT
(100mV/div - 4.95V Offset)
ILED2
(50mA/div)
IL
(200mA/div)
VOUT
(2V/div)
SW
(5V/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 50mA, ILIM = 1750mA
IL
(200mA/div)
PFM/PWM Operation
ENPSM bit = 1
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
LED2 Channel Only
DCLC2[2:0] = 100
t - Time = 200 µs/div
t - Time = 2 ms/div
Figure 66. PFM Operation
Figure 67. Start-Up Into Video Light Operation
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Typical Applications (continued)
10.2.2 1200-mA High Power White LED Solution Featuring Voltage Mode
TPS
61310
L
SW
SW
VOUT
2 .2 mH
CO
AVIN
2 . 5 V .. 5 . 5 V
10 mF
D1
CI
Privacy
Indicator
NRESET
HARDWARE RESET
CAMERA ENGINE
FLASH SYNCHRONIZATION
STRB0
STRB1
LED 1
LED 2
LED 3
INDLED
SCL
2
I C I /F
RF PA TX ACTIVE
SDA
Tx MASK
-
NTC
TS
GPIO/PG
220 k
PGND
AGND
PGND
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Figure 68. 1200-mA High Power White LED Solution Featuring Voltage Mode
10.2.2.1 Design Requirements
TPS6131x operates in standard voltage-boost regulator by setting mode-control bit MODE_CTRL[1:0] = 11. The
LED current sink is turned off in this mode, with VIN = 2.5 V to 5.5 V, VOUT = 4.95 V, operating frequency 2 MHz.
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Typical Applications (continued)
10.2.2.2 Application Curves
VIN = 3.6V, VOUT = 4.95V
ILIM = 1750mA
VOUT
(500mV/div - 4.95V Offset)
VOUT
(100mV/div - 3.825V Offset)
IL
(200mA/div)
IL
(500mA/div)
50mA to 500mA Load Step
SW
(5V/div)
IOUT
(500mA/div)
VIN = 4.2V, VOUT = 3.825V
IOUT = 50mA, ILIM = 1750mA
PFM/PWM Operation
ENPSM bit = 1
PFM/PWM Operation
ENPSM bit = 1
t - Time = 2 ms/div
t - Time = 50 ms/div
Figure 69. Down-Mode Operation (Voltage Mode)
Figure 70. Voltage Mode Load Transient Response
ENVM bit
Voltage Mode Regulation Start
VOUT
(2V/div)
IL
(200mA/div)
VIN = 3.6V, VOUT = 4.95V
IOUT = 0mA, ILIM = 1750mA
t - Time = 100 µs/div
Figure 71. Start-Up Into Voltage Mode Operation
11 Power Supply Recommendations
TPS6131x is designed to operate from an input voltage supply from 2.5 V to 5.5 V. This input supply must be
well regulated and capable to supply the required input current. If the input supply is placed far from the
TPS6131x, additional bulk capacitance may be required to the ceramic bypass capacitors.
12 Layout
12.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks.
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Layout Guidelines (continued)
The input capacitor, output capacitor, and the inductor must be placed as close as possible to the IC. Use a
common ground node for power ground and a different one for control ground to minimize the effects of ground
noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To lay out the control ground, TI recommends using short traces which are separated from the power ground
traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and
control ground current.
12.2 Layout Example
L1
GND
SDA
COUT
INDLED
B2: SCL
B3: NRESET
C3: Tx_MASK
D3: STRB1
D4: GPIO/PG
STRB0
1
TS
CIN
GND
VIN
LED2
LED1 LED3
Figure 72. Suggested Layout (Top)
12.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat generating components affect the powerdissipation limits of a given component.
There are three basic approaches for enhancing thermal performance:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
Junction-to-ambient thermal resistance is highly dependent on application and board layout. In applications
where high maximum power dissipation exists, thermal dissipation issues in board design must be considered.
The maximum junction temperature (TJ) of the TPS6131x is 150°C.
The maximum power dissipation is especially critical when the device operates in the linear down mode at high
LED current. For single-pulse power thermal analysis, such as during a flash strobe, the allowable power
dissipation for the device is given by Figure 73. These values are derived using the reference design.
46
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PDIS - Single Pulse Constant Power Dissipation - W
Thermal Considerations (continued)
10
9
8
TJ = 65°C rise
7
6
5
4
3
2
TJ = 40°C rise
1
No Airflow
0
0
20
40
60
80 100 120 140 160 180 200
Pulse Width - ms
Figure 73. Single Pulse Power Capability
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
UM10204, I2C-Bus Specification and User Manual; (Rev. 6, April 2014),
http://www.nxp.com/documents/user_manual/UM10204.pdf
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 18. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS61310
Click here
Click here
Click here
Click here
Click here
TPS61311
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS61310YFFR
ACTIVE
DSBGA
YFF
20
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS61310
TPS61310YFFT
ACTIVE
DSBGA
YFF
20
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS61310
TPS61311YFFR
ACTIVE
DSBGA
YFF
20
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS61311
TPS61311YFFT
ACTIVE
DSBGA
YFF
20
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS61311
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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