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TPS62090, TPS62091, TPS62092, TPS62093
SLVSAW2C – MARCH 2012 – REVISED OCTOBER 2016
TPS6209x 3-A High Efficiency Synchronous Step Down Converter with DCS-Control™
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The TPS6209x devices are a family of high frequency
synchronous step down converters optimized for
small solution size, high efficiency and suitable for
battery powered applications. To maximize efficiency,
the converters operate in pulse width modulation
(PWM) mode with a nominal switching frequency of
2.8 MHz/1.4 MHz and automatically enter power save
mode operation at light load currents. When used in
distributed power supplies and point of load
regulation, the devices allow voltage tracking to other
voltage rails and tolerate output capacitors ranging
from 10 µF up to 150 µF and beyond. Using the
DCS-Control™ topology the devices achieve
excellent load transient performance and accurate
output voltage regulation.
1
2.5 V to 6 V Input Voltage Range
DCS-Control™
95% Converter Efficiency
Power Save Mode
20 µA Operating Quiescent Current
100% Duty Cycle for Lowest Dropout
2.8 MHz/1.4 MHz Typical Switching Frequency
0.8 V to VIN Adjustable Output Voltage
Fixed Output Voltage Versions
Output Discharge Function
Adjustable Softstart
Hiccup Short Circuit Protection
Output Voltage Tracking
Pin-to-pin compatible with TPS62095
The output voltage start-up ramp is controlled by the
softstart pin, which allows operation as either a standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
enable and power good pins. In power save mode,
the devices operate at typically 20 µA quiescent
current. Power save mode is entered automatically
and seamlessly maintaining high efficiency over the
entire load current range.
2 Applications
•
•
•
•
•
•
Distributed Power Supplies
Notebook, Netbook Computers
Hard Disk Drivers (HDD)
Solid State Drives (SSD)
Processor Supply
Battery Powered Applications
Device Information (1)
DEVICE NAME
PACKAGE
BODY SIZE (NOM)
TPS62090
TPS62091
QFN (16)
TPS62092
3.00 mm x 3.00 mm
TPS62093
(1)
Typical Application Schematic
11
C1
10 mF
10
C3
10 nF
SW
PVIN
SW
AVIN
VOS
13 EN
7
8
C4
10 nF
PVIN
9 SS
2
Vout
1.8 V/3 A
R3
500 kΩ
PG 4
FREQ
3
Power Good
90
85
80
75
70
65
AGND 6
60
PGND PGND
14
95
C2
22 mF
16
FB 5
CP
CN
1
Efficiency (%)
12
100
L1
470 nH
TPS62093
Vin
2.5 V to 6 V
For all available packages, see the orderable addendum at
the end of the data sheet.
sp
sp
Efficiency vs Output Current
55
15
Copyright © 2016, Texas Instruments Incorporated
50
100m
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.8 V
L = 0.4 µH
f = 2.8 MHz
1
10
100
I load (mA)
1k
10k
G004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62090, TPS62091, TPS62092, TPS62093
SLVSAW2C – MARCH 2012 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Applications ................................................ 13
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guideline ................................................... 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2014) to Revision C
Page
•
Changed Feature bullet text From "Two Level...." To "Hiccup..."; and, deleted "Wide Output Capacitance Selection"
bullet ....................................................................................................................................................................................... 1
•
Added CN and CP pin absolute maximum ratings ................................................................................................................. 4
•
Moved Storage Temp spec to the "Absolute Maximum Ratings" table ................................................................................. 4
•
Added Feedback voltage accuracy at TJ = 25°C.................................................................................................................... 5
•
Changed Legend in Figure 2 and Figure 4 to show correct voltages ................................................................................... 6
•
Updated Voltage Tracking (SS) section ................................................................................................................................. 9
•
Added Charge Pump (CP, CN) section ............................................................................................................................... 11
•
Updated PCB layout example .............................................................................................................................................. 19
•
Added Community Resources section ................................................................................................................................. 20
Changes from Revision A (March 2012) to Revision B
Page
•
Changed the data sheet to meet the new TI standard Format ............................................................................................. 1
•
Changed the Typical Characteristics. Moved graphs to the Application and Implementation section................................... 6
•
Added the Layout section .................................................................................................................................................... 19
Changes from Original (March 2012) to Revision A
Page
•
Changed the FUNCTIONAL BLOCK DIAGRAM .................................................................................................................... 8
•
Changed R1 and R2 values in Figure 9 ............................................................................................................................... 13
2
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SLVSAW2C – MARCH 2012 – REVISED OCTOBER 2016
5 Device Comparison Table
DEVICE NUMBER
OUTPUT VOLTAGE
TPS62090RGT
Adjustable
TPS62091RGT
3.3 V
TPS62092RGT
2.5 V
TPS62093RGT
1.8 V
6 Pin Configuration and Functions
PG
4
EN
14
13
12
11
Exposed
Thermal Pad*
10
5
6
7
8
CN
3
PGND
FREQ
15
CP
2
PGND
SW
16
AGND
1
FB
SW
VOS
RGT Package
16-Pin QFN
Top View
9
PVIN
PVIN
AVIN
SS
NOTE: *The exposed thermal pad is connected to AGND.
Pin Functions
PIN
NO.
NAME
1, 2
SW
I/O
I/O
DESCRIPTION
Switch pin of the power stage.
3
FREQ
I
This pin selects the switching frequency of the device. FREQ = Low sets the typical switching frequency to 2.8 MHz. FREQ =
High sets the typical switching frequency to 1.4 MHz. This pin has an active pull down resistor of typically 400 kΩ and can be
left floating for 2.8 MHz operation.
4
PG
O
Power good open drain output. This pin is high impedance if the output voltage is within regulation. This pin is pulled low if
the output is below its nominal value. The pull up resistor can not be connected to any voltage higher than the input voltage of
the device.
5
FB
I
Feedback pin of the device.
For the adjustable version, connect a resistor divider to set the output voltage.
For the fixed output voltage versions this pin may be connected to GND for improved thermal performance and has a pull
down resistor of typically 400 kΩ, which is active when EN is low.
6
AGND
7
CP
I/O
Internal charge pump flying capacitor. Connect a 10 nF capacitor between CP and CN.
8
CN
I/O
Internal charge pump flying capacitor. Connect a 10 nF capacitor between CP and CN.
9
SS
I
Softstart control pin. A capacitor is connected to this pin and sets the softstart time. Leaving this pin floating sets the minimum
start-up time.
10
AVIN
I
Bias supply input voltage pin.
11,12
PVIN
I
Power supply input voltage pin.
EN
I
Device enable. To enable the device this pin needs to be pulled high. Pulling this pin low disables the device. This pin has a
pull down resistor of typically 400 kΩ, which is active when EN is low.
13
14,15
16
Analog ground.
PGND
VOS
Exposed Thermal Pad
Power ground connection.
I
Output voltage sense pin. This pin needs to be connected to the output voltage.
–
The exposed thermal pad is connected to AGND. It must be soldered for mechanical reliability.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
MAX
UNIT
PVIN, AVIN, FB, SS, EN, FREQ, VOS
–0.3
7
SW, PG
–0.3
VIN + 0.3
CN, CP
-0.3
VIN + 7.0
1
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Voltage range (2)
Power Good sink current
(1)
(2)
PG
V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
7.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001, all pins
VALUE
UNIT
±2000
V
±500
V
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1)
MIN
TYP
MAX
UNIT
VIN
Input voltage range VIN
2.5
6
V
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
See the application section for further information
7.4 Thermal Information
TPS6209x
THERMAL METRIC (1)
QFN (16 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance
47
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
60
°C/W
RθJB
Junction-to-board thermal resistance
20
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
20
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
5.3
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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SLVSAW2C – MARCH 2012 – REVISED OCTOBER 2016
7.5 Electrical Characteristics
VIN = 3.6 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
IQIN
Quiescent current
Not switching, FB = FB +5%, into PVIN and AVIN
20
Isd
Shutdown current
Into PVIN and AVIN
0.6
5
Undervoltage lockout threshold
VIN falling
2.2
2.3
UVLO
2.5
2.1
Undervoltage lockout hysteresis
Thermal shutdown
Temperature rising
Thermal shutdown hysteresis
6
V
µA
µA
V
200
mV
150
ºC
20
ºC
0.65
V
Control SIGNALS EN, FREQ
VH
High level input voltage
VIN = 2.5 V to 6 V
1
VL
Low level input voltage
VIN = 2.5 V to 6 V
0.6
0.4
V
Ilkg
Input leakage current
EN, FREQ = GND or VIN
10
100
nA
RPD
Pull down resistance
400
kΩ
Softstart
ISS
Softstart current
6.3
7.5
8.7
Output voltage rising
93%
95%
97%
Output voltage falling
88%
90%
92%
µA
POWER GOOD
Vth
Power good threshold
VL
Low level voltage
IPG
PG sinking current
Ilkg
Leakage current
I(sink) = 1 mA
0.4
V
1
mA
100
nA
VPG = 3.6 V
10
High side FET on-resistance
ISW = 500 mA
50
mΩ
Low side FET on-resistance
ISW = 500 mA
40
mΩ
POWER SWITCH
RDS(on)
ILIM
High side FET switch current
limit
fs
Switching frequency
3.7
4.6
5.5
A
FREQ = GND, IOUT = 3 A
2.8
MHz
FREQ = VIN, IOUT = 3 A
1.4
MHz
OUTPUT
Vs
Output voltage range
Rod
Output discharge resistor
0.8
VFB
Feedback regulation voltage
EN = GND, VOUT = 1.8 V
VIN
V
200
Ω
0.8
V
VIN ≥ VOUT + 1 V, TPS62090 adjustable output version
IOUT = 1 A, PWM mode, TJ = 25°C
Feedback voltage
accuracy (1) (2) (3)
VFB
IFB
Feedback input bias current
-1%
+1%
IOUT = 1 A, PWM mode
-1.4%
+1.4%
IOUT = 0 mA, FREQ = 2.8 MHz, VOUT ≥ 0.8 V, PFM mode
-1.4%
+3%
IOUT = 0 mA, FREQ = 1.4 MHz, VOUT ≥ 1.2 V, PFM mode
-1.4%
+3%
IOUT = 0 mA, FREQ = 1.4 MHz, VOUT < 1.2V, PFM mode
-1.4%
VFB = 0.8 V, TPS62090 adjustable output version
+3.7%
10
100
nA
VIN ≥ VOUT + 1 V, fixed output voltage
VOUT
(1)
(2)
(3)
Output voltage accuracy
(2) (3)
IOUT = 1 A, PWM mode
-1.4%
IOUT = 0 mA, FREQ = High and Low, PFM mode
-1.4%
+1.4%
+2.5%
Line regulation
VOUT = 1.8 V, PWM operation
0.016
%/V
Load regulation
VOUT = 1.8 V, PWM operation
0.04
%/A
For output voltages < 1.2 V, use a 2 x 22 µF output capacitance to achieve +3% output voltage accuracy.
Conditions: f = 2.8 MHz, L = 0.47 µH, COUT = 22 µF or f = 1.4 MHz, L = 1 µH, COUT = 22 µF.
For more information, see the Power Save Mode Operation section of this data sheet.
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7.6 Typical Characteristics
1600
70
1400
60
Frequency (kHz)
Resistance (m:)
1200
50
40
30
20
1000
800
600
400
TA85ƒC
= 85oC
TA-40ƒC
= -40oC
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
0
0
6.5
C00
3500
1.75
3000
Frequency (kHz)
Frequency (MHz)
1.5
1
0.75
0
2
2.5
3
3.5
4
4.5
Voltage (V)
5
5.5
6
2.4
2.8
3.2
G009
L = 1 µH
f = 1.4 MHz
2500
2000
1500
1000
VOUT = 1.8 V
L = 1 µH
f = 1.4 MHz
IOUT = 1 A
0.25
1.2
1.6
2
Load Current (A)
Figure 2. Switching Frequency vs Load Current
2
1.25
400m 800m
VOUT = 1.8 V
Figure 1. High Side FET On-Resistance vs Input Voltage
0.5
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
200
TA25ƒC
= 25oC
10
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
500
0
6.5
0
400m 800m
1.2
1.6
2
Load Current (A)
G010
VOUT = 1.8 V
Figure 3. Switching Frequency vs Input Voltage
2.4
2.8
3.2
G026
L = 0.4 µH
f = 2.8 MHz
Figure 4. Frequency vs Load Current
3500
25
3000
Current (µA)
Frequency (kHz)
20
2500
2000
1500
1000
VOUT = 1.8 V
L = 0.4 µH
f = 2.8 MHz
IOUT = 1 A
500
0
2
2.5
3
3.5
4
4.5
5
Input Voltage (V)
5.5
Figure 5. Frequency vs Input Voltage
6
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6
15
10
VOUT = 1.8 V
L = 1 µH
f = 1.4 MHz
5
6.5
0
2
2.5
3
3.5
G026
TA = 85 °C
TA = 25 °C
TA = −40 °C
4
4.5
Voltage (V)
5
5.5
6
6.5
G011
Figure 6. Quiescent Current vs Input Voltage
Copyright © 2012–2016, Texas Instruments Incorporated
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SLVSAW2C – MARCH 2012 – REVISED OCTOBER 2016
8 Detailed Description
8.1 Overview
The TPS6209x synchronous switched mode converters are based on DCS-Control™ (direct control with
seamless transition into power save mode). This is an advanced regulation topology that combines the
advantages of hysteretic and voltage mode control.
The DCS-Control™ topology operates in pulse width modulation (PWM) mode for medium to heavy load
conditions and in power save mode at light load currents. In PWM, the converter operates with its nominal
switching frequency of 2.8 MHz/1.4 MHz having a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters power save mode, reducing the switching frequency and
minimizing the IC quiescent current to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes (PWM and PFM) using a single building block having a seamless transition from
PWM to power save mode without effects on the output voltage. Fixed output voltage versions provide smallest
solution size combined with lowest quiescent current. The TPS6209x family offers excellent DC voltage
regulation and load transient regulation, combined with low output voltage ripple, minimizing interference with RF
circuits.
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8.2 Functional Block Diagram
PG
CP
PVIN
CN
Charge Pump
for
Gate driver
VFB
Hiccup
current limit
#32 counter
VREF
High Side
Current
Sense
Bandgap
Undervoltage
Lockout
Thermal shutdown
AVIN
PVIN
EN
M1
400kΩ(2)
SW
MOSFET Driver
Anti Shoot Through
Converter Control
Logic
AGND
SW
High =1.4 MHz
Low = 2.8 MHz
FREQ
M2
400kΩ(2)
PGND
PGND
Comparator
ramp
Timer
ton
Direct Control
and
Compensation
VOS
R1
Error Amplifier
(1)
Adjustable
only
Vref
0.8V
R2
(1)
FB
(1)
R3
400kΩ
Vin
DCS - Control™
200Ω
Iss
Voltage clamp
Vref
SS
÷1.56
EN
Output voltage
discharge
logic
M3
Copyright © 2016, Texas Instruments Incorporated
(1)
R1, R2, R3 are implemented in the fixed output voltage version only.
(2)
The resistors are disconnected when the pins are high.
8.3 Feature Description
8.3.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low with a shutdown current of typically 0.6 μA. In shutdown mode, the internal power switches as well as
the entire control circuitry are turned off. An internal resistor of 200 Ω discharges the output through the VOS pin
smoothly. An internal pull-down resistor of 400 kΩ is connected to the EN pin when the EN pin is low. The
pulldown resistor is disconnected when the EN pin is high.
8
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Feature Description (continued)
8.3.2 Softstart (SS) and Hiccup Current Limit During Startup
To minimize inrush current during start up, the device has an adjustable softstart depending on the capacitor
value connected to the SS pin. The device charges the softstart capacitor with a constant current of typically 7.5
µA. The feedback voltage follows this voltage with a fraction of 1.56 until the internal reference voltage of 0.8 V is
reached. The softstart operation is completed once the voltage at the softstart capacitor has reached typically
1.25 V. The soft-start time can be calculated using Equation 1. The larger the softstart capacitor the longer the
softstart time. The relation between softstart voltage and feedback voltage can be estimated using Equation 2.
1.25V
tSS = CSS x
7.5μA
(1)
VFB =
VSS
1.56
(2)
During startup, the switch current limit is reduced to 1/3 (~1.5 A) of its typical current limit of 4.6 A. Once the
output voltage exceeds typically 0.6 V, the current limit is released to its nominal value. The device provides a
reduced load current of ~1.5 A when the output voltage is below typically 0.6 V. Due to this, a small or no
softstart time may trigger the short circuit protection during startup especially for larger output capacitors. This is
avoided by using a larger softstart capacitance to extend the softstart time. See Short Circuit Protection (HiccupMode) for details of the reduced current limit during startup. Leaving the softstart pin floating sets the minimum
start-up time (around 50µs).
8.3.3 Voltage Tracking (SS)
The SS pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in Figure 7. The internal reference voltage follows the voltage at the SS pin with a fraction of 1.56
until the internal reference voltage of 0.8 V is reached. The device achieves ratiometric or coincidental
(simultaneous) output tracking, as shown in Figure 8.
VOUT1
VOUT2
R3
R1
SS
FB
R4
R2
GND
GND
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Figure 7. Output Voltage Tracking
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Feature Description (continued)
Voltage
Voltage
1+
VOUT1
VOUT1
VOUT2
VOUT2
R3 æ
R1 ö
1
< ç1 +
÷´
R 4 è R 2 ø 1.56
1+
R3 æ
R1 ö
1
= ç1 +
÷´
R 4 è R 2 ø 1.56
t
t
a) Ratiometric Tracking
b) Coincidental Tracking
Figure 8. Voltage Tracking Options
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5 μA soft startup current
into account. 1 kΩ or smaller is a sufficient value for R2.
For decreasing the SS pin voltage, the device doesn't sink current from the output when the device is in power
save mode. So the resulting decreases of the output voltage may be slower than the SS pin voltage if the load is
light. When driving the SS pin with an external voltage, do not exceed the voltage rating of the SS pin which is 7
V.
8.3.4 Short Circuit Protection (Hiccup-Mode)
The device is protected against hard short circuits to GND and over-current events. This is implemented by a two
level short circuit protection. During start-up and when the output is shorted to GND the switch current limit is
reduced to 1/3 of its typical current limit of 4.6 A. Once the output voltage exceeds typically 0.6 V the current limit
is released to its nominal value. The full current limit is implemented as a hiccup current limit. Once the internal
current limit is triggered 32 times the device stops switching and starts a new start-up sequence after a typical
delay time of 66 µs passed by. The device will go through these cycles until the high current condition is
released.
8.3.5 Output Discharge Function
To make sure the device starts up under defined conditions, the output gets discharged via the VOS pin with a
typical discharge resistor of 200 Ω whenever the device shuts down. This happens when the device is disabled
or if thermal shutdown, undervoltage lockout or short circuit hiccup-mode is triggered.
8.3.6 Power Good Output (PG)
The power good output is low when the output voltage is below its nominal value. The power good becomes high
impedance once the output is within 5% of regulation. The PG pin is an open drain output and is specified to
typically sink up to 1 mA. This output requires a pull-up resistor to be monitored properly. The pull-up resistor
cannot be connected to any voltage higher than the input voltage of the device. The PG output is low when the
device is disabled, in thermal shutdown or UVLO. The PG output can be left floating if unused.
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Feature Description (continued)
8.3.7 Frequency Set Pin (FREQ)
The FREQ pin is a digital logic input which sets the nominal switching frequency. Pulling this pin to GND sets the
nominal switching frequency to 2.8 MHz and pulling this pin high sets the nominal switching frequency to 1.4
MHz. Since this pin changes the switching frequency it also changes the on-time during pulse frequency
modulation (PFM) mode. At 1.4 MHz the on-time is twice the on-time as operating at 2.8 MHz. This pin has an
active pull-down resistor of typically 400 kΩ. For applications where efficiency is of highest importance, a lower
switching frequency should be selected. A higher switching frequency allows the use of smaller external
components, faster load transient response and lower output voltage ripple when using same L-C values.
8.3.8 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts
down the device at input voltages lower than typically 2.2 V with a 200 mV hysteresis.
8.3.9 Thermal Shutdown
The device goes into thermal shutdown once the junction temperature exceeds typically 150°C with a 20°C
hysteresis.
8.3.10 Charge Pump (CP, CN)
The CP and CN pins must attach to an external 10 nF capacitor to complete a charge pump for the gate driver.
This capacitor must be rated for the input voltage. It is not recommended to connect any other circuits to the CP
or CN pins.
8.4 Device Functional Modes
8.4.1 Pulse Width Modulation Operation
At medium to heavy load currents, the device operates with pulse width modulation (PWM) at a nominal
switching frequency of 2.8 MHz or 1.4 MHz depending on the setting of the FREQ pin. As the load current
decreases, the converter enters the power save mode operation reducing its switching frequency. The device
enters power save mode at the boundary to discontinuous conduction mode (DCM).
8.4.2 Power Save Mode Operation
As the load current decreases, the converter enters power save mode operation. During power save mode, the
converter operates with reduced switching frequency maintaining high efficiency. The power save mode is based
on a fixed on-time architecture following Equation 3. When operating at 1.4 MHz the on-time is twice as long as
the on-time for 2.8 MHz operation. This results in larger output voltage ripple, as shown in Figure 19 and
Figure 20, and slightly higher output voltage at no load, as shown in Figure 16 and Figure 17. To have the same
output voltage ripple at 1.4 MHz during PFM mode, either the output capacitor or the inductor value needs to be
increased. As an example, operating at 2.8 MHz using 0.47 µH inductor gives the same output voltage ripple as
operating with 1.4 MHz using 1 µH inductor.
V
OUT × 360ns
V
IN
V
OUT
ton1.4MHz =
× 360ns × 2
V
IN
2×I
OUT
f =
æ
ö V -V
V
V
OUT ÷ x IN
OUT
ton2 ç 1 + IN
ç
÷
V
L
OUT
è
ø
ton2.8MHz =
(3)
In power save mode the output voltage rises slightly above the nominal output voltage in PWM mode, as shown
in Figure 16 and Figure 17. This effect can be reduced by increasing the output capacitance or the inductor
value. This effect can also be reduced by programming the output voltage of the TPS62090 lower than the target
value. As an example, if the target output voltage is 3.3 V, then the TPS62090 can be programmed to 3.3 V –
0.8%. As a result the output voltage accuracy is now -2.2% to +2.2% instead of -1.4% to 3%. The output voltage
accuracy in PFM operation is reflected in the electrical specification table and given for a 22 µF output capacitor.
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Device Functional Modes (continued)
8.4.3 Low Dropout Operation (100% Duty Cycle)
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high
side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve
longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage
where the output voltage falls below its nominal regulation value is given by:
VIN(min) = VOUT + IOUT x ( RDS(on) + RL )
(4)
Where:
RDS(on) = High side FET on-resistance
RL = DC resistance of the inductor
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6209x 3 A family of devices, are high frequency synchronous step down converters optimized for small
solution size, high efficiency and suitable for battery powered applications.
9.2 Typical Applications
TPS62090
Vin
2.5 V to 6 V
12
11
C1
10 mF
10
C3
10 nF
SW
PVIN
SW
AVIN
VOS
7
1
Vout
1.2 V/3 A
R1
75 kΩ
2
C2
22 mF
16
R2
150 kΩ
FB 5
13 EN
8
C4
10 nF
PVIN
L1
470 nH
R3
500 kΩ
PG 4
CP
FREQ
CN
Power Good
3
AGND 6
9 SS
PGND PGND
14
15
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Figure 9. 1.2 V Adjustable Version Operating at 2.8 MHz
9.2.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions.
The design can be optimized for highest efficiency or smallest solution size and lowest output voltage ripple. For
highest efficiency set the device switching frequency to 1.4 MHz (FREQ = High) and select the output filter
components according to Table 3. For smallest solution size and lowest output voltage ripple set the device
switching frequency to 2.8 MHz (FREQ = Low) and select the output filter components according to Table 2. For
the fixed output voltage option the feedback pin needs to be connected to GND.
Table 1 shows the list of components for the Application Curves.
Table 1. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
TPS62090
High efficiency step down converter
Texas Instruments
L1
Inductor: 1uH, 0.47uH, 0.4uH
Coilcraft XFL4020-102, TOKO DEF252012C-R47, Coilcraft
XAL4020-401
C1
Ceramic capacitor: 10uF, 22uF
(6.3V, X5R, 0603), (6.3V, X5R, 0805)
C2
Ceramic capacitor: 22uF
(6.3V, X5R, 0805)
C3, C4
Ceramic capacitor
Standard
R1, R2, R3
Resistor
Standard
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9.2.2 Detailed Design Procedure
The first step is the selection of the output filter components. To simplify this process, Table 2 and Table 3
outline possible inductor and capacitor value combinations. Checked cells represent combinations that are
proven for stability by simulation and lab. Further combinations should be checked for each individual application.
Table 2. Output Filter Selection (2.8 MHz Operation, FREQ = GND)
INDUCTOR VALUE [µH] (1)
OUTPUT CAPACITOR VALUE [µF] (2)
10
22
47
100
150
(3)
√
√
√
√
√
√
√
√
0.47
√
1.0
2.2
3.3
(1)
(2)
(3)
Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and
-30%.
Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by
+20% and -50%.
Typical application configuration. Other check mark indicates alternative filter combinations
Table 3. Output Filter Selection (1.4 MHz Operation, FREQ = VIN)
INDUCTOR VALUE [µH] (1)
OUTPUT CAPACITOR VALUE [µF] (2)
10
22
47
100
150
√
√
√
√
1.0
√
√ (3)
√
√
√
2.2
√
√
√
√
√
0.47
3.3
(1)
(2)
(3)
Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and
–30%.
Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by
+20% and –50%.
Typical application configuration. Other check mark indicates alternative filter combinations
9.2.2.1 Inductor Selection
The inductor selection is affected by several parameter like inductor ripple current, output voltage ripple,
transition point into power save mode, and efficiency. See Table 4 for typical inductors.
Table 4. Inductor Selection
(1)
INDUCTOR VALUE
COMPONENT SUPPLIER (1)
SIZE (LxWxH mm)
Isat/DCR
0.6 µH
Coilcraft XAL4012-601
4 x 4 x 2.1
7.1 A/9.5 mΩ
1 µH
Coilcraft XAL4020-102
4 x 4 x 2.1
5.9 A/13.2 mΩ
1 µH
Coilcraft XFL4020-102
4 x 4 x 2.1
5.1 A/10.8 mΩ
0.47 µH
TOKO DFE252012 R47
2.5 x 2 x 1.2
3.7 A/39 mΩ
1 µH
TOKO DFE252012 1R0
2.5 x 2 x 1.2
3.0 A/59 mΩ
0.68 µH
TOKO DFE322512 R68
3.2 x 2.5 x 1.2
3.5 A/37 mΩ
1 µH
TOKO DFE322512 1R0
3.2 x 2.5 x 1.2
3.1 A/45 mΩ
See Third-Party Products Disclaimer
In addition, the inductor has to be rated for the appropriate saturation current and DC resistance (DCR).
Equation 6 calculates the maximum inductor current under static load conditions. The formula takes the
converter efficiency into account. The converter efficiency can be taken from the data sheet graph`s or 80% can
be used as a conservative approach. The calculation must be done for the maximum input voltage where the
peak switch current is highest.
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D IL
=
æ
VO U T
VO U T
x çç 1 h
V IN x h
è
f x L
ö
÷÷
ø
(5)
DI
I
=I
+ L
PEAK
OUT
2
where:
•
•
•
ƒ = Converter switching frequency (typical 2.8 MHz or 1.4 MHz)
L = Selected inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.80 as an conservative
assumption)
(6)
Note: The calculation must be done for the maximum input voltage of the application
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current. A margin of 20% needs to be added to cover for load transients during operation.
9.2.2.2
Input and Output Capacitor Selection
For best output and input voltage filtering, low ESR (X5R or X7R) ceramic capacitors are recommended. The
input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail
for the device. A 10-μF or larger input capacitor is recommended when FREQ = Low and a 22-uF or larger when
FREQ = High.
The output capacitor value can range from 10 μF up to 150 μF and beyond. Load transient testing and
measuring the bode plot are good ways to verify stability with larger capacitor values. The recommended typical
output capacitor value is 22 μF (nominal) and can vary over a wide range as outline in the output filter selection
table. For output voltages above 1.8 V, noise can cause duty cycle jitter. This does not degrade device
performance. Using an output capacitor of 2 x 22 μF (nominal) for output voltages >1.8 V avoids duty cycle jitter.
Ceramic capacitor have a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose
the right capacitor carefully in combination with considering its package size and voltage rating.
9.2.2.3 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations:
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
= 0.8 V ´ ç 1 +
÷
R2 ø
R2 ÷ø
è
è
(7)
V
0.8 V
R2 = FB =
» 160 kΩ
IFB
5 μA
(8)
æV
ö
æV
ö
R1 = R2 ´ ç OUT - 1÷ = R2 ´ ç OUT - 1÷
è 0.8V
ø
è VFB
ø
(9)
When sizing R2, in order to achieve low quiescent current and acceptable noise sensitivity, use a minimum of 5
µA for the feedback current IFB. Larger currents through R2 improve noise sensitivity and output voltage
accuracy. Lowest current consumption and best output voltage accuracy can be achieved with the fixed output
voltage versions. For the fixed output voltage versions, the FB pin can be left floating or connected to GND to
improve the thermal performance. A feed forward capacitor is not required for proper operation.
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100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
9.2.2.4 Application Curves
80
75
70
65
60
55
50
100m
80
75
70
65
VOUT = 3.3 V
L = 1 µH
f = 1.4 MHz
1
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
10
100
I load (mA)
1k
60
55
50
100m
10k
95
90
90
85
85
Efficiency (%)
Efficiency (%)
100
95
80
75
70
55
50
100m
1
10
100
I load (mA)
1k
60
55
50
100m
10k
90
85
85
Efficiency (%)
Efficiency (%)
90
80
75
70
1
1k
Figure 14. Efficiency vs Load Current
16
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10
100
I load (mA)
1k
10k
G004
80
75
70
65
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
10
100
I load (mA)
1
Figure 13. Efficiency vs Load Current
95
50
100m
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.8 V
L = 0.4 µH
f = 2.8 MHz
G003
100
55
G001
70
95
VOUT = 1.05 V
L = 1.0 µH
f = 1.4 MHz
10k
75
100
60
1k
80
Figure 12. Efficiency vs Load Current
65
10
100
I load (mA)
65
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
VOUT = 1.8 V
L = 1 µH
f = 1.4 MHz
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
Figure 11. Efficiency vs Load Current
100
60
1
G002
Figure 10. Efficiency vs Load Current
65
VOUT = 3.3 V
L = 1 µH
f = 2.8 MHz
60
55
10k
G005
50
100m
VOUT = 1.05 V
L = 0.4 µH
f = 2.8 MHz
1
10
100
I load (mA)
VIN = 2.7 V
VIN = 3.7 V
VIN = 4.2 V
VIN = 5 V
1k
10k
G006
Figure 15. Efficiency vs Load Current
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1.83
1.82
VIN = 5.0 V
VIN = 4.2 V
VIN = 3.7 V
1.825
Output Voltage (V)
Output Voltage (V)
1.825
1.83
VOUT = 1.8 V
L = 1 µH
f = 1.4 MHz
1.815
1.81
1.805
1.8
1.795
1.82
1.815
1.81
1.805
1.8
1
10
100
I load (mA)
1k
10k
1.79
100m
G007
Figure 16. Output Voltage vs Load Current
Vsw
2 V/div
Vo
20 mV/div
Vo
20 mV/div
Vin = 3.7 V
Vo=1.8 V/3 A
f = 1.4 MHz, L = 1 µH
400 ns/div
1
10
100
I load (mA)
1k
10k
G008
Figure 17. Output Voltage vs Load Current
Vsw
2 V/div
Iinductor
500 mA/div
Vin = 3.7 V
Vo = 1.8 V/100 mA
f = 1.4 MHz, L = 1 µH
1 µs/div
G012
Figure 18. PWM Operation
G013
Figure 19. PFM Operation
Vo
20 mV/div
Vsw
2 V/div
Io
1 A/div
Vo
20 mV/div
Iinductor
500 mA/div
VIN = 5.0 V
VIN = 4.2 V
VIN = 3.7 V
1.795
1.79
100m
Iinductor
1 A/div
VOUT = 1.8 V
L = 0.4 µH
f = 2.8 MHz
Vin = 3.7 V
Vo = 1.8 V/100 mA
f = 2.8 MHz, L = 0.47 µH
1 µs/div
Figure 20. PFM Operation
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Iinductor
500 mA/div
Vin = 3.7 V
Vo = 1.8 V
f = 1.4 MHz, L = 1 µH
200 µs/div
G014
G015
Figure 21. Load Sweep
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Vo
20 mV/div
VEN
2 V/div
Vo
1 V/div
Io
2 A/div
Iinductor
500 mA/div
Vin = 3.7 V
Vo = 1.8 V
f = 2.8 MHz, L = 1 µH
Iinductor
500 mA/div
200 µs/div
G016
VO = 1.8 V /
600mA
400 µs/div
f = 2.8 MHz / L =
1µH
G017
CSS = 10 nF
Figure 22. Load Sweep
Figure 23. Start-Up
Vin = 3.7 V
Vo = 1.8 V
f = 1.4 MHz, L = 1 µH
Vo
1 V/div
VEN
2 V/div
Vo
1 V/div
Io
2 A/div
Iinductor
500 mA/div
Iinductor
1 A/div
VO = 1.8 V / No
Load
2 ms/div
f = 1.4 MHz / L =
1µH
40 µs/div
G018
Figure 25. Hiccup Short Circuit Protection
Figure 24. Shutdown
Vo
1 V/div
Vo
50 mV/div
Io
2 A/div
Vin = 3.7 V
Vo = 1.8 V
f = 1.4 MHz, L = 1 µH
Iinductor
1 A/div
Iinductor
1 A/div
400 µs/div
Figure 26. Hiccup Short Circuit Protection
18
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Vin = 3.7 V
Vo = 1.8 V, 0.3 A to 2.5 A
f = 1.4 MHz, L = 1 µH
Co = 22 µF
40 µs/div
G020
G022
Figure 27. Load Transient Response
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Vo
50 mV/div
Io
1 V/div
Vin = 3.7 V
Vo = 1.8 V, 20 mA to 1 A
f = 1.4 MHz, L = 1 µH
Co = 22 µF
Iinductor
500 A/div
100 µs/div
G023
Figure 28. Load Transient Response
10 Power Supply Recommendations
The power supply to the TPS62090 needs to have a current rating according to the supply voltage, output
voltage and output current of the TPS62090.
11 Layout
11.1 Layout Guideline
•
•
•
•
•
It is recommended to place the input capacitor as close as possible to the IC pins PVIN and PGND.
The VOS connection is noise sensitive and needs to be routed as short and directly to the output pin of the
inductor.
The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a
single joint connection at the exposed thermal pad of the package. This minimizes switch node jitter.
The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of
switching waveforms into other traces and circuits.
Refer to Figure 29 and the evaluation module User Guide (SLVU670) for an example of component
placement, routing and thermal design.
R2x1
R1
AGND
R2
L1x1
11.2 Layout Example
L1
VOUT
C2
SW
PG
SW
FREQ
C5
EN
C4
PVIN
CN
SS
PGND
AVIN
VOS
PGND
CP
PVIN
FB
AGND
VIN
GND
C1
Figure 29. TPS6209x Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62090
Click here
Click here
Click here
Click here
Click here
TPS62091
Click here
Click here
Click here
Click here
Click here
TPS62092
Click here
Click here
Click here
Click here
Click here
TPS62093
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLVSAW2C – MARCH 2012 – REVISED OCTOBER 2016
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS62090 TPS62091 TPS62092 TPS62093
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62090RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBW
TPS62090RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBW
TPS62091RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBX
TPS62091RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBX
TPS62092RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBY
TPS62092RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBY
TPS62093RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBZ
TPS62093RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBZ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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