TPS62150, TPS62150A, TPS62151, TPS62152, TPS62153
SLVSAL5E – NOVEMBER 2011 – REVISED OCTOBER 2021
TPS6215x 3-V to 17-V, 1-A Step-Down Converter in 3-mm × 3-mm QFN Package
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3 Description
DCS-Control™ topology
Input voltage range: 3 V to 17 V
Up to 1-A output current
Adjustable output voltage from 0.9 V to 6 V
Pin-selectable output voltage (nominal, +5%)
Programmable soft start and tracking
Seamless power-save mode transition
Quiescent current of 17 µA (typ.)
Selectable operating frequency
Power-good output
100% duty-cycle mode
Short-circuit protection
Overtemperature protection
Pin-to-pin compatible with the TPS62130 and
TPS62140
Available in a 3-mm × 3-mm, VQFN-16 package
Use the TPS82150 module for faster designs
The TPS6215x family is an easy-to-use synchronous
step down dc-dc converter optimized for applications
with high power density. A high switching frequency
of typically 2.5 MHz allows the use of small inductors
and provides fast transient response as well as high
output-voltage accuracy by the use of DCS-Control
topology.
With their wide operating input-voltage range of 3 V
to 17 V, the devices are ideally suited for systems
powered from either Li-Ion or other batteries as well
as from 12-V intermediate power rails. The devices
support up to 1-A continuous output current at output
voltages between 0.9 V and 6 V (in 100% duty-cycle
mode). The soft-start pin controls the output-voltage
start-up ramp, which allows operation as either a
standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
enable (EN) and open-drain power-good (PG) pins.
2 Applications
•
•
•
•
•
•
•
•
Standard 12-V rail supplies
POL supply from single or multiple Li-ion battery
Solid-state drives
Embedded systems
LDO replacement
Mobile PCs, tablets, modems, cameras
Server, microserver
Data terminal, point of sales (ePOS)
In power-save mode, the devices draw quiescent
current of about 17 μA from VIN. Power-save-mode,
entered automatically and seamlessly if the load is
small, maintains high efficiency over the entire load
range. In shutdown mode, the device turns off and
current consumption is less than 2 μA.
The device, available in adjustable- and fixed-outputvoltage versions, comes in a 16-pin VQFN package
measuring 3 × 3 mm (RGT).
Device Information
PACKAGE(1)
PART NUMBER
TPS6215X
(1)
SW
100
AVIN
VOS
EN
10 F
PG
TPS62151
SS/TR
3.3 nF
DEF
FSW
FB
AGND
PGND
Typical Application Schematic
1.8 V / 1 A
90
100 k
22 uF
Efficiency (%)
PVIN
BODY SIZE (NOM)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2.2 H
(3 .. 17) V
VQFN (16)
80
VIN=5V
VIN=12V
VIN=17V
70
60
50
VOUT=3.3V
fsw=1.25MHz
40
0.0
0.2
0.4
0.6
Output Current (A)
0.8
1.0
G001
Efficiency vs Output Current
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62150, TPS62150A, TPS62151, TPS62152, TPS62153
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SLVSAL5E – NOVEMBER 2011 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings(1) .................................... 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 6
8 Detailed Description........................................................7
8.1 Overview..................................................................... 7
8.2 Functional Block Diagrams......................................... 7
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
9.3 System Examples..................................................... 24
10 Power Supply Recommendations..............................27
11 Layout........................................................................... 28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................30
12.1 Device Support....................................................... 30
12.2 Documentation Support.......................................... 30
12.3 Receiving Notification of Documentation Updates..30
12.4 Support Resources................................................. 30
12.5 Trademarks............................................................. 30
12.6 Electrostatic Discharge Caution..............................30
12.7 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2016) to Revision E (October 2021)
Page
• Added link to TPS82150 product folder.............................................................................................................. 1
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
Changes from Revision C (November 2014) to Revision D (September 2016)
Page
• Added "Pin to Pin Compatible with TPS62130 and TPS62140" to Features list ............................................... 1
• Changed the TJ MAX value From: 125°C To: 150°C in the Absolute Maximum Rating .................................... 4
• Changed the Section 7.4 values ........................................................................................................................4
• Changed (TJ = –40°C to 85°C) To: (TJ = –40°C to 125°C) in the Section 7.5 conditions .................................. 5
• Added a test condition for IQ at TA = -40°C to +85°C in the Section 7.5 ...........................................................5
• Added Table 8-1 and Table 8-2 ..........................................................................................................................8
• Added indicators (C1, C3, and C5) for capacitances to Figure 9-1 ................................................................. 12
• Added Switching Frequency graphs for 1.0-V, 1.8-V, and 5.0-V applications (Figure 9-18 through Figure 9-25)
..........................................................................................................................................................................18
• Changed Layout Example ............................................................................................................................... 28
2
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5 Device Comparison Table
PART NUMBER
OUTPUT VOLTAGE
POWER GOOD LOGIC LEVEL (EN = LOW)
TPS62150
Adjustable
High Impedance
TPS62150A
Adjustable
Low
TPS62151
1.8 V
High Impedance
TPS62152
3.3 V
High Impedance
TPS62153
5.0 V
High Impedance
SW
3
PG
4
PGND
VOS
EN
13
Exposed
Thermal Pad
5
6
7
8
DEF
2
14
FSW
SW
15
AGND
1
16
FB
SW
PGND
6 Pin Configuration and Functions
12
PVIN
11
PVIN
10
AVIN
9
SS/TR
Figure 6-1. 16-Pin VQFN With Thermal Pad RGT Package (Top View)
Table 6-1. Pin Functions
PIN(1)
I/O
DESCRIPTION
NO.
NAME
1,2,3
SW
O
Switch node, which is connected to the internal MOSFET switches. Connect the inductor between SW
and output capacitor.
4
PG
O
Output power good (high = VOUT ready, low = VOUT below nominal regulation); open drain (requires
pullup resistor)
5
FB
I
Voltage feedback of the adjustable version. Connect a resistive voltage divider to this pin. It is
recommended to connect FB to AGND on fixed output voltage versions for improved thermal
performance.
6
AGND
7
FSW
I
Switching Frequency Select (low is approximately 2.5 MHz, high is approximately 1.25 MHz(2) for typical
operation)(3)
8
DEF
I
Output Voltage Scaling (low = nominal, high = nominal + 5%)(3)
9
SS/TR
I
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference
rise time. It can be used for tracking and sequencing.
10
AVIN
I
Supply voltage for control circuitry. Connect to same source as PVIN.
11,12
PVIN
I
Supply voltage for power stage. Connect to same source as AVIN.
13
EN
I
Enable input (high = enabled, low = disabled)(3)
14
VOS
I
Output voltage sense pin and connection for the control loop circuitry
15,16
PGND
Power Ground. Must be connected directly to the exposed thermal pad and common ground plane.
Exposed
Thermal Pad
Must be connected to AGND (pin 6), PGND (pin 15,16), and common ground plane. See the Layout
Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability.
(1)
(2)
(3)
Analog Ground. Must be connected directly to the exposed thermal pad and common ground plane.
For more information about connecting pins, see Section 8 and Section 9.
Connect FSW to VOUT or PG in this case.
An internal pulldown resistor keeps logic level low, if pin is floating.
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7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating junction temperature range (unless otherwise noted)
Pin voltage(2)
Power-good sink current
Temperature
(1)
(2)
MIN
MAX
AVIN, PVIN
–0.3
20
UNIT
EN, SS/TR
–0.3
VIN + 0.3
SW
–0.3
VIN + 0.3
DEF, FSW, FB, PG, VOS
–0.3
V
7
PG
10
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
7.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±2000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
Supply Voltage, VIN (at AVIN and PVIN)
Operating junction temperature, TJ
NOM
MAX
UNIT
3
17
V
–40
125
°C
7.4 Thermal Information
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
ψJT
ψJB
RθJC(bot)
(1)
4
TPS6215x
RGT 16 PINS
UNIT
45
°C/W
Junction-to-case(top) thermal resistance
53.6
°C/W
Junction-to-board thermal resistance
17.4
°C/W
Junction-to-top characterization parameter
1.1
°C/W
Junction-to-board characterization parameter
17.4
°C/W
Junction-to-case(bottom) thermal resistance
4.5
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over operating junction temperature (TJ = –40°C to 125°C), typical values at VIN = 12 V and TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLY
Input voltage range(1)
VIN
3
IQ
Operating quiescent current
EN = High, IOUT = 0 mA,
device not switching
TA = –40°C to +85°C
ISD
Shutdown current(2)
EN = Low
VUVLO
Undervoltage lockout threshold
TA = –40°C to +85°C
Falling input voltage (PWM mode operation)
2.6
Hysteresis
30
17
25
1.5
25
1.5
4
2.7
2.8
200
Thermal shutdown temperature
TSD
17
17
µA
µA
V
mV
160
Thermal shutdown hysteresis
V
°C
20
CONTROL (EN, DEF, FSW, SS/TR, PG)
High level input threshold voltage (EN, DEF,
FSW)
VH
VL
Low level input threshold voltage (EN, DEF,
FSW)
ILKG
Input leakage current (EN, DEF, FSW)
VTH_PG
Power-good threshold voltage
VOL_PG
Power-good output low voltage
ILKG_PG Input leakage current (PG)
ISS/TR
0.9
EN = VIN or GND; DEF, FSW = VOUT or GND
0.65
V
0.45
0.3
V
0.01
1
µA
Rising (%VOUT)
92%
95%
98%
Falling (%VOUT)
87%
90%
94%
IPG = –2 mA
0.07
0.3
V
VPG = 1.8 V
1
400
nA
2.5
2.7
µA
VIN ≥ 6 V
90
170
VIN = 3 V
120
VIN ≥ 6 V
40
VIN = 3 V
50
SS/TR pin source current
2.3
POWER SWITCH
High-side MOSFET ON-resistance
rDS(on)
Low-side MOSFET ON-resistance
ILIMF
High-side MOSFET forward current limit(3)
VIN = 12 V, TA = 25°C
Input leakage current (FB)
TPS62150, VFB = 0.8 V
Output voltage range (TPS62150)
VIN ≥ VOUT
1.4
70
mΩ
mΩ
1.7
2.2
A
1
100
nA
6.0
V
OUTPUT
ILKG_FB
DEF (output voltage programming)
VOUT
Initial output voltage accuracy(4)
Load
regulation(5)
Line regulation(5)
(1)
(2)
(3)
(4)
(5)
0.9
DEF = 0 (GND)
VOUT
DEF = 1 (VOUT)
VOUT + 5%
PWM mode operation, VIN ≥ VOUT + 1 V
785.6
800
814.4
PWM mode operation, VIN ≥ VOUT + 1 V,
TA = –10°C to 85°C
788.0
800
812.8
Power Save Mode operation, COUT = 22 µF
781.6
800
822.4
mV
VIN = 12 V, VOUT = 3.3 V, PWM mode
operation
0.05
%/A
3 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 1 A,
PWM mode operation
0.02
%/V
The device is still functional down to undervoltage lockout (see parameter VUVLO).
Current into AVIN+PVIN pins
This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Section 8.4.4).
This is the accuracy provided at the FB pin for the adjustable VOUT version (line and load regulation effects are not included). For the
fixed voltage versions, the (internal) resistive divider is included.
Line and load regulation depend on external component selection and layout (see Figure 9-16 and Figure 9-17).
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7.6 Typical Characteristics
Figure 7-1. Quiescent Current
Figure 7-2. Shutdown Current
200
100
160
125°C
140
RDSon Low−Side (mW)
RDSon High−Side (mW)
180
85°C
120
25°C
100
80
−10°C
60
−40°C
40
80
125°C
85°C
60
25°C
40
−10°C
20
−40°C
20
0
0
3
6
9
12
Input Voltage (V)
15
18
Figure 7-3. High-Side Switch Resistance
6
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20
0
0
3
6
9
12
Input Voltage (V)
15
18
20
Figure 7-4. Low-Side Switch Resistance
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8 Detailed Description
8.1 Overview
The TPS6215x synchronous switched-mode power converter is based on DCS-Control topology, an advanced
regulation topology that combines the advantages of hysteretic, voltage-mode, and current-mode control,
including an ac loop directly associated with the output voltage. This control loop takes information about
output voltage changes and feeds that information directly to a fast comparator stage. It sets the switching
frequency, which is constant for steady-state operating conditions, and provides immediate response to dynamic
load changes. To get accurate dc load regulation, a voltage feedback loop is used. The internally compensated
regulation network achieves fast and stable operation with small external components and low-ESR capacitors.
The DCS-Control topology supports pulse-width modulation (PWM) mode for medium and heavy load conditions
and a power-save mode at light loads. During PWM, it operates at its nominal switching frequency in continuousconduction mode. This frequency is typically about 2.5 MHz or 1.25 MHz, with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters power-save mode to sustain
high efficiency down to very light loads. In power-save mode, the switching frequency decreases linearly with the
load current. Because DCS-Control topology supports both operation modes within a single building block, the
transition from PWM to power-save mode is seamless without effects on the output voltage.
Fixed-output voltage versions provide the smallest solution size and lowest current consumption, requiring only
three external components. An internal current limit supports nominal output currents of up to 1 A.
The TPS6215x offers both excellent dc voltage and superior load transient regulation, combined with very low
output voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagrams
PG
Soft
start
Thermal
Shtdwn
UVLO
AVIN
PVIN
PVIN
PG control
HS lim
comp
EN*
SW
SS/TR
power
control
control logic
gate drive
SW
DEF*
SW
FSW*
comp
LS lim
VOS
direct control &
compensation
ramp
_
comparator
FB
+
timer tON
error
amplifier
DCS - ControlTM
AGND
PGND
PGND
*This pin is connected to a pulldown resistor internally (see Section 8.3)
Figure 8-1. TPS62150 (Adjustable Output Voltage)
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PG
Soft
start
Thermal
Shtdwn
UVLO
AVIN
PVIN
PVIN
PG control
HS lim
comp
EN*
SW
SS/TR
power
control
control logic
gate drive
SW
DEF*
SW
FSW*
comp
LS lim
VOS
direct control &
compensation
ramp
_
comparator
FB
+
timer tON
error
amplifier
DCS - ControlTM
AGND
PGND
PGND
*This pin is connected to a pulldown resistor internally (see Section 8.3)
Figure 8-2. TPS62151, TPS62152, TPS62153 (Fixed Output Voltage)
8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
When Enable (EN) is set high, the device starts operation. Shutdown is forced if EN is pulled low with a
shutdown current of typically 1.5 µA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must
be set externally to high or low. An internal pulldown resistor of about 400 kΩ is connected and keeps EN logic
low, if low is set initially and then the pin gets floating. It is disconnected if the pin is set high.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
8.3.2 Soft Start or Tracking (SS/TR)
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output-voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50 µs, and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 9-34 and Figure 9-35 for typical start-up operation.
Using a very small capacitor (or leaving the SS/TR pin disconnected) provides fastest start-up behavior. There
is no theoretical limit for the longest start-up time. The TPS6215x can start into a pre-biased output. During
monotonic pre-biased start-up, both the power MOSFETs are not allowed to turn on until the internal ramp of
the device sets an output voltage above the pre-bias voltage. If the device is set to shutdown (EN = GND),
undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low
level. Returning from those states causes a new start-up sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in
both directions, up and down (see Section 9).
8.3.3 Power Good (PG)
The TPS6215x has a built-in power-good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. One use of the PG signal can be for start-up sequencing of multiple rails. The PG pin is
8
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an open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic-low level. With the TPS62150, it is high impedance when the device is turned off due
to EN, UVLO, or thermal shutdown. The TPS62150A features PG = low in this case and can be used to actively
discharge VOUT (see Figure 9-39). VIN must remain present for the PG pin to stay low. See the TPS62130A
Differences to TPS62130 Application Report for application details. If not used, the PG pin should be connected
to GND but can be left floating.
Table 8-1. Power Good Pin Logic Table (TPS62150)
PG LOGIC STATUS
DEVICE STATE
HIGH IMPEDANCE
VFB ≥ VTH_PG
Enable (EN = high)
LOW
√
VFB ≤ VTH_PG
Shutdown (EN = low)
√
√
UVLO
0.7 V < VIN < VUVLO
√
TJ > TSD
√
VIN < 0.7 V
√
Thermal Shutdown
Power Supply Removal
Table 8-2. Power Good Pin Logic Table (TPS62150A)
PG LOGIC STATUS
DEVICE STATE
HIGH IMPEDANCE
VFB ≥ VTH_PG
Enable (EN = high)
LOW
√
VFB ≤ VTH_PG
√
Shutdown (EN = low)
√
UVLO
0.7 V < VIN < VUVLO
√
TJ > TSD
√
Thermal Shutdown
Power Supply Removal
VIN < 0.7 V
√
8.3.4 Pin-Selectable Output Voltage (DEF)
Setting the DEF pin to high increases the output voltage of the TPS62150x devices by 5% above the nominal
voltage 1. When DEF is low, the device regulates to the nominal output voltage. Increasing the nominal voltage
allows adapting the power supply voltage to the variations of the application hardware. More detailed information
on voltage margining using the TPS62150x device is in Voltage Margining Using the TPS62130 Application
Report. The pin has an internally connected pulldown resistor of about 400 kΩ to ensure a proper logic level if
the pin is high-impedance or floating after an initially low setting. Setting the pin high disconnects the resistor.
8.3.5 Frequency Selection (FSW)
To get high power density with a very small solution size, a high switching frequency allows the use of small
external components for the output filter. However, switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typical) by pulling FSW to High. It is mandatory to start with FSW = low to limit inrush current, which connecting
FSW to VOUT or PG can accomplish. Running with lower frequency produces higher efficiency, but also creates
higher output-voltage ripple. Pull FSW to low for high-frequency operation (2.5 MHz typical). To get low ripple
and full output current at the lower switching frequency, the recommended minimum inductor value is 2.2 µH.
An application can change the switching frequency during operation, if needed. An internally-connected pulldown
resistor of about 400 kΩ on this pin acts the same way as one on the DEF pin (see Section 8.3.4).
8.3.6 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents faulty operation of the device by switching off both
the power FETs. The typical undervoltage-lockout threshold setting is 2.7 V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.
1
Maximum allowed voltage is 7 V. Therefore, the recommended connection for DEF is to VOUT, not VIN.
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8.3.7 Thermal Shutdown
An internal temperature sensor monitors the junction temperature (TJ) of the device. If TJ exceeds 160°C (typ.),
the device goes into thermal shutdown. Both the high-side and low-side power FETs turn off and PG goes
into the high-impedance state. When TJ decreases below the hysteresis level, the converter resumes normal
operation, beginning with soft start. To avoid unstable conditions, the device implements a hysteresis of typically
20°C on the thermal shutdown temperature.
8.4 Device Functional Modes
8.4.1 Pulse-Width Modulation (PWM) Operation
The TPS6215x operates using pulse-width modulation in continuous-conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in the PWM
mode is controlled and depends on VIN, VOUT, and the inductance. The device operates in PWM mode as long
the output current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the
device enters power-save mode at the boundary of discontinuous conduction mode (DCM). This happens if the
output current becomes smaller than half the inductor ripple current.
8.4.2 Power-Save Mode Operation
The TPS6215x enters its built-in power-save mode seamlessly if the load current decreases. This secures a
high efficiency in light load operation. The device remains in power-save mode as long as the inductor current is
discontinuous.
In power-save mode, the switching frequency decreases linearly with the load current, maintaining high
efficiency. The transition into and out of power-save mode happens within the entire regulation scheme and
is seamless in both directions.
TPS6215x includes a fixed on-time circuitry. An estimate for this on-time, in steady-state operation with FSW =
low, is:
space
t ON =
VOUT
´ 400 ns
VIN
(1)
space
For very small output voltages, an absolute minimum on-time of about 80 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also, the off-time
can reach its minimum value at high duty cycles. The output voltage remains regulated in such cases. Using tON,
the typical peak inductor current in power-save mode is approximated by:
space
ILPSM(peak) =
(VIN - VOUT )
L
´ t ON
(2)
space
When VIN decreases to typically 15% above VOUT, the TPS62150x device does not enter power-save mode,
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D = VOUT / VIN and increases as the input voltage comes close
to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal set
point. This allows the conversion of small input-to-output voltage differences, for example, for longest operation
time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
10
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The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, is calculated as:
spacing
(
VIN(min) = VOUT(min) + I OUT ´ R DS(on) + R L
)
(3)
where
•
•
•
IOUT is the output current
RDS(on) is the on-state resistance of the high-side FET
RL is the dc resistance of the inductor
8.4.4 Current-Limit and Short-Circuit Protection
The TPS6215x devices have protection against heavy-load and short-circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off.
Avoiding shoot-through current, then the low-side FET switches on to allow the inductor current to decrease. The
low-side current limit is typically 1.2 A. The high-side FET turns on again only if the current in the low-side FET
has decreased below the low-side current-limit threshold.
The output current of the device is limited by the current limit (see Section 7.5). Due to internal propagation
delay, the actual current can exceed the static current limit during that time. The dynamic current limit is
calculated as follows:
spacing
Ipeak(typ) = ILIMF +
VL
L
´ t PD
(4)
where
•
•
•
•
ILIMF is the static current limit, specified in the Section 7.5
VL is the voltage across the inductor (VIN – VOUT)
L is the inductor value
tPD is the internal propagation delay
space
The current limit can exceed static values, especially if the input voltage is high and the application uses very
small inductances. Calculate the peak current in the dynamic high-side switch using the following equation:
space
Ipeak(typ) = ILIMF +
(VIN - VOUT )´ 30 ns
(5)
L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS6215x devices are a switched-mode step-down converters, able to convert a 3-V to 17-V input voltage
into a 0.9-V to 6-V output voltage, providing up to 1 A. They require a minimum number of external components.
Apart from the LC output filter and the input capacitors, only the TPS62150 device needs an additional resistive
divider to set the output voltage level.
9.2 Typical Application
space
2.2 H
(3 .. 17) V
C1
10 F
PVIN
SW
AVIN
VOS
EN
VOUT / 1 A
100 k
PG
SS/TR
C5
3.3 nF
DEF
FB
R2
AGND
FSW
C3
22 uF
R1
TPS62150
PGND
Figure 9-1. A Typical 1-A Step-Down Converter
space
9.2.1 Design Requirements
The following design guideline provides a component selection to operate the device within the recommended
operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution
size and lowest output-voltage ripple. For highest efficiency set FSW = high, and the device operates at the lower
switching frequency. For smallest solution size and lowest output voltage ripple set FSW = low, and the device
operates with higher switching frequency. The typical values for all measurements are VIN = 12 V, VOUT = 3.3 V,
and T = 25°C, using the external components of Table 9-1.
The component selection used for measurements is given as follows:
Table 9-1. List of Components
REFERENCE
MANUFACTURER(1)
DESCRIPTION
IC
17-V, 1-A step-down converter, QFN
L1
2.2-µH, 3.1-A, 0.165-in × 0.165-in (4.19-mm × 4.19-mm)
C1
10-µF, 25-V, ceramic, 1210
Standard
C3
22-µF, 6.3-V, ceramic, 0805
Standard
C5
3300-pF, 25-V, ceramic, 0603
R1
Depending on VOUT
R2
Depending on VOUT
R3
100-kΩ, chip, 0603, 1/16-W, 1%
(1)
12
TPS62150RGT, Texas Instruments
XFL4020-222MEB, Coilcraft
Standard
See Third-Party Products disclaimer
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9.2.2 Detailed Design Procedure
9.2.2.1 Programming the Output Voltage
The output voltage of the TPS62150 (TPS62150A) is adjustable and the TPS62151, TPS62152, and TPS62153
are programmed to fixed output voltages. For fixed output versions, the FB pin is pulled down internally and
can be left floating. It is recommended to connect the FB pin to AGND to decrease thermal resistance. The
adjustable version can be programmed for output voltages from 0.9 V to 6 V by using a resistive divider
from VOUT to AGND. The voltage at the FB pin is regulated to 800 mV. The value of the output voltage is
set by the selection of the resistive divider from Equation 6. It is recommended to choose resistor values
which allow a current of at least 2 µA, meaning the value of R2 should not exceed 400 kΩ. Lower resistor
values are recommended for highest accuracy and most robust design. For applications requiring lowest current
consumption, the use of fixed-output-voltage versions is recommended.
space
æV
ö
R 1 = R 2 ´ ç OUT - 1÷
ç VREF
÷
è
ø
(6)
In case of an open on the FB pin, the device clamps the output voltage at the VOS pin internally to about 7.4 V.
9.2.2.2 External Component Selection
The external components must fulfill the needs of the application, but also the stability criteria for the control
loop of the device. The TPS6215x device is optimized to work within a range of external components. Consider
the inductance and capacitance of the LC output filters in conjunction, creating the double pole responsible
for the corner frequency of the converter (see Section 9.2.2.4). Table 9-2 can be used to simplify the output
filter component selection. Checked cells represent combinations that are proven for stability by simulation
and lab test. Further combinations should be checked for each individual application. See the Optimizing the
TPS62130/40/50/60 Output Filter Application Report for details.
Table 9-2. L-C Output Filter Combinations
4.7 µF(1)
10 µF
22 µF
47 µF
100 µF
200 µF
1 µH
√
√
√
√
2.2 µH
√
√(2)
√
√
√
3.3 µH
√
√
√
√
400 µF
0.47 µH
4.7 µH
(1)
(2)
The values in the table are nominal values. The effective capacitance was considered to vary by +20% and -50%.
This LC combination is the standard value, and is recommended for most applications.
The TPS6215x device can operate with an inductor as low as 1 µH or 2.2 µH. FSW should be set low in this
case. However, for applications running with the low-frequency setting (FSW = high) or with low input voltages,
3.3 µH is recommended.
9.2.2.2.1 Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point, and efficiency. In addition, the inductor selected must be rated for appropriate saturation
current and dc resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under static
load conditions.
spacing
IL(max) = I OUT(max) +
DIL(max)
(7)
2
space
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DIL(max)
VOUT
æ
ç 1- V
IN(max)
= VOUT ´ ç
ç L (min) ´ f SW
çç
è
ö
÷
÷
÷
÷÷
ø
(8)
where
•
•
•
•
IL(max) is the maximum inductor current
ΔIL is the peak-to-peak inductor ripple current
L(min) is the minimum effective inductor value
fSW is the actual PWM switching frequency
Calculating the maximum inductor current using the actual operating conditions gives the minimum required
saturation current of the inductor. An added margin of about 20% is recommended. A larger inductor value is
also useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS6215x device and are recommended for use:
Table 9-3. List of Inductors
TYPE
INDUCTANCE [μH]
SATURATION CURRENT DIMENSIONS [L × W× H,
[A](1)
mm
MANUFACTURER(2)
XFL4020-222ME_
2.2 μH, ±20%
3.5
4 × 4 × 2.1
Coilcraft
XFL3012-222MEC
2.2 μH, ±20%
1.6
3 × 3 × 1.2
Coilcraft
XFL3012-332MEC
2.2 μH, ±20%
1.4
3 × 3 × 1.2
Coilcraft
VLS252012T-2R2M1R3
2.2 μH, ±20%
1.3
2.5 × 2 × 1.2
TDK
LPS3015-332
2.2 μH, ±20%
1.4
3 × 3 × 1.4
Coilcraft
744025003
2.2 μH, ±20%
1.5
2.8 × 2.8 × 2.8
Wuerth
PSI25201B-2R2MS
2.2 μH, ±20%
1.3
2 × 2.5 × 1.2
Cyntec
NR3015T-2R2M
2.2 μH, ±20%
1.5
3 × 3 × 1.5
Taiyo Yuden
(1)
(2)
Lower of IRMS at 40°C rise or ISAT at 30% drop.
See the Third Party Disclaimer.
Iload(PSM) =
1
DIL
2
(9)
Using Equation 9, this current level can be adjusted by changing the inductor value.
9.2.2.2.2 Capacitor Selection
9.2.2.2.2.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS6215x device allows the
use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output-voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value
of output capacitance can have some advantages, like smaller voltage ripple and a tighter dc output accuracy in
power-save mode (see the Optimizing the TPS62130/40/50/60 Output Filter Application Report).
Note
In power-save mode, the output-voltage ripple depends on the output capacitance, the ESR of the
output capacitor, and the peak inductor current. Using ceramic capacitors provides small ESR and low
ripple.
14
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9.2.2.2.2.2 Input Capacitor
For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input-current
ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter
from the supply. A low-ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it is recommended to place a capacitance of 0.1 µF from AVIN to AGND, to avoid
potential noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.
9.2.2.2.2.3 Soft-Start Capacitor
A capacitance connected between the SS/TR pin and AGND allows a user-programmable start-up slope of the
output voltage. A constant-current source supplies 2.5 µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
space
CSS = t SS ´
2.5 mA
1.25 V
éëF ùû
(10)
where
•
•
CSS is the capacitance (F) required at the SS/TR pin
tSS is the desired soft-start ramp time (s)
Note
DC bias effect: High capacitance ceramic capacitors have a DC bias effect, which has a strong
influence on the final effective capacitnace. Therefore, selecting the right capacitor value requires
careful choice. Package size and voltage rating in combination with delectric material are responsible
for differences betweeen the rated capacitor value and the effective capacitance.
9.2.2.3 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50 mV and 1.2 V, the
FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 9-2.
spacing
VFB » 0.64 ´ VSS/TR
(11)
spacing
VSS/
TR [V]
1.2
0.8
0.4
0.2
0.4
0.6
0.8
VFB [V]
Figure 9-2. Voltage Tracking Relationship
Once the SS/TR pin voltage reaches about 1.2 V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
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the device does not sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin, which is VIN + 0.3 V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage goes to
zero, independent of the tracking voltage. Figure 9-3 shows how to connect devices to get ratiometric and
simultaneous sequencing by using the tracking function.
spacing
PVIN
SW
AVIN
VOS
EN
VOUT1
PG
TPS62150
SS/TR
FB
DEF
R1
AGND
FSW
PGND
PVIN
SW
AVIN
VOS
EN
VOUT2
PG
TPS62150
SS/TR
DEF
R2
FSW
FB
AGND
PGND
Figure 9-3. Schematic for Ratiometric and Simultaneous Start-Up
spacing
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower, or the same as
that of VOUT1.
A sequential start-up is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. A ratiometric
start-up sequence happens if both supplies share the same soft-start capacitor. Equation 10 calculates the softstart time, though the SS/TR current must be doubled. Details about these and other tracking and sequencing
circuits are found in Sequencing and Tracking With the TPS621-Family and TPS821-Family Application Report.
Note
If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy can have a
wider tolerance than specified.
9.2.2.4 Output Filter and Loop Stability
The devices of the TPS6215x family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 12:
spacing
16
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fLC =
SLVSAL5E – NOVEMBER 2011 – REVISED OCTOBER 2021
1
2p L ´ C
(12)
space
Proven nominal values for inductance and ceramic capacitance are given in Table 9-2 and are recommended for
use. Different values can work, but care must be taken on the loop stability, which is affected. More information,
including a detailed L-C stability matrix, can be found in the Optimizing the TPS62130/40/50/60 Output Filter
Application Report.
The TPS6215x devices, both fixed and adjustable versions, include an internal 25-pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per equations Equation 13 and Equation 14:
spacing
f zero =
1
2p ´ R 1 ´ 25 pF
(13)
æ 1
1
1 ö
´ç
+
÷
ç
2p ´ 25 pF è R 1 R 2 ÷ø
(14)
spacing
f pole =
spacing
Though the TPS6215x devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in power-save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more-detailed discussion
on the optimization for stability versus transient response can be found in the Optimizing Transient Response
of Internally Compensated dc-dc Converters With Feedforward Capacitor and Using a Feedforward Capacitor to
Improve Stability and Bandwidth of TPS62130/40/50/60/70 application reports.
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9.2.3 Application Curves
VIN= 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
100
100
90
90
70
VIN = 12 V
80
VIN = 17 V
Efficiency (%)
Efficiency (%)
80
60
50
40
70
60
30
30
20
20
10
10
0
0.0001
0.001
0.01
Output Current (A)
0.1
0
1
7
8
9
IOUT = 100 mA
10
VOUT = 5 V
90
80
80
70
Efficiency (%)
Efficiency (%)
100
90
VIN = 17 V
VIN = 12 V
40
60
20
10
10
0.1
0
1
7
8
9
10
90
80
80
VIN = 12 V
VIN = 17 V
VIN = 5 V
50
40
60
20
10
10
0.1
Figure 9-8. Efficiency With 1.25 MHz
1
IOUT = 10 mA
40
30
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17
IOUT = 1 mA
IOUT = 100 mA
50
20
0.01
Output Current (A)
16
IOUT = 1 A
70
30
VOUT = 3.3 V
18
Efficiency (%)
Efficiency (%)
100
90
0.001
15
Figure 9-7. Efficiency With 2.5 MHz
100
0
0.0001
11
12
13
14
Input Voltage (V)
VOUT = 5 V
Figure 9-6. Efficiency With 2.5 MHz
60
IOUT = 1 A
IOUT = 100 mA
VOUT = 5 V
70
17
40
20
0.01
Output Current (A)
IOUT = 10 mA
50 IOUT = 1 mA
30
0.001
16
70
30
0
0.0001
15
Figure 9-5. Efficiency With 1.25 MHz
100
50
11
12
13
14
Input Voltage (V)
VOUT = 5 V
Figure 9-4. Efficiency With 1.25 MHz
60
IOUT = 1 A
IOUT = 10 mA
50 IOUT = 1 mA
40
0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
VOUT = 3.3 V
Figure 9-9. Efficiency With 1.25 MHz
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100
100
90
90
80
80
70
70
60
50
VIN = 12 V
Efficiency (%)
Efficiency (%)
www.ti.com
VIN = 17 V
VIN = 5 V
40
60
30
20
20
10
10
0.001
0.01
Output Current (A)
0.1
0
1
4
5
6
7
8
VOUT = 3.3 V
90
80
80
70
VIN = 12 V
Efficiency (%)
Efficiency (%)
100
90
VIN = 17 V
VIN = 5 V
40
70
20
10
10
0.1
0
1
IOUT = 1 mA
3
4
5
6
7
VOUT = 1.8 V
Figure 9-13. Efficiency With 1.25 MHz
100
90
90
80
80
70
Efficiency (%)
Efficiency (%)
Figure 9-12. Efficiency With 1.25 MHz
VIN = 17 V
VIN = 12 V
50
40
VIN = 5 V
70
60
20
20
10
10
0.01
Output Current (A)
0.1
VOUT = 0.9 V
Figure 9-14. Efficiency With 1.25 MHz
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1
IOUT = 100 mA
40
30
0.001
IOUT = 1 A
50
30
0
0.0001
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
VOUT = 1.8 V
100
60
IOUT = 10 mA
40
30
0.01
Output Current (A)
IOUT = 100 mA
50
20
0.001
IOUT = 1 A
60
30
0
0.0001
9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 9-11. Efficiency With 2.5 MHz
100
50
IOUT = 1 A
VOUT = 3.3 V
Figure 9-10. Efficiency With 2.5 MHz
60
IOUT = 1 mA
IOUT = 10 mA
40
30
0
0.0001
IOUT = 100 mA
50
0
IOUT = 10 mA
IOUT = 1 mA
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
VOUT = 0.9 V
Figure 9-15. Efficiency With 1.25 MHz
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3.4
3.4
3.35
Output Voltage (V)
Output Voltage (V)
VIN = 17 V
3.3
VIN = 5 V
VIN = 12 V
3.25
3.2
0.0001
0.001
0.01
Output Current (A)
0.1
4
3.5
2.5
2
IOUT=0.5A
IOUT=1A
1.5
1
0
6
8
10
12
14
Input Voltage (V)
16
10
13
Input Voltage (V)
16
3
2.5
2
1.5
1
0
18
VOUT = 5 V
0.4
0.6
Output Current (A)
3.5
Switching Frequency (MHz)
3.5
3
2.5
IOUT=1A
1.5
1
0.5
0.8
1
G000
VOUT = 0.9 V
Figure 9-19. Switching Frequency vs Output
Current
4
IOUT=0.5A
0.2
FSW = low
4
2
0
G000
Figure 9-18. Switching Frequency vs Input Voltage
0
7
0.5
FSW = low
Switching Frequency (MHz)
4
4
3
IOUT = 100 mA
3.25
3.5
0.5
3
2.5
2
1.5
1
0.5
4
6
8
10
12
Input Voltage (V)
FSW = low
14
16
18
VOUT = 3.3 V
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0
0
G000
Figure 9-20. Switching Frequency vs Input Voltage
20
IOUT = 1 A
Figure 9-17. Output Voltage Accuracy (Line
Regulation)
Switching Frequency (MHz)
Switching Frequency (MHz)
Figure 9-16. Output Voltage Accuracy (Load
Regulation)
IOUT = 10 mA
3.3
3.2
1
IOUT = 1 mA
3.35
0.2
0.4
0.6
Output Current (A)
FSW = low
0.8
1
G000
VOUT = 3.3 V
Figure 9-21. Switching Frequency vs Output
Current
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4
4
3.5
3.5
Switching Frequency (MHz)
Switching Frequency (MHz)
www.ti.com
3
2.5
2
IOUT=0.5A
1.5
IOUT=1A
1
3
5
7
9
11
Input Voltage (V)
FSW = low
13
15
1.5
1
0
VOUT = 1.8 V
2.5
2.5
2
1.5
IOUT=1A
IOUT=0.5A
0.5
3
5
7
9
11
Input Voltage (V)
FSW = low
13
15
0.8
1
G000
VOUT = 1.8 V
2
1.5
1
0.5
0
17
0
0.2
0.4
0.6
Output Current (A)
G000
VOUT = 1 V
FSW = low
Figure 9-24. Switching Frequency vs Input Voltage
0.8
1
G000
VOUT = 1 V
Figure 9-25. Switching Frequency vs Output
Current
3
0.05
2.5
Output Current (A)
0.04
0.03
VIN = 17 V
0.02
0.01
2
0
0.1
0.2
0.3
1.5
1
85°C
VIN = 12 V
0.4 0.5 0.6 0.7
Output Current (A)
0.8
Figure 9-26. Output Voltage Ripple
Copyright © 2021 Texas Instruments Incorporated
25°C
−40°C
0.5
VIN = 5 V
0
0.4
0.6
Output Current (A)
Figure 9-23. Switching Frequency vs Output
Current
3
0
0.2
FSW = low
3
1
0
G000
Switching Frequency (MHz)
Switching Frequency (MHz)
2
17
Figure 9-22. Switching Frequency vs Input Voltage
Output Voltage Ripple (V)
2.5
0.5
0.5
0
3
0.9
1
0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 9-27. Maximum Output Current
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100
100
90
80
PSRR (dB)
PSRR (dB)
70
VIN=17V
60
50
40
VIN=17V
60
50
40
30
30
20
20
VOUT=3.3V, IOUT=1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
10
100
100k
1M
0
10
100
G000
fSW= 2.5 MHz
Figure 9-28. Power-Supply Rejection Ratio
Figure 9-30. PWM-to-PSM Transition
Figure 9-32. Load Transient Response, Rising
Edge
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VOUT=3.3V, IOUT=0.1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
1k
10k
Frequency (Hz)
IOUT = 1 A
22
VIN=5V
80
VIN=12V
70
0
VIN=12V
90
VIN=5V
1k
10k
Frequency (Hz)
IOUT = 0.1 A
100k
1M
G000
fSW = 2.5 MHz
Figure 9-29. Power-Supply Rejection Ratio
Figure 9-31. Load Transient Response
Figure 9-33. Load Transient Response, Falling
Edge
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Figure 9-34. Start-Up Into 100 mA
IOUT = 1 A
Figure 9-36. Typical Operation in PWM Mode
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Figure 9-35. Start-Up Into 1 A
IOUT = 10 mA
Figure 9-37. Typical Operation in Power-Save Mode
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9.3 System Examples
9.3.1 LED Power Supply
The TPS62150 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Because this pin provides 2.5 µA, the feedback pin voltage can be adjusted by an
external resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output
voltage (anode voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with
the TPS62150. Figure 9-38 shows an application circuit, tested with analog dimming:
2.2 H
(4 .. 17) V
10 F
PVIN
SW
AVIN
VOS
EN
PG
ADIM
22 F
TPS62140
FB
SS/TR
187 k
DEF
AGND
FSW
PGND
0.3 R
Figure 9-38. Single Power-LED Supply
The resistor at SS/TR sets the FB voltage to a level of about 300 mV, with a value calculated from Equation 15.
spacing
VFB = 0.64 ´ 2.5 mA ´ RSS/TR
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The forward voltage requirement of the LED determines the minimum input voltage rating. More
information is available in the Using the TPS62150 as Step-Down LED Driver With Dimming Application Report.
9.3.2 Active Output Discharge
The TPS62150A device pulls the PG pin Low when the device is shut down by EN, UVLO, or thermal shutdown.
Connecting PG to VOUT through a resistor can be used to discharge VOUT in those cases (see Figure 9-39). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10 mA.
2.2 H
TPS62150A
(3 .. 13.7 )V
10 uF
PVIN
SW
AVIN
VOS
EN
PG
SS/TR
FB
Vout / 1 A
R3
R1
22 uf
3.3 nF
DEF
FSW
AGND
R2
PGND
Figure 9-39. Discharge VOUT Through PG Pin with TPS62150A
24
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9.3.3 Inverting Power Supply
The TPS6215x device can be used as an inverting power supply by rearranging external circuitry as shown
in Figure 9-40. As the former GND node now represents a voltage level below system ground, the voltage
difference between VIN and VOUT must be limited for operation to the maximum supply voltage of 17 V (see
Equation 16).
spacing
VIN + VOUT £ VIN max
(16)
spacing
10 F
2.2 H
(3 .. 13.7 )V
PVIN
SW
AVIN
VOS
10 uF
EN
1.21 M
PG
TPS62150
22 F
SS/TR
3.3 nF
FB
DEF
383 k
AGND
FSW
PGND
-3.3 V
Figure 9-40. –3.3-V Inverting Power Supply
The transfer function of the inverting power supply configuration differs from the buck-mode transfer function,
additionally incorporating a right half-plane zero. The loop stability must be adapted, and an output capacitance
of at least 22 µF is recommended. A detailed design example is given in the Using the TPS6215x in an Inverting
Buck-Boost Topology Application Report.
9.3.4 Various Output Voltages
The following example circuits show how to use the various devices and configure the external circuitry to furnish
different output voltages at 1 A.
spacing
2.2 H
(5 .. 17) V
PVIN
SW
AVIN
VOS
EN
10 F
5V/1A
100 k
22 uF
PG
TPS62153
SS/TR
3.3 nF
DEF
FSW
FB
AGND
PGND
Figure 9-41. 5-V, 1-A Power Supply
spacing
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2.2 H
(3.3 .. 17) V
PVIN
SW
AVIN
VOS
EN
10 F
3.3 V / 1 A
100 k
22 uF
PG
TPS62152
SS/TR
FB
3.3 nF
DEF
AGND
FSW
PGND
Figure 9-42. 3.3-V, 1-A Power Supply
spacing
2.2 H
(3 .. 17) V
PVIN
SW
AVIN
VOS
EN
10 F
2.5 V / 1 A
100 k
390 k
PG
22 uF
TPS62150
3.3 nF
SS/TR
FB
DEF
180 k
AGND
FSW
PGND
Figure 9-43. 2.5-V, 1-A Power Supply
spacing
2.2 H
(3 .. 17) V
PVIN
SW
AVIN
VOS
EN
10 F
1.8 V / 1 A
100 k
22 uF
PG
TPS62151
SS/TR
FB
3.3 nF
DEF
FSW
AGND
PGND
Figure 9-44. 1.8-V, 1-A Power Supply
spacing
2.2 H
(3 .. 17) V
PVIN
SW
AVIN
VOS
EN
10 F
1.5 V / 1 A
100 k
PG
130 k
22 uF
TPS62150
SS/TR
3.3 nF
DEF
FSW
FB
AGND
150 k
PGND
Figure 9-45. 1.5-V, 1-A Power Supply
spacing
26
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2.2 H
(3 .. 17) V
PVIN
SW
AVIN
VOS
EN
10 F
1.2 V / 1 A
100 k
75 k
PG
22 uF
TPS62150
SS/TR
FB
3.3 nF
DEF
150 k
AGND
FSW
PGND
Figure 9-46. 1.2-V, 1-A Power Supply
spacing
2.2 H
(3 .. 17) V
PVIN
SW
AVIN
VOS
EN
10 uF
PG
1V/1A
100 k
51 k
22 uF
TPS62150
SS/TR
3.3 nF
DEF
FSW
FB
AGND
200 k
PGND
Figure 9-47. 1-V, 1-A Power Supply
10 Power Supply Recommendations
The TPS6215x devices are designed to operate from a 3-V to 17-V input voltage supply. The output current of
the input power supply must be rated according to the output voltage and the output current of the power rail
application.
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11 Layout
11.1 Layout Guidelines
Proper layout is critical for the operation of a switched-mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS6215x device demands careful attention to ensure operation
and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),
stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.
See Figure 11-1 for the recommended layout of the TPS6215x device, which is designed for common external
ground connections. Both AGND (pin 6) and PGND (pins 15 and 16) are directly connected to the exposed
thermal pad. On the PCB, the direct common-ground connection of AGND and PGND to the exposed thermal
pad and the system ground (ground plane) is mandatory. Also, connect VOS (pin 14) in the shortest way to VOUT
at the output capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the
VOUT power line and plane as shown in Section 11.2.
Provide low-inductance and -resistance paths for loops with high di/dt. Paths conducting the switched load
current should be as short and wide as possible. Provide low-capacitance paths (with respect to all other nodes)
for wires with high dv/dt. The input and output capacitance should be placed as close as possible to the IC
pins, and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct
an alternating current should outline an area as small as possible, as this area is proportional to the energy
radiated.
Sensitive nodes like FB (pin 5) and VOS (pin 14) must be connected with short wires and not near high dv/dt
signals [for example, SW (pins 1, 2, and 3)]. As FB and VOS pins carry information about the output voltage,
they should be connected as closely as possible to the actual output voltage (at the output capacitor). The
capacitor on SS/TR (pin 9) and on AVIN (pin 19), as well as the FB resistors, R1 and R2, should be kept close to
the IC and connect directly to those pins and the system ground plane.
The exposed thermal pad must be soldered to the circuit board for mechanical reliability and to achieve
adequate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the
EVM Gerber data are available for download here, SLVC394.
11.2 Layout Example
AGND
C5
R1
FB
AGND
DEF
SS/TR
PG
AVIN
SW
PGND
SW
PGND
SW
PVIN
EN
PVIN
VOS
VIN
FSW
R2
C3
C1
L1
VOUT
GND
Figure 11-1. TPS6215x Example Layout
28
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11.2.1 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad
Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics application reports.
The TPS6215x devices are designed for a maximum operating junction temperature (TJ) of 125°C. Therefore,
the maximum output power is limited by the power losses that can be dissipated over the actual thermal
resistance, given by the package and the surrounding PCB structures. Because the thermal resistance of the
package is fixed, increasing the size of the surrounding copper area and improving the thermal connection to
the IC can reduce the thermal resistance. To get improved thermal behavior, it is recommended to use top-layer
metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly
under the IC for improved thermal performance.
If short-circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
•
•
•
Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor,
SLVA289
Using the TPS62150 as Step-Down LED Driver With Dimming, SLVA451
Optimizing the TPS62130/40/50/60/70 Output Filter, SLVA463
Using a Feedforward Capacitor to Improve Stability and Bandwidth of TPS62130/40/50/60/70, SLVA466
Using the TPS6215x in an Inverting Buck-Boost Topology, SLVA469
TPS62130/40/50 Sequencing and Tracking, SLVA470
Voltage Margining Using the TPS62130, SLVA489
TPS62130EVM-505, TPS62140EVM-505, and TPS62150EVM-505 Evaluation Modules User's Guide,
SLVU437
Semiconductor and IC Package Thermal Metrics, SPRA953
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, SZZA017
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
DCS-Control™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
30
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62150ARGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PA8I
TPS62150ARGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PA8I
TPS62150RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUA
TPS62150RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QUA
TPS62151RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QWO
TPS62151RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QWO
TPS62152RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QWP
TPS62152RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QWP
TPS62153RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QWQ
TPS62153RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QWQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of