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TPS62510
SLVS651B – MAY 2006 – REVISED DECEMBER 2015
TPS62510 1.5-A, Low VIN High Efficiency Step-Down Converter
1 Features
3 Description
•
•
The TPS62510 is a high-efficiency step-down
converter targeted for operation from a 1.8-V to 3.8-V
input voltage rail, ideally suited for 2-cell alkaline or
NiMHd applications. The TPS62510 is also ideal as a
point-of-load regulator running from a fixed 3.3-V, 2.5V, or 1.8-V input voltage rail.
1
•
•
•
•
•
•
•
1.8-V to 3.8-V Input Voltage Range
Up to 96% High Efficiency Synchronous StepDown Converter
1.5-MHz Fixed Frequency PWM Operation
1% Output Voltage Accuracy in Fixed Frequency
PWM Mode
Power Save Mode Operation for High Efficiency
Over the Entire Load Current Range
22-μA Quiescent Current
Adjustable Output Voltage
Output Voltage Tracking (OVT) for Reliable
Sequencing
Available in a 3-mm × 3-mm 10-Pin VSON
Package
2 Applications
•
•
•
•
•
•
The converter operates in fixed frequency pulse width
modulation (PWM) mode switching at 1.5 MHz with
the MODE pin high. Pulling the MODE pin low
enables the high efficiency mode. In high efficiency
mode, the device operates with a 1.5-MHz fixed
frequency PWM at nominal load current, and
automatically enters the power save mode at light
load currents. For maximum system reliability, the
converter features output voltage tracking using the
OVT pin to allow sequencing, and to allow for the
output voltage to track an external voltage applied to
this pin.
The TPS62510 is available in a 3-mm × 3-mm 10-pin
VSON package.
Portable Devices (Mobile Phone, Smartphone)
2-Cell NiMHd/Alkaline Applications
Hard Disc Drives
Point-of-Load Regulation
Notebook Computers
WiMAX and WLAN Applications
Device Information(1)
PART NUMBER
TPS62510
10
Rf 1 W
Cf
100 nF
9
6
5
7
PVIN
SW
AVIN
FB
EN
PG
OVT
AGND
MODE
PGND
4
8
3
2
C3
22 pF
Efficiency vs Load Current
VO
1.5 V/1.5 A
L1
1 2.2 mH
R1
300 kW
R2
200 kW
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
95
VI = 1.9 V
(Mode Low)
90
C2
22 mF
85
Efficiency - %
C1
22 mF
TPS62510
BODY SIZE (NOM)
VSON (10)
Typical Application Schematic
VI
1.8 V to 3.8 V
PACKAGE
VI = 2.4 V
(Mode Low)
80
75
VI = 1.9 V
(Mode High)
70
VI = 2.4 V
(Mode High)
VI = 3.2 V
(Mode Low)
65
VI = 3.2 V
(Mode High)
60
55
VO = 1.2 V
50
0.01
0.1
1
10
100
1k
10 k
IL - Load Current- mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62510
SLVS651B – MAY 2006 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
8.3 System Example ..................................................... 17
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2009) to Revision B
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Original (May 2006) to Revision A
Page
•
Changed VFB - Feedback voltage inputs ................................................................................................................................ 5
•
Added Note 4 to the Electrical Characteristics Table - Min/Max values established by characterization and not
production tested. ................................................................................................................................................................... 5
2
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SLVS651B – MAY 2006 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
SW
1
PGND
2
AGND
3
FB
4
OVT
5
Exposed
Thermal Pad
(Note A)
DRC Package
10-Pin VSON
Top View
10
PVIN
9
AVIN
8
PG
7
MODE
6
EN
The exposed thermal pad is connected to AGND.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SW
1
—
Switch pin of the converter. The inductor is connected here.
PGND
2
—
Power ground for the converter
AGND
3
—
Analog ground connection
FB
4
I
Feedback voltage sense input. Connect directly to VOUT or to the midpoint of an external voltage divider
for the adjustable version.
OVT
5
I
Output voltage tracking input. The signal applied to this pin is used as reference voltage overriding the
internal reference voltage when it is below the internal 0.6-V reference. If this feature is not used, the
OVT pin is connected to VIN.
EN
6
I
Enable pin. A logic high enables the regulator, a logic low disables the regulator. This pin needs to be
terminated and not left floating.
MODE
7
I
This pin is used to force fixed frequency PWM operation or to synchronize the device to an external clock
signal. With MODE = High, the device is forced into 1.5-MHz fixed frequency PWM operation. With
MODE = Low, the device automatically enters the power save mode at light load currents.
PG
8
O
Power good indication. This is a open drain output that is low when the device is disabled or the output
voltage drops 10% below target.
AVIN
9
—
Power supply for control circuitry. Must be connected to the same voltage supply as PVIN through RC
filter.
PVIN
10
—
Input voltage for the power stage. VIN must be connected to the same voltage supply as AVIN.
Exposed
Thermal Pad
C2
—
Connect the exposed thermal pad to analog ground AGND.
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SLVS651B – MAY 2006 – REVISED DECEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
VS
(1)
Supply voltage at PVIN, AVIN
Voltage at EN, MODE, OVT, FB, PG
(2)
MIN
MAX
UNIT
–0.3
4
V
V
–0.3
4
Voltage at SW (2)
–0.3
VIN + 0.3
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage on pins PVIN and AVIN
1.8
3.8
VOUT
Output voltage
0.6
VIN
IOUT
Output current, VIN = 1.8 V to 3.6 V
L
Inductor value
2.2
μH
CIN
Input capacitor value (1)
10
μF
COUT
Output capacitance value (1)
22
μF
TA
Operating ambient temperature
-40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
1500
V
V
mA
See Application and Implementation for more information.
6.4 Thermal Information
TPS62510
THERMAL METRIC (1)
DRC [VSON]
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
48.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
71.2
°C/W
RθJB
Junction-to-board thermal resistance
23.0
°C/W
ψJT
Junction-to-top characterization parameter
2.1
°C/W
ψJB
Junction-to-board characterization parameter
23.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLVS651B – MAY 2006 – REVISED DECEMBER 2015
6.5 Electrical Characteristics
VIN = 3.3 V, OVT = EN = VIN, MODE = GND, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage
I(q)
Power save mode quiescent current
AVIN + PVIN
1.8
FB = FB nominal + 5%, MODE = Low
3.8
V
22
30
μA
PWM Mode quiescent current into AVIN
MODE = High
4.4
5
mA
I(SD)
Shutdown current into PVIN + AVIN
EN = Low, SW = GND
0.1
5
μA
UVLO
Undervoltage lockout threshold at AVIN
V(AVIN) falling
1.55
1.58
(1)
Undervoltage lockout hysteresis
Thermal shutdown threshold
T(SD)
Increasing junction temperature
Thermal shutdown hysteresis
V
150
mV
160
°C
20
°C
CONTROL SIGNALS EN, MODE
VIH
High level input voltage
VIL
Low level input voltage
IIB
Input bias current
f(sync)
1.2
VIN = 1.8 V to 3.8 V
V
0.01
MODE synchronization range
1.15
Duration of high or low level for synchronization signal (2)
0.4
V
0.1
μA
2.25
MHz
75
ns
OUTPUT VOLTAGE TRACKING (OVT)
IIB
Input bias current
VOS
OVT offset voltage
0.001
VOS = V(OVT) - V(FB), 0.1 V < V(OVT) < 0.5 V
–15
0.05
μA
15
mV
POWER GOOD (PG)
Power good threshold
V(th)
–7%
VOUT
Feedback voltage rising
Power good hysteresis
–5%
VOUT
2% VOUT
VOL
Low level voltage
I(PG) = 1 mA
Ilkg
Power good leakage current
V(PG) = 3.8 V
1
–3%
VOUT
V
7% VOUT
V
0.3
V
100
nA
OUTPUT
RDS(on)
P-channel MOSFET on-resistance
Ilkg
P-channel leakage current
VIN = V(GS) = 1.8 V
330
VIN = V(GS) = 3.3 V
120
VIN = 3.6 V
10
VIN = V(GS) = 1.8 V
RDS(on)
N-channel MOSFET on-resistance
Ilkg
N-channel leakage current
V(DS) = 3.6 V
IF
Forward current limit (P- and N-channel)
1.8 V < VIN < 3.8 V
fs
Oscillator frequency
MODE = High
Vref
Reference voltage
200
VIN = V(GS) = 3.3 V
80
Feedback voltage
tSS
(1)
(2)
(3)
(4)
mΩ
μA
mΩ
μA
1.75
2
2.25
A
1.3
1.5
1.7
MHz
0.6
(3)
PFM operation
VIN = (VOUT + 0.2 V) to 3.8 V; VOUT= 1.8 V,
C2 = 15 μF, L1= 2.1 μH (effective values),
IOUT = 0 mA to 150 mA
VIN = (VOUT + 0.3 V) to 3.8 V; VOUT= 2.5V,
C2 = 15 μF, L1= 2.1 μH (effective values),
IOUT = 0 mA to 150 mA
PWM operation
IFB
130
10
VIN = (VOUT + 0.3 V) to 3.8 V
VFB
170
V
–2%
5%
–2%
2.5%
–1.3%
2.3%
(4)
(4)
VIN = VOUT + 0.3 V
Feedback bias current
V(FB) = 0.6 V, EN = High
Line Regulation
VIN = VOUT + 0.3 V (minimum 1.8 V) to 3.8 V;
IOUT = 800 mA
Load Regulation
Soft start time
–1%
1%
0.001
0.05
μA
0
%/V
IOUT = 10 mA to 1500 mA, PWM mode
0.1
%/A
VOUT ramping from 5% to 95% of nominal value
750
μs
The undervoltage lockout threshold is detected at the AVIN pin. Current through the RC filter causes a UVLO trip at higher VIN
The minimum and maximum duty cycle applied to the MODE pin is calculated as:
D(min) = 75 ns × f(sync) and D(max) = 1 - 75 ns × f(sync).
When using the output voltage tracking function, the feedback regulates to the voltage applied to OVT as long as the OVT < 0.6 V.
Minimum and maximum values established by characterization and not production tested. Includes line and load regulation in PFM
mode operation. For the measurements, a proper PCB layout and usage of recommended inductors and capacitors are essential.
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Electrical Characteristics (continued)
VIN = 3.3 V, OVT = EN = VIN, MODE = GND, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Leakage resistance from SW pin to GND
VIN > VOUT, 0 V ≤ V(SW) ≤ VIN
Leakage resistance from FB pin to GND
EN = Low
MIN
TYP
700
1000
17
23
MAX
UNIT
kΩ
6.6 Typical Characteristics
30
6
Mode = Low
Mode = High
28
5
o
85 C
24
22
o
25 C
20
o
-40 C
18
16
14
o
25 C
o
85 C
I(q) - Quiescent Current - mA
I(q) - Quiescent Current - mA
26
4
o
-40 C
3
2
1
12
10
1.6 1.8
2
2.2 2.4 2.6 2.8
3
0
1.6 1.8
3.2 3.4 3.6 3.8
2
2.2 2.4 2.6 2.8
VI - Input Voltage - V
1610
1600
VI = 3.8 V
f - Frequency - kHz
1590
1580
VI = 3.3 V
1570
1560
1550
1540
VI = 1.8 V
1530
1520
0
-20
20
60
40
80
0.25
0.2
o
85 C
0.15
o
25 C
0.1
o
-20 C
0.05
0
1.6 1.8
2
2.2 2.4 2.6 2.8
o
Temperature - C
3.2 3.4 3.6 3.8
Figure 4. PMOS RDS(on) vs Input Voltage
15
0.2
10
o
25 C
o
-40 C
0.15
5
FB Offset - mV
rDS(on) - Static Drain-Source On-State Resistance - W
3
VI - Input Voltage - V
Figure 3. Frequency vs Temperature
o
85 C
o
25 C
0.1
o
o
85 C
0
-5
-20 C
0.05
OVT £ 0.6 V,
VI = 2.4 V,
IO = 1 mA
-10
0
1.6 1.8
0
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
0
0.1
0.2
0.3
0.4
0.5
0.6
Voltage on OVT - V
VI - Input Voltage - V
Figure 5. NMOS RDS(on) vs Input Voltage
6
3.2 3.4 3.6 3.8
Figure 2. No Load Quiescent Current vs Input Voltage,
MODE = High
rDS(on) - Static Drain-Source On-State Resistance - W
Figure 1. No Load Quiescent Current vs Input Voltage,
MODE = Low
1510
-40
3
VI - Input Voltage - V
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Figure 6. FB Offset vs Voltage ON VOUT
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7 Detailed Description
7.1 Overview
The TPS62510 has two target areas of operation. The high efficiency area is defined when the MODE pin is held
low. In this condition, the converter operates at typically 1.5-MHz fixed frequency pulse width modulation (PWM)
mode at moderate to heavy load currents. At light load currents, the converter automatically enters power save
mode and operates with pulse frequency modulation (PFM) mode. Low noise operation is defined when the
MODE pin is held high. In this condition, the converter is forced into fixed frequency PWM mode and runs at
1.5 MHz. The converter is capable of delivering 1.5-A output current.
The TPS62510 can also be synchronized to an external clock in the frequency range between 1.15 MHz and
2.25 MHz. Synchronization is aligned with the falling edge of the incoming clock signal. This allows simple
synchronization of two step-down converters running 180° out of phase reducing overall input RMS current.
During PWM operation, the converters use a unique fast response voltage mode control scheme with input
voltage feed-forward to achieve good line, and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded.
After the adaptive dead time, which is used to prevent shoot through current, the N-channel MOSFET rectifier is
turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the Nchannel rectifier, and turning on the P-channel switch.
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7.2 Functional Block Diagram
PG
MODE
PVIN
Q3
PLL
High Side
Current
Sense
Summing
Comparator
1.5 MHz
SawTooth
0.6 V
(See Note A)
R1
Q1
VOUT
Generator
Loop
Error Amplifier Compensation
EN
FB
R2
MOSFET Driver
Anti Shoot Through
Converter Control
Logic
Vref
0.6 V
Q2
PFM
Comparator
Vref
0.6 V
Analog
Softstart
Low Side
Current
Sense
PFM/PWM
Transition
Vref
0.6 V
Vref - 2%
AVIN
Bandgap
Undervoltage
Lockout
Thermal Shutdown
R3
Output Voltage
Tracking
R4
EN
Q4
AGND
A.
SW
0.6 V
OVT
PGND
R1 and R2 are only used for the fixed output voltage version.
7.3 Feature Description
7.3.1 Output Voltage Tracking (OVT)
In applications where a processor or FPGA is powered, it is important that the I/O voltage and core voltage startup in a controlled way to avoid possible processor and FPGA latch-up. To implement this, the TPS62510 has an
output voltage tracking feature where the internal reference voltage for the error amplifier follows the voltage
applied to OVT, until OVT reaches Vref. Vref is the nominal internal reference voltage, typically 0.6 V. Figure 7
shows a typical application where an external voltage (V1) is applied to OVT pin using a resistor divider.
8
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Feature Description (continued)
VI
1.8 V to 3.8 V
TPS62510
10
Rf 1 W
C1
10 mF
9
6
Cf
100 nF
V1
Output of External
DC-DC Converter
e.g. I/O Rail
5
R3
300 kW
7
PVIN
SW
AVIN
FB
EN
PG
1
L1
2.2 mH
V2
1.5 V/1.5 A
C3
22 pF
4
R1
300 kW
C2
22 mF
8
OVT
AGND
MODE
PGND
R2
200 kW
3
2
R4
200 kW
Figure 7. Output Voltage Tracking, V2 Tracks V1
In this application, the output voltage (V2) of the TPS62510 tracks the voltage (V1) as long as the OVT voltage is
smaller than the internal device reference voltage, Vref = 0.6 V. Depending on the resistor divider (R3, R4), the
tracking can be adjusted. V2 can rise faster, at the same timer, or slower than V1.
Voltage
V1
V2
R3
R4
<
R1
R2
Time
Figure 8. V2 Comes Up Before V1
Simultaneous tracking is achieved when the resistor divider (R3/R4) is equal to the resistor divider of the
TPS65210.
R3
=
R4
V2 - Vref
1.5 V - 0.6 V
= 1.5
=
Vref
V2(tracking) = V(OVT) x
0.6 V
V2
Vref
(1)
= V1 x
R4
R3 + R4
x
V2
Vref
= V1
200 k
300 k + 200 k
x
1.5 V
0.6 V
= V1
(2)
If V2 needs to rise before V1, then R4 must be increased as shown in Figure 9.
V1
Voltage
V2
R3
R4
=
R1
R2
Time
Figure 9. Simultaneous Tracking of V2 and V1
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Feature Description (continued)
If V2 needs to rise after V1, then R4 must be decreased as shown in Figure 10.
Voltage
V1
V2
R3
R4
>
R1
R2
Time
Figure 10. V2 Comes Up After V1
7.3.2 Power Good
The power good output can be used for sequencing purposes, enabling a separate regulator once the output
voltage is reached, or to indicate that the output voltage is in regulation. When the device is disabled, the PG pin
is pulled low by the internal open-drain output transistor. Internally, the TPS62510 compares the feedback
voltage FB to the nominal reference voltage of typically 0.6 V. If the feedback voltage is more than 95% of this
value then the power good output goes high impedance. If the feedback voltage is less than 90% of the
reference voltage then PG pin is pulled low.
7.3.3 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages. It disables the
converter. The UVLO circuit monitors the AVIN pin, the falling threshold is set internally to 1.55 V with 150-mV
hysteresis. Note that when the DC/DC converter is running, there is an input current at the AVIN pin, which is up
to 5 mA when in PWM mode. This current must be taken into consideration if an external RC filter is used at the
AVIN pin to remove switching noise from the TPS62510 internal analog circuitry supply.
7.3.4 Thermal Shutdown
As soon as the device junction temperature exceeds 160°C (typical), all switching activity ceases and both highside and low-side power transistors are off. The device continues operation once the temperature fall to 20°C
(typical) below its thermal shutdown threshold of 160°C.
7.4 Device Functional Modes
7.4.1 Soft Start
The converter has an internal soft start circuit that limits the inrush current during start-up. The soft start is
realized by using a low current to control the output of the error amplifier during start-up. The soft start time is
typically 750 μs to ramp the output voltage to 95% of the final target value. There is a short delay of typically
120 μs between the converter being enabled and switching activity actually starting. See the typical soft start
characteristic shown in Figure 20.
7.4.2 100% Duty Cycle Low Dropout Operation
The TPS62510 converter offers a low input to output voltage difference while maintaining operation with the use
of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the entire
battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load
current and output voltage, as shown in Equation 3.
VI min = VO min + IO max x
(rDS(on) max + RL )
where
•
•
10
IOmax = Maximum load current (Note: ripple current in the inductor is zero under these conditions)
RDS(on)max = Maximum P-channel switch RDS(on)
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Device Functional Modes (continued)
•
•
RL = DC resistance of the inductor
VOmin = Nominal output voltage minus 2% tolerance limit
(3)
7.4.3 Power Save Mode Operation (MODE)
When the MODE pin is connected to GND, the device automatically enters the power save mode when the
average output current reaches the appropriate threshold. This reduces the switching frequency and minimum
quiescent current, maintaining efficiency over the entire load current range. For low noise operation, the device
can be forced into fixed frequency PWM mode operating at 1.5 MHz over the entire load current range. This is
done by pulling the MODE pin high.
Many applications require a low output ripple voltage during power save mode. This is accomplished by a single
threshold PFM comparator which allows control of the output voltage ripple in power save mode. The larger the
output capacitor value, the smaller the output voltage ripple (see Figure 19). During power save mode, the device
monitors the output voltage with the PFM comparator. As soon as the output voltage falls below the nominal
output voltage, the device starts switching for a minimum of 1 μs (typical), or until the output voltage is above the
nominal output voltage.
7.4.4 Power Save Mode Transition Thresholds
To achieve an accurate transition into and out of power save mode, the device monitors the average inductor
current which is equal to the average output current. The device enters power save mode when the average
output current is ≤ I(PFM enter) as calculated in Equation 4.
VIN
I(PFM enter) =
(4)
22 W
The device leaves the power save mode when the output current is ≥ I(PFM enter).
VIN
I(PFM leave) =
(5)
17 W
To minimize any delay times during a load transient, the device enters PWM mode when the output voltage is
2% below the nominal value, and the PFM/PWM transition comparator trips.
7.4.5 Short-Circuit Protection
The TPS62510 monitors the forward current through both the high-side and low-side power devices. This
enables the converter to limit the short-circuit current, which helps to protect the device and other circuits
connected to its output.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS62510 is a high-efficiency step-down converter targeted for operation from a 1.8-V to 3.8-V input voltage
rail, ideally suited for 2-cell alkaline or NiMHd applications. The TPS62510 is also ideal as a point-of-load
regulator running from a fixed 3.3-V, 2.5-V or 1.8-V input voltage rail.
8.2 Typical Application
Figure 11 shows the adjustable version programming to 1.5 V.
VI
1.8 V to 3.8 V
TPS62510
10
Rf 1 W
9
C1
22 mF
Cf
100 nF
6
5
7
PVIN
SW
AVIN
FB
EN
PG
OVT
AGND
MODE
PGND
1
4
VO
1.5 V/1.5 A
L1
2.2 mH
C3
22 pF
R1
300 kW
C2
22 mF
8
R2
200 kW
3
2
Figure 11. Adjustable Version Programmed to 1.5 V Example
8.2.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions. The output voltage tracking is not used and the output voltage is programmed using the external
voltage divider. The connection of the power good output is shown in one of the system examples.
8.2.2 Detailed Design Procedure
8.2.2.1 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering, and minimizing the interference with other circuits caused by high input
voltage spikes. The converter needs a ceramic input capacitor of 22 μF. The input capacitor may be increased
without any limit for better input voltage filtering. The AVIN pin is separated from the power input of the converter.
Note that the filter resistor may affect the undervoltage lockout threshold since up to 5 mA can flow via this
resistor into the AVIN pin when the converter runs in PWM mode.
Table 1. Input Capacitor Selection
12
CAPACITOR VALUE
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
22 μF
1206
TDK C3216X5R0J226M
Ceramic
22 μF
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
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8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
The TPS62510 step-down converter has an internal loop compensation. Therefore, the external L-C filter must
be selected to work with the internal compensation.
The internal compensation is optimized to operate with an output filter of L = 2.2 μH with an output capacitor of
COUT = 22 μF. The output filter has its corner frequency per Equation 6:
1
ƒc =
2p x
1
=
2p x
L x CO
= 22.8 kHz
2.2 mH x 22 mF
where
•
•
L = 2.2 μH
CO = 22 μF
(6)
As a general rule of thumb, the product L x C should not move over a wide range when selecting a different
output filter. This is because the internal compensation is designed to work with a certain output filter corner
frequency, as calculated in Equation 6. This is especially important when selecting smaller inductor or output
capacitor values that move the corner frequency to higher frequencies. However, when selecting the output filter
a low limit for the inductor value exists due to other internal circuit limitations. The minimum inductor value for the
TPS62510 should be kept at 2.2 μH. Selecting a larger capacitor value is less critical because the corner
frequency drops, causing fewer stability issues.
Table 2. Output Capacitor Selection
(1)
L
CO
2.2 μH
≥22 μF (ceramic capacitor)
3.3 μH
≥22 μF (ceramic capacitor) (1)
For output currents
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