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Table of Contents
User’s Guide
TPS629206-Q1 Buck Converter Evaluation Module User's
Guide
ABSTRACT
The TPS629206-Q1EVM is designed to help user easily evaluate the performance of TPS629206-Q1. The
user’s guide includes the following:
• Performance characteristics
• EVM configuration
• Test setup
• Test result
• PCB layout
• Schematic diagram
• Bill of materials
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Performance Specification.................................................................................................................................................... 2
3 EVM Configuration and Modification....................................................................................................................................3
3.1 Input and Output Capacitors.............................................................................................................................................. 3
3.2 Configurable Enable Threshold Voltage.............................................................................................................................3
3.3 MODE/S-CONF Setting......................................................................................................................................................3
3.4 Power Good....................................................................................................................................................................... 3
3.5 Power-Good Pullup Voltage............................................................................................................................................... 3
3.6 Feedforward Capacitor Option........................................................................................................................................... 3
3.7 Output Voltage Setting....................................................................................................................................................... 4
3.8 Loop Response Measurement........................................................................................................................................... 4
4 EVM Test Setup....................................................................................................................................................................... 5
4.1 Input and Output Connectors............................................................................................................................................. 5
4.2 Jumper Configuration.........................................................................................................................................................5
5 Test Results.............................................................................................................................................................................6
6 Board Layout.........................................................................................................................................................................12
7 Schematic and Bill of Materials...........................................................................................................................................15
7.1 Schematic........................................................................................................................................................................ 15
7.2 Bill of Materials.................................................................................................................................................................15
8 References............................................................................................................................................................................ 17
Trademarks
All trademarks are the property of their respective owners.
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Introduction
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1 Introduction
The TPS629206-Q1 is high-efficiency and highly flexible synchronous step-down buck converter in a small
1.6-mm × 2.1-mm SOT583 package. The TPS629206-Q1 can be configured to run 2.5 MHz or 1 MHz in either
forced PWM mode or auto PFM/PWM mode. In 2.5-MHz auto PFM/PWM mode, TI AEE mode automatically
adjusts the switching frequency based on both input and output voltage to hold a high efficiency through the
whole operation range without needing to use different inductors. The device includes a MODE/S-CONF input to
select different combinations of following:
• External and internal feedback
• Maximum switching frequency
• Output discharge enable/disable
• Auto PFM/PWM (with AEE) and forced PWM operations
The TPS629206-Q1EVM(BSR131-002) uses a 600-mA TPS629206-Q1 to produce a 3.3-V output from a 12-V
input.
2 Performance Specification
Table 2-1 provides a summary of the TPS629206-Q1EVM performance specifications. All the specifications are
given at an ambient temperature of 25°C.
Table 2-1. TPS629206-Q1EVM Performance Specification Summary
Specification
Test Conditions
Input voltage
MIN
TYP
MAX
5
12
17
V
600
mA
Output voltage
3.3
Output current
Input current
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A, forced PWM, 2.5 MHz,
2.2-μH inductor
VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA, forced PWM, 2.5 MHz,
2.2-μH inductor
Switching frequency
Set by the Mode/S-CONF pin
Line regulation
VIN = 5 V–17 V, VOUT= 3.3 V, IOUT = 0 A and 600 mA, forced
PWM, 2.5 MHz, VSET, 2.2-μH inductor
Load regulation
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A–600 mA, forced PWM and
auto PFM/PWM with AEE, 2.5 MHz, VSET, 2.2-μH inductor
Output ripple
VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA, forced PWM, 2.5 MHz,
2.2-μH inductor
Peak efficiency
2
0
6.2
0.181
2.5
UNIT
V
mA
A
MHz
+0.3%, –
0.15%
±0.15%
10.6
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A–600 mA, forced PWM, 2.5
MHz, 2.2-μH inductor
91.3%
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A–600 mA, auto PFM/PWM
with AEE, 2.5 MHz, 2.2-μH inductor
91.72%
VIN = 12 V, VOUT = 3.3 V, IOUT = 10 mA, auto PFM/PWM with
AEE, 2.5 MHz, 2.2-μH inductor
86.2%
mV
Output rise time
VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA, forced PWM, 2.5 MHz,
2.2-μH inductor
500
μs
Load transient
VIN = 12 V, VOUT = 3.3 V, IOUT = 300 mA–600 mA, slew rate: 1
A/μs, forced PWM, VSET, 2.5 MHz, 2.2-μH inductor
±29
mV
Loop bandwidth
VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA, forced PWM, VSET, 2.5
MHz, 2.2-μH inductor
153
kHz
Phase margin
VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA, forced PWM, VSET, 2.5
MHz, 2.2-μH inductor
86.7
deg
IC case temperature
VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA, forced PWM, 2.5 MHz,
2.2-μH inductor, 10 minutes soaking
30.5
°C
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EVM Configuration and Modification
3 EVM Configuration and Modification
The EVM is designed to provide access to features of the TPS629206-Q1. The EVM also provides jumpers for
different configurations. Jumper selections must be made prior to enabling the TPS629206-Q1. Additional input
and output capacitors can be added. The input voltage at which the IC turns on can be programmed with a
voltage divider. The TPS629206-Q1EVM allows multiple MODE/S-CONF pin configurations. The loop response
can also be measured.
3.1 Input and Output Capacitors
C2 is provided for additional input capacitance. This capacitor is not required for proper operation but can be
used to reduce the input voltage ripple. C6, C7, C8, and C9 are provided for additional output capacitors. These
capacitors are not required for proper operation but can be used to reduce the output voltage ripple. The total
output capacitance must remain within the recommended range for the TPS629206-Q1.
3.2 Configurable Enable Threshold Voltage
JP1 is provided as option for Enable pin with a precise threshold voltage. R4 and R5 can be adjusted to set a
user-selectable input voltage at which the IC turns on. The EVM pre-configures R4 and R5 to have 6.5-V rising
and 5.85-V falling threshold voltage.
3.3 MODE/S-CONF Setting
JP2 is used to set different MODE/S-CONF configurations. MODE/S-CONF can be connected to VIN and GND
as a traditional HIGH or LOW level. R6 and R7 select the other device configurations including the following:
•
•
•
•
Internal and external feedback
Switching frequency
Output discharge
Auto PFM/PWM(with AEE) or forced PWM options
The values of R6 and R7 can be changed per the user’s requirement.
•
•
While using the internal feedback (VSET) configuration for the output voltage setting, either float the FB pin
by cutting the net tie (NT1) included on the back of the board or remove both R1 and R2 for 3.3-V output
voltage. Other output voltages can be programmed by removing R1 and changing the value of R2. Ensure
the JP2 jumper is placed correctly for proper operation with internal feedback.
WARNING
Do not to set the MODE/S-CONF pin for external feedback if either the net tie (NT1) is cut or
R1 and R2 are removed. This can cause damage to the device due to lack of external feedback
control.
Dynamic mode option is an advanced feature that allows MODE/S-CONF pin to actively switch between
forced PWM and auto PFM/PWM during operation, but this is only possible by driving the MODE/S-CONF pin
between VIN and GND. This feature provides the user with the option of controlling if and when the device
enters power save mode (DCM).
3.4 Power Good
JP3 is provided as an option for power-good test point. If power good is not used, it is recommended to tie to
GND or leave open.
3.5 Power-Good Pullup Voltage
JP4 is provided as an option for power-good pullup voltage. Either VIN or VOUT with a 100-kΩ pullup resistor.
3.6 Feedforward Capacitor Option
C10 is provided as an optional of feedforward capacitor (CFF). It helps to improve the loop stability if needed.
More detailed discussion on the optimization for stability versus transient response can be found in the
Optimizing Transient Response of Internally Compensated DC-DC Converter With Feedforward Capacitor
and Feedforward Capacitor to Improve Stability and Bandwidth With the TPS621-Family and TPS821-Family
application reports.
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EVM Configuration and Modification
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3.7 Output Voltage Setting
The TPS629206-Q1EVM is configured for external feedback as a default with an output voltage of 3.3 V set by
R1 and R2. Additionally, if the internal feedback (VSET) configuration is used, the user can cut the net tie NT1
located on the back of the board (shown in Figure 3-1). This will float the FB pin resulting in a 3.3-V output
voltage using the internal VSET. Resistors R1 and R2 can also be changed to set the output voltage between 0.6
V and 5.5 V. See the TPS629206-Q1 data sheet for recommended values. R2 was populated with 34 k such that
if the internal (VSET) is chosen while R1 is removed, the device will regulate to 1.8-V output voltage.
WARNING
If the output voltage is increased, make sure the voltage rating of output capacitor C5 is sized
appropriately.
Figure 3-1. Internal Feedback (VSET) Configuration Board Modification
3.8 Loop Response Measurement
The loop response can be measured after simply changing to the board. First, cut the net tie (NT2) and install
a 10-Ω 0603 resistor on the bottom of the board (shown in Figure 3-2). An AC signal (10-mV, peak-to-peak
amplitude is recommended) can be injected into the control loop across the added 10-Ω resistor.
Figure 3-2. Bode Plot Measurement Board Modification
4
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EVM Test Setup
4 EVM Test Setup
This section describes how to properly test the EVM.
4.1 Input and Output Connectors
Table 4-1. Input and Output Connector
Connector
J1
J2
Pins
Description
Pin 1 and Pin 2
VIN positive input for input supply
Pin 3 and Pin 4
S+ and S– input voltage sense. Input voltage measure points
Pin 5 and Pin 6
GND return for input supply
Pin 1 and Pin 2
VOUT output voltage connection
Pin 3 and Pin 4
S+ and S– output voltage sense. Output voltage measure points
Pin 5 and Pin 6
GND output return connection
4.2 Jumper Configuration
4.2.1 JP1 Enable
Table 4-2. Enable Pin Configuration
Jumper Short Location
Description
Pin 2 and Pin 3
Turn on the device as default.
Pin 3 and Pin 4
Turn off the device.
Pin 1 and Pin 2, Pin 3 and Pin 4
Set programmable Enable threshold voltage with R4 and R5.
Pin 3 and Pin 4
Pin1 can be used for external supply voltage with R4 and R5 resistor divider.
4.2.2 JP2 MODE/S-CONF
Table 4-3. MODE/S-CONF Pin Configuration
Jumper Short Location
Description
Pin 1 and Pin 3
Forced PWM, 2.5 MHz, external FB, output discharge enabled
Pin 3 and Pin 5
Auto PFM/PWM with AEE, 2.5 MHz, external FB, output discharge enabled
Pin 2 and Pin 4
52.3 k to GND, forced PWM, 2.5 MHz, internal FB (VSET), output discharge disabled
Pin 4 and Pin 6
42.2 k to GND, auto PFM/PWM, 2.5 MHz, internal FB (VSET), output discharge disabled
4.2.3 JP3 Power Good
The PGOOD output is on pin 1 of this header with a convenient ground on pin 2. If PG is not used, short pin 1
and pin 2 by a jumper.
4.2.4 JP4 PG Pullup Voltage
Table 4-4. PG Pullup Voltage Option
Jumper Short Location
Description
Pin 1 and Pin 2
PG pulls up to the output voltage.
Pin 2 and Pin 3
PG pulls up to the input voltage.
No jumper
JP4 pin2 can pull up to different external voltage. This external voltage must remain
below 18 V.
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Test Results
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5 Test Results
This section provides the test results of TPS629206-Q1EVM.
Figure 5-1. Efficiency, VIN = 12 V, VOUT = 3.3 V, FSW = 2.5 MHz
Figure 5-2. Load Regulation, VIN = 12 V, VOUT = 3.3 V, FSW = 2.5 MHz
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Test Results
Figure 5-3. Line Regulation, VIN = 5 V–17 V, VOUT = 3.3 V, IOUT = 0 A, and 600-mA FSW = 2.5 MHz
Figure 5-4. Loop Response Forced PWM VSET, VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA
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Test Results
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Figure 5-5. Output Voltage Ripple Auto PFM/PWM, VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A
Figure 5-6. Output Voltage Ripple Forced PWM, VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA
8
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Test Results
Figure 5-7. Input Voltage Ripple Forced PWM, VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA
Figure 5-8. Enable Start-Up Forced PWM, VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA
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Test Results
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Figure 5-9. Enable Shutdown Forced PWM, VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA
Figure 5-10. Enable Pre-Bias Start-Up Forced PWM, VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A
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Test Results
Figure 5-11. Load Transient Forced PWM VSET, VIN = 12 V, VOUT = 3.3 V, IOUT= 300 mA–600 mA, Slew Rate
= 1 A/μs
Figure 5-12. Thermal Performance Forced PWM, VIN = 12 V, VOUT = 3.3 V, IOUT = 600 mA, FSW = 2.5 MHz
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Board Layout
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6 Board Layout
This section provides the EVM board layout and illustrations.
Figure 6-1. Top Assembly
Figure 6-2. Top Layer
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Board Layout
Figure 6-3. Internal Layer 1
Figure 6-4. Internal Layer 2
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Board Layout
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Figure 6-5. Bottom Layer
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Schematic and Bill of Materials
7 Schematic and Bill of Materials
This section provides the EVM schematic and bill of materials (BOM).
7.1 Schematic
J3
1
2DNP
U1
1
2
3
4
5
6
VIN
3V to 17V
S+
SGND
6
VIN
SW
4
L1
SW
VOUT 1
DNPC2
10uF
C1
47uF
4.7uF
C4
100nF
EN
7
VOS
EN
FB/VSET
MODE 8
J1
MODE/S-CONF
PG
GND
2.2µH
1
FB/VSET
2
PG
ON
EN
OFF
C5
22uF
DNPC6
22µF
DNPC7
22uF
DNPC8
22uF
DNPC9
47uF
S+
SGND
J2
VOS
5
R1
154k
TPS629206QDRLRQ1
1
2
3
4
NT2
Net-Tie
VOUT
2
3
4
5
6
XGL3530-222MEC
C3
3
R4
549k
DNPC10
22pF
NT1
VIN
VOUT
1
2 PGPU
VIN
3
VOUT
PG_PULL-UP
VIN
Net-Tie
JP4
R2
34.0k
JP1
R5
100k
R3
100k
JP3
GND
PG
VIN
MODE
APFM
PG
GND
R6
JP2
FPWM
1
2
1
3
5
2
4
6
52.3k
R7
EXTFB
INTFB
GND
42.2k
GND
Figure 7-1. TPS629206-Q1EVM Schematic
7.2 Bill of Materials
Table 7-1. TPS629206-Q1EVM Bill of Materials
Designator
Qty
Value
Description
Package
Part Number
Manufacturer
C1
1
47 μF
CAP, TA, 47 μF, 35 V, ±10%, 0.3 Ω, SMD
7343-43
T495X476K035ATE300
Kemet
C3
1
4.7 μF
Cap Ceramic 4.7-μF 25-V X7R 10% Pad SMD
1206 +125°C Automotive T/R
1206
CGA5L1X7R1E475K160AC
TDK
C4
1
0.1 μF
CAP, CERM, 0.1 μF, 25 V, ±10%, X7R, 0603
0603
C0603C104K3RACTU
Kemet
C5
1
22 μF
CAP, CERM, 22-μF, 6.3 V, ±20%, X7T, AEC-Q200 0805
Grade 1, 0805
GCM21BD70J226ME36L
MuRata
J1, J2
2
Header, 2.54 mm, 6 × 1, Gold, TH
Header, 2.54 mm, 6 × 61300611121
1, TH
Wurth Elektronik
JP1
1
Header, 2.54 mm, 4 × 1, Gold, TH
Header, 2.54 mm, 4 × 61300411121
1, TH
Wurth Elektronik
JP2
1
Header, 2.54 mm, 3 × 2, Gold, TH
Header, 2.54 mm, 3 × 61300621121
2, TH
Wurth Elektronik
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Schematic and Bill of Materials
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Table 7-1. TPS629206-Q1EVM Bill of Materials (continued)
Designator
Qty
JP3
Value
Description
Package
1
Header, 2.54 mm, 2 × 1, Gold, TH
Header, 2.54 mm, 2 × 61300211121
1, TH
Wurth Elektronik
JP4
1
Header, 2.54 mm, 3 × 1, Gold, TH
Header, 2.54 mm, 2 × 61300311121
1, TH
Wurth Elektronik
L1
1
Molded Power Inductor, Shielded, 2.2-μH 20%,
7.2A, 23 mΩ DCR Max, AEC-Q200, T/R
SMT_IND_3MM2_3M XGL3530-222MEC
M5
Coilcraft
LBL1
1
Thermal Transfer Printable Labels, 0.650" W ×
0.200" H - 10,000 per roll
PCB Label 0.650 ×
0.200 inch
THT-14-423-10
Brady
R1
1
154 k
RES, 154 k, 1%, 0.1 W, 0603
0603
RC0603FR-07154KL
Yageo
R2
1
34.0 k
RES, 34.0 k, 1%, 0.1 W, 0603
0603
RC0603FR-0734KL
Yageo
R3, R5
2
100 k
RES, 100 k, 1%, 0.1 W, 0603
0603
RC0603FR-07100KL
Yageo
R4
1
549 k
RES, 549 k, 1%, 0.1 W, 0603
0603
RC0603FR-07549KL
Yageo
R6
1
52.3 k
RES, 52.3 k, 1%, 0.1 W, 0603
0603
RC0603FR-0752K3L
Yageo
R7
1
42.2 k
RES, 42.2 k, 1%, 0.1 W, 0603
0603
U1
1
C2
0
C6
2.2 μH
Part Number
Manufacturer
RC0603FR-0742K2L
Yageo
3-V to 17-V, Synchronous Buck Converters in 1.6- SOT583
mm × 2.1-mm SOT583 Package
TPS629206QDRLRQ1
Texas Instruments
10 μF
CAP, CERM, 10 uF, 25 V, ±20%, X7R, 1206_190
C3216X7R1E106M160AE
TDK
0
22 μF
CAP, CERM, 22 µF, 6.3 V, ±20%, X7T, AEC-Q200 0805
Grade 1, 0805
CGA4J1X7T0J226M
TDK
C7, C8
0
22 μF
CAP, CERM, 22 μF, 10 V, ±20%, X7S, 0805
0805
C2012X7S1A226M125AC
TDK
C9
0
47 μF
CAP, CERM, 47 μF, 6.3 V, ±20%, X7R, 1210
1210
GRM32ER70J476ME20L
MuRata
C10
0
22 pF
CAP, CERM, 22 pF, 50 V, ±5%, C0G/NP0, 0603
0603
GRM1885C1H220JA01D
MuRata
J3
0
Header, 2.54 mm, 2 × 1, Gold, TH
Header, 2.54 mm, 2 × 61300211121
1, TH
16
1206_190
TPS629206-Q1 Buck Converter Evaluation Module User's Guide
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Schematic and Bill of Materials
8 References
Texas Instruments, TPS629206-Q1, 3-V to 17-V, 600-mA Low Iq Buck Converter in SOT583 Package data sheet
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