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TPS65055
SLVS844A – SEPTEMBER 2008 – REVISED JUNE 2015
TPS65055 2.25-MHz Dual Step-Down Converter With 4 Low-Input Voltage LDOs
1 Features
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Up to 95% Efficiency
Output Current for DCDC Converters 2 × 0.6 A
Two Selectable Fixed Output Voltages 1 V and
1.2 V for DCDC2
VIN Range for DCDC Converters From 2.5 V to 6
V
2.25-MHz Fixed-Frequency Operation
Power Save Mode at Light Load Current
180° Out-of-Phase Operation
Output Voltage Accuracy in PWM Mode ±1%
Low Ripple PFM Mode
Total Typical 32-μA Quiescent Current for Both
DC-DC Converters
100% Duty Cycle for Lowest Dropout
2 General-Purpose 400 mA High PSRR LDOs
2 General-Purpose 200 mA High PSRR LDOs
VIN Range for LDOs From 1.5 V to 6.5 V
Digital Voltage Selection for the LDOs
I2C Compatible Interface
Available in a 4 mm × 4 mm 32-Pin QFN Package
2 Applications
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Cell Phones, Smart Phones
WLAN
PDAs, Pocket PCs
OMAP™ and Low Power DSP Supplies
XScale
Portable Media Players
Digital Cameras
The device allows the use of small inductors and
capacitors to achieve a small solution size.
The TPS65055 provides an output current of up to
0.6 A on each DC-DC converter.
The TPS65055 also integrates two 400-mA LDO and
two 200-mA LDO voltage regulators, which can be
turned on/off using separate enable pins on each
LDO. Each LDO operates with an input voltage range
from 1.5 V to 6.5 V allowing them to be supplied from
one of the step-down converters or directly from the
main battery. Two digital input pins are used to set
the output voltage of the LDOs from a set of 9
different combinations for LDO1 to LDO4.
Additionally, the converters can be controlled by an
I2C compatible interface.
The TPS65055 is available in a small 32-pin leadless
package (4 mm × 4 mm QFN) with a 0.4-mm pitch.
Device Information(1)
PART NUMBER
TPS65055
The TPS65055 device is an integrated Power
Management IC for applications powered by one LiIon or Li-Polymer cell, which require multiple power
rails.
The TPS65055 provides two highly efficient,
2.25 MHz step-down converters targeted at providing
the core voltage and I/O voltage in a processor-based
system. Both step-down converters enter a low power
mode at light load for maximum efficiency across the
widest possible range of load currents.
For low noise applications the device can be forced
into fixed frequency PWM mode using the I2C
compatible interface. In shutdown mode, current
consumption is reduced to less than 1 μA.
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VINDCDC1/2
1R
Vbat
VCC
10 mF
1 mF
2.2 mH
DCDC1 (I/O)
ENABLE
SCLK
SDAT
DEFLDO1
DEFLDO2
ENABLE
1 V / 1.2 V
ENABLE
VIN
ENABLE
VIN
ENABLE
ENABLE
L1
EN_DCDC1
STEP-DOWN
CONVERTER
600 mA
VDCDC1
10 mF
PGND1
Interface
L2
DCDC2 (core)
VIN
3 Description
PACKAGE
VQFN (32)
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
DEFDCDC2
VDCDC2
2.2 mH
10 mF
PGND2
VLDO1
VIN_LDO1
VLDO1
EN_LDO1
4.7 mF
400 mA LDO
VIN_LDO2
VLDO2
EN_LDO2
VLDO2
4.7 mF
400 mA LDO
VIN_LDO3/4
VLDO3
EN_LDO3
200 mA LDO
EN_LDO4
VLDO4
VLDO3
2.2mF
BP
0.1 mF
VLDO4
2.2 mF
200 mA LDO
RST
I/O voltage
R19
I/O voltage
DPD
R20
discharge
THRESHOLD
comparator
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65055
SLVS844A – SEPTEMBER 2008 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
5
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 17
8.6 Register Maps ......................................................... 20
9
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Application ................................................. 31
10 Power Supply Recommendations ..................... 35
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 36
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2008) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SLVS844A – SEPTEMBER 2008 – REVISED JUNE 2015
5 Pin Configuration and Functions
VDCDC1
PGND1
L1
VINDCDC1/2
L2
PGND2
VDCDC2
DEFDCDC2
RSM Package
32-Pin VQFN
Top View
24 23 22 21 20 19 18 17
EN_DCDC1
EN_DCDC2
EN_LDO1
EN_LDO2
VINLDO1
VLDO1
SDAT
SCLK
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
TPS65055
2 3
4
5
6
7
8
BP
AGND
Vcc
VINLDO2
VLDO2
DEFLDO2
threshold
RST
1
EN_LDO4
EN_LDO3
discharge
DPD
VLDO4
VINLDO3/4
VLDO3
DEFLDO1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
2
I
Analog GND, connect to PGND and PowerPAD
BP
1
I
Input for bypass capacitor for internal reference
DEF_DCDC2
17
I
Select pin of converter 2 output voltage. High = 1 V, low = 1.2 V
DEFLDO1
9
I
Digital input, used to set the default output voltage of LDO1 to LDO4; LSB
DEFLDO2
6
I
Digital input, used to set the default output voltage of LDO1 to LDO4; MSB
discharge
14
O
Open-drain output driven by the signal at the threshold input
DPD
13
O
Open-drain active low output; low after UVLO event
EN_DCDC1
25
I
Enable input for converter1, active high
EN_DCDC2
26
I
Enable input for converter2, active high
EN_LDO1
27
I
Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
EN_LDO2
28
I
Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
EN_LDO3
15
I
Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
EN_LDO4
16
I
Enable input for LDO4. Logic high enables the LDO, logic low disables the LDO.
L1
22
O
Switch pin of converter1. Connected to inductor
L2
20
O
Switch pin of converter 2. Connected to inductor.
PGND1
23
I
GND for converter 1
PGND2
19
I
GND for converter 2
RST
8
O
Open-drain active low output; low after UVLO event
SCLK
32
I
Clock input for the I2C compatible interface.
SDAT
31
I/O
threshold
7
I
Input to comparator driving the discharge output. If the input voltage at threshold is < 0.8 V, the discharge
output is actively pulled low.
Vcc
3
I
Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected
to the same voltage supply as VINDCDC1/2.
Data line for the I2C compatible interface.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
VDCDC1
24
I
Feedback voltage sense input, connect directly to Vout1
VDCDC2
18
I
Feedback voltage sense input, connect directly to Vout2
VINDCDC1/2
21
VINLDO1
29
I
Input voltage for LDO1
VINLDO2
4
I
Input voltage for LDO2
VINLDO3/4
11
I
Input voltage for LDO3 and LDO4
VLDO1
30
O
Output voltage of LDO1
VLDO2
5
O
Output voltage of LDO2
VLDO3
10
O
Output voltage of LDO3
VLDO4
12
O
Output voltage of LDO4
PowerPAD™
–
Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same
voltage supply as VCC.
Connect to GND
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Input voltage range on all pins except A/PGND, EN_LDO1 pins with respect to AGND
–0.3
7
V
Input voltage range on EN_LDO1 pins with respect to AGND
–0.3
VCC+0.5
V
Output voltage range on LDO1, LDO2, LDO3, LDO4 pins with respect to AGND
–0.3
4
V
Current at VINDCDC1/2, L1, PGND1, L2, PGND2
1800
mA
Current at all other pins
1000
mA
Continuous total power dissipation
See Dissipation Ratings
TA
Operating free-air temperature
85
°C
TJ
Maximum junction temperature
125
°C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds
260
°C
150
°C
Tst
(1)
–40
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This device
contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have
been qualified to protect this device against electrostatic discharges; HBM according to EIA/JESD22-A114-B: 1.5 kV; and CDM
according EIA/JESD22C101C: 500 V, however, it is advised that precautions should be taken to avoid application of any voltage higher
than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
4
MAX
UNIT
VINDCDC1/2
Input voltage range for step-down converters
2.5
6
V
VDCDC1
Output voltage range for VDCDC1 step-down converter
0.6
VINDCDC1
V
VDCDC2
Output voltage range for VDCDC2 step-down converter
0.6
VINDCDC2
V
VINLDO1, VINLDO2,
VINLDO3/4
Input voltage range for LDOs
1.5
6.5
V
VLDO1-3
Output voltage range for LDO1 and LDO3
0.8
2.8
V
VLDO2-4
Output voltage range for LDO2 and LDO4
1
3
V
IOUTDCDC1
Output current at L1
L1
Inductor at L1 (1)
1.5
CINDCDC1/2
Input capacitor at VINDCDC1/2 (1)
22
COUTDCDC1
Output capacitor at VDCDC1 (1)
10
22
IOUTDCDC2
Output current at L2
L2
Inductor at L2 (1)
1.5
2.2
μH
COUTDCDC2
Output capacitor at VDCDC2 (1)
10
22
μF
600
μH
μF
μF
600
(1)
mA
2.2
mA
CVCC
Input capacitor at VCC
1
μF
Cin1-2
Input capacitor at VINLDO1/2 (1)
2.2
μF
Cin3-4
Input capacitor at VINLDO3/4 (1)
2.2
μF
(1)
2.2
COUT1-2
Output capacitor at VLDO1-4
ILDO1,2
Output current at VLDO1,2
ILDO3,4
Output current at VLDO3,4
TA
Operating ambient temperature
–40
TJ
Operating junction temperature
–40
RCC
Resistor from battery voltage to Vcc used for filtering (2)
(1)
(2)
μF
1
400
mA
200
mA
85
°C
125
°C
10
Ω
See Application and Implementation for more details.
Up to 2 mA can flow into Vcc when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted
accordingly.
6.4 Thermal Information
TPS65055
THERMAL METRIC (1)
RSM [VQFN]
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
37.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
30.1
°C/W
RθJB
Junction-to-board thermal resistance
7.8
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
7.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VIN = 3.6 V, EN = VIN, MODE = GND, L = 2.2 μH, COUT = 22 μF, TA = –40°C to 85°C, Typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Vcc
Input voltage range
2.5
6
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5
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Electrical Characteristics (continued)
VIN = 3.6 V, EN = VIN, MODE = GND, L = 2.2 μH, COUT = 22 μF, TA = –40°C to 85°C, Typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
30
40
μA
40
55
μA
One converter, IOUT = 0 mA, PFM mode enabled; device not
switching, EN_DCDC1 = VIN or EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = VIN
190
260
μA
One converter, IOUT = 0 mA,
Switching with no load, PWM operation EN_DCDC1 = VIN or
EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND
0.85
mA
Two converters, IOUT = 0 mA,
Switching with no load, PWM operation EN_DCDC1 = VIN AND
EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND
1.25
mA
One converter, IOUT = 0 mA. PFM mode enabled; device not
switching, EN_DCDC1 = VIN or EN_DCDC2 = VIN;
EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND
Operating quiescent current
Two converters, IOUT = 0 mA, PFM mode device not switching,
Total current into VCC, VINDCDC1/2, VINLDO1, EN_DCDC1 = VIN and EN_DCDC2 = VIN;
VINLDO2, VINLDO3/4
EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND
IQ
IQ
Operating quiescent current into VCC
UNIT
I(SD)
Shutdown current
EN_DCDC1 = EN_DCDC2 = GND
EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = GND
18
22
μA
V(UVLO)
Undervoltage lockout threshold for DCDC
converters and LDOs
Voltage at VCC
1.8
2
V
1.2
VCC
V
0
0.4
V
1
μA
EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4
VIH
High-level input voltage, SDAT, SCLK,
EN_DCDC1, EN_DCDC2, DEFDCDC2,
EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4
VIL
Low-level input voltage SDAT, SCLK,
EN_DCDC1, EN_DCDC2, EN_LDO1,
EN_LDO2, EN_LDO3, EN_LDO4, DEFDCDC2
IIN
Input bias current SDAT, SCLK,
EN_DCDC1, EN_DCDC2, DEFDCDC2,
DEFLDO1, DEFLDO2, EN_LDO1, EN_LDO2,
EN_LDO3, EN_LDO4
VIH
DEFLDO1, DEFLDO2
VCC = 2.5 V
VIL
DEFLDO1, DEFLDO2
VCC = 6.5 V
RPD
Pulldown resistor at DEFLDO1, DEFLDO2 for
LOW signal
Pulled to GND
1
kΩ
RPU
Pullup resistor at DEFLDO1, DEFLDO2 for
HIGH signal
Pulled to VCC
1
kΩ
0.01
1.0
V
0.38
V
RGNDop Resistance at DEFLDO1, DEFLDO2 to GND to
en
detect open state
10
MΩ
RVCCop
en
20
MΩ
Resistance at DEFLDO1, DEFLDO2 to Vcc to
detect open state
POWER SWITCH
DCDC1,
DCDC2
VINDCDC1/2 = 3.6 V
280
VINDCDC1/2 = 2.5 V
400
630
rDS(on)
P-channel MOSFET on
resistance
ILD_PMOS
P-channel leakage current
rDS(on)
N-channel MOSFET on
resistance
ILK_NMOS
N-channel leakage current
I(LIMF)
Forward current limit PMOS
(high-side) and NMOS (low
side)
TSD
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
VDS = 6 V
DCDC1,
DCDC2
1
VINDCDC1/2 = 3.6 V
220
VINDCDC1/2 = 2.5 V
320
VDS = 6 V
DCDC1
DCDC2
2.5 V ≤ VIN ≤ 6 V
450
7
10
0.85
1.0
1.15
0.85
1.0
1.15
mΩ
μA
mΩ
μA
A
OSCILLATOR
fSW
6
Oscillator frequency
2.025
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2.25
2.475
MHz
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Electrical Characteristics (continued)
VIN = 3.6 V, EN = VIN, MODE = GND, L = 2.2 μH, COUT = 22 μF, TA = –40°C to 85°C, Typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOUT
VOUT
Output voltage range
DC output voltage accuracy
0.8
DCDC1,
DCDC2 (1)
(2)
VIN
VIN = 2.5 V to 6 V, Mode = GND,
PFM operation, 0 mA < IOUT < IOUTMAX
–1.5
%
0%
3.5%
VIN = 2.5 V to 6 V, Mode = VIN,
PWM operation, 0 mA < IOUT < IOUTMAX
–1.5
%
0%
1.5%
V
ΔVOUT
Power save mode ripple voltage
25
mVPP
tStart
Start-up time
Time from active EN to start switching
170
μs
tRamp
VOUT Ramp up time
Time to ramp from 5% to 95% of VOUT
750
μs
RDIS
Internal discharge resistor at L1, L2
VOL
RST, DPD, discharge output low voltage
IOUT = 1 mA, PFM = GND, Bandwidth = 20 MHz
IOL = 1 mA, Vthreshold < 0.8 V
0.3
RST, DPD sink current
IOL
discharge sink current
Vth
Ω
350
RST, DPD, discharge output leakage current
Vthreshold > 0.8 V, RST and DPD outputs turned off (internal
NMOS in high impedance state)
Vthreshold voltage
Voltage rising
Hysteresis on threshold
Voltage decreasing
V
1
mA
10
mA
0.78
0.01
1
μA
0.8
0.82
V
80
mV
VLDO1, VLDO2, VLDO3 and VLDO4 LOW DROPOUT REGULATORS
VINLDO
Input voltage range for LDO1, LDO2, LDO3,
LDO4
1.5
6.5
V
VLDO1
LDO1 output voltage range
0.8
2.8
V
VLDO2
LDO2 output voltage range
1.2
3
V
VLDO3
LDO3 output voltage
0.8
2.8
V
VLDO4
LDO4 output voltage range
1.2
3
V
Maximum output current for LDO1,LDO2
400
Maximum output current for LDO3, LDO4
200
IO
mA
LDO1 and LDO2 short-circuit current limit
VLDO1 = GND, VLDO2 = GND
800
mA
LDO3 and LDO4 short-circuit current limit
VLDO3 = GND, VLDO4 = GND
400
mA
Dropout voltage at LDO1
IO = 250 mA, VINLDO = 1.8 V
600
mV
Dropout voltage at LDO2
IO = 400 mA, VINLDO = 3.3 V
450
mV
Dropout voltage at LDO3, LDO4
IO = 200 mA, VINLDO = 1.8 V
280
mV
Output voltage accuracy for LDO1, LDO2,
LDO3
IO = 10 mA
Leakage current from VINLDOx to VLDOx
LDO enabled, VINLDOx = 6.5 V; VO = 1.0 V, T = 140°C
Output voltage accuracy for LDO1, LDO2,
LDO3, LDO4
IO = 10 mA
–2%
1%
Line regulation for LDO1, LDO2, LDO3, LDO4
VINLDO1,2 = VLDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V,
VINLDO3,4 = VLDO3,4 + 0.5 V (minimum 2.5 V) to 6.5 V,
IO = 10 mA
–1%
1%
Load regulation for LDO1, LDO2, LDO3, LDO4
IO = 0mA to 400 mA for LDO1, LDO2
IO = 0mA to 200 mA for LDO3, LDO4
–1%
1%
Regulation time for LDO1, LDO2, LDO3, LDO4
Load change from 10% to 90%
10
μs
PSRR
Power supply rejection ratio
f = 10 kHz; IO = 50 mA; VI = VO + 1 V
70
dB
RDIS
Internal discharge resistor at VLDO1, VLDO2,
VLDO3, VLDO4
350
Ω
TSD
Thermal shutdown
Increasing junction temperature
140
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
I(SC)
(1)
(2)
–2%
1%
μA
3
Output voltage specification does not include tolerance of external voltage programming resistors.
In power save mode, PWM operation is typically entered at IPSM = VIN/32 Ώ.
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6.6 Dissipation Ratings
(1)
PACKAGE
RθJA
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
RSM (1)
58 K/W
1.7 W
17 mW/K
0.95 W
0.68 W
The thermal resistance junction-to-case of the RSM package is 4 K/W measured on a high K board.
6.7 Typical Characteristics
Table 1. Table Of Graphs
FIGURE
η
Efficiency DCDC1 (VO = 2.1 V)
vs Load current / PWM mode
Figure 1
η
Efficiency DCDC1 (VO = 2.1 V)
vs Load current / PFM mode
Figure 2
η
Efficiency DCDC2 (VO = 1.575 V)
vs Load current / PWM mode
Figure 3
η
Efficiency DCDC2 (VO = 1.575 V)
vs Load current / PFM mode
Figure 4
η
Efficiency DCDC2 (VO = 1.2 V)
vs Load current / PWM mode
Figure 5
η
Efficiency DCDC2 (VO = 1.2 V)
vs Load current / PFM mode
Figure 6
Output voltage ripple in PFM mode
Scope plot
Figure 7
Output voltage ripple in PWM mode
Scope plot
Figure 8
Startup timing DCDC1, DCDC2, LDO1
Scope plot
Figure 9
Startup timing LDO1, LDO2, LDO3, LDO4
Scope plot
Figure 10
Load transient response DCDC1; PWM
Scope plot
Figure 11
Load transient response DCDC1; PFM
Scope plot
Figure 12
Load transient response DCDC2; PWM
Scope plot
Figure 13
Load transient response DCDC2;PFM
Scope plot
Figure 14
Line transient response DCDC1 (VO = 2.1 V)
Scope plot
Figure 15
Line transient response DCDC2 (VO = 1.2 V)
Scope plot
Figure 16
Load transient response LDO1
Scope plot
Figure 17
Load transient response LDO4
Scope plot
Figure 18
Line transient response LDO1
Scope plot
Figure 19
100
100
90
80
TA = 25°C,
PWM Mode,
VO = 2.1 V
90
3V
80
3V
70
60
Efficiency - %
Efficiency - %
70
3.6 V
50
4.2 V
40
60
5V
40
30
5V
20
0.001
0.01
0.1
IO - Output Current - A
1
Figure 1. Efficiency DCDC1 (VO = 2.1 V) vs Load Current /
PWM Mode
8
TA = 25°C,
PWM/PFM Mode,
VO = 2.1 V
10
10
0
0.0001
4.2 V
50
30
20
3.6 V
0
0.0001
0.001
0.01
0.1
IO - Output Current - A
1
Figure 2. Efficiency DCDC1 (VO = 2.1 V) vs Load Current /
PFM Mode
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100
100
TA = 25°C,
90
PWM Mode,
80 VO = 1.575 V
3V
90 2.5 V
80
5V
4.2 V
70
Efficiency - %
Efficiency - %
70
60
4.2 V
50
3.6 V
40
3.3 V
30
60
50
40
30
5V
3V
20
10
0
0.0001
0.001
0.01
0.1
IO - Output Current - A
0
0.0001
1
Figure 3. Efficiency DCDC2 (VO = 1.575 V) vs Load Current /
PWM Mode
0.001
0.01
0.1
IO - Output Current - A
1
Figure 4. Efficiency DCDC2 (VO = 1.575 V) vs Load Current /
PFM Mode
100
100
80
TA = 25°C,
PWM/PFM Mode,
VO = 1.575 V
20
6V
10
90
3.6 V
3.3 V
TA = 25°C,
PWM Mode,
VO = 1.2 V
90
80
3V
70
60
5V
50
4.2 V
40
30
20
3.6 V
Efficiency - %
Efficiency - %
70
60
50
40
5V
30
3.6 V
20
3V
10
10
0
0.0001
4.2 V
0.001
0.01
0.1
IO - Output Current - A
1
Figure 5. Efficiency DCDC2 (VO = 1.2 V) vs Load Current /
PWM Mode
0
0.0001
TA = 25°C,
PWM/PFM Mode,
VO = 1.2 V
0.001
0.01
0.1
IO - Output Current - A
1
Figure 6. Efficiency DCDC2 (VO = 1.2 V) vs Load Current /
PFM Mode
TEST CONDITIONS
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
VDCD1 = 2.1 V
VDCD2 = 1.2 V
VIN = 3.6 V
TA = 25°C
VDCD1 = 2.1 V
VDCD2 = 1.2 V
Load DCDC1 = 600 mA
Load DCDC2 = 600 mA
Load DCDC1 = 80 mA
Load DCDC2 = 80 mA
ENDCDC1 = High
ENDCDC2 = High
ENLDO1 = Low
ENLDO2 = Low
ENLDO3 = Low
ENLDO4 = Low
ENDCDC1 = High
ENDCDC2 = High
ENLDO1 = Low
ENLDO2 = Low
ENLDO3 = Low
ENLDO4 = Low
CH1: VDCD1 (Black)
CH2: VDCD2 (Green)
CH3: Inductor Current DCDC2 (Red)
CH4: Inductor Current DCDC1 (Blue)
CH1: VDCD1 (Black)
CH2: VDCD2 (Green)
CH3: Inductor Current DCDC2 (Red)
CH4: Inductor Current DCDC1 (Blue)
Figure 7. Output Voltage Ripple in PFM Mode
Figure 8. Output Voltage Ripple in PWM Mode
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TEST CONDITIONS
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
VDCD1 = 2.1 V
VDCD2 = 1.2 V
VIN = 3.6 V
TA = 25°C
VLDO1 = 3.3 V
VLDO2 = 2.85 V
VLDO3 = 1.1 V
VLDO3 = 1.3 V
Load DCDC1 = 600 mA
Load DCDC2 = 600 mA
Load Current = 100 mA each
ENDCDC1 = 0 V to 3.6 V
ENDCDC2 = 0 V to 3.6 V
ENLDO1 = 0 V to 3.6 V
ENLDO2 = Low
ENLDO3 = Low
ENLDO4 = Low
ENLDO1 = 0 V to 3.6 V
ENLDO2 = 0 V to 3.6 V
ENLDO3 = 0 V to 3.6 V
ENLDO4 = 0 V to 3.6 V
R1: Enable (Blue)
CH1: VDCD1 (Black)
CH2: VDCD2 (Green)
CH3: VLDO3 (Red)
CH4: VLDO4 (Turquoise)
CH4: EN_DCDC1/2, ENLDO1 (Blue)
CH3: VLDO1 (Red)
CH2: VDCDC2 (Green)
CH1: VDCDC1 (Black)
Figure 9. Startup Timing DCDC1, DCDC2, and LDO1
Figure 10. Startup Timing LDO1, LDO2, LDO3, and LDO4
TEST CONDITIONS
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
VIN = 3.6 V
TA = 25°C
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
Figure 11. Load Transient Response DCDC1; PWM
Figure 12. Load Transient Response DCDC1; PFM
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
Figure 13. Load Transient Response DCDC2; PWM
10
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
Figure 14. Load Transient Response DCDC2; PFM
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TEST CONDITIONS
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
VIN = 3.3 V to 4.2 V to 3.3 V
TA = 25°C
Load Current = 600 mA
VDCDC2 = 2.1 V
Load Current = 600 mA
VDCDC2 = 2.1 V
CH1: Input Voltage (Black)
CH2: Output Voltage (Green)
CH1: Input Voltage (Black)
CH2: Output Voltage (Green)
Figure 15. Line Transient Response DCDC1 (VO = 2.1 V)
Figure 16. Line Transient Response DCDC2 (VO = 1.2 V)
TEST CONDITIONS
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
VIN = 3.6 V
TA = 25°C
Load Current = 40 mA to 360 mA
VLDO1 = 1.2 V
Load Current = 20 mA to 180 mA
VLDO4 = 2.8 V
CH1: VLDO1 (Green)
CH2: Load Current (Blue)
CH1: VLDO4 (Green)
CH2: Load Current (Blue)
Figure 17. Load Transient Response LDO1
Figure 18. Load Transient Response LDO4
TEST CONDITIONS
VIN = 3.6 V to 4.2 V to 3.6 V
TA = 25°C
Load Current = 100 mA
VLDO1 = 1.2 V
CH1: VINLDO1 (Black)
CH2: VLDO1 (Green)
Figure 19. Line Transient Response LDO1
7 Parameter Measurement Information
The measurements for the graphs were taken using the EVM in the configuration shown in Functional Block
Diagram. The inductors used were Coilcraft LPS3010.
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8 Detailed Description
8.1 Overview
The TPS65055 device includes two synchronous step-down converters. The converters operate with typically
2.25-MHz fixed-frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load
currents the converters automatically enter power save mode and operate with PFM (pulse frequency
modulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feedforward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator also turns off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead time preventing shoot through current, the N-channel MOSFET rectifier is
turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off
the N-channel rectifier and turning on the P-channel switch.
The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase
shift between converter 1 and converter 2 decreases the input RMS current. Therefore smaller input capacitors
can be used.
8.1.1 DCDC1 Converter
The converter 1 output voltage is set by the status of the DEFLDO1 and DEFLDO2 pins. The pins can be pulled
low, pulled high or left floating to allow 9 different logic states. See the description for the LDOs for further
details. With the TPS65055 it is also possible to change the output voltage of converter DCDC1 through the I2C
compatible interface. The VDCDC1 pin must be directly connected to VOUT1 and no external resistor network may
be connected.
8.1.2 DCDC2 Converter
The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converter
output voltage can be selected through the DEFDCDC2 pin or the I2C compatible interface.
The DEFDCDC2 pin can either be connected to GND, or to VCC. The converter 2 defaults to 1 V or 1.2 V
depending on the logic level of the DEFDCDC2 pin. If DEFDCDC2 is tied to ground, the default is 1.2 V; if it is
tied to VCC, the default is 1 V.
With the TPS65055, the voltage can also be changed using the I2C registers – see Application and
Implementation for details.
12
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8.2 Functional Block Diagram
VINDCDC1/2
1R
Vbat
VCC
10 mF
1 mF
2.2 mH
DCDC1 (I/O)
ENABLE
SCLK
SDAT
DEFLDO1
DEFLDO2
STEP-DOWN
CONVERTER
600 mA
1 V / 1.2 V
VIN
ENABLE
VIN
ENABLE
VIN
ENABLE
ENABLE
VDCDC1
10 mF
PGND1
Interface
L2
DCDC2 (core)
ENABLE
L1
EN_DCDC1
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
DEFDCDC2
VDCDC2
2.2 mH
10 mF
PGND2
VLDO1
VIN_LDO1
VLDO1
EN_LDO1
4.7 mF
400 mA LDO
VIN_LDO2
VLDO2
EN_LDO2
VLDO2
4.7 mF
400 mA LDO
VIN_LDO3/4
VLDO3
EN_LDO3
200 mA LDO
EN_LDO4
VLDO4
VLDO3
2.2mF
BP
0.1 mF
VLDO4
2.2 mF
200 mA LDO
I/O voltage
R19
RST
I/O voltage
R20
DPD
discharge
THRESHOLD
comparator
AGND
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8.3 Feature Description
8.3.1 Power Save Mode
Power save mode is enabled per default and can be disabled using the I2C compatible interface. If the load
current decreases, the converters enter power save mode operation automatically. During power save mode the
converters operate with reduced switching frequency in PFM mode and with a minimum quiescent current to
maintain high efficiency. The converter positions the output voltage typically 1% above the nominal output
voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step.
To optimize converter efficiency at light load the average current is monitored, and if in PWM mode the inductor
current remains below a certain threshold, then power save mode is entered. The typical threshold can be
calculated according to:
Equation 1: Average output current threshold to enter PFM mode
VINDCDC
IPFM_enter =
32 W
(1)
Equation 2: Average output current threshold to leave PFM mode
VINDCDC
IPSMDCDCleave =
24 W
(2)
During power save mode, the output voltage is monitored with a comparator. As the output voltage falls below
the skip comparator threshold (skip comp) of VOUTnominal +1%, the P-channel switch turns on and the converter
effectively delivers a constant current as defined above. If the load is below the delivered current, then the output
voltage rises until the same threshold is crossed again, whereupon all switching activity ceases, hence reducing
the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load
current is greater than the delivered current, then the output voltage falls until it crosses the skip comparator low
(skip comp low) threshold set to 1% below nominal Vout, whereupon power save mode is exited and the
converter returns to PWM mode.
These control methods reduce the quiescent current typically to 12 μA per converter and the switching frequency
to a minimum achieving the highest converter efficiency. PFM mode operates with very low output voltage ripple.
The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values
makes the output ripple tend to zero.
8.3.1.1 Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
activated in power save mode operation when the converter runs in PFM mode. It provides more headroom for
both, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transient
behavior.
At light loads, in which the converter operates in PFM mode, the output voltage is regulated typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During a
load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
Smooth
increased load
+1%
PFM Mode
light load
Fast Load Transient
PFM Mode
light load
VOUT_NOM
PWM Mode
Medium/Heavy Load
PWM Mode
Medium/Heavy Load
COMP_LOW threshold
Figure 20. Dynamic Voltage Positioning
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Feature Description (continued)
8.3.1.2 Soft Start
The two converters have an internal soft-start circuit that limits the inrush current during start-up. During soft
start, the output voltage ramp up is controlled as shown in Figure 21.
EN
95%
5%
VOUT
tStart
tRAMP
Figure 21. Soft Start
8.3.1.3 100% Duty Cycle Low Dropout Operation
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery
voltage range, for example. The minimum input voltage to maintain regulation depends on the load current and
output voltage and can be calculated as:
Vinmin = Voutmax + Ioutmax ´ (RDSonmax + RL )
where
•
•
•
•
Ioutmax = maximum output current plus inductor ripple current.
RDSonmax = maximum P-channel switch RDSon.
RL = DC resistance of the inductor.
Voutmax = nominal output voltage plus maximum output voltage tolerance.
(3)
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current maintaining high efficiency.
In power save mode the converter only operates when the output voltage trips below its nominal output voltage.
It ramps up the output voltage with several pulses and goes again into power save mode once the output voltage
exceeds the nominal output voltage.
8.3.1.4 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery and disables the converters and LDOs. The undervoltage lockout threshold is
typically 1.8 V.
8.3.2 Enable
The DC-DC converters and the LDOs are enabled using external enable pins or enable bits with the I2C
compatible interface. The signal of the enable pin and the enable bit are logically XORed to generate the enable
signal to the converter or LDO. There is one enable pin and one enable bit for each of the LDOs or DCDC
converters, which allows start-up of each converter independently. If EN_DCDC1, EN_DCDC2, EN_LDO1,
EN_LDO2, ENLDO3, or EN_LDO4 are set to high, the corresponding converter starts up with soft start as
previously described. The converters and LDOs can also be enabled by setting the enable bits for each of the
LDOs or DCDC converters in register REG_CTRL. See the register description for more details.
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Feature Description (continued)
Disabling the DC-DC converter or LDO forces the device into shutdown with a shutdown quiescent current as
defined in Electrical Characteristics. In this mode, the P- and N-Channel MOSFETs are turned off, and the entire
internal control circuitry is switched off. For proper operation the enable pins must be terminated and must not be
left floating.
8.3.3 Discharge
The TPS65055 contains a comparator that supervises a voltage applied to the threshold pin and drives a opendrain NMOS according to the input level applied at threshold. If the input voltage at the threshold pin is lower
than 1 V, the open-drain NMOS at the discharge output is turned on, pulling the pin to GND. This circuitry is
functional as soon as the supply voltage at Vcc exceeds the undervoltage lockout threshold. Therefore the
TPS65055 has a shutdown current (all DC-DC converters and LDOs are off) of 9 μA to supply bandgap and
comparator.
Vbat
threshold
+
discharge
Vref = 1V
Vbat
threshold
discharge
Figure 22. Discharge
8.3.4 RST and DPD
The TPS65055 contains two open-drain outputs that are controlled by the I2C compatible interface. The RST and
DPD outputs are low (internal NMOS active) per default, once the undervoltage lockout threshold has been
exceeded. The status of these outputs can be changed using the REG_CTRL register. See Register Maps for
more details.
8.3.5 Short-Circuit Protection
All outputs are short-circuit protected with a maximum output current as defined in Electrical Characteristics.
8.3.6 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds typically 150°C for the DC-DC converters, the device goes into
thermal shutdown. In this mode, the P- and N-Channel MOSFETs are turned off. The device continues its
operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown
for one of the DC-DC converters disables both converters simultaneously.
The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO which may be
used to power an external voltage never heats up the device that high to turn off the DC-DC converters. If one
LDO exceeds the thermal shutdown temperature, all LDOs turn off simultaneously.
8.3.7 LDO1 to LDO4
The low dropout voltage regulators are designed to operate well with low value ceramic input and output
capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280
mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1,
ENLDO2, EN_LDO3, and EN_LDO4 pin EXOR with a bit in register REG_CTRL (Reg#02h).
16
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Feature Description (continued)
8.3.7.1 Default Voltage Setting for LDOs and DCDC1
In the TPS65055, the output voltage of the LDOs and of DCDC1 is set using two pins, DEFLDO1 and DEFLDO2.
These pins can either be connected to a logic low level, a logic high level, or left floating to define a set of output
voltages for LDO1 to LDO4 and DCDC1 according to the following table. The status of the DEFLDO pins is
latched after an undervoltage lockout event (UVLO) and sets the registers LDO_CTRL1, LDO_CTRL2, and
DEFDCDC1 accordingly. The output voltage of each LDO and DCDC1 can be changed later by reprogramming
these registers. See Register Maps for more details.
The TPS65055 default voltage options are adjustable with DEFLDO2 and DEFLDO1 according to the following
table:
Table 2. Voltage Table for LDOs and DCDC1
DEFLDO2
DEFLDO1
VLDO1
VLDO2
VLDO3
VLDO4
DCDC1
400mA LDO
400mA LDO
200mA LDO
200mA LDO
600mA
0
0
1.2 V
1.8 V
2.8 V
1.3 V
2.1 V
0
float
1.2 V
1.8 V
2.8 V
2.8 V
1.8 V
0
1
1.2 V
1.8 V
2.8 V
1.3 V
1.8 V
float
0
1.2 V
1.8 V
2.8 V
2.8 V
2.1 V
float
float
1.2 V
1.8 V
2.8 V
1.8 V
2.1 V
float
1
1.2 V
1.8 V
2.8 V
2.8 V
1.2 V
1
0
1.2 V
1.8 V
2.8 V
1.0 V
1.9 V
1
float
1.2 V
1.8 V
2.8 V
3.0 V
2.1 V
1
1
1.0 V
1.2 V
1.0 V
1.0 V
1.2 V
8.4 Device Functional Modes
The TPS6505x devices are either in the ON or the OFF mode. The OFF mode is entered when the voltage on
VCC is below the UVLO threshold, 1.8 V (typically). Once the voltage at VCC has increased above UVLO, the
device enters ON mode. In the ON mode, the DCDCs and LDOs are available for use.
8.5 Programming
8.5.1 Interface Specification
8.5.1.1 Serial Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above the UVLO threshold. The TPS65055 has a 7bit
address: 1001000, other addresses are available upon contact with the factory. Attempting to read data from
register addresses not listed in this section result in 00h being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65055 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65055 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge – related
clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the
end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave.
In this case, the slave TPS65055 device must leave the data line high to enable the master to generate the stop
condition.
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Programming (continued)
DATA
CLK
Change
of data
allowed
Data line
stable;
data valid
Figure 23. Bit Transfer on the Serial Interface
DATA
CLK
S
P
START Condition
STOP Condition
Figure 24. Start and Stop Conditions
SCLK
...
SDAT
A6
A5 A4 ...
...
A0 R/W
AC
K
0
Start
R7
R6
...
...
R5
R0
AC
K
0
D7
AC
D6 D5 ... D0
K
0
Slave Address
0
Register Address
Stop
Data
NOTE: SLAVE = TPS65055
Figure 25. Serial Interface Write to the TPS65055 Device
SCLK
SDAT
...
A6
..
...
A0
R/W ACK
0
R7
..
...
R0
0
Start
Slave Address
NOTE: SLAVE = TPS65055
ACK
A6
..
...
A0
R/W ACK D7
1
0
Register
Address
Slave Address
.. D0
ACK
0
Slave
Drives
the Data
Repeated
Start
Stop
Master
Drives
ACK and Stop
Figure 26. Serial Interface Read From TPS65055: Protocol A
18
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Programming (continued)
SCLK
...
SDAT
A6 ..
...
R/W ACK
A0
0
Start
R7
..
..
...
R0 ACK
0
0
A6
A0
R/W ACK
1
Stop Start
Register
Address
Slave Address
..
D7
..
D0
0
Slave
Drives
the Data
Slave Address
NOTE: SLAVE = TPS65055
ACK
Stop
Master
Drives
ACK and Stop
Figure 27. Serial Interface Read From TPS65055: Protocol B
DATA
t(BUF)
th(STA)
t(LOW)
tr
tf
CLK
t(HIGH)
th(STA)
th(DATA)
STO
STA
tsu(STA)
th(DATA)
t su(STO)
STA
STO
Figure 28. Serial Interface Timing Diagram
Table 3. Serial Interface Timing
MIN
MAX
UNIT
400
kHz
fMAX
Clock frequency
twH(HIGH)
Clock high time
600
twL(LOW)
Clock low time
1300
tR
DATA and CLK rise time
300
ns
tF
DATA and CLK fall time
300
ns
th(STA)
Hold time (repeated) start condition (after this period the first clock pulse is generated)
600
ns
th(DATA)
Setup time for repeated start condition
600
ns
th(DATA)
Data input hold time
100
ns
tsu(DATA)
Data input setup time
100
ns
tsu(STO)
Stop condition setup time
600
ns
t(BUF)
Bus free time
1300
ns
ns
ns
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8.6 Register Maps
Table 4. PGOODZ. Register Address: 01h (read only)
PGOODZ
B7
B6
B5
B4
B3
B2
B1
BO
discharge
DVM
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
LDO1
PGOODZ
LDO2
PGOODZ
LDO3
PGOODZ
LDO4
Set by signal
PGOODZ
VDCDC1
PGOODZ
VDCDC2
PGOODZ
LDO1
PGOODZ
LDO2
PGOODZ
LDO3
PGOODZ
LDO4
Default value loaded
by:
PGOOD
VDCDC1
PGOOD
VDCDC2
PGOOD
LDO1
PGOOD
LDO2
PGOOD
LDO3
PGOOD
LDO4
R
R
R
R
R
R
Bit name and function
Read/write
R
R
Bit 7
discharge:
0 = Indicates that the comparator input voltage is below the 1 V threshold.
1 = Indicates that the comparator input voltage is above the 1 V threshold.
Bit 6
DVM:
0 = Indicates that the voltage of DCDC2 is not changing.
1 = Indicates that a voltage change of DCDC2 is ongoing.
Bit 5
PGOODZ VDCDC1:
0 = Indicates that the VDCDC1 converter output voltage is within its nominal range.
1 = Indicates that the VDCDC1 converter output voltage is below its target regulation voltage or is
disabled.
Bit 4
PGOODZ VDCDC2:
0 = Indicates that the VDCDC2 converter output voltage is within its nominal range.
1 = Indicates that the VDCDC2 converter output voltage is below its target regulation voltage or is
disabled.
Bit 3
PGOODZ LDO1:
0 = Indicates that the LDO1 output voltage is within its nominal range.
1 = Indicates that the LDO1 output voltage is below its target regulation voltage or is disabled.
Bit 2
PGOODZ LDO2:
0 = Indicates that the LDO2 output voltage is within its nominal range.
1 = Indicates that LDO2 output voltage is below its target regulation voltage or is disabled.
Bit 1
PGOODZ LDO3:
0 = Indicates that the LDO3 output voltage is within its nominal range.
1 = Indicates that the LDO3 output voltage is below its target regulation voltage or is disabled.
Bit 0
PGOODZ LDO4:
0 = Indicates that the LDO4 output voltage is within its nominal range.
1 = Indicates that the LDO4 output voltage is below its target regulation voltage or is disabled.
Table 5. REG_CTRL. Register Address: 02h (read/write)
REG_CTRL
Bit name and function
Default Value: 00h
B7
B6
B5
B4
B3
B2
B1
BO
RST
DPD
DCDC1
ENABLE
DCDC2
ENABLE
LDO1
ENABLE
LDO2
ENABLE
LDO3
ENABLE
LDO4
ENABLE
0
0
0
0
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Set by signal
Default value loaded by:
Read/write
20
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The REG_CTRL register can be used to disable and enable all power supplies through the serial interface. The
following tables indicate how the enable pins and the REG_CTRL register are combined.
EN_DCDC1 Pin
REG_CTRL
DCDC1 Converter
0
0
Disabled
0
1
Enabled
1
0
Enabled
1
1
Disabled
EN_DCDC2 pin
REG_CTRL
DCDC2
0
0
Disabled
0
1
Enabled
1
0
Enabled
1
1
Disabled
EN_LDO1 pin
REG_CTRL
LDO1
0
0
Disabled
0
1
Enabled
1
0
Enabled
1
1
Disabled
EN_LDO2 Pin
REG_CTRL
LDO2
0
0
Disabled
0
1
Enabled
1
0
Enabled
1
1
Disabled
EN_LDO3 pin
REG_CTRL
LDO3
0
0
Disabled
0
1
Enabled
1
0
Enabled
1
1
Disabled
EN_LDO4 pin
REG_CTRL
LDO4
0
0
Disabled
0
1
Enabled
1
0
Enabled
1
1
Disabled
Bit 7
RST:
0 = The internal NMOS is turned on and drives the output to GND.
1 = The internal NMOS is turned off, an external pullup resistor at RST drives the output high.
Bit 6
DPD:
0 = The internal NMOS is turned on and drives the output to GND.
1 = The internal NMOS is turned off, an external pullup resistor at DPD drives the output high.
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Table 6. CON_CTRL. Register Address: 03h (read/write)
CON_CTRL
B7
B6
B5
B4
Bit name and function
Default
0
0
0
Read/write
R
R
R
B3
B2
B1
BO
LOW RIPPLE
DCDC1
LOW RIPPLE
DCDC2
FPWM
DCDC1
FPWM
DCDC2
0
Default value loaded by:
R
Default Value: 00h
0
0
0
1
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low
output voltage ripple is vital.
Bit 3
LOW RIPPLE DCDC1:
0 = PFM mode operation optimized for high efficiency for DCDC1.
1 = PFM mode operation optimized for low output voltage ripple for DCDC1.
Bit 2
LOW RIPPLE DCDC2:
0 = PFM mode operation optimized for high efficiency for DCDC2.
1 = PFM mode operation optimized for low output voltage ripple for DCDC2.
Bit 1
FPWM DCDC1:
0 = DCDC1 converter operates in PWM / PFM mode.
1 = DCDC1 converter is forced into fixed frequency PWM mode.
Bit 0
FPWM DCDC2:
0 = DCDC2 converter operates in PWM / PFM mode.
1 = DCDC2 converter is forced into fixed frequency PWM mode.
Table 7. CON_CTRL2. Register Address: 04h (read/write)
CON_CTRL2
B7
Bit name and function
GO
Default
0
Default value loaded by:
Read/write
B6
0
UVLO +
DONE*
R
R
Default Value: 0Fh
B5
B4
B3
B2
B1
BO
DCDC1
discharge
DCDC2
discharge
LDO1
discharge
LDO2
discharge
LDO3
discharge
LDO4
discharge
0
0
1
1
1
1
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
The CON_CTRL2 register can be used to take control of the inductive converters.
Bit 7
GO:
0 = No change in the output voltage for the DCDC2 converter.
1 = A voltage change for the DCDC2 converter is ongoing. The voltage is changed to the value written
into the DEFDCDC2_HIGH or DEFDCDC2_LOW register with the slew rate defined in DEFSLEW.
This bit is automatically set and cleared internally. The transition is considered complete in this case
when the desired output voltage code has been reached, not when the VDCDC2 output voltage is
actually in regulation at the desired voltage. The GO bit is also high when a voltage change is ongoing
caused by changing the logic level of the DEFDCDC2 pin.
Bit 5–0 0 = The output capacitor of the associated converter or LDO is not actively discharged when the
converter or LDO is disabled.
1 = The output capacitor of the associated converter or LDO is actively discharged when the converter
or LDO is disabled. This decreases the fall time of the output voltage at light load.
22
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Table 8. DEFDCDC2_LOW. Register Address: 05h (read/write)
DEFDCDC2_LOW
B7
B6
Bit name and function
Default
0
0
Default value loaded by:
Read/write
R
R
B5
B4
B3
B2
B1
BO
DCDC2[5]
DCDC2[4]
DCDC2[3]
DCDC2[2]
DCDC2[1]
DCDC2[0]
0
1
0
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
Table 9. DEFDCDC2_HIGH. Register Address: 06h (read/write)
DEFDCDC2_HIGH
B7
B6
Bit name and function
Default
0
0
R
R
Default value loaded by:
Read/write
Default Value: 10h
Default Value: 08h
B5
B4
B3
B2
B1
BO
DCDC2[5]
DCDC2[4]
DCDC2[3]
DCDC2[2]
DCDC2[1]
DCDC2[0]
0
0
1
0
0
0
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R/W
R/W
R/W
R/W
R/W
R/W
The output voltage for DCDC2 is switched between the value defined in DEFDCDC2_LOW and
DEFDCDC2_HIGH depending on the status of the DEFDCDC2 pin. IF DEFDCDC2 is low, the value in
DEFDCDC2_LOW is selected, if DEFDCDC2 = high, the value in DEFDCDC2_HIGH is selected.
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Table 10. Voltage Table for DCDC2
24
OUTPUT VOLTAGE
[V]
B5
B4
B3
B2
B1
B0
0
0.800
0
0
0
0
0
0
1
0.825
0
0
0
0
0
1
2
0.850
0
0
0
0
1
0
3
0.875
0
0
0
0
1
1
4
0.900
0
0
0
1
0
0
5
0.925
0
0
0
1
0
1
6
0.950
0
0
0
1
1
0
7
0.975
0
0
0
1
1
1
8
1.000
0
0
1
0
0
0
9
1.025
0
0
1
0
0
1
10
1.050
0
0
1
0
1
0
11
1.075
0
0
1
0
1
1
12
1.100
0
0
1
1
0
0
13
1.125
0
0
1
1
0
1
14
1.150
0
0
1
1
1
0
15
1.175
0
0
1
1
1
1
16
1.200
0
1
0
0
0
0
17
1.225
0
1
0
0
0
1
18
1.250
0
1
0
0
1
0
19
1.275
0
1
0
0
1
1
20
1.300
0
1
0
1
0
0
21
1.325
0
1
0
1
0
1
22
1.350
0
1
0
1
1
0
23
1.375
0
1
0
1
1
1
24
1.400
0
1
1
0
0
0
25
1.425
0
1
1
0
0
1
26
1.450
0
1
1
0
1
0
27
1.475
0
1
1
0
1
1
28
1.500
0
1
1
1
0
0
29
1.525
0
1
1
1
0
1
30
1.550
0
1
1
1
1
0
31
1.575
0
1
1
1
1
1
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Table 11. Voltage Table for DCDC2
OUTPUT VOLTAGE
[V]
B5
B4
B3
B2
B1
B0
0
1.600
1
0
0
0
0
0
1
1.650
1
0
0
0
0
1
2
1.700
1
0
0
0
1
0
3
1.750
1
0
0
0
1
1
4
1.800
1
0
0
1
0
0
5
1.850
1
0
0
1
0
1
6
1.900
1
0
0
1
1
0
7
1.950
1
0
0
1
1
1
8
2.000
1
0
1
0
0
0
9
2.050
1
0
1
0
0
1
10
2.100
1
0
1
0
1
0
11
2.150
1
0
1
0
1
1
12
2.200
1
0
1
1
0
0
13
2.250
1
0
1
1
0
1
14
2.300
1
0
1
1
1
0
15
2.350
1
0
1
1
1
1
16
2.400
1
1
0
0
0
0
17
2.450
1
1
0
0
0
1
18
2.500
1
1
0
0
1
0
19
2.550
1
1
0
0
1
1
20
2.600
1
1
0
1
0
0
21
2.650
1
1
0
1
0
1
22
2.700
1
1
0
1
1
0
23
2.750
1
1
0
1
1
1
24
2.800
1
1
1
0
0
0
25
2.850
1
1
1
0
0
1
26
2.900
1
1
1
0
1
0
27
2.950
1
1
1
0
1
1
28
3.000
1
1
1
1
0
0
29
3.100
1
1
1
1
0
1
30
3.200
1
1
1
1
1
0
31
3.300
1
1
1
1
1
1
Table 12. DEFSLEW. Register Address: 07h (read/write)
DEFSLEW
B7
B6
B5
B4
B3
0
0
0
0
0
Bit name and function
Default
Default value loaded by:
Read/write
R
R
R
R
R
Default Value: 06h
B2
B1
BO
SLEW2
SLEW1
SLEW0
1
1
0
UVLO
UVLO
UVLO
R/W
R/W
R/W
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SLEW2
SLEW1
SLEW0
VDCDC3 SLEW RATE
0
0
0
0.11 mV/μs
0
0
1
0.22 mV/μs
0
1
0
0.45 mV/μs
0
1
1
0.9 mV/μs
1
0
0
1.8 mV/μs
1
0
1
3.6 mV/μs
1
1
0
7.2 mV/μs
1
1
1
Immediate
Table 13. LDO_CTRL1. Register Address: 08h (r/w)
LDO_CTRL
B7
Bit name and function
Default
0
Default value loaded by:
Read/write
R
Default Value: Set With DEFLDO1, DEFLDO2
B6
B5
B4
LDO2[2]
LDO2[1]
LDO2[0]
DEFLDO
pins
DEFLDO
pins
DEFLDO
pins
UVLO
UVLO
UVLO
R/W
R/W
R/W
B3
0
R
B2
B1
BO
LDO1[2]
LDO1[1]
LDO1[0]
DEFLDO
pins
DEFLDO
pins
DEFLDO
pins
UVLO
UVLO
UVLO
R/W
R/W
R/W
The LDO_CTRLx registers can be used to set the output voltages of LDO1 to LDO4. The default value is loaded
at power-up depending on the status of the DEFLDO pins. See Default Voltage Setting for LDOs and DCDC1 for
details. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the
voltage can be changed by reprogramming the register content.
26
LDO2[2]
LDO2[1]
LDO2[0]
LDO2
OUTPUT VOLTAGE
0
0
0
1.2 V
0
0
1
1.3 V
0
1
0
1.8 V
0
1
1
2.6 V
1
0
0
2.7 V
1
0
1
2.8 V
1
1
0
2.9 V
1
1
1
3V
LDO1[2]
LDO1[1]
LDO1[0]
LDO1
OUTPUT VOLTAGE
0
0
0
0.8 V
0
0
1
1V
0
1
0
1.2 V
0
1
1
1.5 V
1
0
0
1.8 V
1
0
1
2.1 V
1
1
0
2.5 V
1
1
1
2.8 V
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Table 14. LDO_CTRL2. Register Address: 09h (r/w)
DEFLDO1, DEFLDO2
LDO_CTRL
B7
Bit name and function
Default
0
Default value loaded
by:
Read/write
R
B6
B5
B4
LDO4[2]
LDO4[1]
LDO4[0]
DEFLDO
pins
DEFLD
O pins
DEFLDO
pins
UVLO
UVLO
UVLO
R/W
R/W
R/W
Default Value: Set With
B3
B2
B1
BO
LDO3[2 LDO3[1 LDO3[0]
]
]
0
DEFLD
O pins
DEFLD
O pins
DEFLD
O pins
UVLO
UVLO
UVLO
R/W
R/W
R/W
R
The default value is loaded at power-up depending on the status of the DEFLDO pins. See Default Voltage
Setting for LDOs and DCDC1 for details. The status of the DEFLDO pins is latched after the undervoltage
lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.
LDO4[1]
LDO4[0]
0
0
0
1V
0
0
1
1.2 V
0
1
0
1.3 V
0
1
1
1.8 V
1
0
0
2.6 V
1
0
1
2.7 V
1
1
0
2.8 V
1
1
1
3V
LDO3[2]
LDO3[1]
LDO3[0]
LDO3
OUTPUT VOLTAGE
0
0
0
0.8 V
0
0
1
1V
0
1
0
1.2 V
0
1
1
1.5 V
1
0
0
1.8 V
1
0
1
2.1 V
1
1
0
2.5 V
1
1
1
2.8 V
Table 15. DEFDCDC1. Register Address: 0Ah (r/w)
DEFDCDC1
B7
B6
B5
B4
B3
B2
B1
BO
DCDC1[4]
DCDC1[3]
DCDC1[2]
DCDC1[1]
DCDC1[0]
0
DEFLDO pins
DEFLDO
pins
DEFLDO
pins
DEFLDO
pins
DEFLDO
pins
DEFLDO
pins
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
R
R/W
R/W
R/W
R/W
R/W
R/W
0
Default value loaded by:
Read/write
Default Value: Set With DEFLDO1, DEFLDO2
DCDC1[5]
Bit name and function
Default
LDO4
OUTPUT VOLTAGE
LDO4[2]
R
Per default the DCDC1 converter is internally adjustable and the default output voltage for DCDC1 (bits B0 to
B5) depends on the status of the DEFLDO pins – see Default Voltage Setting for LDOs and DCDC1. The status
of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be
changed by reprogramming the register content.
DCDC1 voltage is listed in Table 16.
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Table 16. Voltage Table for DCDC1
28
OUTPUT VOLTAGE
[V]
B5
B4
B3
B2
B1
B0
0
0.800
0
0
0
0
0
0
1
0.825
0
0
0
0
0
1
2
0.850
0
0
0
0
1
0
3
0.875
0
0
0
0
1
1
4
0.900
0
0
0
1
0
0
5
0.925
0
0
0
1
0
1
6
0.950
0
0
0
1
1
0
7
0.975
0
0
0
1
1
1
8
1.000
0
0
1
0
0
0
9
1.025
0
0
1
0
0
1
10
1.050
0
0
1
0
1
0
11
1.075
0
0
1
0
1
1
12
1.100
0
0
1
1
0
0
13
1.125
0
0
1
1
0
1
14
1.150
0
0
1
1
1
0
15
1.175
0
0
1
1
1
1
16
1.200
0
1
0
0
0
0
17
1.225
0
1
0
0
0
1
18
1.250
0
1
0
0
1
0
19
1.275
0
1
0
0
1
1
20
1.300
0
1
0
1
0
0
21
1.325
0
1
0
1
0
1
22
1.350
0
1
0
1
1
0
23
1.375
0
1
0
1
1
1
24
1.400
0
1
1
0
0
0
25
1.425
0
1
1
0
0
1
26
1.450
0
1
1
0
1
0
27
1.475
0
1
1
0
1
1
28
1.500
0
1
1
1
0
0
29
1.525
0
1
1
1
0
1
30
1.550
0
1
1
1
1
0
31
1.575
0
1
1
1
1
1
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Table 17. Voltage Table for DCDC1
OUTPUT VOLTAGE
[V]
B5
B4
B3
B2
B1
B0
0
1.600
1
0
0
0
0
0
1
1.650
1
0
0
0
0
1
2
1.700
1
0
0
0
1
0
3
1.750
1
0
0
0
1
1
4
1.800
1
0
0
1
0
0
5
1.850
1
0
0
1
0
1
6
1.900
1
0
0
1
1
0
7
1.950
1
0
0
1
1
1
8
2.000
1
0
1
0
0
0
9
2.050
1
0
1
0
0
1
10
2.100
1
0
1
0
1
0
11
2.150
1
0
1
0
1
1
12
2.200
1
0
1
1
0
0
13
2.250
1
0
1
1
0
1
14
2.300
1
0
1
1
1
0
15
2.350
1
0
1
1
1
1
16
2.400
1
1
0
0
0
0
17
2.450
1
1
0
0
0
1
18
2.500
1
1
0
0
1
0
19
2.550
1
1
0
0
1
1
20
2.600
1
1
0
1
0
0
21
2.650
1
1
0
1
0
1
22
2.700
1
1
0
1
1
0
23
2.750
1
1
0
1
1
1
24
2.800
1
1
1
0
0
0
25
2.850
1
1
1
0
0
1
26
2.900
1
1
1
0
1
0
27
2.950
1
1
1
0
1
1
28
3.000
1
1
1
1
0
0
29
3.100
1
1
1
1
0
1
30
3.200
1
1
1
1
1
0
31
3.300
1
1
1
1
1
1
Table 18. VERSION. Register Address: 0Bh (r)
VERSION
B7
B6
B5
B4
B3
B2
B1
BO
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R
R
R
R
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This device integrates two step-down converters and four LDOs, which can be used to power the voltage rails
needed by a processor or any other application. The PMIC can be controlled through the ENABLE and MODE
pins or sequenced from the VIN using RC delay circuits. In addition to these control pins the device can be
controlled by software through I2C interface. Thus, the TPS65055 is very flexible and compatible with many
application systems. There is a logic output, RESET, provide the application processor or load a logic signal
indicating power good or reset.
30
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9.2 Typical Application
VINDCDC1/2
1R
Vbat
VCC
10 mF
1 mF
2.2 mH
DCDC1 (I/O)
ENABLE
SCLK
SDAT
DEFLDO1
DEFLDO2
STEP-DOWN
CONVERTER
600 mA
1 V / 1.2 V
VIN
ENABLE
VIN
ENABLE
VIN
ENABLE
ENABLE
VDCDC1
10 mF
PGND1
Interface
L2
DCDC2 (core)
ENABLE
L1
EN_DCDC1
STEP-DOWN
CONVERTER
600 mA
EN_DCDC2
DEFDCDC2
VDCDC2
2.2 mH
10 mF
PGND2
VLDO1
VIN_LDO1
VLDO1
EN_LDO1
4.7 mF
400 mA LDO
VIN_LDO2
VLDO2
EN_LDO2
VLDO2
4.7 mF
400 mA LDO
VIN_LDO3/4
VLDO3
EN_LDO3
200 mA LDO
EN_LDO4
VLDO4
VLDO3
2.2mF
BP
0.1 mF
VLDO4
2.2 mF
200 mA LDO
I/O voltage
R19
RST
I/O voltage
R20
DPD
discharge
THRESHOLD
comparator
AGND
Figure 29. Typical Application Schematic
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Typical Application (continued)
9.2.1 Design Requirements
The TPS6505x devices have only a few design requirements. Use the following parameters for the design
examples:
• 1-μF bypass capacitor on VCC, located as close as possible to the VCC pin to ground.
• VCC and VINDCDC1/2 must be connected to the same voltage supply with minimal voltage difference.
• Input capacitors must be present on the VINDCDC1/2, VIN_LDO1, VINLDO2, and VIN_LDO3/4 supplies if
used.
• Output inductor and capacitors must be used on the outputs of the DC-DC converters if used.
• Output capacitors must be used on the outputs of the LDOs if used.
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Setting
9.2.2.1.1 Converter 1 (DCDC1)
The output voltage of converter 1 is set by the status of the DEFLDO pins and the I2C compatible interface. See
Table 2 for output voltage options.
9.2.2.1.2 Converter 2 (DCDC2)
The output voltage of converter 2 is selected with the DEFDCDC2 pin.
Table 19. Default Fixed Output Voltages
CONVERTER 2
DEFDCDC2 = LOW
DEFDCDC2 = HIGH
TPS65055
1.2 V
1V
9.2.2.2 Output Filter Design (Inductor and Output Capacitor)
9.2.2.2.1 Inductor Selection
The two converters operate typically with 2.2 μH output inductors. Larger or smaller inductor values can be used
to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated
for its DC resistance and saturation current. The DC resistance of the inductance influences directly the
efficiency of the converter. Therefore an inductor with the lowest DC resistance should be selected for highest
efficiency. Due to the internal control scheme used, the inductor should have a minimum value of 3.3 μH for an
output voltage of 3 V or higher.
Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is
recommended because during heavy load transient the inductor current rises above the calculated value.
Vout
1DI
Vin
Formula 1: DIL = Vout ´
(3) ILmax = Ioutmax + L
L ´ f
2
where
•
•
•
•
f = Switching frequency (2.25 MHz typical)
L = Inductor value
ΔIL = Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
(4)
The highest inductor current occurs at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
32
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A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. It must be considered, that the core material from inductor to inductor differs and has
an impact on the efficiency especially at high switching frequencies.
Refer to Table 20 and the typical applications for possible inductors.
Table 20. Tested Inductors
INDUCTOR TYPE
INDUCTOR VALUE
SUPPLIER
LPS3010
2.2 μH
Coilcraft
VLF3010
2.2 μH
TDK
LPS4012
2.2 μH
Coilcraft
VLF4012
2.2 μH
TDK
9.2.2.2.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the two converters allows the use of small ceramic
capacitors with a typical value of 22 μF, without having large output voltage under and overshoots during heavy
load transients. Ceramic capacitors having low ESR values result in the lowest output voltage ripple and are
therefore recommended. Refer to Table 21 for recommended components.
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. For completeness, the RMS ripple current is calculated as:
Vout
11
Vin ´
IRMSCout = Vout ´
L ´ f
2 ´ 3
(5)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
Vout
1ö
1
Vin × æ
DVout = Vout ´
+ ESR ÷
ç
L ´ f
è 8 ´ Cout ´ f
ø
(6)
Where the highest output voltage ripple occurs at the highest input voltage, Vin.
At light load currents the converters operate in power save mode, and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
9.2.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing interference with other circuits caused by high input
voltage spikes. The converters require a ceramic input capacitor of 10 μF. The input capacitor can be increased
without limit for better input voltage filtering.
Table 21. Possible Capacitors
CAPACITOR VALUE
SIZE
SUPPLIER
TYPE
22 μF
0805
TDK C2012X5R0J226MT
Ceramic
22 μF
0805
Taiyo Yuden JMK212BJ226MG
Ceramic
10 μF
0805
Taiyo Yuden JMK212BJ106M
Ceramic
10 μF
0805
TDK C2012X5R0J106M
Ceramic
10 μF
0603
Taiyo Yuden JMK107BJ106MA
Ceramic
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9.2.3 Application Curves
TEST CONDITIONS
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
VIN = 3.6 V
TA = 25°C
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
Figure 30. Load Transient Response DCDC1; PWM
Figure 31. Load Transient Response DCDC1; PFM
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
Load Current = 60 mA to 540 mA
VDCDC1 = 2.1 V
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
CH1: VDCD1 (Green)
CH2: Load Current (Blue)
Figure 32. Load Transient Response DCDC2; PWM
34
TEST CONDITIONS
VIN = 3.6 V
TA = 25°C
Figure 33. Load Transient Response DCDC2; PFM
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10 Power Supply Recommendations
Any supply from 2.5 V to 6 V will work as long as the power supply can supply enough current at the VIN voltage
that the application demands.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
The input capacitors for the DC-DC converters should be placed as close as possible to the VINDCDC1/2 pin
and the PGND1 and PGND2 pins.
The inductor of the output filter should be placed as close as possible to the device to provide the shortest
switch node possible, reducing the noise emitted into the system and increasing the efficiency.
Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy.
Feedback should be routed away from noisy sources such as the inductor. If possible route on the opposing
side as the switch node and inductor and place a GND plane between the feedback and the noisy sources or
keepout underneath them entirely.
Place the output capacitors as close as possible to the inductor to reduce the feedback loop as much as
possible. This will ensure best regulation at the feedback point.
Place the device as close as possible to the most demanding or sensitive load. The output capacitors should
be placed close to the input of the load. This will ensure the best AC performance possible.
The input and output capacitors for the LDOs should be placed close to the device for best regulation
performance.
TI recommends using a common ground plane for the layout of this device. The AGND can be separated
from the PGND but, a large low parasitic PGND is required to connect the PGNDx pins to the CIN and
external PGND connections. If the AGND and PGND planes are separated, have one connection point to
reference the grounds together. Place this connection point close to the IC.
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Cout
DCDC2 FB
R1 FB
R2 FB
11.2 Layout Example
C
CD
VD
2
Lout
Cin
L2
L1
Vin
Cin
DC
DC
1
FB
Lout
R2 FB
Cout
R1 FB
Figure 34. Layout Example From EVM for TPS6505x
36
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
OMAP, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65055RSMR
ACTIVE
VQFN
RSM
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65055
TPS65055RSMT
ACTIVE
VQFN
RSM
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65055
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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