TPS65230, TPS65231
www.ti.com.................................................................................................................................... SLVSA10A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009
POWER MANAGEMENT IC FOR DIGITAL SET TOP BOXES
FEATURES
1
•
•
•
•
•
•
Wide Input Supply Voltage Range
(10.8 V - 22 V)
One Adjustable PWM Buck Controller
– 10.8-V - 22-V Input Voltage Range
– 3.3-V - 6.1-V Output Voltage Range
– 500kHz switching frequency
– Type III Compensation
– Programmable Current Limit
Two Adjustable Step-Down Converter with
Integrated Switching FETs:
– 4.75-V - 5.5-V Input
– 0.9-V-3.3-V Output Voltage Range
– 3-A Output Current
– 1-MHz Switching Frequency
– Voltage Scaling Option
– Type III Compensation
Two 100-mΩ, 0.5-A (TPS65230) 1-A (TPS65231)
USB Switches with Over Current Protection
and Open-Drain Fault Pin
Early Supply Failure Flag (Open Drain Output)
is Set when Input Voltage Drops Below 9.3 V
Early Temperature Warning Flag (Open Drain
Output) is Set if Temperature Approaches
Shut-Down Threshold
•
•
•
•
•
•
•
Supply Voltage Supervisor Circuit with Two
Monitor Inputs and Open Drain Output
Parallel I/O or I2C Control with User Selectable
Address
Advanced Fault Detection and Output Voltage
Adjustment Options in I2C Mode
Pull-Up Current Sources on Buck Enable Pins
for Accurate Start-Up Timing Control with
Preset Default
Over Current Protection on All Rails
Thermal Shutdown to Protect Device During
Excessive Power Dissipation
Thermally Enhanced Package for Efficient
Heat Management (48-pin HTSSOP)
APPLICATIONS
•
•
•
•
•
Digital Set Top Boxes
xDSL & Cable Modems
DVD Players
Home Gateway and Access Point Networks
Wireless Routers
DESCRIPTION/ORDERING INFORMATION
The TPS652x provides one PWM buck controller, two adjustable, synchronous buck regulators, two independent
USB power switches and a supply voltage supervisor (SVS) to provide main power functions for satellite set top
boxes, xDSL and cable modem applications operating off a single 12- to 22-V supply.
The SMPS have integrated switching FETs for optimized power efficiency and reduced external component
count. Each USB switch provides up to 0.5-A (TPS65230) or 1-A (TPS65231) of current as required by
downstream USB devices. All power blocks have thermal and over current/short circuit protection.
The SVS provides two inputs for monitoring positive supply rails. The active-low open-drain output remains low
for at least 180 ms after all supply rails rise above their rising edge threshold. Threshold value for VMON1 input
is set for monitoring a 3.3-V rail without the need for additional external components. Threshold for VMON2 input
is set to 0.8 V and requires resistor dividers on the input to monitor any positive voltage in the system. The
nBOR/nHOT open-drain output is pulled low if the input supply drops below 9.3 V or the chip temperature
approaches the thermal shutdown limit. This allows the system processor to save critical data and shut down
gracefully before the supply fails.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS65230, TPS65231
SLVSA10A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com
The TPS65230 and TPS65231 can be controlled either through parallel I/Os or through I2C interface. When the
pull-up resistor on the USBFLAG2/nINT pin is connected to a 3.3-V or lower supply the I2C interface is disabled
and the device is controlled through parallel I/O pins only. With the pull-up resistor connected to 6 V the I2C
interface is enabled and the device is controlled by writing to the control registers. Any fault or abnormal
operating condition is flagged by the interrupt pin. The interrupt is cleared by reading the status register via the
I2C interface.
FUNCTIONAL BLOCK DIAGRAM
1 2V DC Sup ply
VINB an d VINBQ p in s m u st b e t ied
t og th e r o n PC b o ar d
VI NB 2b
VI NB 2a
6V I 2C MODE
3. 3V UC MODE
VI NB 3b
VI N
VI NB 3a
Op tion al
1 2V
HDRV
INT
to uC or DSP
BS T1
VIN
Vou t BUC K1
DIG ITA L LOGI C
E N_BCK1
f ro m e na ble log ic
E N_BCK2
f ro m e na ble log ic
E N_BCK3
f ro m e na ble log ic
PH1
B UCK 1
LDRV
FB1
CM P1
E NUS B1 /S CL
BS T2
fro m uC o r DSP
E ENUS B2/ SDA
I 2C
REF
PH2a
VINB2
fro m uC o r DSP
Vou t BUCK2
PH2b
TRIM
OS C
TS D
UVLO
B UCK 2
FB2
CM P2
V 3p3
VLS D
BS T3
INTE RNA L
VO LT AGE RA ILS
PH3a
VINB3
Vou t BUCK3
PH3b
B UCK 3
FB3
CM P3
nRST
VREF1
t o u C or DSP
VREF2
VM ON1
F r om 3. 3v s up py
V3p3
RE SE T GENE RA TOR
US BF LG1/CTRL
T o/f rom u C o r DSP
VM ON2
f ro m pos mo nit or Sup ply
USB 1
I 2C_A DD
US BO UT 1
To USB p ort
V3p3
US BF LG2/nI NT
T o/f rom u C o r DSP
USB 2
US BO UT 2
PGND
PGND
PGND
PGND
AGND
DGND
To USB p ort
ORDERING INFORMATION (1)
TA
0°C to 85°C
(1)
(2)
2
PACKAGE (2)
48-pin (HTSSOP) - DCA
Reel of 2000
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS65230A2DCAR
TPS65230
TPS65231A2DCAR
TPS65231
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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TPS65230, TPS65231
www.ti.com.................................................................................................................................... SLVSA10A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009
TERMINAL FUNCTIONS
NAME
NO.
I/O
BG
1
I
Reference filter pin
VINBQ
2
I
Reference supply for BUCK2 and BUCK3
V6V
3
I
Filter pin for internal voltage regulator (6 V)
VIN
4
I
Input supply for BUCK1 and support circuitry
FB2
5
I
Feedback pin (BUCK2)
CMP2
6
I
Regulator compensation (BUCK2)
EN_BCK2
7
I
Enable pin for BUCK2, active high
PGND2
8, 9
PH2
10, 11
VINB2
12, 13
BST2
14
DGND
15
LDRV
DESCRIPTION
Power ground BUCK2
O
Switching pin (BUCK2)
I
Bootstrap input (BUCK2)
16
O
Low-side gate drive output (PWM controller)
HDRV
17
O
High-side gate drive output (PWM controller)
PH1
18
O
Switching pin (BUCK1)
BST1
19
I
Bootstrap input (BUCK1)
EN_BCK1
20
I
Enable pin for BUCK1, active high
CMP1
21
I
Regulator compensation (PWM controller)
FB1
22
I
Feedback pin (PWM controller)
SS
23
I
External capacitor for soft start
TRIP
24
I
BUCK1 over current trip point set-up
V3P3
25
I
Filter pin for internal voltage regulator (3.3 V)
AGND
26
nRST
27
O
Reset output (open drain), active low
EN_USB1/SCL
28
I
Enable pin for USB switch 1, active high / Clock input (I2C enabled).
EN_USB2/SDA
29
I
Enable pin for USB switch 2, active high / Data input (I2C enabled)
USBFLAG2/nINT
30
I/O
Input supply for BUCK2 (must be tied to VINB3, VINBQ)
Digital ground. All grounds should be joined together.
Analog ground
USB2 fault flag / Interrupt pin
FB3
31
I
Feedback pin (BUCK3)
CMP3
32
I
Regulator compensation (BUCK3)
33
I
Enable pin for BUCK3, active high
EN_BCK3
PGND3
34, 35
Power ground BUCK3
PH3
36, 37
O
VINB3
38, 39
I
Input supply for BUCK3 (must be tied to VINB2, VINBQ)
BST3
40
I
Bootstrap input (BUCK3)
USBOUT1
41
O
USB switch output (channel1)
VINU
42
I
Input supply for USB switches
USBOUT2
43
O
USB switch output (channel2)
USBFLG1/VCTRL
44
I/O
USB1 fault flag, active low, open drain / Voltage control pin for BUCK2
(I2C enabled)
nBOR/nHOT
45
I/O
Brownout and hot warning, active low, open drain
VMON1
46
I
Voltage monitor input (3.3 V rail)
VMON2
47
I
Voltage monitor input (positive reference)
I2C_ADD
48
I
If grounded, I2C address is 48h. Tied to V3P3 I2C address is 49.
Switching pin (BUCK3)
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DCA HTSSOP PACKAGE
(TOP VIEW)
BG
VINBQ
1
2
48
47
I2C_ADD
VMON2
V6V
3
46
VMON1
VIN
FB2
4
5
45
44
nBOR/nHOT
USBFLG1/VCTRL
CMP2
6
43
USBOUT2
EN_BCK2
PGND2
7
8
42
41
VINU
USBOUT1
PGND2
9
40
BST3
PH2
PH2
10
11
39
38
VINB3
VINB3
VINB2
12
37
PH3
VINB2
BST2
13
14
36
35
PH3
PGND3
DGND
15
34
PGND3
LDRV
HDRV
16
17
33
32
EN_BCK3
CMP3
PH1
18
31
FB3
BST1
EN_BCK1
19
20
30
29
USBFLG2/nINT
EN_USB2/SDA
CMP1
21
28
EN_USB1/SCL
FB1
SS
22
23
27
26
nRST
AGND
TRIP
24
25
V3P3
ABSOLUTE MAXIMUM RATINGS (1) (2)
over operating free-air temperature range (unless otherwise noted)
Input voltage range at VIN
–0.3 to 25
V
Input voltage range at VINB, VINBQ, VINU
–0.3 to 7.0
V
Voltage range at INT
–0.3 to 7.0
V
Voltage range at EN_BCK1, EN_BCK2, EN_BCK3, EN_USB1/SCL, EN_USB2/SDA,
nRST, USBFLG1/VCTRL2, USBFLG2/VCTRL3
–0.3 to 3.6
V
Voltage on HDRV, BST1
–0.3 to 31
V
Voltage on PH1
–0.3 to 24
V
Voltage on FB1, CMP1, FB2, CMP2, FB3, CMP3
–0.3 to 3.6
V
Voltage on PH2, PH3, LDRV
–0.3 to 7.0
V
Voltage on BST2, BST3
–0.3 to 15V
V
Voltage on VMON1, VMON2, VMON3
–0.3 to 3.6
V
3.8
A
Output Current BUCK2, BUCK3
Peak output current
Internally limited
ESD rating
θJA
Human body model (HBM)
2k
Charged device model (CDM)
500
Thermal Resistance – Junction to ambient (3)
Continuous total power dissipation 55°C
(3)
°C/W
2.6
W
TJ
Operating virtual junction temperature range
0 to 150
°C
TA
Operating ambient temperature range
0 to 85
°C
TSTG
Storage temperature range
–65 to 150
°C
(1)
(2)
(3)
4
no thermal warning
25
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Using JEDEC 51-5 (High K) board. This is based on standard 48DCA package, 4 layers, top/bottom layer: 2 oz Cu, inner layer: 1 oz Cu.
Board size: 114.3 x 76.2 mm (4.5 x 3 inches), board thickness: 1.6 mm (0.0629 inch).
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TPS65230, TPS65231
www.ti.com.................................................................................................................................... SLVSA10A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Input voltage range at VIN
10.8
12
22
V
Input voltage range at VINU
4.75
5.5
V
Input voltage range at VINB
4.75
6.1
Voltage range, EN_BCK1, EN_BCK2, EN_BCK3, EN_USB1/SCL, EN_USB2/SDA,
nRST, USBFLG1/VCTRL2, USBFLG2/VCTRL3 pins
Input voltage, nRST pin
Voltage range, INT pin (I2C disabled)
TA
5.4
UNIT
3.3
V
3.3
V
6.6
V
Voltage range, INT pin (I2C enabled)
3.3
V
Ambient operating temperature
50
°C
MAX
UNIT
ELECTRICAL CHARACTERISTICS
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, VINU = 5 V ±5% TJ = 0°C to 150°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
10.8
12
INPUT VOLTAGE
VIN
Input supply voltage
VBOR
Brown Out Reset threshold
UVLO VIN
UVLO threshold – VIN (main supply)
UVLO VINB
UVLO threshold – VINB
(BUCK2/BUCK3 supply)
UVLO VINU
UVLO threshold – VINU (USB supply)
VIN rising
VIN falling
9.3
VIN rising
VIN falling
10.8
4.7
VINB rising
VINB falling
4.75
4.25
VINU rising
VINU falling
22
10.8
4.4
3.8
V
V
V
V
V
INPUT CURRENT
ICCQ
All regulators/USB switches
disabled
Input supply current
4
mA
LOGIC INPUT LEVEL (SCL, SDA, INT, VCTRL2, VCTRL3)
VIH
Input high level
VIL
Input low level
VI2C_disable
I2C disable voltage (INT)
1.2
V
0.4
4
V
V
BUCK ENABLE INPUTS (EN_BCK1,2,3)
VEN
Enable threshold
1.2
V
VENHYS
Enable voltage hysteresis
100
mV
IPULLUP
Pull-up current
RD
Discharge resistor
tD
Discharge time
tEN = 0.2 ms/nF
6
uA
1
Power-up
5
kΩ
ms
2
I C ENABLE THRESHOLD (INT pin)
VINTTH
I2C enable threshold
I2C enabled if pull-up resistor
is connected to a value
above threshold
4.8
V
LOGIC OUTPUT LEVEL(SDA, INT, nRST, USBFLG1, USBFLG2 )
OL
Output low level
IOUT = 3 mA through pull-up
0.3
0.4
V
PWM CONTROLLER (BUCK1)
VOUT
Output voltage range (1)
PG
Power good threshold
(1)
3.3
VOUT rising
6.1
95
V
%
Output voltage range is limited by the minimum and maximum duty cycle. VOUT(min) ~ d(min) x VINPUT and VOUT(max) ~ d(max) x
VINPUT.
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, VINU = 5 V ±5% TJ = 0°C to 150°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
UVD
Under voltage detect
VFB
Feedback voltage
LDRV
HDRV
High and low side drive voltage
R_ONLDRV
Low side ON resistance
R_OFFLDRV
R_ONHDRV
MIN
VOUT falling
TYP
MAX
UNIT
75
–2%
No load
0.804
%
2%
V
6
V
8
Ω
Low side OFF resistance
1
Ω
High side ON resistance
20
Ω
R_OFFHDRV
High side OFF resistance
1
d
Duty cycle (2)
AMOD
Modulator gain
fSW
Switching frequency
ITRIP
Current source for setting OCP trip
point
TCTRIP
Temperature coefficient of ITRIP
RTRIP
Current-limit setting resistor
COUT
Output capacitance
L
Nominal Inductance
20
Ω
80
%
12
TA = 25°C
500
kHz
10
µA
3700
80
22 (3)
Recommended
ppm/°C
250
kW
47
µF
4.7
µH
BUCK2
VOUT
Output voltage range (4)
PG
Power good threshold
VOUT rising
95
UVD
Under voltage detect
VOUT falling
75
VFB
Feedback voltage
IOUT
Output current
η
Efficiency
0.9
– 2%
High-side MOSFET On resistance
ILIMIT
VINB = 4.75 V - 6.1 V,
IOUT = 1 A
VLOADREG
Load regulation - DC
ΔVOUT/ΔIOUT
IOUT = 10 – 90% IOUT,MAX
VOUTTOL
DC set tolerance
Feedback resistor tolerance
not included
(5)
fSW
Switching frequency
COUT
Output capacitance
ESR
Capacitor ESR
L
Nominal inductance
mA
%
mΩ
5
Line regulation - DC
ΔVOUT/ΔVINB
Modulator gain
V
36
–30
VLINEREG
Duty cycle
%
2%
32
VIN12V = 12 V
Current limit accuracy
AMOD
%
95
Switch current limit
d
0.804
V
3000
IO = 2 A, VOUT = 3.3V
Low-side MOSFET On resistance
RDS(ON)
3.3
A
30
%
1
%
0.5
–2
15
%/A
2
%
85
%
5
1
10 (3)
MHz
µF
47
50
mW
µH
2.2
BUCK3
VOUT
Output voltage range (4)
PG
Power good threshold
VOUT rising
95
%
UVD
Under voltage detect
VOUT falling
75
%
(2)
(3)
(4)
(5)
6
0.9
3.3
V
Performance outside these limits is not guaranteed.
Absolute value. User should make allowances for tolerance and variations due to component selection.
Output voltage range is limited by the minimum and maximum duty cycle. VOUT(min) ~ d(min) x VINPUT and VOUT(max) ~ d(max) x
VINPUT.
Performance outside these limits is not guaranteed.
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, VINU = 5 V ±5% TJ = 0°C to 150°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
PG glitch rejection
VFB
Feedback voltage
IOUT
Output current
η
Efficiency
RDS(ON)
ILIMIT
–2%
High-side MOSFET On resistance
–30
VLINEREG
Line regulation - DC
ΔVOUT/ΔVINB
VINB = 4.75 V - 6.1 V,
IOUT = 1000 mA
VLOADREG
Load regulation - DC
ΔVOUT/ΔIOUT
IOUT = 10 – 90% IOUT,MAX
VOUTTOL
DC Set Tolerance
Feedback resistor tolerance
not included
(5)
Modulator gain
fSW
Switching frequency
COUT
Output capacitance
ESR
Capacitor ESR
L
Nominal inductance
A
30
%
1
%
0.5
–2
15
A
mΩ
36
5
Current limit accuracy
V
%
32
VIN12V = 12 V
UNIT
µs
2%
86
Switch current limit
Duty cycle
0.804
3
Low-side MOSFET On resistance
AMOD
MAX
50
IO = 2 A, VOUT = 1.2 V
d
TYP
%/A
2
%
85
%
5
1
MHz
µF
10
50
mW
2.2
µH
2
µA
SOFT START (BUCK1, 2, and 3)
ISS
VSS,
Soft start current source
MAX
CSS
Soft start ramp voltage
Ramp end
Soft start capacitor
tSS = 0.4 ms/nF
0.8
2
3.3
V
5
nF
SSDONE_BK
Deglitch time
2.5
ms
SSDONE_DCH
SS discharge time
500
µS
SUPPLY VOLTAGE SUPERVISOR
Supply rising
VMON1
Threshold voltage
(VMON1)
Supply falling
VMON2
Threshold voltage
(VMON2)
tdeglitch
Deglitch time (both edges)
VOL
Reset pin output-low voltage
tRP
Minimum reset period
3.2
3
V
Hysteresis
.05
Supply rising
850
Supply falling
750
Hysteresis
mV
20
µs
192
Isink = 3.2 mA
0.4
V
180
ms
100
mΩ
USB POWER SWITCHES
RDS(on)
On resistance
tr
Rise time output
VINU = 5.5 V, CL = 120 mF,
VOUT 10% to 90%.
ton
Turn-on time
CL = 100 µF, rL = 10 Ω
3
ms
toff
Turn-off time
CL = 100 µF, rL = 10 Ω
10
ms
IOC
OC deglitch
1
Over Current limit
TPS65230
0.6
0.8
1
Output shorted to ground
TPS65231
1.2
1.6
2
4
8
15
Over current deglitch
ms
A
ms
THERMAL SHUTDOWN
Thot
Thermal warning
120
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°C
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SLVSA10A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, VINU = 5 V ±5% TJ = 0°C to 150°C, unless otherwise noted.
PARAMETER
Ttrip
Thermal S/D trip point
Thyst
Thermal S/D hysteresis
TEST CONDITIONS
MIN
TYP
MAX
UNIT
160
°C
20
°C
SUPPLY VOLTAGE SUPERVISOR (SVS)
The supply voltage supervisor monitors two inputs, VMON1 and VMON2, and generates a reset pulse of at least
180-ms length when one or more supplies fall below their respective thresholds. All inputs are deglitched for very
short dips on the supplies. The reference values for VMON1 is specified for monitoring a 3.3-V rail without the
need of external components. The reference for VMON2 is set to monitor arbitrary supply voltages and require
resistor dividers at the inputs.
VMONx
Please note that the reset signal generated by the SVS is for external use only and has no impact on the power
rails or USB switches of the TPS65230 and TPS65231.
Hysteresis
nRST
Time
min 180ms
Figure 1. Supply Voltage Supervisor Reset Generation
USB POWER SWITCHES
The TPS65230 and TPS65231 provide two power-distribution switches intended for applications where heavy
capacitive loads and short-circuits are likely to be encountered. Gate drive is provided by an internal regulator.
Each switch is controlled by a logic enable input or, when I2C interface is enabled, switches are controlled
through EN_USBx bits of the ENABLE register.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the USBFAULTx output low. When continuous
heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature
to rise, a thermal protection circuit shuts off the switches when a thermal warning condition occurs to prevent
damage. Recovery from a thermal warning is automatic once the device has cooled sufficiently. Internal circuitry
ensures that the switch remains off until valid input voltage is present.
8
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POWER-UP SEQUENCING
ON/OFF control and power sequencing of the three buck regulators is controlled through EN_BCK1, EN_BCK2,
and EN_BCK3 enable pins. Each pin is internally connected to a 6-µA constant-current source and monitored by
a comparator with Schmitt trigger input with defined threshold. Connecting EN_BCKn pin to ground disables
BUCKn and connecting EN_BCKn to V3P3 will enable the respective buck without delay. If more than one buck
enable pin is connected to V3P3 the default startup sequence is BUCK1, BUCK2, BUCK3 and the minimum
startup delay between rails is the soft-start time (typical 1.5 ms) plus 1 ms.
To create a startup-sequence different from the default, capacitors are connected between the EN_BUCKn pins
and ground. At power-up the capacitors are first discharged and then charged to V3P3 level by internal current
sources (6 µA typical) creating a constant-slope voltage ramp. A regulator is enabled when its EN pin voltage
crosses the enable threshold (typical 1.2 V). A delay of 0.2 ms is generated for each 1-nF of capacitance
connected to the enable pin. If two enable pins are pulled high while the third regulator is starting up, the default
sequence will be applied to enable the remaining two regulators. To override default power-up sequence it is
recommended that delay times differ by more than the soft-start time (typical 1.3 ms) plus 1 ms.
V3p3
(1)
V (EN pin)
In I2C mode regulators can also be enabled by setting their respective EN bits in the ENABLE register. The same
startup-time limitations and arbitration rules apply in I2C mode as described above.
V3p3
6uA
EN_BCKx
BUCK ENABLE
Enable
Threshold
Delay time = 0.2ms/nF
1.2V
(2)
BUCK A
Enable
BUCK C
Enable
BUCK B
Enable
Time
(1) Connect EN_BCKx pin to V3P3 to follow the default power-up sequence or
(2) Connect a capacitor from EN_BCKx to GND to generate a custom power-up sequence.
Figure 2. Customizing the Power-Up Sequence
OVER CURRENT PROTECTION
Over current protection (OCP) for BUCK1 is achieved by comparing the drain-to-source voltage of the low-side
MOSFET to a set-point voltage, which is defined by both the internal current source, ITRIP, and the external
resistor connected between the TRIP pin and ground. Over current threshold is calculated as Equation 1.
RTRIP · ITRIP
¾
ILIM = 10
· RDS(ON)
(1)
ITRIP has a typical value of 10 µA at 25°C and a temperature coefficient of 3700 ppm/°C to compensate the
temperature dependency of the MOS RDS(ON). The TPS65230 and TPS65231 support cycle-by-cycle over current
limiting control which means that the controller compares the drain-to-source voltage of the low-side FET to the
set-point voltage once per switching cycle and blanks out the next switching cycle if an over-current condition is
detected. If in the following cycle over current condition is detected again, the controller blanks out 2, then 4, 8,
and up to 16 cycles before turning on the high-side driver again. In an over current condition the current to the
load exceeds the current to the output capacitor thus the output voltage will drop, and eventually cross the under
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voltage protection threshold and shut down the BUCK controller. Buck 2 and 3 show a similar mode of operation.
All converters operate in hiccup mode: Once an over-current is sensed, the controller shuts off the converter for
a given time and then tries to start again. If the overload has been removed, the converter will ramp up and
operate normally. If this is not the case the converter will see another over-current event and shuts-down again
repeating the cycle (hiccup) until the failure is cleared.
SOFT START
Soft start (SS) for all three BUCKs is controlled by a single capacitor connected to the SS pin and an internal
current source. When one of the BUCKs is enabled, the SS capacitor is pre-charged to the output voltage
divided by the feed-back ratio before the internal SS current source starts charging the external capacitor. The
output voltage of the BUCK ramps up as the SS pin voltage increased from its pre-charged value to 0.8 V. The
soft start time is calculated from the SS supply current (ISS) and the capacitor value and has a typical value of
0.4 ms/nF or 1.3 ms for a 3.3-nF capacitor connected to the SS pin. Before the next rail is enabled, the SS cap is
discharged and the SS cycle starts over again.
BROWNOUT MONITOR (BOR)
The TPS65230 and TPS65231 monitor the input supply and issues a warning if the input voltage drops below the
BOR threshold of 9.3 V. The nBOR/nHOT pin is pulled low to alarm the host processor of the brown-out
condition. nBOR is released after the supply voltage has risen above 10.8 V. nBOR/nHOT pin is also pulled low
when the chip temperature rises above the HOT threshold and is released when the chip has cooled off. The
purpose of the nBOR/nHOT function is to give the host processor time to finish operations and store data before
the system shuts down. Both events, BOR and HOT, are individually flagged in the STATUS1 register. Note that
unlike the INT output pin, reading the STATUSx registers has no effect on the state of the nBOR/nHOT pin in I2C
mode. nBOR/nHOT depends only of the input voltage and temperature condition.
10
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VIN (12 V)
S ys tem resumes norm al
operation.
10.8V
9.3V
4.8V
nBOR /nHOT
Under Voltage Lock Out(UVLO)
disables all output rails and USB
UVLO (internal signal )
Time
Available time for controlled
shutdown of System
Thermal Shutdown (TSD )
Thermal warning (HOT )
160C
130C
NOTE: All rails are shutdown
when temperature exceeds TSD
threshold. System recovers
automatcally when IC has cooled
down to TSD- TSDHYSTERESIS
.
Temperature
nBOR/nHOT
Available time for controlled
shutdown of System
Figure 3. Brownout Monitoring
UNDER VOLTAGE LOCKOUT (UVLO)
TPS65230 and TPS65231 monitors VIN, VINB, and VINU pin voltages and will disable one or more power paths
depending on the current use condition:
• If VIN drops below 9.3 V, both USB power paths are disabled and the nBOR/nHOT output pin is pulled low.
• If VIN drops below 4.7 V, BUCK1, 2, and 3 are disabled.
• If VINB drops below 4.25 V and either BUCK2 or BUCK3 are enabled, all three output rails are disabled.
• If VINU drops below 3.9V and either USB1 or USB2 are enabled, both USB switches are disabled.
UVLO state is not latched and the system recovers as soon as the input voltage rises above its respective
threshold. All three BUCK_ENx pins are discharged and remain discharged during UVLO to ensure proper power
sequencing when the system recovers.
In I2C mode the EN_BUCKx and EN_USBx bits of the ENABLE register are reset in an UVLO event and interrupt
is issued. To re-enable the output supplies, the respective EN_BUCKx bits have to be set through the I2C
interface or the BUCK_ENx pins have to be pulled high. To re-enable the USB power switches in I2C mode, the
EN_USBx bits of the ENABLE register have to be set through the I2C interface.
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THERMAL SHUTDOWN (TSD)
TPS65230x monitors junction temperature and will disable all power paths (BUCK1-3, USB1 and 2) if junction
temperature rises above the specified trip point. nBOR/nHOT pin will be pulled low if the temperature approaches
the TSD trip point within 40°C. In I2C mode the device will also issue an interrupt and set the HOT bit in
STATUS1 register. The system recovers as soon as the temperature falls below the falling-edge trip
temperature. All three BUCK_ENx pins are discharged and remain discharged during TSD to ensure proper
power sequencing when the system recovers.
In I2C mode the EN_BUCKx and EN_USBx bits of the ENABLE register are reset in a TSD event and interrupt is
issued. To re-enable the output supplies the respective EN_BUCKx bits have to be set through the I2C interface
or the BUCK_ENx pins have to be pulled high. To re-enable the USB power switches in I2C mode, the EN_USBx
bits of the ENABLE register have to be set through the I2C interface.
LOOP COMPENSATION
All three BUCKs are voltage mode converters designed to be stable with ceramic capacitors. Refer to
Component Selection Procedure section for calculating feedback components.
3.3-V REGULATOR
The TPS6532x has a built-in 3.3-V regulator for powering internal circuitry. The 3.3-V rail can also be used for
enabling the BUCK regulators and/or the USB switches, but is not intended for supplying any other external
circuitry. For light loading of this rail during stand-by operation consult TI FAE.
6-V REGULATOR
The TPS6532x has a built-in 6-V regulator for powering internal circuitry. The 6-V rail can also be used for
enabling I2C functionality by connecting the pull-up resistor on the USBFLG2/nINT pin to V6V but is not intended
for supplying any other external circuitry. For light loading of this rail during stand-by operation consult TI FAE.
USER SELECTABLE SERIAL INTERFACE
TPS65230 and TPS65231 feature an I2C slave interface which can be enabled or disabled by the user and offers
advanced control and diagnostic features. I2C control is enabled when the pull-up resistor on the USBFLG2/nINT
pin is connected to a supply voltage > 4.5 V and is disabled otherwise. When disabled, BUCK1, 2, 3, and USB1,
2 are controlled through their respective enable pins. When the I2C interface is enabled, USB1 and USB2 are
controlled through the serial interface and BUCK1, 2, and 3 are controlled either through the serial interface or
their respective enable pins. In addition, the USBFLG1/VCTRL pin is reconfigured when I2C is enabled to offer
output voltage control for BUCK2 and BUCK3.
I2C operation offers brownout and thermal shutdown warning, thermal shut down flag, power-good and
under-voltage indicator for BUCK1-3 and USB fault indicator for both USB switches. Whenever a fault is
detected, the associated status bit in the STATUS1 and 2 registers are set and the INT pin is pulled low.
Reading of the STATUS1 and 2 registers resets the flag bits and INT pin is released after all flags have been
reset. Note that in I2C mode the nINT pin is active high with voltage swing of > 3.3 V. To invert the signal and
shift the voltage level down to an I/O compatible level, connect the circuit shown in Figure 5 to the USBFL2/nINT
pin.
INT Dependent Device Pin Configuration
USBFLG2/INT CONNECTED TO V6V (1)
USBFLG2/INT CONNECTED TO 3.3V (1)
PIN NO.
DEVICE PIN
30
USBFLG2/nINT
nINT
Error flag for USB switch 2
28
EN_USB1/SCL
SCL (Clock)
Enable pin for USB switch 1
29
EN_USB2/SDA
SDA (Data)
Enable pin for USB switch 2
44
USBFLG1/VCTRL
Voltage control input for BUCK2 and 3
Error flag for USB switch 1
(1)
12
Via pull-up resistor
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I2C operation also offers output voltage adjustment options for BUCK2 and BUCK3. This is feature is useful to
reduce power dissipation in the system by lowering the supply voltages when the system is in idle state. Output
voltage can be scaled down by 5, 10 and 15% depending on the VBCKn[1:0] bit settings in the VADJUST
register. Settings are activated when the USBFLG1/VCTRL pin is pulled high and are deactivated when the pin is
pulled low. This allows for fast output voltage transition without involvement of the I2C interface. Alternatively the
settings can be activated by setting the the VCTRLx bits of the ENABLE register.
VBCK3[1:0 ]
00 – 0%
01 – 5%
10 – 10%
11 – 15%
VBUCK3
VBCK2[1:0 ]
00 – 0%
01 – 5%
10 – 10%
11 – 15%
VBUCK2
VBUCK1
VCTRL pin
or VCTRL bit
Time
Figure 4. BUCK2 and BUCK3 Output Voltages
V6V
3.3V
4.7K
10K
To uC
USBFLG2/nINT
2222A
47.5K
Figure 5. Circuit for Level-Shifting and Inverting nINT Signal
I2C BUS OPERATION
The TPS65230 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment
addressing and is compliant to I2C standard 3.0.
Slave Address + R/nW
Start
G3
G2
G1
G0
A2
A1
A0
Sub Address
R/nW
ACK
S7
S6
S5
S4
S3
S2
Data
S1
S0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Stop
Figure 6. Subaddress in I2C Transmission
Start —
Start condition
G(3:0) —
Group ID: 1001
A(2:0) —
Device address: 000
R/nW —
Read/not write select bit
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ACK —
Acknowledge
S(7:0) —
Subaddress: defined per register map
D(7:0) —
Data: data to be loaded into the device
Stop —
Stop condition
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 7. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Map section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. The I2C interface will auto-sequence through register addresses, so that multiple
data words can be sent for a given I2C transmission. Reference Figure 7.
...
SDA
SCL
1
2
3
4
5
6
7
START CONDITION
8
...
9
ACKNOWLEDGE
STOP CONDITION
Figure 7. I2C Start / Stop / Acknowledge Protocol
t LO W
t r(
t H (S T A)
tF
SCL
t H (S TA )
t H (D A T )
tH I G H
t S( D AT )
t S (S TA )
t S (S TO )
SDA
P
t (B U F)
S
S
P
Figure 8. I2C Data Transmission Timing
14
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DATA TRANSMISSION TIMING
VBUS = 3.6 V ±5%, TA = 25 °C, CL = 100 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f(SCL)
Serial clock frequency
t(BUF)
Bus free time between stop and start condition
t(SP)
Tolerable spike width on bus
tLOW
SCL low time
tHIGH
SCL high time
tS(DAT)
SDA → SCL setup time
tS(STA)
Start condition setup time
tS(STO)
Stop condition setup time
tH(DAT)
SDA → SCL hold time
tH(STA)
Start condition hold time
tr(SCL)
Rise time of SCL signal
tf(SCL)
Fall time of SCL signal
tr(SDA)
Rise time of SDA signal
tf(SDA)
Fall time of SDA signal
MIN
MAX UNIT
SCL = 100 kHz
100
SCL = 400 kHz
400
SCL = 100 kHz
4.7
SCL = 400 kHz
1.3
SCL = 100 kHz
µs
50
SCL = 400 kHz
SCL = 100 kHz
4.7
SCL = 400 kHz
1.3
SCL = 100 kHz
4
SCL = 400 kHz
0.6
SCL = 100 kHz
250
SCL = 400 kHz
100
SCL = 100 kHz
4.7
SCL = 400 kHz
0.6
SCL = 100 kHz
4
SCL = 400 kHz
0.6
µs
ns
µs
µs
3.45
SCL = 400 kHz
0.9
4
SCL = 400 kHz
0.6
ns
µs
SCL = 100 kHz
SCL = 100 kHz
kHz
µs
µs
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 kHz
300
SCL = 400 kHz
300
SCL = 100 kHz
1000
SCL = 400 kHz
300
SCL = 100 kHz
300
SCL = 400 kHz
300
ns
ns
ns
ns
THERMAL MANAGEMENT AND SAFE OPERATING AREA
Total power dissipation inside TPS6523x is limited not to exceed the maximum allowable junction temperature of
150°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (θJA)
and ambient temperature. θJA itself is highly dependent on board layout. The maximum allowable power inside
the IC for operation at maximum ambient temperature without exceeding the temperature warning flag using the
JEDEC High-K board is calculated as Equation 3.
DT = qJA · P
TMAX - Tambient 120°C - 55°C
PMAX = ¾
= ¾
qJA
25°C/W » 2.6 W
(2)
(3)
For different PCB layout arrangements the thermal resistance (θJA) will change as the following table shows.
BOARD TYPE
θJA
STACK-UP
8" x 10" FR4 PCB, four layers
1.5-oz Cu, 60% Cu coverage top layer, 80% Cu coverage bottom
layer, no airflow
0.5-oz 30%Cu coverage inner layers
29
8” x 10” FR4 PCB, two layers
1-oz Cu, 20% Cu coverage top layer, 90% Cu coverage bottom
layer, no airflow
44
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A minimum of two layers of 1-oz Cu with 20% Cu coverage on the top and 90% coverage on the bottom and the
use of thermal vias to connect the thermal pad to the bottom layer is recommended. Note that the maximum
allowable power inside the device will depend on the board layout. For recommendations on board layout for
thermal management using TPS6523x consult your TI field application engineer.
3.5
3.5
3
3
3
2.5
2
S afe Operating Area
1.5
1
0.5
Current from BUCK3 [A] @ 3.3V
3.5
Cur rent fr om BUCK3 [A] @ 3.3V
Current from BUCK3 [A] @ 3 .3V
In the example shown above the maximum allowable power dissipation for the IC has been calculated. This
figure includes all heat sources inside the device including the power dissipated in BUCK1, BUCK2, BUCK3,
USB switches, and all supporting circuitry. Power dissipated in BUCK1, USB switches (500 mA full load) , and all
supporting circuitry is approximately 0.4 W and almost independent of the application. Power dissipated in
BUCK2 and BUCK3 depends on the output voltage, output current, and efficiency of the switching converters.
The following examples of safe operating area assume 90% efficiency for BUCK2 and BUCK3, 3.3-V output from
BUCK3 and 1.2-V, 1.8-V, and 2.5-V output from BUCK2, respectively.
2.5
2
Safe Operat ing Area
1.5
1
0.5
0
0.5
1
1.5
2
2.5
3
3.5
2
Sa fe Operating Area
1.5
1
0.5
0
0
2.5
0
0
Curr ent from BUCK2 [A] @ 1.2V or less
0.5
1
1.5
2
2.5
3
3.5
Curr ent from BUCK2 [A] @ 1.8V
0
0.5
1
1.5
2
2.5
3
3.5
Curre nt from BUCK2 [A] @ 2.5V
For any voltage / current comination inside the shaded area, the dissipated power inside the chip is below the allowable
maximum. The examples assume Tambient < 60°C, h = 90% and qJA < 44°C/W.
Figure 9. Examples of Thermal Safe Operating Area for V(BUCK3) = 3.3 V and V(BUCK1) = 1.2 V, 1.8 V
and 2.5 V, Respectively
COMPONENT SELECTION PROCEDURE
The following example illustrates the design procedure for selecting external components for the three buck
converters. The example focuses on BUCK1 but the procedure can be directly applied to BUCK2 and 3 as well.
The design goal parameters are given in the table below. A list of symbol definitions is found at the end of this
section. For this example the schematic in Figure 10 will be used.
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Figure 10. Sample Schematic for TPS6523x Showing Components Relevant to BUCK1
PARAMETER
VIN
VIN
TEST CONDITIONS
Input supply voltage
RIPPLE
VOUT
Input voltage ripple
MIN
TYP
10.8
IOUT,
BUCK1
MAX
12
=6A
Output Voltage
4.75
5
VIN = 10.8 V to 13.2 V
25
Load regulation
IOUT,
BUCK1
= 0 A to 6 A
25
Output ripple
IOUT,
BUCK1
=6A
VTRANS
Transient deviation
IOUT,
BUCK1
= 2 A to 6 A
IOUT
Output current
VIN = 10.8 V to 13.2 V
fSW
Switching frequency
RIPPLE
13.2
60
Line regulation
VOUT
UNIT
5.25
V
mV
mV
50
125
0
V
mV
mV
mV
6
500
A
kHz
INDUCTOR SELECTION
For BUCK1 the recommended inductor value is 4.7 µH and for BUCK2 and 3 it is 2.2 µH. These values will
provide a good balance between ripple current, efficiency, loop bandwidth and inductor cost. The inductor is
typically sized for < 30% peak-to-peak ripple current (IRIPPLE). Given this target ripple current, the required
inductor size is calculated by Equation 4.
VIN(MAX) - VOUT
L= ¾
0.3 · IOUT
·
VOUT
¾
VIN(MAX)
·
1
¾
fSW
(4)
Solving Equation 4 with VIN(MAX) = 13.2 V, an inductor value of 3.5 µH is obtained. A standard value of 4.7 µH is
selected, resulting in 1.25-A peak-to-peak ripple. The RMS current through the inductor is approximated by
Equation 5.
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¾2
¾
2
2
1 (I
1
IL(RMS) = Ö(IL(avg)2 + ¾
RIPPLE) ) = Ö(IOUT) + ¾ (IRIPPLE)
12
12
(5)
Using Equation 5, the maximum RMS current in the inductor is about 6.01 A.
OUTPUT CAPACITOR SELECTION
The selection of the output capacitor is typically driven by the output load transient response requirement. The
output capacitance (base) proposed is 2 x 22 µF (or 4 X 10 µF or 1 x 47 µF) ceramic, providing a good balance
between ripple, cost and performance. Extra caps added should be electrolyte or far from base cap to have
considerable amount of ESR and not to affect compensation.
Equation 6 and Equation 7 estimate the output capacitance required for a given output voltage transient
deviation.
ITRAN(MAX)2 · L
COUT(MIN) = ¾
(VIN(MIN) - VOUT) · VTRAN
when VIN(MIN) < 2 · VOUT
(6)
2
ITRAN(MAX) · L
COUT(MIN) = ¾
VOUT · VTRAN
when VIN(MIN) > 2 · VOUT
(7)
For this example, Equation 7 is used in calculating the minimum output capacitance.
Based on a 4-A load transient with a maximum 125-mV deviation (2.5% of set voltage), a minimum of 120-µF
output capacitance is required. We choose two 22-µF ceramic capacitors and two electrolytic 47 µF in parallel for
a total capacitance of 138 µF.
The output ripple is divided into two components. The first is the ripple generated by the inductor ripple current
flowing through the output capacitor’s capacitance, and the second is the voltage generated by the ripple current
flowing in the output capacitor’s ESR. The maximum allowable ESR is then determined by the maximum ripple
voltage and is approximated by Equation 8.
IRIPPLE
VRIPPLE(total) - ( ¾
VRIPPLE(total) - VRIPPLE(cap)
COUT · fSW )
ESRMAX = ¾
¾
=
IRIPPLE
IRIPPLE
(8)
Based only on the 138-µF of capacitance, 1.25-A ripple current, 500-kHz switching frequency and a design goal
of 50-mV ripple voltage (1% of set voltage), we calculate a capacitive ripple component of 18 mV and a
maximum ESR of 25 mΩ. The X5R ceramic capacitors selected provide significantly less than 25-mΩ of ESR.
PEAK CURRENT RATING OF THE INDUCTOR
With output capacitance known, it is now possible to calculate the charging current during start-up and determine
the minimum saturation current rating of the inductor. The start-up charging current is approximated by
Equation 9.
VOUT · COUT
ICHARGE = ¾
TSS
(9)
Using the TPS65230 and TPS65231’s recommended 1.3-ms soft-start time, COUT = 188 µF and VOUT = 5 V,
ICHARGE is found to be 720 mA. The peak current rating of the inductor is now found by Equation 10.
1
IL(PEAK) = IOUT(MAX) + ¾
2 IRIPPLE + ICHARGE
(10)
For this example an inductor with a peak current rating of 7.3 A is required. Note however that the inductor will
need to withstand the current limit figure without a major reduction of its rated inductance.
INPUT CAPACITOR SELECTION
The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(cap) = 60 mV (0.5% of
supply) and VRIPPLE(ESR) = 30 mV (0.25% of supply). The minimum capacitance and maximum ESR are
estimated by Equation 11 and Equation 12.
18
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ILOAD · VOUT
CIN(MIN) = ¾
VRIPPLE(cap) · VIN · fSW
(11)
VRIPPLE(ESR)
ESRMAX = ¾
1
ILOAD + ¾
2 IRIPPLE
(12)
For this design, CIN > 8 µF and ESR < 4 mΩ. The RMS current in the output capacitors is estimated by
Equation 13.
¾
2
1
VOUT VOUT · IOUT
IRMS(CIN) = IIN(RMS) - IIN(avg) = Ö((IOUT)2 + ¾
- ¾
12 (IRIPPLE) ) · ¾
VIN
VIN
(13)
With VIN = VIN(MAX), the input capacitors must support a ripple current of 1.4-A RMS. It is important to check the
DC bias voltage de-rating curves to ensure the capacitors provide sufficient capacitance at the working voltage.
Typically a 10-µF capacitor per converter is used. These capacitors should be placed as close as possible to the
VINB2 and VINB3 pins (BUCK2 and BUCK3) and to the external MOSFET arrangement for BUCK1.
BOOTSTRAP CAPACITOR
To ensure proper charging of the high-side MOSFET gate, limit the ripple voltage on the bootstrap capacitor to
< 5% of the minimum gate drive voltage.
20 · QGS, HSD
CBOOST = ¾
VIN(MIN)
(14)
Based on the FDS6982 MOSFET with a maximum total gate charge of 26 nC, calculate a minimum of 80-nF of
capacitance. A standard value of 220 nF is selected for BUCK1 and 100 nF for BUCK2.
SHORT CIRCUIT PROTECTION (BUCK1 ONLY)
The TPS65230 and TPS65231 uses the forward drop across the low-side MOSFET during the OFF time to
measure the inductor current. The voltage drop across the low-side MOSFET is given by Equation 15.
VDS = IL(PEAK) · RDSON, LSD
(15)
When VIN = 10.8 V to 13.2 V, IPEAK = 7.4A for full load (6 A). Using the FDS6982 MOSFET with a RDSON,MAX at TJ
= 25°C of 20 mΩ we calculate the peak voltage drop to be 148 mV. Adding a 50% margin to include inductor
variations and overload margin, the drop voltage for tip is set at 210 mV. Solving Equation 1 for RTRIP and using
ITRIP = 10 µA:
RTRIP = RDS(ON) · ILIM · 106
(16)
We calculate a trip resistor value of 210 kΩ. Place a 1-nF capacitor parallel to R9. Please note that typical FET
RDS(ON) is specified at 10 mΩ. Since we used RDSON,MAX, for setting the current limit, the actual current flowing
through the inductor with a nominal FET can be higher than the peak current of 7.4 A before the current limit
kicks in. Make sure that the chosen inductor has the correct peak current capabilities.
SHORT CIRCUIT PROTECTION (BUCK2 AND 3 ONLY)
Current limits for BUCK2 and 3 are internally set to 5 A.
FEEDBACK LOOP DESIGN
For the TPS6523x, the switching frequency and nominal output filter combination have been chosen to be
0.5 MHz 4.7 µH/~40 µF for BUCK1 and 1 MHz 2.2 µH/~40 µF for BUCK2 and 3 respectively. These values were
seen as a good compromise between efficiency and small solution size. The bandwidth has been chosen to be
around 1/8th - 1/11th of the switching frequency to maximize transient response whilst retaining low noise
sensitivity. As indicated before it is required that the output capacitor is ceramic and further that the very low ESR
causes it’s associated zero to be at or above the bandwidth of the converter.
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The control loop for the TPS6523x has an internal mid- to high-frequency zero-pole pair to compensate the
resonant pole caused by the output L-C filter. The maximum phase boost occurs at the geometric mean of the
pole zero arrangement and therefore aimed to be equal to the desired bandwidth. The pole limits the gain at high
frequencies to reduce noise sensitivity and it is about 5 times higher than the zero located at ~45 kHz.
The COMP pin of the buck converters is the output of an integrator Used to get high DC accuracy. The integrator
also takes care of any offsets in the zero-pole pair amplifier and the summing comparator inside the device. Also
a feed-forward loop is added to the attenuator circuit.
Vout
R2
FB
Cz
R1
Comp
Rc
Cc
Croll
Figure 11. External Compensation Circuit
The procedure to set the integrator values is very simple (see Figure 11):
1. Set the feed-forward circuit making R2 = 20 kΩ, CZ= 1 nF.
2. Calculate R1 as per output voltage requirement. Select R25 between 10 kΩ and 100 kΩ. For this design
select 22.1 kΩ, 0.1% resistor for the upper side of all dividers. Next, R29 Is selected to produce the desired
output voltage when VFB = 0.8 V using Equation 17.
VFB · R25
R29 = ¾
VOUT - VFB
(17)
VFB = 0.8 V and R25 = 22.1 kΩ for VOUT = 5.0 V, R25 = 4.209 kΩ. The closest value 4.22 kΩ.
3. Set the integrator values, RC = 20 kΩ, CC = 1 nF.
4. Make Croll = 100 pf to roll-off gain at high frequencies.
5. If VIN is ~20 - 24 V use 200 pF for Croll on DCDC1.
Other Components
A
•
•
•
•
20
1-µF ceramic capacitor should be connected as close as possible to the following pins:
BG (pin 1): Bandgap reference
VIN (pin 4): Bypass capacitor (higher values are acceptable)
V6V (pin 3): Internal 6 V supply
V3P3 (pin 25): Internal 3.3 V supply
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Register Address Map
REGISTER
ADDRESS (HEX)
NAME
DEFUALT VALUE
0
1
DESCRIPTION
00
ENABLE
0000 0000
Enable control register
01
VADJUST
0000 0000
Voltage adjustment register
2
02
STATUS1
0000 0000
Status bit register
3
03
STATUS2
0000 0000
Status bit register
ENABLE Register (ENABLE), Address - 0X00H
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
Not used
Not used
VCTRL
EN_BCK1
EN_BCK2
EN_BCK3
EN_USB1
EN_USB2
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
VALUE
0
0
0
0
0
0
0
0
FIELD NAME (1)
BIT DEFINITION
Voltage control bit for BUCK2 and BUCK3
0 – Nominal output voltage
1 – Enable voltage adjustment level set by VADJUST register
VCTRL
(1)
EN_BCK1
Enable BUCK1
0 – Disabled
1 - Enabled
EN_BCK2
Enable BUCK2
0 – Disabled
1 - Enabled
EN_BCK3
Enable BUCK3
0 – Disabled
1 - Enabled
EN-USB1
Enable USB1
0 – Disabled (OFF)
1 - Enabled
EN_USB2
Enable USB2
0 – Disabled (OFF)
1 – Enabled
Enable bits EN_BCK1, EN_BCK2, and EN_BCK3 are ORed with EN_BCK1, EN_BCK2, and EN_BCK3 enable pins, respectively. To
disable a block, EN bit and EN pin must be low.
VADJUST Register (VADJUST), Address - 0X01H
DATA BIT
D7
D6
D5
D4
D3
D2
D1
FIELD NAME
Not used
Not used
Not used
Not used
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
VALUE
0
0
0
0
0
0
0
0
FIELD NAME (1)
(1)
VBCK2[1:0]
D0
VBCK3[1:0]
BIT DEFINITION
VBCK2[1:0]
BUCK2 voltage adjustment
00 - Nominal
01 - 5% Decrease
10 - 10% Decrease
11 - 15% Decrease
VBCK3[1:0]
BUCK3 voltage adjustment
00 - Nominal
01 - 5% Decrease
10 - 10% Decrease
11 - 15% Decrease
Voltage adjustment settings for BUCK2 and BUCK3 are effective only when VCTRL pin is pulled high or VCTRL bit of ENABLE register
is set to ‘1’.
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STATUS Register (STATUS1), Address - 0X02H
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
BOR
TSD
HOT
UVLO
UVLOB
UVLOU
USBFLG1
USBFLG2
READ/WRITE
R
R
R
R
R
R
R
R
RESET
VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
(1)
BOR
Brownout. This bit is set whenever the input voltage drops below 9.3 V.
TSD
Thermal shutdown
HOT
Thermal shutdown early warning
UVLO
VIN under-voltage lockout
UVLOB
VINB under-voltage lockout
UVLOU
VINU under-voltage lockout
USBFLG1
USB fault flag (channel1)
USBFLG2
USB fault flag (channel2)
All status bits are cleared after register read access. INT output pin will go high-impedance (open drain output) after STATUS1 and
STATUS2 register have been read and / or all flags have been reset.
STATUS Register (STATUS2), Address - 0X03H
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
Not used
Not used
BCK1_UVD
BCK2_UVD
BCK3_UVD
BCK1_PG
BCK2_PG
BCK3_PG
READ/WRITE
R
R
R
R
R
R
R
R
RESET
VALUE
0
0
0
0
0
0
0
0
BIT DEFINITION (1)
FIELD NAME
BCK1_UVD
Under voltage detect, BUCK1
BCK2_UVD
Under voltage detect, BUCK2
BCK3_UVD
(1)
22
Under voltage detect, BUCK3
BCK1_PG
Power Good, BUCK1
BCK2_PG
Power Good, BUCK2
BCK3_PG
Power Good, BUCK3
Bits [5:3] are cleared after register read access. INT output pin will go high-impedance (open drain output) after STATUS1 and
STATUS2 register have been read and / or all flags have been reset.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65230A2DCA
ACTIVE
HTSSOP
DCA
48
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
TPS65230
A2
TPS65230A2DCAR
ACTIVE
HTSSOP
DCA
48
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
TPS65230
A2
TPS65231A2DCAR
ACTIVE
HTSSOP
DCA
48
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 85
TPS65231
A2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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