TPS65233RTER

TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 LNB VOLTAGE REGULATOR WITH I2C INTERFACE Check for Samples: TPS65233 FEATURES 1 • • • • • • • • • Complete Integration Solution for LNB and I2C DiSEqC 1.x Compatible Supports 5-V and 12-V Power Bus Up to 1000-mA Accurate Output Current Limit Adjustable by External Resistor and I2C Boost Converter With Low Rdson Internal Power Switch Dedicated Enable Pin for Non-I2C Application Low Noise, Low Drop Output With Push-Pull Output Stage Built-In Accurate 22-kHz Tone Generator or External Pin Adjustable Soft-Start and 13-V/18-V Voltage Transition Time • • • • • Compliant with main satellite receiver systems Specifications LNB Short Circuit Dynamic Pprotection Diagnostics for Output Voltage Level, Input Supply UVLO, and DiSEqC Tone Output Cable Disconnect Diagnostic Available in a 16-Pin QFN 3-mm x 3-mm (RTE) Package APPLICATIONS • • • Set Top Box Satellite Receiver TV Satellite Receiver PC Card Satellite Receiver DESCRIPTION/ORDERING INFORMATION Designed for analog and digital satellite receivers, the TPS65233 is a monolithic voltage regulator with I2C interface, specifically to provide the 13-V/18-V power supply and the 22-kHz tone signaling to the LNB downconverter in the antenna dish or to the multi-switch box. It offers a complete solution with very low component count, low power dissipation together with simple design and I2C standard interfacing. TPS65233 features high power efficiency. The boost converter integrates a 120-mΩ power MOSFET running at 500-kHz switching frequency. Drop out voltage at the linear regulator is 0.8 V to minimize power loss. TPS65233 provides multiple ways to generate the 22-kHz signal. Integrated linear regulator with push-pull output stage generates clean 22-kHz tone signal superimposed at the output even at zero loading. Current limit of linear regulator can be programmed by external resistor with ±10% accuracy. Full range of diagnostic read by I2C is available for system monitoring. The part is available in a 16-pin QFN 3-mm x 3-mm (RTE) package. ORDERING INFORMATION (1) TA -40°C to 85°C (1) (2) PACKAGE (2) 16-Pin (QFN) - RTE Reel of 2500 PART NUMBER TOP-SIDE MARKING TPS65233RTE TPS65233RTE For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM VIN VIN LX VCC EN REF_Boost Internal Regulator PWM Controller PGND REF_Boost TCAP VCTRL REF BOOST REF_LDO Charge Pump VCP SDA SCL I2C Interface EN/ADDR TGATE Fault Diagnose OCP OTP UVL FAULT 2 REF_LDO I2C EN TGATE 22kHz Tone Generator VLNB ISEL EXTM Submit Documentation Feedback AGND Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 10 9 SDA SCL/ VADJ 14 VCP FAULT 8 13 VLNB EN/ADDR 7 100nF 11 VCTRL VOUT 12 EXTM 13V/18V TYPICAL APPLICATION VCC AGND 6 VIN TCAP 1 2 3 4 22nF 1uF 22uH 1uF VIN 22uF (25V) 16 PGND LX 2x22uF (25V) ISEL 5 130k Ohm 15 BOOST Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 3 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com PIN OUT 11 10 9 VCTRL SDA SCL/ VADJ FAULT EN/ADDR 7 15 BOOST ISEL 6 16 PGND TCAP 5 13 VLNB 8 12 EXTM RTE PACKAGE (TOP VIEW) 14 VCP LX VIN VCC AGND Thermal Pad 1 2 3 4 Exposed pad must be soldered to PCB for optimal thermal performance. TERMINAL FUNCTIONS NAME NO. DESCRIPTION LX 1 Switching node of the boost converter VIN 2 Input of internal linear regulator VCC 3 Internal 6.5-V power supply bias. Connect a 1-µF ceramic capacitor from this pin to ground. When VIN is 5 V, connect VCC to VIN. AGND 4 Analog ground. Connect all ground pins and power pad together. TCAP 5 Connect a capacitor to this pin to set the rise time and fall time of the LNB output between 13 V and 18 V. ISEL 6 Connect a resistor to this pin to set the LNB output current limit. EN/ADDR 7 Enable pin to enable the whole chip; pull to ground to disable output, output will be pulled to ground. For I2C interface, pulling this pin high or low gives different I2C addresses. FAULT 8 This pin is an open drain output pin, it goes low if any fault flag is set. SCL/VADJ 9 I2C compatible clock input; if I2C function is not used, connect this pin to low set output voltage 13 V/18 V, connect to high set output voltage 13.4 V/18.6 V. SDA 10 I2C compatible bi-directional data VCTRL 11 Logic control pin for 13-V or 18-V voltage selection at LNB output EXTM 12 External modulation logic input pin which activates the 22-kHz tone output, feeding signal can be 22-kHz tone or logic high or low. VLNB 13 Output of the LNB power supply connected to satellite receiver or switch VCP 14 Gate drive supply voltage, output of charge pump, connect a capacitor between this pin to pin BOOST. BOOST 15 Output of the boost regulator and input voltage of the internal linear regulator PGND 16 Power ground for Boost Converter Thermal PAD 4 Must be soldered to PCB for optimal thermal performance. Have thermal vias on the PCB to enhance power dissipation. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND) Voltage range at VIN, LX, BOOST, VLNB Voltage range at VCP –1 to 30 V BOOST + 7V V Voltage at LX –1 to 30 V Voltage at VCC, EN, FAULT, SCL, SDA, VCTRL, ISEL, EXTM –0.3 to 7 V Voltage at TCAP –0.3 to 3.6 V Voltage at PGND, AGND –0.3 to 0.3 V TJ Operating junction temperature range –40 to 125 °C TSTG Storage temperature range –55 to 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 4.5 20 V TA Junction temperature –40 85 °C THERMAL INFORMATION TPS65233 THERMAL METRIC (1) RTE UNITS 16 PINS θJA Junction-to-ambient thermal resistance (2) 43.4 θJCtop Junction-to-case (top) thermal resistance (3) 45.6 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) 15 (7) 3.3 θJCbot (1) (2) (3) (4) (5) (6) (7) Junction-to-case (bottom) thermal resistance 15 °C/W 0.6 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN MAX UNIT Human body model (HBM), pin 13 (VLNB) 6000 V Human body model (HBM), other pins 2000 V 500 V Charge device model (CDM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 5 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = 12 V, fSW = 528 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 12 20 UNIT INPUT SUPPLY VIN Input voltage range VIN IDDSDN Shutdown supply current EN = 0 IDDQ Quiescent power supply current EN = 1, IOUT = 0 A, VLNB = 18 V UVLO VIN under voltage lockout 4.5 µA 23 mA Rising VIN 4.05 4.25 4.45 Falling VIN 3.6 3.8 4.1 Hysteresis V 160 450 V mV OUTPUT VOLTAGE Vctrl = 1, IOUT = 500 mA 18.2 18.6 19 Vctrl = 0, IOUT = 500 mA 13.1 13.4 13.7 VOUT Regulated output voltage VLINEREG Line regulation-DC VIN = 7.5 V to 16 V, IOUT = 500 mA VLOADREG Load regulation-DC IOUT = (10-90%)*IOUTMAX IOCP Output short circuit current limit RSEL = 200 kΩ, TJ = 25°C Tr, Tf 13 V/18 V Transition rising falling time Ccap = 5.6 nF fSW Boost switching frequency Ilimitsw Switching current limit VIN = 12 V, VOUT = 18.6 V 3.2 A Rdson_LS On resistance of low side FET on CH VIN = 12 V 120 mΩ Vdrop Linear regulator voltage drop-out IOUT = 500 mA 0.8 V Irev Reverse bias current EN = 1, VLNB = 21 V 50 mA Irev_dis Disabled reverse bias current EN = 0, VLNB = 21 V 3 mA 0.2 %/V 0.7 580 650 %/A 720 mA 570 kHz 0.33 490 528 V ms LOGIC SIGNALS VEN Enable threshold level VENH Enable threshold level hysterisis VLOGICh, VLOGICl VCTRL, EXTM Logic threshold level VOL FAULT Output low voltage FAULT 1.15 High level input voltage mV 2 Low level input voltage 0.8 FAULT open drain, IOL= 1 mA 0.4 2 fI2C V 80 Maximum I C clock frequency 400 V V kHz TONE ftone Tone frequency Atone Tone amplitude Dtone Tone duty cycle IOUT = 0 mA to 500 mA, COUT = 100 nF Trtone Tone rise time IOUT = 0 mA to 500 mA, COUT = 100 nF Tftone Tone fall time IOUT = 0 mA to 500 mA, COUT = 100 nF 20 22 24 kHz 550 680 750 mV 45 50 55 % 10 µS 10 µS PROTECTION TON Over Current Protection On Time 4 ms TOFF Over Current Protection Off Time 128 ms 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VIN = 12 V, fSW = 528 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN TTRIP Thermal shut down trip point THYST Thermal shut down hysteresis Rising temperature 160 °C 20 °C I2C READ BACK FAULT STATUS Feedback voltage low side rising VPGOOD PGOOD Trip levels Twarn Temperature warning threshold 95.3 Feedback voltage low side falling 94.7 Feedback voltage high side rising 105.3 Feedback voltage high side falling 104.7 % 125 °C I2C INTERFACE VIH SDA,SCL Input high voltage VIL SDA,SCL Input low voltage 2 II Input current SDA, SCL, VI = 0.4 V to 4.5 V VOL SDA Output low voltage SDA open drain, IOL = 2 mA f(SCL) Maximum SCL clock frequency 400 kHz tBUF Bus free time between a STOP and START condition 1.3 µs tHD_STA Hold time (Repeated) START condition 0.6 µs tSU_STO Setup time for STOP condition 0.6 µs tLOW LOW Period of the SCL clock 1.3 µs tHIGH HIGH Period of the SCL clock 0.6 µs tSU_STA Setup time for a repeated START condition 0.6 µs tSU_DAT Data setup time 0.1 tHD_DAT Data hold time -10 V 0.8 V 10 µA 0.4 V µs 0 0.9 µs 300 ns tRCL Rise time of SCL signal Capacitance of one bus line (pF) 20 + 0.1CB tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge BIT Capacitance of one bus line (pF) 20 + 0.1CB 300 ns tFCL Fall time of SCL signal Capacitance of one bus line (pF) 20 + 0.1CB 300 ns tRDA Rise time of SDA signal Capacitance of one bus line (pF) 20 + 0.1CB 300 ns tFDA Fall time of SDA signal Capacitance of one bus line (pF) 20 + 0.1CB 300 ns CB Capacitance of one bus line (SCL and SDA) 400 pF Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 7 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) 100.00% 13.67 98.00% 13.62 96.00% 13.57 92.00% Vout (V) Efficiency (%) 94.00% 90.00% 88.00% 86.00% 13.52 13.47 13.42 84.00% 13.37 82.00% 80.00% 13.32 0.00 0.20 0.40 0.60 0.80 1.00 0.00 0.20 0.40 Loading (A) 0.80 1.00 Figure 2. Load Regulation (VIN = 12 V, VLNB = 13.4 V) 100.00% 18.80 98.00% 18.78 96.00% 18.76 94.00% 18.74 92.00% 18.72 Vout (V) Efficiency (%) Figure 1. Efficiency (VIN = 12 V, VLNB = 13.4 V) 90.00% 88.00% 18.70 18.68 86.00% 18.66 84.00% 18.64 82.00% 18.62 18.60 80.00% 0.00 0.20 0.40 0.60 0.80 1.00 0.00 0.20 Loading (A) 8 0.60 Loading (A) 0.40 0.60 0.80 1.00 Loading (A) Figure 3. Efficiency (VIN = 12 V, VLNB = 18.6 V) Figure 4. Load Regulation (VIN = 12 V, VLNB = 18.6 V) Figure 5. Boost LX Waveform at 0 A, (VIN = 12 V, VLNB = 13.4 V) Figure 6. Boost LX Waveform at 0.5 A, (VIN = 12 V, VLNB = 13.4 V) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) Figure 7. Boost LX Waveform at 0 A, (VIN = 12 V, VLNB = 18.6 V) Figure 8. Boost LX Waveform at 0.5 A, (VIN = 12 V, VLNB = 18.6 V) Figure 9. Boost LX Waveform at 0 A, (VIN = 5 V, VLNB = 13.4 V) Figure 10. Boost LX Waveform at 0.5 A, (VIN = 5 V, VLNB = 13.4 V) Figure 11. Boost LX Waveform at 0 A, (VIN = 5 V, VLNB = 18.6 V) Figure 12. Boost LX Waveform at 0.5 A, (VIN = 5 V, VLNB = 18.6 V) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 9 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) 10 Figure 13. VIN = 12 V, VLNB = 13.4 V, No Loading, Soft Start Figure 14. VIN = 12 V, VLNB = 13.4 V, 1 A, Soft Start Figure 15. VIN = 12 V, VLNB = 18.6 V, No Loading, Soft Start Figure 16. VIN = 12 V, VLNB = 18.6 V, 1 A, Soft Start Figure 17. VIN = 12 V, VLNB = 13.4 V, 0 A, Shutdown Figure 18. VIN = 12 V, VLNB = 18.6 V, 0 A, Shutdown Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) Figure 19. VIN = 12 V, VLNB = 13.4 V to 18.6 V, 0 A, Voltage Transition Figure 20. VIN = 12 V, VLNB = 13.4 V to 18.6 V, 1 A, Voltage Transition Figure 21. VIN = 12 V, VLNB = 18.6 V to 13.4 V, 0 A, Voltage Transition Figure 22. VIN = 12 V, VLNB = 18.6 V to 13.4 V, 1 A, Voltage Transition Figure 23. VIN = 5 V, VLNB = 13.4 V to 18.6 V, 0 A, Voltage Transition Figure 24. VIN = 5 V, VLNB = 13.4 V to 18.6 V, 0.5 A, Voltage Transition Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 11 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) 12 Figure 25. VIN = 5 V, VLNB = 18.6 V to 13.4 V, 0 A, Voltage Transition Figure 26. VIN = 5 V, VLNB = 18.6 V to 13.4 V, 0.5 A, Voltage Transition Figure 27. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Figure 28. VIN = 12 V, VLNB = 13.4 V, 1 A, 22-kHz Tone Figure 29. VIN = 12 V, VLNB = 18.6 V, No Loading, 22-kHz Tone Figure 30. VIN = 12 V, VLNB = 18.6 V, 1 A, 22-kHz Tone Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) Figure 31. VIN = 5 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Figure 32. VIN = 5 V, VLNB = 13.4 V, 0.5 A, 22-kHz Tone Figure 33. VIN = 5 V, VLNB = 18.6 V, No Loading, 22-kHz Tone Figure 34. VIN = 5 V, VLNB = 18.6 V, 0.5 A, 22-kHz Tone Figure 35. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from EXTM Turns High to Output Tone, On Figure 36. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from EXTM Turns High to Output Tone, On Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 13 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) 14 Figure 37. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from I2C SDA to Output Tone, On Figure 38. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from I2C Gated, EXTM Provides 22 kHz to Output Tone, On Figure 39. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from EXTM 22 kHz to Output Tone, Off Figure 40. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from EXTM Turns High to output Tone, Off Figure 41. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from I2C SDA to Output Tone, Ooff Figure 42. VIN = 12 V, VLNB = 13.4 V, No Loading, 22-kHz Tone Delay from I2C Ggated, EXTM Provides 22 kHz to Output Tone, Off Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) Figure 43. VIN = 12 V, VLNB = 13.4 V, No Loading, Tone Burst Figure 44. VIN = 12 V, VLNB = 13.4 V, No Loading, EXTM Level Figure 45. VIN = 12 V, VLNB = 13.4 V, Hard Short Figure 46. VIN = 12 V, VLNB = 13.4 V, Hard Short Figure 47. VIN = 12 V, VLNB = 13.4 V, Hard Short Recovery Figure 48. VIN = 5 V, VLNB = 13.4 V, Hard Short Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 15 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TA = 25°C, VIN = 12 V, fSW = 528 kHz, Cboost = 2 x 22 µF (unless otherwise noted) Figure 49. VIN = 5 V, VLNB = 13.4 V, Hard Short 16 Figure 50. VIN = 5 V, VLNB = 13.4 V, Hard Short Recovery Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 OVERVIEW TPS65233 is a power management IC that integrates a boost converter, a LDO and a 22-kHz tone generator serves as a LNB power supply. This solution compiles the DiSEqC 1.x standard with or without I2C interface. Output current can be precisely programmed by an external resistor. There are four ways to generate the 22-kHz tone signal with or without I2C. Integrated boost features low Rdson MOSFET and internal compensation. Fixed 500-kHz switching frequency is designed to reduce components size. DETAILED DESCRIPTION Boost Converter The TPS65233 consists of an internal compensated boost converter and linear regulator. The boost converter tracks the output LNB voltage to within 800 mV even at loading 750 mA, to minimize power dissipation. Under conditions where the input voltage, VBOOST, is greater than the output voltage, VLNB, the linear regulator must drop the differential voltage. When operating in these conditions, care must be taken to ensure that the safe operating temperature range of the TPS65233 is not exceeded. The boost converter operates at 528 kHz typical. The TPS65233 has internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is limited. The current limit is set by the external resistor. And the IC will be shut down if the overcurrent condition lasts for more than 4 ms, the converter enters hiccup mode and will re-try startup in 128 ms. At extremely light loads, the boost converter operates in a pulse-skipping mode. If two or more set top box LNB outputs are connected together, one output voltage could be set higher than others. The output with lower set voltage would be effectively turned off. Once the voltage drops to the set level, the LNB output with lower set output voltage will return to normal conditions. Linear Regulator and Current Limit The linear regulator is used to generate the 22-kHz tone signal by changing the reference voltage. The linear regulator features low drop out voltage to minimize power loss while keeps enough head room for the 0.68-V, 22-kHz tone. It also implements a tight current limit for over current protection. The current limit is set by an external resistor connected to ISEL pin. The curve below shows the relationship between the current limit threshold and the resistor value. Figure 51. Linear Regulator Current Limit Versus Resistor Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 17 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com RSEL (kW) = 124.11× ISEL -1.178 (A) (1) A 270-kΩ resistor set the current to be 0.5 A. The current limit can also be set by I2C through register. Charge Pump The charge pump circuitry generates a voltage to drive the NMOS of the linear regulator. One end the charge pump capacitor is connected to the output of the boost converter. The voltage on the charge pump capacitor is about 6.25 V. Slew Rate Control When LNB output voltage transits from 13 V to 18 V or vice versa, the capacitor at pin TCAP controls the transition time. This transition is to make sure the boost converter can follow the voltage change. Usually boost converter has low bandwidth and can’t response fast. The voltage at TCAP acts as the reference voltage of the linear regulator. The boost converter’s reference is also based on TCAP with additional fixed voltage to generate 0.8 V above the output. The charging and discharging current is 10 µA, thus the transition time can be calculated as: C (nF) Tcad (ms) = 0.5 × ss Iss (mA) (2) A 22-nF capacitor generates 1.1-ms transition time. In light load conditions, when LNB output voltage is set from 18 V to 13 V, the voltage might drops very slow, which might cause wrong logic detection at LNB side. TPS65233 has the integrated a pull down circuit to pull down the output during the transition. This will ensure the voltage change can follow the voltage at TCAP. Meanwhile, when 22-kHz tone signal is superimposing on the LNB output voltage, the pull down current can also provide square wave instead of a distorted waveforms, which could cause another detection problem. Capacitor Selection TPS65233 works fine with all ceramic capacitors. Two 22-uF, 35-V capacitors can be put at the output of the boost converter. If lower cost is demanded, a 100-µF electrolytic and a 1-µF ceramic capacitor work well also. Short Circuit Protection, Hiccup and Over Temperature Protection The LNB output limit can be set by an external resistor. When short circuit conditions occur, the output current is clamped at the current limit for 4 ms. If the condition remains, the converter will shut down for 128 ms and then try restart. This hiccup behavior prevents the IC from overheating. The low side MOSFET of the boost converter has a current limit threshold at 3.2 A, which serves as secondary protection. If the boost converter’s peak current limit is triggered, the peak current will clamp at 3.2 A. If loading current continues to increase, output voltage starts to drop and output power drops. Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die temperature exceeds 160°C, the output shuts down. When the temperature drops below its lower threshold, typically 140°C, the output is enabled. When the chip is in over current protection or thermal shutdown, the I2C interface and some logic are still active. The Fault pin is pulled down to signal the processor. The Fault pin signal will remain low unless the following actions are taken: 1. If I2C interface is not used to control, Enable pin must be recycled in order to pull Fault pin back to high. 2. If I2C interface is used, the I2C master needs to read the OCP or OTP bit in the register, then the Fault pin returns to high. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 Tone Generation A 22-kHz tone signal is superimposed at the LNB output voltage as a carrier for DiSEqC command. This tone signal can be generated by feeding an external 22-kHz clock at the EXTM pin. It can also be generated with its internal tone generator gated by control logic. The output stage of the regulator facilitates a push-pull circuit, so even at zero loading the 22-kHz tone at the output is still clear of distortion. There are four ways to generate the 22-kHz tone signal at the output. EXTM TMODE TGATE TONE VLNB(V) Option 1, Use external tone EXTM TMODE TGATE TONE VLNB(V) Option 2, Use internal tone, gated by EXTM logic EXTM TMODE TGATE TONE VLNB(V) Option 3, Use external tone, gated by TGATE EXTM TMODE TGATE TONE VLNB(V) Option 4, Use internal tone, gated by TGATE Figure 52. Four Ways to Generate 22-kHz Tone Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 19 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com Serial Interface Description I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and transmits data on the bus under control of the master device. The TPS65233 device works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 4.5 V (typical). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The TPS65233 device supports 7-bit addressing; 10-bit addressing and general call address are not supported. The TPS65233 device has a 7-bit address with the 2 LSB bits set by EN pin. Connecting EN to ground set the address 0x60H, connecting to high set the address 0x61H. Table 1. I2C Address Selection EN/ADDR PIN I2C ADDRESS Connect to Ground 0x60H Connect to High 0x61H Figure 53. I2C Interface Timing Diagram TPS65233 I2C Update Sequence The TPS65233 requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, TPS65233 device acknowledges by pulling the SDA line low during the high period of a single clock pulse. TPS65233 performs an update on the falling edge of the LSB byte. When the TPS65233 is disabled (EN pin tied to ground) the device can still be updated via the I2C interface. S 7-Bit Slave Address 0 A Register Address A Data Byte A P Figure 54. I2C Write Data Format 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 S 0 A 7-Bit Slave Address A Sr Register1 Address 7-Bit Slave Address 1 A N P Data Byte Figure 55. I2C Read Data Format A: Acknowledge N: Not Acknowledge S: Start System Host P: Stop Chip Sr: Repeated Start Register Description Register descriptions are shown below tables. Table 2. Control Register 1 NO. OF BITS ACCESS NAME DEFAULT VALUE I2C_CON 0 1: I2C control enabled; 0: I2C control disabled 0 reserved DESCRIPTION Control Register Bit 8 address: 0x00H Bit 7 R/W Bit 6 R/W Bit 5 R/W TGATE 0 Tone Gate. Allows either the internal or external 22-kHz tone signals to be gated. 1: Tone Gate on, 0: Tone gate off Bit 4 R/W TMODE 0 Tone mode. Select between the use of an external 22-kHz or internal 22-kHz signal. 1: internal; 0: external Bit 3 R/W EN 1 LNB output voltage Enable 1: output enabled; 0: output disabled Bit 2 R/W VSEL2 0 VSEL1 0 Bit 1 R/W Bit 0 See Table 3 for output voltage selection R/W VSEL0 0 Table 3. Voltage Selection Bits VSEL2 VSEL1 VSEL0 0 0 0 LNB(V) 13 0 0 1 13.4 0 1 0 13.8 0 1 1 14.2 1 0 0 18 1 0 1 18.6 1 1 0 19.2 1 1 1 19.8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 21 TPS65233 SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 www.ti.com Table 4. Control Register 2 NO. OF BITS ACCESS NAME DEFAULT VALUE Control Register Bit 8 address: 0x01H Bit 7 R/W Bit 6 R/W Bit 5 R/W Bit 4 R/W TONE_POS1 0 Bit 3 R/W TONE_POS0 1 Bit 2 R/W CL1 0 Bit 1 R/W CL0 0 Bit 0 R/W CL_EXT 1 DESCRIPTION 00: tone above Vout; 01: tone in the middle of Vout; 10: tone below Vout Current limit set bits 1: current limit set by external resistor; 0: current limit set by register Some tone detection circuits in LNB is sensitive to the position of the tone on the output voltage. TPS65233 provides options to selection the position by setting the TONE_POS1 and TONE_POS0 bits, as illustrated below. Option 1, TONE_POS1=0, TONE_POS0=0, Tone above VLNB Option 2, TONE_POS1=0, TONE_POS0=1, Tone in the middle of VLNB Option 2, TONE_POS1=1, TONE_POS0=0, Tone below VLNB Figure 56. Tone Position Programmed by TONE_POS1, TONE_POS0 Bits In addition to program the LDO’s current continuously via an external resistor, internal registers also provide options to program the current limit. There are four options can be selected. Table 5. Current Limit Selection Bits CL1 CL0 CURRENT LIMIT (mA) 0 0 400 0 1 600 1 0 750 1 1 1000 TPS65233 has full range of diagnostic flags for operation and debug. If any of the flags are triggered, pin FAULT will be pulled low, sending an interrupt signal to processor. Processor then can read the status register to check the error conditions. Status bits are described as follow. Among these bits, TSD and OCP are different from others. Once TSD and OCP are set to “1”, the Fault pin logic is latched to low, processor need to reset the bits in order to release the fault conditions. Other bits will change as conditions change without latch. 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS65233 TPS65233 www.ti.com SLVSC22A – AUGUST 2013 – REVISED SEPTEMBER 2013 Table 6. Status Register 1 ACCESS NAME DEFAULT VALUE Bit 6 R T125 0 1: if die temperature T>125°C; 0: if die temperature T