TPS65252
www.ti.com
SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
4.5-V TO 16-V INPUT, HIGH CURRENT, SYNCHRONOUS STEP DOWN DUAL BUCK
SWITCHER WITH INTEGRATED FET AND ONE USB SWITCH AND SVS
Check for Samples: TPS65252
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Input Supply Voltage Range
(4.5 V - 16 V)
Output Range 0.8 to ~VIN - 1 V
Fully Integrated Dual Buck,
3.5-A/2.5-A Maximum Current,
3-A/2-A Continuous Operation
High Efficiency
Switching Frequency:
300 kHz - 2.2 MHz Set By External Resistor
External Enable/Sequencing Pins
Adjustable Cycle-By-Cycle Current Limit Set
By External Resistor
Soft Start Pins
Current Mode Control With Simple
Compensation Circuit
Power Good and Reset Generator
Low Power Mode Set By External Signal
One Current Adjustable USB Switch With Over
Current Protection
Supervisory Circuit
QFN Package, 28-Pin 5 mm x 5 mm RHD
DTV
DSL Modems
Cable Modems
Set Top Boxes
Car DVD Players
Home Gateway and Access Point Networks
Wireless Routers
ROSC
OSC
VPULL
V3V
V7V
INTERNAL
VOLTAGE RAILS
PGOOD
Vin
PGOOD
BST1
VIN1
Vout BUCK1
LX1
SS1
LX1
BUCK1
EN1
FB1
from enable logic
CMP1
Rlim1
BST2
VIN2
Vout BUCK2
LX2
SS2
LX2
BUCK2
EN2
from enable logic
FB2
CMP2
Rlim2
Low_P
Light Load
Power Saving
USB Input
VPULL
USB_VIN
rUSB
Enable logic
USB
USB_EN
USB over current
USB_nILIM
USB Output
USB_VO
DESCRIPTION/ORDERING INFORMATION
The TPS65252 features two synchronous wide input range high efficiency buck converters. The converters are
designed to simplify its application while giving the designer the option to optimize their usage according to the
target application.
The converters can operate in 5-, 9- or 12-V systems and have integrated power transistors. The output voltage
can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each
converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows
adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables
designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The COMP
pin allows optimizing transient versus dc accuracy response with a simple RC compensation.
The switching frequency of the converters can be set with an external resistor connected to ROSC pin. The
switching regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase
between them to minimize the input filter requirements.
TPS65252 also features a low power mode enabled by an external signal, which allows for a reduction on the
input power supplied to the system when the host processor is in stand-by (low activity) mode.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
TPS65252
SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
www.ti.com
The USB switch provides up to 1-A of current as required by downstream USB devices. When the output load
exceeds the current-limit threshold selected with an external resistor or a short is present, the PMU limits the
output current to a safe level by switching into a constant-current mode and pulling the over current logic output
low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing
the junction temperature to rise, a thermal protection circuit shuts off the switch to allow continuous noninterrupted operation the buck converters.
The TPS65252 features a supervisor circuit that monitors both converters and provides a PGOOD signal (End of
Reset) with a 256-ms timer.
TPS65252 is packaged in a small, thermally efficient 28-pin QFN package.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL APPLICATION
V PULL
EN2
RLIM2
CMP2
FB2
LOW_P
V7V
Host
SS2
FB2
Host
V3V
FB 2
rUSB
BST 2
PGOOD
VIN 2
VIN 2
V2
Host
USB _EN
USB _ nILIM
V PULL
USB _I
Host
LX 2
TPS65252
LX 2
V1
USB _ VIN
LX 1
USB _ Vo
LX 1
BST1
EN1
RLIM1
SS1
CMP1
VIN 1
2
VIN 1
FB 1
FB1
FB1
ROSC
USB _O
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Copyright © 2010–2012, Texas Instruments Incorporated
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SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
FUNCTIONAL BLOCK DIAGRAM
ROSC
OSC
V PULL
V3V
V7V
12V DC Supply
INTERNAL
VOLTAGE RAILS
PGOOD
PGOOD
BST 1
VIN1
Vout BUCK 1
LX1
SS 1
V3V
EN1
from enable logic
LX1
BUCK 1
FB1
Rlim 1
CMP1
VIN 2
BST2
V3V
EN2
from enable logic
LX2
BUCK 2
FB2
CMP2
Rlim2
Low _P
Vout BUCK 2
LX2
SS2
Light Load
Power Saving
rUSB
USB_VIN
V3 V
USB
USB_EN
USB Input
USB _nILIM
USB_VO
V PULL
Enable logic
USB over current
USB Output
ORDERING INFORMATION (1)
(1)
(2)
TA
PACKAGE (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
28-pin (QFN) - RHD
TPS65252RHD
TPS65252
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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TPS65252
SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
www.ti.com
PIN OUT
LOW_P
FB2
COMP2
SS2
RLIM2
20
19
18
17
16
EN2
V7V
4
21
24
QFN RHD28
12
LX2
USB_EN
25
POWER PAD
(GND)
11
LX2
USB_nILIM
26
10
LX1
USB_VIN
27
9
LX1
USB_VO
28
8
VIN1
1
2
3
4
5
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6
7
BST1
PGOOD
EN1
VIN2
RLIM1
13
SS1
23
COMP1
V3V
rUSB
FB1
22
ROSC
V3V
15
14
BST2
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: TPS65252
TPS65252
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SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
TERMINAL FUNCTIONS
NAME
I/O
NO.
ROSC
I
1
Oscillator set. This resistor sets the frequency of internal autonomous
clock.
FB1
I
2
Feedback pin for buck 1. Connect a divider set to 0.8V from the output of
the converter to ground.
COMP1
O
3
Compensation pin for buck 1. Fit a series RC circuit to this pin to
complete the compensation circuit of this converter.
SS1
I
4
Soft start pin for buck 1. Fit a small ceramic capacitor to this pin to set the
converter soft start time.
RLIM1
I
5
Current limit setting pin for buck 1. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
EN1
I
6
Enable pin for buck 1. A high signal on this pin enables the regulator
buck. For a delayed start-up add a small ceramic capacitor from this pin
to ground.
BST1
I
7
Bootstrap capacitor for buck 1. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
VIN1
I
8
Input supply for buck 1. Fit a 10-µF ceramic capacitor close to this pin.
LX1
LX1
LX2
LX2
O
O
9
10
11
12
DESCRIPTION
Switching node for buck 1
Switching node for buck 2
VIN2
I
13
Input supply for buck 2. Fit a 10-µF ceramic capacitor close to this pin.
BST2
I
14
Bootstrap capacitor for buck 1. Fit a 47-nF ceramic capacitor from this pin
to the switching node.
EN2
I
15
Enable pin for buck 2. A high signal on this pin enables the regulator
buck. For a delayed start-up add a small ceramic capacitor from this pin
to ground.
RLIM2
I
16
Current limit setting pin for buck 2. Fit a resistor from this pin to ground to
set the peak current limit on the output inductor.
SS2
I
17
Soft start pin for buck 2. Fit a small ceramic capacitor to this pin to set the
converter soft start time.
COMP2
O
18
Compensation pin for buck 2. Fit a series RC circuit to this pin to
complete the compensation circuit of this converter.
FB2
I
19
Feedback pin for buck 2. Connect a divider set to 0.8V from the output of
the converter to ground.
LOW_P
I
20
Low power operation mode (active high) input for TPS65252
V7V
O
21
Internal supply. Connect a 10-µF ceramic capacitor from this pin to
ground.
V3V
O
22
Internal supply. Connect a 3.3-µF to 10-µF ceramic capacitor from this pin
to ground.
rUSB
I
23
USB current limit setting resistor. Fit a resistor from this pin to ground to
set the peak current limit on the USB switch.
PGOOD
24
Open drain power good output
USB_EN
I
25
Enable input, logic high turns on the USB
USB_nILIM
O
26
Over current open-drain output, active low
USB_VIN
I
27
USB input supply
USB_VO
O
28
USB switch output
PAD
Power pad. Connect it to ground
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TPS65252
SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
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ABSOLUTE MAXIMUM RATINGS (OPERATING IN A TYPICAL APPLICATION CIRCUIT)
(1)
Over operating free-air temperature range and all voltages are with respect to GND (unless otherwise noted).
Voltage range at VIN1,VIN2, LX1, LX2
–0.3 to 18
V
Voltage range at LX1, LX2 (maximum withstand voltage transient < 20 ns)
–3 to 18
V
Voltage at BST1, BST2, referenced to Lx pin
–0.3 to 7
V
Voltage at V7V, COMP1, COMP2, USB_VIN, USB_VO
–0.3 to 7
V
Voltage at V3V, RLIM1, RLIM2, EN1,EN2, SS1, SS2, FB1, FB2, ROSC, LOW_P,
USB_EN, USB_nILIM, PGOOD, rUSB
–0.3 to 3.6
V
Voltage at GND
–0.3 to 0.3
V
TJ
Operating virtual junction temperature range
–40 to 125
°C
TSTG
Storage temperature range
–55 to 150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
16
V
TA
Operating ambient temperature
–40
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
Human body model (HBM)
Charge device model (CDM)
MAX
UNIT
2000
V
500
V
PACKAGE DISSIPATION RATINGS (1)
(1)
6
PACKAGE
θJA (°C/W)
TA = 25°C
POWER RATING (W)
TA = 55°C
POWER RATING (W)
RHD
34 (simulated)
2.9
2
Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x .6-mm board with the following layer arrangement:
(a) Top layer: 2 Oz Cu, 6.7% coverage
(b) Layer 2: 1 Oz Cu, 90% coverage
(c) Layer 3: 1 Oz Cu, 90% coverage
(d) Bottom layer: 2 Oz Cu, 20% coverage
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SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
ELECTRICAL CHARACTERISTICS
TJ = -40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN
Input Voltage range
IDDSDN
Shutdown
EN pin = low for all converters
0.3
mA
IDDQ
Quiescent, low power disabled (Lo)
Converters enabled, no load
10
mA
IDDQ_LOW_P
Quiescent, low power enabled (Hi)
Converters enabled, no load
0.5
mA
UVLOVIN
4.5
VIN under voltage lockout
UVLODEGLITCH
V3p3
Internal biasing supply
I3V
Biasing supply output current
V7V
Internal biasing supply
I7V
Biasing supply output current
V7VUVLO
UVLO for internal V7V rail
16
Rising VIN
4.22
Falling VIN
4.1
Both edges
110
V
V
µs
3.3
VIN = 12 V
V
10
mA
10
mA
6.25
VIN = 12 V
V7VUVLO_DEGLITCH
Rising V7V
3.8
Falling V7V
3.6
Falling edge
110
V
V
µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT START, SWITCHING FREQUENCY AND LOW POWER MODE)
Enable threshold high
V3p3 = 3.2 V - 3.4 V, VENx
rising
1.55
Enable high level
External GPIO, VENX rising
0.66 x
V3p3
Enable threshold Low
V3p3 = 3.2 V - 3.4 V, VENx
falling
0.98
Enable low level
External GPIO, VENX falling
VIH
VIL
1.82
V
1.24
V
0.33 x
V3p3
ICHEN
Pull up current enable pin
REN_DIS
Enable discharge resistor
1.1
tD
Discharge time enable pins
ISS
Soft start pin current source
FSW_BK
Converter switching frequency range
Set externally with resistor
0.3
2.2
MHz
RFSW
Frequency setting resistor
Depending on set frequency
50
600
kΩ
fSW_TOL
Internal oscillator accuracy
fSW = 800 kHz
-10
10
%
VIHLOW_P
Low power mode threshold high
V3p3 = 3.3 V
1.55
1.82
V
VILLOW_P
Low power mode threshold Low
V3p3 = 3.3 V
0.98
1.24
V
VIN = 12 V, TJ = 25°C
-1%
0.8
1%
VIN = 4.5 V to 16 V
-2%
0.8
2%
-25%
Power-up
2.1
µA
25%
kΩ
10
ms
5
µA
FEEDBACK, REGULATION, OUTPUT STAGE
VFB
Feedback voltage
V
IFB
Feedback leakage current
tON_MIN
Minimum on time
(current sense blanking)
80
H.S. Switch
Turn-On resistance high side FET on
TJ = 25°C, VIN = 12 V
CH1
95
mΩ
L.S. Switch
Turn-On resistance low side FET on
CH1
TJ = 25°C, VIN = 12 V
50
mΩ
H.S. Switch
Turn-On resistance high side FET on
TJ = 25°C, VIN = 12 V
CH2
120
mΩ
L.S. Switch
Turn-On resistance low side FET on
CH2
80
mΩ
50
nA
120
ns
MOSFET (BUCK 1)
MOSFET (BUCK 2)
TJ = 25°C, VIN = 12 V
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SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
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ELECTRICAL CHARACTERISTICS (continued)
TJ = -40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
gM
Error amplifier transconductance
–2 µA < ICOMP < 2 µA
gmPS
COMP to ILX gM
ILX = 0.5 A
130
µmhos
10
A/V
USB
VINUSB
USB input voltage
RDS_USB
Static drain-source on-state
resistance
USB_VIN = 5 V and
Io_USB = 0.5 A
VIH
USB_EN high level input voltage
V3p3 = 3.2 V - 3.4 V
VIL
USB_EN low level input voltage
V3p3 = 3.2 V - 3.4 V
ICS_USB_1
USB current limit when 154 kΩ is
connected from rUSB to GND
Increasing USB_VO current
di/dt < 1A/s
0.42
ICS_USB_2
USB current limit when 76.8 kΩ is
connected from rUSB to GND
Increasing USB_VO current
di/dt < 1A/s
KOVERCURRENT
Overcurrent detection factor Ratio of
ILIM_START/ ICS_USB
Increasing USB_VO current
di/dt < 1A/s
VUSB_ILIM
USB ILIM output voltage low
IUSB_ILIM = 3 mA
TCS_USB
USB over current fault deglitch
Fault assertion or de-assertion
due to OCP
TUSB_TRIP
USB thermal trip point
Rising temperature
Usb switch alarm low level
Pulled to 3V3 with 100-kΩ
resistors
VUSB_Nilim_LO
3.3
6
120
V
mΩ
1.55
V
1.3
V
0.55
0.68
A
0.84
1.10
1.36
A
1.8
2.1
2.4
0.4
V
6
ms
130
°C
0.3
V
POWER GOOD RESET GENERATOR
VUVBUCKX
Threshold voltage for buck under
voltage
Output falling (device will be
disabled after tON_HICCUP )
85
Output rising (PG will be
asserted)
90
%
tUV_deglitch
Deglitch time (both edges)
11
ms
tON_HICCUP
Hiccup mode ON time
VUVBUCKX asserted
12
ms
tOFF_HICCUP
Hiccup mode OFF time before restart is attempted
All converters disabled. Once
tOFF_HICCUP elapses, all
converters will go through
sequencing again.
20
ms
Threshold voltage for buck over
voltage
Output rising (high side fet will
be forced off)
109
VOVBUCKX
Output falling (high side fet will
be allowed to switch )
107
256
tRP
Minimum reset period
Measured after minimum reset
period of all bucks power-up
successfully
PGOODLO
Power good low level
Pulled to 3V3 with 100-kΩ
resistors
%
ms
0.3
V
THERMAL SHUTDOWN
TTRIP
Thermal shut down trip point
Rising temperature
THYST
Thermal shut down hysteresis
Device re-starts
TTRIP_DEGLITCH
Thermal shut down deglitch
160
°C
20
°C
100
120
µs
CURRENT LIMIT PROTECTION
RLIMx
Limit resistance range
ILIM1
Buck 1 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 17
ILIM2
Buck 2 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 18
8
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75
300
kΩ
1.1
5.2
A
0.9
4.5
A
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SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
0.50
0.50
0.40
0.40
0.30
0.30
0.20
0.20
0.10
0.10
% Regulation
% Regulation
TYPICAL CHARACTERISTICS
0
-0.10
0
-0.10
-0.20
-0.20
-0.30
-0.30
-0.40
-0.40
-0.50
-0.50
0
500
1000
1500
2000
2500
0
3000
200 400
600
800 1000 1200 1400 1600 1800 2000
Output Current - mA
Output Current - mA
Buck1 = 0 A
Buck2 = 0 A
Buck2 = 2 A
Figure 1. Buck1 Load Regulation, VO = 1.2 V
Buck1 = 3 A
Figure 2. Buck2 Load Regulation VO = 1.8 V
95
90
85
90
80
75
Efficiency - %
Efficiency - %
85
80
75
VI = 12 V,
fsw = 500 kHz,
VO = 3.3,
70
65
60
0
500
70
65
60
55
LO = 4.7 mH,
VI = 12 V,
fsw = 500 kHz,
VO = 1.2 V,
50
DCR = 10 mW,
CO = 22 mF
LO = 4.7 mH,
45
DCR = 10 mW,
CO = 22 mF
1000
1500
2000
Supply Current - mA
2500
3000
40
0
Figure 3. Buck 1 Efficiency, VO = 3.3 V,
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
500
1000
1500
2000
Supply Current - mA
2500
Figure 4. Buck 1 Efficiency, VO = 1.2 V,
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
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TYPICAL CHARACTERISTICS (continued)
100
90
95
85
80
90
80
75
VI = 12 V,
fsw = 500 kHz,
VO = 5 V,
70
65
60
0
10
Efficiency - %
Efficiency - %
75
85
500
70
65
60
55
VI = 12 V,
fsw = 500 kHz,
VO = 3.3 V,
LO = 4.7 mH,
50
LO = 4.7 mH,
DCR = 10 mW,
CO = 22 mF
45
DCR = 10 mW,
CO = 22 mF
1000
1500
Supply Current - mA
2000
40
0
500
1000
1500
Supply Current - mA
Figure 5. Buck 2 Efficiency, VO = 5 V,
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
Figure 6. Buck 2 Efficiency, VO = 3.3 V,
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
Figure 7. Soft Start for Buck 1 (Yellow Trace) 1.2 V, 3 A and
Buck 2 (Blue Trace) 1.8 V, 2 A,
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
Figure 8. Power Up and PGOOD
(From Top to Bottom, Buck2 = 1.8 V,
Buck1 = 1.2 V, PGOOD)
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
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SLVSAM1C – DECEMBER 2010 – REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
Figure 9. Power Down Behavior
(From Top to Bottom VIN, Buck2 = 1.8 V,
Buck1 = 1.2 V, PGOOD)
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
Figure 10. Ripple for Buck 1 (Yellow Trace) 1.2 V, 3 A and
Buck 2 (Blue Trace) 1.8 V, 2 A, 50 mV per Division
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
Figure 11. Buck 1 (Yellow Trace) Dynamic Response
1-A - 2-A Step, 50 mV/div. Buck 2 (Blue Trace), 50 mV/div
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
Figure 12. Buck 2 (Blue Trace) Dynamic Response 0.5-A 1.5-A Step, 50 mV/div. Buck 1 (Yellow Trace), 50 mV/div
VIN = 12 V, fSW = 500 kHz, LO = 4.7 µH,
DCR = 10 mΩ, CO = 22 µF
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OVERVIEW
TPS65252 is a power management IC with two step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65252 can support
4.5-V to 16-V input supply, high load current, 300-kHz to 2.2-MHz clocking. The buck converters have an
optional PFM mode, which can improve power dissipation during light loads. Alternatively, the device implements
a constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency of 300 kHz to
2.2 MHz allows for efficiency and size optimization. The switching frequency is adjustable by selecting a resistor
to ground on the ROSC pin. Input ripple is reduced by 180° out-of-phase operation between buck 1 and buck 2.
Both buck converters have peak current mode control which simplifies external frequency compensation. A
traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover,
an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and
makes the crossover frequency over 100 kHz.
Each buck converter has an individual current limit, which can be set up by a resistor to ground from the RLIM
pin. The adjustable current limiting enables high efficiency design with smaller and less expensive inductors.
The device has two built-in LDO regulators. During a standby mode, the 3.3-V LDO and the 6.5-V LDO can be
used to drive MCU and other active loads. By this, the system is able to turn off the two buck converters and
improve the standby efficiency.
The device has a power good comparator monitoring the output voltage. Each converter has its own soft start
and enable pins, which provide independent control and programmable soft start.
12
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DETAILED DESCRIPTION
Adjustable Switching Frequency
R (kW)
To select the internal switching frequency connect a resistor from ROSC to ground. Figure 13 shows the required
resistance for a given switching frequency.
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0.3
0.8
1.3
1.8
F (MHz)
Figure 13. ROSC vs Switching Frequency
ROSC(kW) = 174 · f
-1.122
(1)
Out-of-Phase Operation
In order to reduce input ripple current, buck 1 and buck 2 operate 180° out-of-phase. This feature allows for
lower component cost, reduced board space and reduced EMI.
Start-Up and Sequencing
Figure 14 shows the start-up sequencing and PGOOD signal generation.
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VIN
V7V
V3V
Internal
EN
EN treshold
Enx rise time
dictated by CEN
EN1
EN2
Enable discharge
12mS
Pre-bias timing
4-5mS
BUCK1
PG asserted
BUCK2
Pre-biased output
Soft star rise time
dictated by CSS
Soft start timer
10ms
PGOOD
PG timer
256ms
Figure 14. Start-Up Sequencing and PGOOD Signal Generation
Delayed Start-Up
On power-up the internal LDOs are powered immediately after the UVLO threshold is reached. The ENx (enable)
pins will be shorted for 12 ms and then released to make sure they are always at 0 V at power-up. Once
released the EN pins have a weak 1-MΩ pull-up to the 3V3 rail and the converters will start immediately. If a
delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~1.67 ms per nF connected to the pin.
Soft Start Time
The device has an internal pull-up current source of 5 µA that charges an external slow start capacitor to
implement a slow start time. Equation 2 shows how to select a slow start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the slow start charge current (Iss) is 5 µA. The soft start
circuit requires 1 nF per 167 µS to be connected at the SS pin. A 0.8-ms soft-start time is implemented for all
converters fitting 4.7 nF to the relevant SS pin.
( )
Css(nF)
Tss(ms) = VREF(V) · Iss(µA)
(2)
The Power Good circuit for the bucks has a 10-ms watchdog. Therefore the soft start time should be lower than
this value. It is recommended not to exceed 5 ms.
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with a value close to 40 kΩ
for the R1 resistor and use the Equation 3 to calculate R2.
14
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æ 0.8V ö
R 2 = R1 × ç
÷
è VO - 0.8V ø
(3)
Vo
TPS65252
R1
FB
R2
0.8V
+
Figure 15. Voltage Divider Circuit
Loop Compensation
TPS65252 is a current mode control dc/dc converter. The error amplifier is a transconductance amplifier with a
gM of 130 µA/V.
A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60° and 90°, or type
III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to attenuate
high-frequency noise when needed. . It may also prevent noise coupling from other rails if there is possibility of
cross coupling in between rails when layout is very compact.
Vo
iL
RL
Co
R ESR
gm ps = 10 A / V
Cff
R1
Current Sense
I/V Gain
FBx
g M = 130 u
Vref = 0 . 8V
COMPx
R2
Rc
C Roll
Cc
Figure 16. Loop Compensation
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To calculate the external compensation components follow the following steps:
TYPE II CIRCUIT
TYPE III CIRCUIT
Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies between 500 kHz
and 1 MHz give best trade off between performance and
cost. When using smaller L and Cs, switching frequency
can be increased. To optimize efficiency, switching
frequency can be lowered.
Type III circuit recommended for
switching frequencies higher than
500 kHz.
Select cross over frequency (fc) to be less than 1/5 to 1/10
of switching frequency.
Suggested
fc = fs/10
RC =
Set and calculate Rc.
2p × fc × Vo × Co
g M × Vref × gm ps
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
Cc =
1
fp =
CO × RL × 2p
Suggested
fc = fs/10
RL × Co
Rc
RC =
2p × fc × Co
g M × gm ps
Cc =
RL × Co
Rc
Add CRoll if needed to remove large signal coupling to high
impedance COMP node. Make sure that
fpRoll =
1
2 × p × RC × CRoll
CRoll =
Re sr × Co
RC
CRoll =
Re sr × Co
RC
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
that the zero frequency (fzff is smaller than soft start
equivalent frequency (1/Tss).
NA
C ff =
1
2 × p × fz ff × R1
Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control.
Input Capacitor
Use 10-µF X7R/X5R ceramic capacitors at the input of the converter inputs. These capacitors should be
connected as close as physically possible to the input pins of the converters.
Bootstrap Capacitor
The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.047 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage.
Power Good
The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled up when both buck converters’ outputs are more than
90% of its nominal output voltage. The default reset time is 256 ms. The polarity of the PGOOD is active high.
16
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Current Limit Protection
Figure 17 shows the (peak) inductor current limit for Buck 1. The typical limit can be approximated with the
following graph.
Figure 17. Buck 1
Figure 18 shows the (peak) inductor current limit for Buck 2. The typical limit can be approximated with the
following graph.
Figure 18. Buck 2
All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the
converters, all the converters will shut down for 10 ms and then the start-up sequencing will be tried again. If the
overload has been removed, the converter will ramp up and operate normally. If this is not the case the converter
will see another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.
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If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start
and no global hiccup mode will occur.
Overvoltage Transient Protection
The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The
OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP
threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVP threshold,
the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot.
When the FB voltage drops below the lower OVP threshold which is 107%, the high side MOSFET is allowed to
turn on the next clock cycle.
Low Power Mode Operation
By pulling the Low_p pin high all converters will operate in pulse-skipping mode, greatly reducing the overall
power consumption at light and no load conditions. Although each buck converter has a skip comparator that
makes sure regulation is not lost when a heavy load is applied and low power mode is enabled, system design
needs to make sure that the LP pin is pulled low for continuous loading in excess of 100 mA.
When low power is implemented, the peak inductor current used to charge the output capacitor is:
IN - VOUT
ILIMIT = 0.25 · TSLEEP_CLK · V
¾
L
(4)
Where TSLEEP_CLK is half of the converter switching period, 2/fSW.
The size of the additional ripple added to the output is:
1 ·
DVOUT = ¾
C
(
VIN
L · ILIMIT2
ILOAD
- ¾
¾· ¾
2
VOUT · (VIN - VOUT) fSLEEP_CLK
)
(5)
And the peak output voltage during low power operation is:
DVOUT
VOUT_PK = VOUT + ¾
2
(6)
VOUT_PK
VOUT
Figure 19. Peak Output Voltage During Low Power Operation
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USB Switch
The USB switch has a typical resistance of 120 mΩ and can also operate in 3.3-V distribution systems. The USB
switch is enabled with an active high signal to the USB_EN pin. The switch current limit can be set by a resistor
connected to the rUSB pin to ground. When an over-current condition occurs at the output the switch will limit it
to a value set by the following formula:
I CS _ USB ( A) =
85
rUSB(k W)
(7)
USB_Vin = 5 V
The overcurrent trip point (when current limit starts to operate and the switch operation changes from resistive
mode to constant current mode) is typically twice the set value of ICS_USB. If the overcurrent condition lasts more
than TCS_USB the USB_nLIM pin (active low, open drain) will change status to indicate an alarm condition.
USB_Vin
0
USB_EN
USB_Vo
OVERCURRENT DETECTED
ICS_USB
OVERCURRENT IS CLEARED
USB_LOAD
USB_I
Normal operation
Overcurrent at the output. Alarm
is asserted after 6 ms.
Normal operation is restored.
Alarm is cleared.
USB_nILIM
TCS_USB
Figure 20. USB Switch
The TPS65252 switch will safely handle overcurrent conditions due to heavy capacitive loads or overcurrent and
solid short conditions at the output of the switch. If a continuous short-circuit condition is applied to its output, the
USB switch will shut-down once its temperature reaches 130°C, allowing for the buck converters to operate
unaffected. Once the USB switch cools down it will restart automatically, as long as the USB_EN pin stays
enabled during the whole procedure.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
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APPLICATION INFORMATION
3.3-V and 6.5-V LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
• 10 µF for V7V pin 21
• 3.3 µF to 10 µF for V3V pin 22
Power Dissipation
Total power dissipation inside TPS65252 should not to exceed the maximum allowable junction temperature of
125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (RJA)
and ambient temperature.
To calculate the temperature inside the device under continuous loading use the following procedure.
1. Define the set voltage for arch converter.
2. Define the continuous loading on each converter. The maximum loading for continuous operation is 3 A for
buck1 and 2 A for buck 2 for the whole operational voltage range. Extended loading to 3.5 A and 2.5 A is
acceptable for short time periods.
3. Determine from the graphs below the expected losses in watts per converter inside the device. The losses
depend on the input supply, the selected switching frequency, the output voltage and the converter chosen.
1.4
Power Dissipated - W
1.2
1
0.8
0.6
0.4
0.2
1
1.2 1.4
1.6
1.8 2
2.2 2.4 2.6 2.8
IDD - Supply Current - A
3
3.2 3.4
3.6
Figure 21. Buck 1 VIN = 12 V, fS = 500 kHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
1.6
1.5
1.4
Power Dissipated - W
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1
1.2
1.4
1.6
1.8
2.2
2.4
2
IDD - Supply Current - A
2.6
2.8
3
Figure 22. Buck 2 VIN = 12 V, fS = 500 kHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
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1.8
1.6
Power Dissipated - W
1.4
1.2
1
0.8
0.6
0.4
0.2
1
1.2 1.4
1.6
1.8 2
2.2 2.4 2.6 2.8
IDD - Supply Current - A
3
3.2 3.4
3.6
Figure 23. Buck 1 VIN = 12 V, fS = 1.1 MHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
1.7
1.6
1.5
Power Dissipated - W
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1
1.2
1.4
1.6
1.8
2.2
2.4
2
IDD - Supply Current - A
2.6
2.8
3
Figure 24. Buck 2 VIN = 12 V, fS = 1.1 MHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
1.6
1.4
Power Dissipated - W
1.2
1
0.8
0.6
0.4
0.2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
IDD - Supply Current - A
2.6
2.8
3
Figure 25. Buck 1 VIN = 5 V, fS = 500 kHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
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2
1.8
Power Dissipated - W
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
1
1.2 1.4
1.6
1.8 2
2.2 2.4 2.6 2.8
IDD - Supply Current - A
3
3.2 3.4
3.6
Figure 26. Buck 2 VIN = 5 V, fS = 500 kHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
1.6
1.4
Power Dissipated - W
1.2
1
0.8
0.6
0.4
0.2
0
1
1.2 1.4
1.6
1.8 2
2.2 2.4 2.6 2.8
IDD - Supply Current - A
3
3.2 3.4
3.6
Figure 27. Buck 1 VIN = 5 V, fS = 1.1 MHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
2
1.8
Power Dissipated - W
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
IDD - Supply Current - A
2.6
2.8
3
Figure 28. Buck 2 VIN = 5 V, fS = 1.1 MHz,
VO (From Top to Bottom) = 5, 3.3, 2.5, 1.8, 1.2 V
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4. To calculate the maximum temperature inside the IC use the following formula.
THOTSPOT = TA + PDIS · RJA
(8)
Where:
TA is the ambient temperature
PDIS is the sum of losses in all converters
RJA is the junction to ambient thermal impedance of the device and it is heavily dependant on the board
layout
Layout Recommendation
Layout is a critical portion of PMIC designs.
• Place VOUT, and LX on the top layer and an inner power plane for VIN.
• Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
ground.
• The top layer ground area sould be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter cpacitor and directly under the TPS65252 device to provide a thermal path from the
Powerpad land to ground.
• For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
• The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
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PACKAGE OPTION ADDENDUM
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16-Jan-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65252RHDR
ACTIVE
VQFN
RHD
28
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65252
TPS65252RHDT
ACTIVE
VQFN
RHD
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65252
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS65252RHDR
VQFN
RHD
28
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
TPS65252RHDT
VQFN
RHD
28
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65252RHDR
VQFN
RHD
28
3000
367.0
367.0
35.0
TPS65252RHDT
VQFN
RHD
28
250
210.0
185.0
35.0
Pack Materials-Page 2
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remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
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used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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