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Table of Contents
User’s Guide
TPS65261-1 Buck Converter Evaluation Module User's
Guide
ABSTRACT
This document presents the information required to operate the TPS65261/TPS65261-1 PMIC as well as the
support documentation including schematic, layout, hardware setup and bill of materials.
Table of Contents
1 Background.............................................................................................................................................................................2
2 Board Layout...........................................................................................................................................................................3
3 Bench Test Setup Conditions................................................................................................................................................ 5
4 Power-Up Procedure.............................................................................................................................................................. 7
5 Schematic................................................................................................................................................................................8
6 Bill of Materials....................................................................................................................................................................... 9
7 Revision History......................................................................................................................................................................9
List of Figures
Figure 2-1. Placement................................................................................................................................................................. 3
Figure 2-2. Board Layout (Top Layer)..........................................................................................................................................4
Figure 2-3. Board Layout (Second Layer)................................................................................................................................... 4
Figure 2-4. Board Layout (Third Layer)....................................................................................................................................... 4
Figure 2-5. Board Layout (Bottom Layer).................................................................................................................................... 4
Figure 3-1. Headers Description and Jumper Placement............................................................................................................5
Figure 5-1. TPS65261/TPS65261-1 Schematic.......................................................................................................................... 8
Trademarks
All trademarks are the property of their respective owners.
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Background
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1 Background
The TPS65261/TPS65261-1 PMIC is a triple 3-A/2-A/2-A output current, synchronous step-down (buck)
converter with an operational range of 4.5 V to 18 V. The TPS65261/TPS65261-1 features an automatic power
sequence with connecting MODE pin to V7V and configuring EN1/2/3 pins. The device also features an open
drain RESET signal to monitor power down. The TPS65261 operates in pulse skipping mode (PSM) and the
TPS65261-1 operates in force continuous current mode (FCC) at light load.
As there are many possible options to set the converters, Table 1-1 presents the performance specification
summary for the EVM.
Table 1-1. Summary of Performance
Test Conditions
Performance
VIN = 4.5 V to 18 V
fSW = 600 kHz
(25°C ambient)
BUCK1, 1.2 V, up to 3 A
BUCK2, 3.3 V, up to 2 A
BUCK3, 1.8 V, up to 2 A
RESET, pull low when VDIV lower than 1.23 V
This evaluation module is designed to provide access to the features of the TPS65261/TPS65261-1. Some
modifications can be made to this module to test performance at different input and output voltages, current and
frequency operation. Contact TI Field Applications Group for advice on these matters.
2
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Board Layout
2 Board Layout
Figure 2-1. Placement
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Board Layout
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2.1 EVM Layout
4
Figure 2-2. Board Layout (Top Layer)
Figure 2-3. Board Layout (Second Layer)
Figure 2-4. Board Layout (Third Layer)
Figure 2-5. Board Layout (Bottom Layer)
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Bench Test Setup Conditions
3 Bench Test Setup Conditions
Figure 3-1. Headers Description and Jumper Placement
Test points:
A: LX of VOUT1
B: LX of VOUT2
C: LX of VOUT3
VOUT1, VOUT2, VOUT3, VIN, PGOOD, RESET, V7V
Table 3-1. Input/Output Connection
Number
Function
Description
J1
BUCK1 connector
Output of BUCK1
J2
BUCK2 connector
Output of BUCK2
J3
BUCK3 connector
Output of BUCK3
J4
VIN connector
Apply power supply to this connector.
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Bench Test Setup Conditions
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3.1 Jumpers and Switches
Number
Function
Placement
BUCK3 enable (EN3)
Connect EN3 to GND to disable VOUT3,
connect EN3 to VIN through a 100-kΩ resistor
to enable VOUT3; Leave open to enable
VOUT3.
JP2
PGOOD pull-up
PGOOD pull-up resistor connected to the
V7V; Leave the two pins un-connected set the
On board V7V is 6.3 V when VIN is 12 V
pull-up voltage open; short the two pins set
the pull-up voltage to be V7V.
JP3
RESET pull-up
RESET pull-up resistor connected to the V7V;
Leave the two pins un-connected set the pullOn board V7V is 6.3 V when VIN is 12 V
up voltage open; short the two pins set the
pull-up voltage to be V7V.
Mode
Power sequencing mode control pin. Connect
this pin to GND to set power sequence with
dedicated enable pin; Connect this pin to V7V
set the power sequence with the pre-defined
power up and power down sequence.
BUCK1 enable (EN1)
Connect EN1 to GND to disable VOUT1,
connect EN1 to VIN through a 100-kΩ resistor
to enable VOUT1; Leave open to enable
VOUT1.
BUCK2 enable (EN2)
Connect EN2 to GND to disable VOUT2,
connect EN2 to VIN through a 100-kΩ resistor
to enable VOUT2; Leave open to enable
VOUT2.
JP1
JP4
JP31
JP32
6
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Comment
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Power-Up Procedure
4 Power-Up Procedure
Power sequence with dedicated enable pin:
1.
2.
3.
4.
Connect JP4 to GND.
Apply 4.5 V - 18 V to J4.
Toggle JP31, JP32 or JP1 to enable VOUT1, VOUT2 and VOUT3 respectively.
Apply loads to the output connectors.
Power sequence with the pre-defined power up and power down sequence:
1.
2.
3.
4.
5.
Connect JP4 to V7V.
Connect JP31 to High (or Low), JP32 to High (or Low)
Apply 4.5 V - 18 V to J4.
Toggle JP1 to enable VOUT1, VOUT2 and VOUT3.
Apply loads to the output connectors.
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Schematic
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5 Schematic
Figure 5-1. TPS65261/TPS65261-1 Schematic
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Bill of Materials
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6 Bill of Materials
No.
Designator
Value
Quantity
Footprint
Manufacturer
1
C1, C31, C32
4.7nF
3
0603
Generic
Part Number
Description
CAP 4.7nF 50V CERAMIC X7R 0603
2
C9, C16, C25
47nF
3
0603
Generic
CAP 47nF 50V CERAMIC X7R 0603
3
C231
3.3nF
1
0603
Generic
CAP 3.3nF 50V CERAMIC X7R 0603
4
C71, C181
2.2nF
2
0603
Generic
CAP 2.2nF 50V CERAMIC X7R 0603
5
C101, C102, C151,
22uF
C152, C161, C162
6
1206
Generic
CAP 22uF 16V CERAMIC X5R 1206
6
C72, C182, C232
22pF
3
0603
Generic
CAP 22pF 50V CERAMIC X7R 0603
7
C10, C15
47pF
2
0603
Generic
CAP 47pF 50V CERAMIC X7R 0603
8
C12, C13, C28
10uF
3
1206
Generic
CAP 10uF 25V CERAMIC X5R 0603
9
C26
82pF
1
0603
Generic
CAP 82pF 50V CERAMIC X7R 0603
10
C8, C17, C24
10nF
3
0603
Generic
CAP 10nF 50V CERAMIC X7R 0603
11
C5
1uF
1
0603
Generic
CAP 1uF 50V CERAMIC X5R 0603
12
R011, R312, R322
51K
3
0603
Generic
RES 51k OHM 1/10W 1% 0603 SMD
13
R011, R2, R3,
R311, R321
100K
5
0603
Generic
RES 100k OHM 1/10W 1% 0603 SMD
14
R29
146K
1
0603
Generic
RES 146k OHM 1/10W 1% 0603 SMD
15
R23, R30, R262,
R263
20K
4
0603
Generic
RES 20k OHM 1/10W 1% 0603 SMD
16
R7, R18
30K
2
0603
Generic
RES 30k OHM 1/10W 1% 0603 SMD
17
R20
73.2K
1
0603
Generic
RES 73.2k OHM 1/10W 1% 0603 SMD
18
R9, R16, R25,
R101, R151, R261
0
6
0603
Generic
RES 0 OHM 1/10W 1% 0603 SMD
19
R102, R152
39K
2
0603
Generic
RES 39k OHM 1/10W 1% 0603 SMD
20
R153
19.5K
1
0603
Generic
RES 19.5k OHM 1/10W 1% 0603 SMD
21
R103
8.67K
1
0603
Generic
RES 8.67k OHM 1/10W 1% 0603 SMD
744311470
L1, L2, L3
4.7uH
3
IND_744311470
Wurth Electronics
Inc
23(1)
JP1, JP4, JP31,
JP32
HEADER 3
PIN
4
JMP0.3
Mil-Max
800-10-064-10-001 Three Pin Header, Break SIPs into
000
groups of 3
24(2)
JP2, JP3
HEADER 2
PIN
2
JMP0.2
Mil-Max
800-10-064-10-001 Two Pin Header, Break SIPs into
000
groups of 2
25
J1, J2, J3, J4
ED500/2DS 4
TB_2X5.0MM
OnShore Technology
ED500/2DS
Inc
Terminal Block, 2-pin, 15-A, 5.0mm
26
TP6, TP7, TP8,
TP9, TP10, TP11,
TP12
Test Point
White
7
TP
Keystone
5002
TEST POINT PC MINI .040"D WHITE
27
TP1, TP2, TP3,
TP4, TP5
Test Point
Black
5
TP
Keystone
5001
TEST POINT PC MINI .040"D BLACK
28
TP13, TP14, TP15
Test Point
White
DNI
TP
Keystone
5002
TEST POINT PC MINI .040"D WHITE
22
29
6
30(3)
4
Jumper, 2.54mm, open top, Applied on
item 23, 24
3M
SJ-5303 (CLEAR)
31(4)
U1
1
RHB
Texas Instruments
TPS65261RHBR
32(4)
U1
1
RHB
Texas Instruments
TPS65261-1RHBR
(1)
(2)
(3)
(4)
SMT power inductor
BUMPON HEMISPHERE .44X.20
CLEAR
Item 23: split into 3 pins.
Item 24: split into 2 pins.
Install item 25 on bottom at corners.
Select item 31 (TPS65261RHBR) or item 32 (TPS65261-1RHBR) according to product target.
7 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2013) to Revision A (May 2021)
Page
• Updated user's guide title................................................................................................................................... 2
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Revision History
•
10
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Updated the numbering format for tables, figures, and cross-references throughout the document. ................2
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