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TPS65266-1
SLVSDA6 – OCTOBER 2016
TPS65266-1 2.7 to 6-V Input Voltage, 3-A/2-A/2-A Output Current Triple Synchronous
Step-Down Converter
1 Features
•
•
•
•
•
Operating Input Voltage Range 2.7 to 6 V
Feedback Reference Voltage 0.6 V ±1%
Maximum Continuous Output Current 3 A/2 A/2 A
Dedicated Enable and Soft Start
Accurate Start-Up Timing Control With Enable
Pins Discharge
Pulse Skipping Mode (PSM) at Light Load
Cycle-by-Cycle Current Limiting With Hiccup
Mode Overcurrent Protection
Adjustable Clock Frequency 250 kHz to 2.4 MHz
External Clock Synchronization
Power-Good Indicator
Overtemperature Protection
1
•
•
•
•
•
•
2 Applications
•
•
•
•
•
The buck DC/DC converter integrates power
MOSFETs for optimized power efficiency and
reduces external component counts. The peak
current mode control simplifies the compensation and
fast transient response. High clock frequency allows
smaller and low-value inductors and capacitors.
External compensation supports optimized loop
compensation and fast transient response. In light
load condition, the buck converter operates in PSM
mode for a reduction on the input power supplied to
the system. Cycle-by-cycle overcurrent limiting with
hiccup mode limits MOSFET power dissipation in
short circuit or overloading fault conditions.
The TPS65266-1 features a power-good supervisor
circuit that monitors all converter outputs. The
PGOOD pin is asserted after the output voltages in
each channel are in regulation and sequencing is
done.
When continuous heavy overload or short circuit
increases power dissipation in the buck converter,
internal thermal protection circuit shuts off the device
to prevent damage. Recovery from a thermal
shutdown is automatic after the device has cooled
sufficiently.
Printer and Scanner
Digital TV
Set Top Box
Home Gateway and Access Point Networks
Surveillance
Device Information(1)
PART NUMBER
3 Description
The TPS65266-1 incorporates 3 channels of highefficiency
synchronous
buck
converter
for
applications operating off the adaptor or battery with
input voltage lower than 6 V.
TPS65266-1
PACKAGE
VQFN (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Simplified Application Schematic
Vin
Efficiency vs Output Load
Vout1
VINx
LX1
100%
TPS65266-1
90%
FB1
80%
VINQ
Vout2
70%
PGOOD
FB2
ENx
SSx
Vout3
ROSC
LX3
Efficiency (%)
LX2
60%
50%
40%
30%
FB3
AGND
PGND
Copyright © 2016, Texas Instruments Incorporated
20%
VOUT = 1.5 V
VOUT = 2.5 V
10%
0
0
0.5
1
1.5
2
Output Load (A)
2.5
3
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65266-1
SLVSDA6 – OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
2
DATE
REVISION
NOTES
October 2016
*
Initial release.
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5 Pin Configuration and Functions
A.
SS1
COMP1
FB1
AGND
ROSC
FB3
COMP3
SS3
24
23
22
21
20
19
18
17
RHB PACKAGE
32-Pin (VQFN)
Top View
BST1
25
16
BST3
LX1
26
15
LX3
PGND1
27
14
PGND3
VIN1
28
13
VIN3
12
VIN2
Thermal
Pad
8
SS2
9
7
32
COMP2
GND
6
LX2
FB2
10
VINQ 5
31
PGOOD 4
EN3
3
PGND2
AGND
11
2
30
AGND
EN2
1
29
AGND
EN1
BST2
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
optimal thermal performance.
Pin Functions
PIN
NO.
DESCRIPTION
NAME
1
AGND
Analog ground pin
2
AGND
Analog ground pin
3
AGND
Analog ground pin
4
PGOOD
An open-drain output; asserts low if output voltage of bucks beyond regulation range due to thermal shutdown, overcurrent, under-voltage, or ENx low.
5
VINQ
Input voltage of converter controller and reference power supply bias. TI recommends to connect a 1-µF capacitor
from the pin to analog ground and put the capacitor as near as possible to this pin.
6
FB2
Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 feedback resistor divider.
7
COMP2
Error amplifier output and loop compensation pin for buck2. Connect a series resistor and capacitor to compensate
the control loop of buck converter 2 with peak current PWM mode.
8
SS2
Soft-start and tracking input for buck2 converter. An internal 5.5-µA pullup current source is connected to this pin.
The soft-start time of buck2 can be programmed by connecting a capacitor between this pin and ground.
9
BST2
Boot strapped supply to the high-side floating gate driver in buck2 converter. Connect a capacitor (47 nF
recommended) from BST2 pin to LX2 pin.
10
LX2
Switching node connection to the inductor and bootstrap capacitor for buck2 converter. The voltage swing at this pin
is from a diode voltage below the ground up to VIN2 voltage.
11
PGND2
Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input
ceramic capacitor.
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Pin Functions (continued)
PIN
NO.
4
DESCRIPTION
NAME
12
VIN2
Input power supply for buck2. Connect VIN2 pin as close as practical to the (+) terminal of an input ceramic capacitor
(10 µF suggested).
13
VIN3
Input power supply for buck3. Connect VIN3 pin as close as practical to the (+) terminal of an input ceramic capacitor
(10 µF suggested).
14
PGND3
Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input
ceramic capacitor.
15
LX3
Switching node connection to the inductor and bootstrap capacitor for buck3 converter. The voltage swing at this pin
is from a diode voltage below the ground up to VIN3 voltage.
16
BST3
Boot strapped supply to the high-side floating gate driver in buck3 converter. Connect a capacitor (47 nF
recommended) from BST3 pin to LX3 pin.
17
SS3
Soft-start and tracking input for buck3 converter. An internal 5.5-µA pullup current source is connected to this pin.
The soft-start time of buck3 can be programmed by connecting a capacitor between this pin and ground.
18
COMP3
Error amplifier output and loop compensation pin for buck3. Connect a series resistor and capacitor to compensate
the control loop of buck converter 3 with peak current PWM mode.
19
FB3
Feedback Kelvin sensing pin for buck3 output voltage. Connect this pin to buck3 feedback resistor divider.
20
ROSC
Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.
21
AGND
Analog ground common to buck controllers and other analog circuits. It must be routed separately from high-current
power grounds to the (–) terminal of bypass capacitor of input voltage VINQ.
22
FB1
Feedback Kelvin sensing pin for buck1 output voltage. Connect this pin to buck1 feedback resistor divider.
23
COMP1
Error amplifier output and loop compensation pin for buck1. Connect a series resistor and capacitor to compensate
the control loop of buck converter 1 with peak current PWM mode.
24
SS1
Soft-start and tracking input for buck1 converter. An internal 5.5-µA pullup current source is connected to this pin.
The soft-start time of buck1 can be programmed by connecting a capacitor between this pin and ground.
25
BST1
Boot strapped supply to the high-side floating gate driver in buck1 converter. Connect a capacitor (47 nF
recommended) from BST1 pin to LX1 pin.
26
LX1
Switching node connection to the inductor and bootstrap capacitor for buck1 converter. The voltage swing at this pin
is from a diode voltage below the ground up to VIN1 voltage.
27
PGND1
Power ground connection of buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input
ceramic capacitor.
28
VIN1
Input power supply for buck1. Connect VIN1 pin as close as practical to the (+) terminal of an input ceramic capacitor
(suggest 10 µF).
29
EN1
Enable for buck1 converter. Float to enable. Can use this pin to adjust the input undervoltage lockup of buck1 with
resistors divider.
30
EN2
Enable for buck2 converter. Float to enable. Can use this pin to adjust the input undervoltage lockup of buck2 with
resistors divider.
31
EN3
Enable for buck3 converter. Float to enable. Can use this pin to adjust the input undervoltage lockup of buck3 with
resistors divider.
32
GND
Ground pin
—
Thermal
PAD
No electric connection to any signal. Soldered to the ground in PCB for better thermal performance.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
MIN
MAX
VIN1, VIN2, VIN3, VINQ
–0.3
7
LX1, LX2, LX3 (maximum withstand voltage transient 2.7 V
VINQ
VIN
ih
R1
ip
EN
R2
Figure 24. Adjustable VIN and VINQ UVLO
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7.3.3 Soft-Start Time
The voltage on the respective SS pin controls the start-up of buck output. When the voltage on the SS pin is less
than the internal 0.6-V reference, the TPS65266-1 regulates the internal feedback voltage to the voltage on the
SS pin instead of 0.6 V. The SS pin can be used to program an external soft-start function or to allow output of
buck to track another supply during start-up. The device has an internal pullup current source of 5.5 μA (typical)
that charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The TPS65266-1
regulates the internal feedback voltage to the voltage on the SS pin, allowing VOUT to rise smoothly from 0 V to
its regulated voltage without inrush current. Calculate the approximate soft-start time with Equation 4.
Css(nF) u Vref (V)
t ss (ms)
Iss(µA)
(4)
Many of the common power-supply sequencing methods can be implemented using the SSx and ENx pins.
Figure 25 shows the method implementing ratiometric sequencing by connecting the SSx pins of three buck
channels together. The regulator outputs ramp up and reach regulation at the same time. When calculating the
soft-start time, the pullup current source must be tripled in Equation 4.
EN
29
EN threshold = 1.2 V
EN1
30
EN2
31
EN3
Vout3 = 1.8 V
24
SS1
Vout2 = 1.5 V
8
SS2
Vout1 = 1.0 V
17
SS3
Css
tSS =
CSS × 0.6 V
16.5 µA
Figure 25. Ratiometric Power-Up Using SSx Pins
Simultaneous power-supply sequencing can be implemented by connecting capacitor to SSx pin, shown in
Figure 26. Using Equation 4 and Equation 5, calculate the capacitors.
Css1
Css2
Css3
Vout1 Vout2 Vout3
(5)
16
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EN
29
EN1
EN threshold = 1.2 V
30
EN2
31
EN3
Vout3 = 1.8 V
24
SS1
Css1
Vout2 = 1.5 V
8
SS2
Css2
Vout1 = 1.0 V
17
SS3
Css3
tSS =
CSS3 × 0.6 V
5.5µA
Figure 26. Simultaneous Startup Sequence Using SSx Pins
7.3.4 Power-Up Sequencing
The TPS65266-1 has a dedicated enable pin and soft-start pin for each converter. The converter enable pins are
biased by a current source that allows for easy sequencing by the addition of an external capacitor. Enable pins
have a discharge function, which ensures power-up sequencing is effective at quickly powering down and up
status. Disabling the converter with an active pulldown transistor on the ENs pin allows for a predictable powerdown timing operation. Figure 27 shows the timing diagram of a typical buck power-up sequence with connecting
a capacitor at ENx pin.
When VINQ pin voltage rises to about 1 V, the internal EN turns on and a typical 1.4-µA current is charging ENx
pin from input supply. If any of the EN pin voltages reaches 0.5 V when powered up, three EN pin discharge
functions are triggered and keep 2 ms with discharge resistor around 1.2 kΩ to GND, then a 2.1-µA pullup
current is sourcing ENx. After ENx pin voltage reaches to ENx enabling threshold, 3.2-µA hysteresis current
sources to the pin to improve noise sensitivity.
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About 1 V
VINQ
Internal EN
EN Threshold
EN Threshold
ENx
0.5 V
1.2V
ENx Rise Time
Dictated by CEN
t = CENx × 1.2 V / 2.1 µA
Discharge time 2 ms
t = CENx × 0.5 V / 1.4 µA
About 1.7 V
0.6 V
SSx
Pre-Bias Startup
VOUTx
Soft Start Rise Time
Dictated by CSS
PGOOD Deglitch Time 16350 cycles
t = CSSx × 0.6 V / 5.5 µA
PGOOD
Figure 27. Startup Power Sequence
7.3.5 Bootstrap Voltage and BST-LX UVLO
Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in Figure 28, which is
normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than VIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47 nF. TI
recommends a ceramic capacitor with an X7R- or X5R-grade dielectric with a voltage rating of 10 V or higher
because of the stable characteristics over temperature and voltage.
To improve dropout, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.1 V. When the voltage between BST and LX
drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.
18
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VINQ
VINx
LDO
(VBSTx-VLXx)
nBootUV
+2.1 V
BSTx
UVLO
Bias
Buck Controller
High-side
MOSFET
nBootUV
CB
Gate Driver
PWM
LXx
Low-side
MOSFET
nBootUV
BootUV
Protection
PWM
Gate Driver
Clk
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Bootstrap Voltage and Diagram
7.3.6 Out of Phase Operation
To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.
This enables the system by having less input current ripple to reduce input capacitors’ size, cost, and EMI.
7.3.7 Output Overvoltage Protection (OVP)
The device incorporates an OVP circuit to minimize output voltage overshoot. When the output is overloaded, the
error amplifier compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower
than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum
output current. After the condition is removed, the regulator output rises and the error amplifier output transitions
to the steady-state voltage. In some applications with small output capacitance, the load can respond faster than
the error amplifier. This leads to the possibility of an output overshoot. Each buck compares the FB pin voltage to
the OVP threshold. If the FB pin voltage is greater than the OVP threshold, the high-side MOSFET is turned off
preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower
than the OVP threshold, the high-side MOSFET turns on at the next clock cycle.
7.3.8 Slope Compensation
To prevent the subharmonic oscillations when the device operates at duty cycles greater than 50%, the
TPS65266-1 adds built-in slope compensation, which is a compensating ramp to the switch current signal.
7.3.9 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and low-side MOSFET.
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7.3.9.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control, which uses the COMP pin voltage to control the turn off of the
high-side MOSFET and the turn-on of the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch
current and the current reference generated by the COMP pin voltage are compared, when the peak switch
current intersects the current reference, the high-side switch is turned off.
7.3.9.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays on for the
next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing
current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario, both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time, which is programmed for 512 cycles (typical) shown in Figure 29, the device shuts down
itself and restarts after the hiccup time of 16382 cycles (typical). The hiccup mode helps to reduce the device
power dissipation under a severe overcurrent condition.
OCP peak inductor current threshold
OC limiting (waiting) time
512 cycles (typical)
hiccup time
16382 cycles (typical)
Soft-start time
t = Css × 0.6 V / 5.5 µA
Output over loading
iL
Inductor Current
Soft-start is reset after OC waiting time
About 1.7 V
SS
OC fault removed, soft-start and output recovery
0.6 V
SS Pin Voltage
Output OC circuit
Vout
Output Voltage
Figure 29. Overcurrent Protection
7.3.10 Power Good
The PGOOD pin is an open-drain output. After the feedback voltage of each buck is higher than 95% (rising) of
the internal voltage reference, the PGOOD pin pulldown is deasserted and the pin floats. TI recommends to use
a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.0 V or less.
The PGOOD pin is pulled low when any feedback voltage of a buck is lower than 92.5% (falling) of the nominal
internal reference voltage. Also, the PGOOD is pulled low if the input voltage is undervoltage locked up, thermal
shutdown is asserted, the EN pin is pulled low, or the converter is in a soft-start period.
20
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7.3.11 Adjustable Switching Frequency
The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching
frequency of the device is adjustable from 250 kHz to 2.4 MHz.
To determine the ROSC resistance for a given switching frequency, use Equation 6 or the curve in Figure 30. To
reduce the solution size, the user should set the switching frequency as high as possible, but consider the
tradeoffs of the supply efficiency and minimum controllable on-time.
¦osc N+]
u 5 N:
±
(6)
2400
Switching Frequency (kHz)
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
0
20
40
60
80
100 120 140 160 180 200 220
ROSC (kO)
D021
Figure 30. ROSC vs Switching Frequency
When an external clock applies to the ROSC pin, the internal phase locked loop (PLL) has been implemented to
allow internal clock synchronizing to an external clock between 250 kHz and 2.4 MHz. To implement the clock
synchronization feature, connect a square wave clock signal to the ROSC pin with a duty cycle between 20% to
80%. The clock signal amplitude must transition lower than 0.4 V and higher than 2.0 V. The start of the
switching cycle is synchronized to the falling edge of the ROSC pin.
In applications where both resistor mode and synchronization mode are needed, the device can be configured as
shown in Figure 31. Before an external clock is present, the device works in resistor mode and ROSC resistor
sets the switching frequency. When an external clock is present, the synchronization mode overrides the resistor
mode. The first time the ROSC pin is pulled above the ROSC high threshold (2.0 V), the device switches from
the resistor mode to the synchronization mode and the ROSC pin becomes high impedance as the PLL starts to
lock onto the frequency of the external clock. TI does not recommended to switch from synchronization mode
back to resistor mode because the internal switching frequency drops to 100 kHz first before returning to the
switching frequency set by ROSC resistor.
Mode
Selection
IC
ROSC
ROSC
Figure 31. Works With Resistor Mode and Synchronization Mode
7.3.12 PSM
The TPS65266-1 can enter high-efficiency PSM operation at light load current.
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When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 250-mA
current typically. Because the integrated current comparator catches the peak inductor current only, the average
load current entering PSM varies with the applications and external output filters. In PSM, the sensed peak
inductor current is clamped at 250 mA (see Figure 32).
When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current
comparator turns off the low-side MOSFET when the inductor current reaches 0, preventing it from reversing and
going negative.
Due to the delay in the circuit and current comparator tdly (typical 50 nS at VIN = 5 V), the real peak inductor
current threshold to turn off high-side power MOSFET could shift higher depending on inductor inductance and
input/output voltages. Calculate the threshold of peak inductor current to turn off high-side power MOSFET with
Equation 7.
VIN - VOUT
ILPEAK
250 mA
x tdly
(7)
L
When the charge accumulated on VOUT capacitor is more than loading need, COMP pin voltage drops to low
voltage driven by error amplifier. There is an internal comparator at COMP pin. If comp voltage is < 0.35 V, the
power stage stops switching to save power.
250 mA
Turn off
high-side Power MOSFET
IL_Peak
Inductor Peak Current
Inductor
Current Peak
Current
Sensing
x1
Current Comparator
Delay: tdly
Figure 32. PSM Current Comparator
7.3.13 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 140°C
typically.
7.4 Device Functional Modes
7.4.1 Operation With VIN < 2.6 V (Minimum VIN)
The device operates with input voltages above 2.6 V. The maximum UVLO voltage is 2.6 V and will operate at
input voltages above 2.6 V. The typical UVLO voltage is 2.45 V and the device may operate at input voltages
above that point. The device also may operate at lower input voltages, the minimum UVLO voltage is 2.35 V
(rising) and 2.15V (falling). At input voltages below the UVLO minimum voltage, the devices will not operate.
7.4.2 Operation With EN Control
The enable rising edge threshold voltage is 1.2 V typical and 1.26 V maximum. With EN held below that voltage
the device is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When input
voltage is above the UVLO threshold and the EN voltage is increased above the rising edge threshold, the
device becomes active. Switching is enabled, and the soft start sequence is initiated. The device will start at the
soft start time determined by the external soft start capacitor as shown in Figure 35 to Figure 37.
22
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a triple-synchronous step-down DC/DC converter. It is typically used to convert a higher DC
voltage to lower DC voltages with a continuously available output current of 3 A/2 A/2 A. The following design
procedure can be used to select component values for the TPS65266-1. This section presents a simplified
discussion of the design process.
8.2 Typical Application
R1
0
U1
C1
0.047 µF
VIN 3.3 V
28
VIN
VIN1
BST1
L1
25
VOUT1 1.0 V 3 A
VOUT1
C5
C7
22 µF
C8
22 µF
C9
22 µF
12
13
VIN2
LX1
VIN3
FB1
COMP1
5
VINQ
BST2
C11
2.2 µF
LX2
22
R3
VFB1
DNI
9.1 kΩ
23
R7
9
C2
22 µF
2.2 µH
C4
26
C3
22 µF
DNI
C6
R6
GND
GND
1000 pF
C10
0.047 µF
EN2
EN3
29
30
31
EN1
FB2
GND
C12
22 µF
2.2 µH
10
EN2
COMP2
EN3
BST3
LX3
24
8
17
C22
0.01 µF
C23
0.01 µF
GND
20 kΩ
R13
16
0
FB3
SS2
COMP3
SS3
PGOOD
ROSC
AGND
AGND
AGND
AGND
AGND
SYN
PGND1
PGND2
PGND3
PAD
R18
51.1 kΩ
VFB2
DNI
R12
GND
C16
GND
R11
10.0 kΩ
15.0 kΩ
1000 pF
GND
GND
C17
L3
0.047 µF
VOUT3 1.8 V 2 A
15
VOUT1
C21
C18
22 µF
2.2 µH
SS1
C24
0.01 µF
20
7
VOUT1
C13
22 µF
C14
DNI
R10
VFB2
VOUT2 1.5 V 2 A
C15
0Ω
6
R5
15.0 kΩ
10.0 kΩ
L2GND
GND
EN1
VFB1
19
VFB3
R15
18
R9
4
100 kΩ
1
2
3
21
32
27
11
14
33
VIN
20 kΩ
C19
22 µF
VFB3
DNI
C20
R17
GND
1000 pF
GND
R16
10.0 kΩ
20.0 kΩ
C25
GND
DNI
GND
GND
TPS65266RHB
GND
GND
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Figure 33. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
This example details the design of a triple-synchronous step-down converter. The designer must know a few
parameters to start the design process. These parameters are typically determined at the system level. For this
example, start with the following known parameters in Table 2.
Table 2. Design Parameters
Parameter
Value
Vout1
1.0 V
Iout1
3A
Vout2
1.5 V
Iout2
2A
Vout3
1.8 V
Iout3
2A
Transient response 1-A load step
±5%
Input voltage
5.0 V normal, 2.7 to 6 V
Output voltage ripple
±1%
Switching frequency
1 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Inductor Selection
To calculate the value of the output inductor, use Equation 8. LIR is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for
the majority of applications.
Vinmax Vout
V out
L
u
,o u /,5
9inmax u ¦sw
(8)
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS and peak inductor current can be found from Equation 10 and Equation 11.
Vinmax Vout
V out
Iripple
u
/
9inmax u ¦sw
(9)
Vout u (Vinmax Vout ) 2
)
9inmax u / u ¦VZ
12
I ripple
(
ILrms
2
IO
ILpeak
Iout
(10)
2
(11)
The current flowing through the inductor is the inductor ripple current plus the output current. During power-up,
faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit
of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
8.2.2.2 Output Capacitor Selection
The three primary considerations for selecting the value of the output capacitor are: the output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance must be selected based on the most stringent of these three criteria.
24
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The first criterion is the desired response to a large change in the load current. The output capacitor needs to
supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be
sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a
tolerable amount of droop in the output voltage. Equation 12 shows the minimum output capacitance necessary
to accomplish this.
2 u 'Iout
Co
¦sw u '9out
where
•
•
•
ΔIout is the change in output current.
ƒSW is the regulator's switching frequency.
ΔVout is the allowable change in the output voltage.
(12)
Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
1
1
Co !
u
u ¦sw Voripple
Ioripple
where
•
•
•
ƒSW is the switching frequency.
Vripple is the maximum allowable output voltage ripple.
Iripple is the inductor ripple current.
(13)
Equation 14 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
Voripple
RESR
Ioripple
(14)
Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increase this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some
capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 15 can
be used to calculate the RMS ripple current the output capacitor needs to support.
Vout u (Vinmax Vout )
Icorms
u 9inmax u / u ¦sw
(15)
8.2.2.3 Input Capacitor Selection
The TPS65266-1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF
of effective capacitance on the VIN input voltage pins. In some applications, additional bulk capacitance may also
be required for the VIN input. The effective capacitance includes any DC bias effects. The voltage rating of the
input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current
rating greater than the maximum input current ripple of the TPS65266-1. Calculate the input ripple current using
Equation 16.
Iinrms
Iout u
V
Vout
Vout
u inmin
Vinmin
Vinmin
(16)
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The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple
voltage of the regulator. Calculate the input voltage ripple using Equation 17.
u 0.25
I
'Vin out max
&in u ¦sw
(17)
8.2.2.4 Loop Compensation
The TPS65266-1 incorporates a peak current mode control scheme. The error amplifier is a transconductance
amplifier with a gain of 290 µS. A typical type II compensation circuit adequately delivers a phase margin
between 30° and 90°. Cb adds a high-frequency pole to attenuate high-frequency noise when needed. To
calculate the external compensation components, follow these steps.
1. Select switching frequency, ƒSW, that is appropriate for application depending on L and C sizes, output ripple,
EMI, and so forth. Switching frequency between 500 kHz to 1.5 MHz gives best trade-off between
performance and cost. To optimize efficiency, lower switching frequency is desired.
2. Set up crossover frequency, ƒc, which is typically between 1 / 5 and 1 / 20 of ƒSW.
3. RC can be determined by:
S u ¦C u 9O u &O
RC
GP±($ u Vref u GP±36
where
•
•
Gm_EA is the error amplifier gain (290 µS).
Gm_PS is the power stage voltage to current conversion gain (10 A/V).
(18)
4. Calculate CC by placing a compensation zero at or before the dominant pole
RL u CO
CC
RC
¦p
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
RESR u CO
Cb
RC
1
CO u RL u 2S
(19)
(20)
6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C1 is calculated from Equation 21.
1
C1
S u 51 u ¦c
(21)
26
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LX
VOUT
iL
RESR
RL
Current Sense
I/V Converter
Gm _ PS
10 A / V
Co
C1
R1
FB
Vfb
COMP
EA
Vref
0.6 V
R2
Rc
Gm _ EA
290 µS
Cb
Cc
Copyright © 2016, Texas Instruments Incorporated
Figure 34. DC/DC Loop Compensation
8.2.3 Application Curves
Figure 35. Buck1, Soft-Start, Iout = 3 A
Figure 36. Buck2, Soft-Start, Iout = 2 A
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Figure 37. Buck3, Soft-Start, Iout = 2 A
Figure 38. Buck1, Output Voltage Ripple, Iout = 3 A
Figure 39. Buck2, Output Voltage Ripple, Iout = 2 A
Figure 40. Buck3, Output Voltage Ripple, Iout = 2 A
SR = 0.25 A/µs
SR = 0.25 A/µs
Figure 41. Buck1, Load Transient, 0.75 to 1.5 A
Figure 42. Buck1, Load Transient, 1.5 to 2.25 A
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SR = 0.25 A/µs
SR = 0.25 A/µs
Figure 43. Buck2, Load Transient, 0.5 to 1.0 A
Figure 44. Buck2, Load Transient, 1.0 to 1.5 A
SR = 0.25 A/µs
SR = 0.25 A/µs
Figure 45. Buck3, Load Transient, 0.5 to 1.0 A
Figure 46. Buck3, Load Transient, 1.0 to 1.5 A
Figure 47. Buck1, Hiccup and Recovery
Figure 48. Buck2, Hiccup and Recovery
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Figure 49. Buck3, Hiccup and Recovery
30
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Figure 50. 180° Out of Phase
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9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.7 and 6 V. This input power
supply should be well regulated. If the input supply is located more than a few inches from the TPS65266-1
converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 47 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
The TPS65266-1 supports a 2-layer PCB layout, shown in Figure 51.
Layout is a critical portion of good power supply design. See Figure 51 for a PCB layout example. The top
contains the main power traces for VIN, VOUT, and LX. The top layer also has connections for the remaining
pins of the TPS65266-1 and a large top-side area filled with ground. The top-layer ground area should be
connected to the bottom layer ground using vias at the input bypass capacitor, the output filter capacitor, and
directly under the TPS65266-1 device to provide a thermal path from the exposed thermal pad land to ground.
The bottom layer acts as ground plane connecting analog ground and power ground.
For operation at full-rated load, the top-side ground area together with the bottom-side ground plane must
provide an adequate heat dissipating area. Several signals paths conduct fast changing currents or voltages that
can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies'
performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR
ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. The VIN pin must also be bypassed to ground
using a low-ESR ceramic capacitor with X5R or X7R dielectric.
Because the LX connection is the switching node, the output inductor should be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground should use the same power ground trace as the VIN input bypass capacitor. Try to minimize this
conductor length while maintaining adequate width. The small signal components should be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors should be located as close as
possible to the IC and routed with minimal lengths of trace. Place the additional external components
approximately as shown in Figure 51.
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10.2 Layout Example
VOUT1
SS3
FB3
COMP3
AGND
ROSC
FB1
SS1
PGND2
EN3
LX2
AGND
BST2
VIN
SS2
EN2
FB2
VIN2
COMP2
VIN3
EN1
VINQ
PGND3
VIN1
AGND
LX3
PGND1
PGOOD
BST3
LX1
AGND
BST1
AGND
VIN
COMP1
VOUT3
VOUT2
TOPSIDE
GROUND
AREA
0.010-inch Diameter
Thermal VIA to Ground Plane
VIA to Ground Plane
Figure 51. PCB Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
TPS65261
TPS65261-1
4.5 to 18 V, triple bucks with input voltage Triple bucks 3-A/2-A/2-A output current, features an open-drain RESET
power failure indicator
signal to monitor input power failure, automatic power sequencing
TPS65262
TPS65262-1
4.5 to 18 V, triple bucks with dual
adjustable LDOs
Triple bucks 3-A/1-A/1-A output current, automatic power sequencing.
Dual LDOs:
TPS65262, 200 mA/100 mA
TPS65262-1, 350 mA/150 mA
TPS65263
4.5 to 18 V, triple buck with I2C interface
Triple buck 3-A/2-A/2-A output current, I2C-controlled dynamic voltage
scaling (DVS)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65266-1RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65266-1
TPS65266-1RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65266-1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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