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TPS65320C-Q1
SLVSD50D – MARCH 2016 – REVISED JUNE 2017
TPS65320C-Q1 36-V Step-Down Converter With Eco-mode™ and LDO Regulator
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
One High-VIN Step-Down DC-DC Converter
– Input Range of 3.6 V to 36 V
– 250-mΩ High-Side MOSFET
– Maximum Load Current 3.2 A, Output
Adjustable 1.1 V to 20 V
– Adjustable Switching Frequency 100 kHz to
2.5 MHz
– Synchronizes to External Clock
– High Efficiency at Light Loads With PulseSkipping Eco-mode™ Control Scheme
– Maximum 140-µA Operating Quiescent
Current
One Low-Dropout Voltage (LDO) Regulator
– Input Range of 3 V to 20 V, With Auto-Source
to Balance Efficiency and Lower Standby
Current
– 280-mA Current Capability With Typical 45-µA
Quiescent Current in No-Load Condition
– Power-Good Output (Push-Pull)
– Low-Dropout Voltage of 300 mV at
IO = 200 mA (Typical)
Overcurrent Protection for Both Regulators
Overtemperature Protection
14-Pin HTSSOP Package With PowerPAD™
Integrated Circuit Package
Automotive Infotainment and Cluster
Advanced Driver Assistance System (ADAS)
Automotive Telematics, eCall
3 Description
The TPS65320C-Q1 device is a combination of a
high-VIN DC-DC step-down converter, referred to as
the buck regulator, with an adjustable switch-mode
frequency from 100-kHz to 2.5-MHz, and a high-VIN
280-mA low-dropout (LDO) regulator. The input range
is 3.6 V to 36 V for the buck regulator, and 3 V to
20 V for the LDO regulator. The buck regulator has
an integrated high-side MOSFET. The LDO regulator
features a low-input supply current of 45-μA typical in
no-load, also has an integrated MOSFET with an
active-low, push-pull reset output pin. The input
supply of the LDO regulator auto-source from the
output of the buck regulator when it is in operation.
Low-voltage tracking feature enables TPS65320C-Q1
to track the input supply during cold-crank conditions.
The buck regulator provides a flexible design to fit
system needs. The external loop compensation circuit
allows for optimization of the converter response for
the appropriate operating conditions. A low-ripple
pulse-skip mode reduces the no-load input-supply
current to maximum 140 μA.
The device has built-in protection features such as
soft start, current-limit, thermal sensing and shutdown
due to excessive power dissipation. Furthermore, the
device has an internal undervoltage-lockout (UVLO)
function that turns off the device when the supply
voltage is too low.
Device Information(1)
PART NUMBER
TPS65320C-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
VIN_LDO
VI = 3.6 V to 36 V
BOOT
VIN
SW
Supply
Buck Efficiency Versus Output Current
100
1.1 V to 20 V,
3.2 A
5V
90
80
70
EN2
LDO Input
Auto Source FB1
RT/CLK
SS
COMP
LDO_OUT
1.1 V to 5.5 V,
280 mA
Efficiency (%)
EN1
60
50
40
30
20
fs = 300 kHz
fs = 2 MHz
10
GND
Regulator FB2
Control RST
PowerPAD
0
0
1
2
Load Current (A)
3
4
D001
TPS65321-Q1
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65320C-Q1
SLVSD50D – MARCH 2016 – REVISED JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 25
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2016) to Revision D
•
Page
Added the Soft-Start Discharge section ............................................................................................................................... 22
Changes from Revision B (June 2016) to Revision C
Page
•
Changed the maximum value for the LDO regulator input range from 36 V to 20 V in the Features section ....................... 1
•
Changed the description for the BOOT pin in the Pin Functions table ................................................................................. 3
•
Changed the maximum supply input voltage for VIN_LDO from 20 to 22 in the Absolute Maximum Ratings table ............. 4
•
Added a note about the nRST pin to the test conditions for the output high parameter in the Electrical
Characteristics table .............................................................................................................................................................. 7
•
Deleted that the device can can operate at high duty cycles under the dropout mode operation from the Overview
section .................................................................................................................................................................................. 10
•
Added the Receiving Notification of Documentation Updates section ................................................................................. 36
Changes from Revision A (April 2016) to Revision B
•
2
Page
Changed the device status from Product Preview to Production Data .................................................................................. 1
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SLVSD50D – MARCH 2016 – REVISED JUNE 2017
5 Pin Configuration and Functions
PWP Package
14-Pin HTSSOP With Thermal Pad
Top View
BOOT
1
14
SW
VIN
2
13
GND
VIN_LDO
3
12
COMP
LDO_OUT
4
11
FB1
SS
Thermal
Pad
FB2
5
10
nRST
6
9
RT/CLK
EN2
7
8
EN1
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
1
O
A bootstrap capacitor is required between the BOOT and SW pins. Every time the high-side MOSFET (HSFET) turns off, the capacitor is recharged. In case of drop-out mode, the FET is forced off every 8th clock-cycle
to refresh the boot voltage.
COMP
12
O
The COMP pin is the error-amplifier output of the buck regulator, and the input to the output switch-current
comparator of the buck regulator. Connect frequency-compensation components to the COMP pin.
EN1
8
I
The EN1 pin is the enable and disable input for the buck regulator (high-voltage tolerant) and is internally
pulled to ground. Pull this pin up externally to enable the buck regulator.
EN2
7
I
The EN2 pin is the enable and disable input for the LDO regulator (high-voltage tolerant) and is internally
pulled to ground. Pull this pin up externally to enable the LDO regulator.
FB1
11
I
The FB1 pin is the feedback pin of the buck regulator. Connect an external resistive divider between the buck
regulator output, the FB2 pin, and the GND pin to set the desired output voltage of the buck regulator.
FB2
5
I
The FB2 pin is the feedback pin of the LDO regulator. Connect an external resistive divider between the
LDO_OUT pin, the FB2 pin, and the GND pin to set the desired output voltage of the LDO regulator.
GND
13
—
This pin is the ground pin.
LDO_OUT
4
O
This pin is the LDO regulator output.
nRST
6
O
The nRST pin is the active-low, push-pull reset output of the LDO regulator. Connect this pin with an external
bias voltage through an external resistor. This pin is asserted high after the LDO regulator begins regulating.
RT/CLK
9
I
Connect this pin to an external resistor to ground to program the switching frequency of the buck regulator. An
alternative option is to feed an external clock to provide a reference for the switching frequency of the buck
regulator.
SS
10
I
Connect this pin to an external capacitor to ground which sets the soft-start time of the buck regulator.
SW
14
I
The SW pin is the source node of the internal high-side MOSFET of the buck regulator.
VIN
2
—
The VIN pin is the input supply pin for the internal biasing and high-side MOSFET of the buck regulator.
VIN_LDO
3
—
The VIN_LDO pin is the input supply pin for the LDO regulator.
—
Electrically connect the PowerPAD to ground and solder to the ground plane of the PCB for thermal
performance.
NAME
NO.
BOOT
Exposed
PowerPAD
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply inputs
Control
MIN
MAX
UNIT
VIN
–0.3
40
V
VIN_LDO
–0.3
22
V
VIN-VIN_LDO
–0.3
40
V
EN1, EN2
–0.3
40
V
1
V
FB1
–0.3
3.6
SW
–0.3
–2 V for 30 ns
40
–0.3
46
EN1-VIN, EN2-VIN
BOOT
Buck converter
BOOT-SW
V
8
COMP
–0.3
3.6
SS
–0.3
3.6
RT/CLK, SS
–0.3
3.6
LDO_OUT
–0.3
7
FB2
–0.3
7
nRST
–0.3
7
Operating ambient temperature, TA
–40
125
°C
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
165
°C
LDO regulator
(1)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
4
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100011
UNIT
±2000
All pins
±500
Corner pins (1, 7, 8, and 14)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply inputs
Buck regulator
MIN
MAX
3.6
36
3
20
BOOT1
3.6
42
SW1
–1
36
VFB1
0
0.8
SS
0
3
COMP
0
3
VIN
VIN_LDO
RT/CLK
0
3
1.1
5.5
VFB2
0
0.8
nRST
0
5.25
EN1
0
36
EN2
0
36
–40
150
LDO_OUT
LDO regulator
Control
Temperature
Operating junction temperature range, TJ
UNIT
V
V
V
V
°C
6.4 Thermal Information
TPS65320C-Q1
THERMAL METRIC
(1)
PWP (HTSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
41
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
33.1
°C/W
Junction-to-board thermal resistance
25.4
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
25.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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6.5 Electrical Characteristics
VI = 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA = –40°C to 125°C and maximum operating
junction temperature TJ = 150°C, unless otherwise noted. VI is the voltage on the battery-supply pins, VIN and VIN_LDO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.6
12
36
V
2
7
μA
36
V
0.7
V
VIN (INPUT POWER SUPPLY)
Operating input voltage
Normal mode, after initial start-up
Shutdown supply current
V(EN1) = V(EN2) = 0 V, 25°C
Initial start-up voltage
6
ENABLE AND UVLO (EN1 AND EN2 PINS)
Enable low level
Enable high level
2.5
V
V(VIN)(f)
Internal UVLO falling threshold
Ramp V(VIN) down until output turns OFF
1.8
2.6
3
V
V(VIN)(r)
Internal UVLO rising threshold
Ramp V(VIN) up until output turns ON
2.2
2.8
3.2
V
110
140
μA
BUCK REGULATOR
I(Qon)
V(ref1)
DC(LDR)
T(LDSR)
Operating: non-switching supply
Measured at the VIN pin
V(FB1) = 0.83 V, V(VIN) = 12 V, 25°C
Output capacitance
ESR = 0.001 Ω to 0.1 Ω, large output
capacitance may be required for load
transient
Voltage reference for FB1 pin
Buck regulator output: 1.1 V to 20 V.
Buck regulator in continuous conducting
mode without pulse-skipping
DC output voltage accuracy
Includes voltage references, DC load
and line regulation, process and
temperature
DC Load regulation, ΔVOUT / VOUT
IOUT = 0 to IOUTmax
Transient load step response
V(VIN) = 12 V, IOUT = 200 mA to 3 A,
TR = TF = 1 µs,
Buck Output Voltage = 5 V, ƒS = 2 MHz
5%
V(VIN) = 12 V, V(SW) = 6 V
127
10
0.788
μF
0.8
–2%
0.812
V
2%
0.5%
BUCK REGULATOR: HIGH-SIDE MOSFET
r(DS(on) HS
On-resistance
FET)
250
mΩ
BUCK REGULATOR: CURRENT-LIMIT
Current-limit threshold
V(VIN) = 12 V, TJ = 25°C
4
6
A
BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK
High threshold
RT/CLK
Low threshold
1.9
0.5
2.2
0.7
V
V
LDO REGULATOR
ΔVO(ΔVI)
Line regulation
V(VIN_LDO) = 6 V to 20 V, V(VIN) = 20 V,
I(LDO_OUT) = 10 mA, V(LDO_OUT) = 3.3 V
20
mV
ΔVO(ΔIL)
Load regulation
I(LDO_OUT) = 10 mA to 200 mA, V(VIN) =
12 V, V(VIN_LDO) = 5 V,
V(LDO_OUT) = 3.3 V
35
mV
VDROPOUT
Dropout voltage
(V(VIN_LDO) – V(LDO_OUT))
I(LDO_OUT) = 200 mA
450
mV
I(LDO_OUT)
Output current
V(LDO_OUT) in regulation, V(VIN) ≥ 4 V
280
mA
VI(VIN_LDO)
Operating input voltage on
VIN_LDO pin
V(LDO_OUT) in regulation
20
V
V(ref2)
Voltage reference FB2 pin
V(LDO_OUT) = 1.1 V to 5.5 V
0.812
V
ICL(LDO_OUT)
Output current-limit
V(LDO_OUT) = 0 V (the LDO_OUT pin is
shorted to ground)
1000
mA
IQ(LDO)
Quiescent current
V(VIN) = 12 V; Measured at VIN pin
V(EN1) = 0 V, V(EN2) = 5 V,
I(LDO_OUT) = 0.01 mA to 0.75 mA
65
μA
6
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300
3
0.788
0.8
280
45
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Electrical Characteristics (continued)
VI = 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA = –40°C to 125°C and maximum operating
junction temperature TJ = 150°C, unless otherwise noted. VI is the voltage on the battery-supply pins, VIN and VIN_LDO.
PARAMETER
PSRR
Power supply ripple rejection
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(VIN_LDO)(rip) = 0.5 VPP,
I(LDO_OUT) = 200 mA,
frequency (ƒ) = 100 Hz,
V(LDO_OUT) = 5 V and V(LDO_OUT) = 3.3 V
60
dB
V(VIN_LDO)(rip) = 0.5 VPP,
I(LDO_OUT) = 200 mA, ƒ = 150 kHz,
V(LDO_OUT) = 5 V and V(LDO_OUT) = 3.3 V
30
dB
C(LDO_OUT)
Output capacitor
ESR = 0.001 Ω to 100 mΩ, large output
capacitance may be required for load
transient; V(LDO_OUT) ≥ 3.3 V
1
40
μF
C(LDO_OUT)
Output capacitor
ESR = 0.001 Ω to 100 mΩ, large output
capacitance may be required for load
transient; 1.2 V ≤ V(LDO_OUT) < 3.3 V
20
40
μF
LDO REGULATOR: RESET (nRST PIN)
RESET threshold
V(LDO_OUT) decreasing
VOH
Output high
Reset released due to rising LDO_OUT,
V(LDO_OUT) ≥ 3.3 V, IOH= 100 μA (1)
VOL
Output low
Reset asserted due to falling LDO_OUT,
IOL = 1 mA
85%
90%
95%
–5% ×
V(LDO_OUT)
V
0.045
0.4
V
OVER TEMPERATURE PROTECTION
TSD
Thermal-shutdown trip point
Thys
Hysteresis
(1)
175
ºC
10
ºC
The nRST pin is still pulled high even if V(LDO_OUT) >3.3 V, but it may not meet the –5% level.
6.6 Switching Characteristics
VI = 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA = –40°C to 125°C and maximum operating
junction temperature TJ = 150°C, unless otherwise noted. VI is the voltage on the battery-supply pins, VIN and VIN_LDO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK REGULATOR: HIGH-SIDE MOSFET
tonmin
Minimum on-time
ƒS = 2.5 MHz
115
ns
BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching-frequency range using
RT mode
ƒS
Switching frequency
100
200-kΩ resistor connected between pin
RT/CLK and GND
Switching-frequency range using
CLK mode
523
585
300
2500
kHz
640
kHz
2200
kHz
Minimum CLK input pulse width
Measures at CLK input = 2.2 MHz
30
ns
RT/CLK
Falling edge to SW rising edge
delay
Measured at 500 kHz with 200-kΩ series
resistor connected to RT/CLK pin
60
ns
PLL
Lock-in time
Measured at 500 kHz
100
μs
LDO REGULATOR: RESET (nRST PIN)
Filter time
Delay before asserting nRST low
7
14
21
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6
100
5.5
90
5
80
RI 1RPLQDO ¦SW
Buck Output Voltage (V)
6.7 Typical Characteristics
4.5
4
3.5
3
2
3.75
4
4.25
4.5 4.75 5 5.25
Input Voltage (V)
40
5.5
5.75
10
0
0.0
6
2500
2000
1500
1000
500
0
V(VIN) = 12 V
400
600
800 1000 1200
RT/CLK Resistance (k:)
1400
1600
0.8
C004
0.8
0.798
0.796
-50
300
3.3
270
3.298
240
Dropout Voltage (mV)
3.302
3.288
0.7
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D001
D003
V(VIN) = 12 V
Figure 4. Buck-Regulator Feedback-Voltage Reference
(V(FB1)) vs Junction Temperature
Figure 3. Buck-Regulator Switching Frequency vs RT_CLK
Resistance
3.29
0.6
0.802
No Load
3.292
0.5
0.804
TJ = 25°C
3.294
0.4
Figure 2. Buck-Regulator Switching Frequency vs V(FB1)
Feedback Voltage
D002
3.296
0.3
V(VIN) = 12 V
Buck-Regulator Feedback-Voltage Resistance (V)
3000
200
0.2
VFB1 (V)
Figure 1. Buck Output Voltage vs Minimum Input Voltage
0
0.1
D001
3.6 V ≤ V(VIN) ≤ 6 V
ƒS = 2 MHz
Switching Frequency (kHz)
50
20
No Load
100-mA Load
1-A Load
1
3.5
LDO Output Voltage (Vt)
60
30
2.5
1.5
210
180
150
120
90
3.286
60
3.284
30
0
3.282
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27
LDO Load Current (A)
V(VIN_LDO) = 5 V
0.3
D004
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27
LDO Load Current (mA)
0.3
D005
V(LDO_OUT) = 3.3 V
V(LDO_OUT) = 3.3 V
Figure 5. LDO-Regulator Load Regulation
8
70
Figure 6. LDO-Regulator Dropout Voltage vs Load Current
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LDO-Regulator Feedback-Voltage Resistance (V)
Typical Characteristics (continued)
0.7995
0.799
0.7985
0.798
0.7975
0.797
0.7965
0.796
-50
-25
0
I(LDO_OUT) = 100 mA
25
50
75
100
Junction Temperature (qC)
125
150
D006
V(VIN_LDO) = 5 V
Figure 7. LDO-Regulator Feedback-Voltage Reference (V(FB2)) vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS65320C-Q1 device is a 36-V, 3.2-A, DC-DC step-down converter (also referred to as a buck regulator)
with a 280-mA low-dropout (LDO) linear regulator. Both of these regulators have low quiescent consumption
during a light load to prolong battery life.
The buck regulator improves performance during line and load transients by implementing a constant-frequency
and current-mode control (CCM) that reduces output capacitance which simplifies external frequencycompensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size
optimization when selecting the output-filter components. The switching frequency is adjusted by using a resistor
to ground on the RT/CLK pin. The buck regulator has an internal phase-locked loop (PLL) on the RT/CLK pin
that synchronizes the power-switch turnon to the falling edge of an external system clock.
The TPS65320C-Q1 device reduces the external component count by integrating the boot recharge diode. A
capacitor between the BOOT pin and the SW pin supplies the bias voltage for the integrated high-side MOSFET.
The output voltage can step-down to as low as the 0.8-V reference. The soft start minimizes inrush currents and
provides power-supply sequencing during power up. Connect a small-value capacitor to the pin to adjust the softstart time. For critical power-supply sequencing requirements couple a resistor divider to the pin.
The LDO regulator consumes only about a 45-µA current in light load. The LDO regulator also tracks the battery
when the battery voltage is low (in a cold-crank condition).The input of the LDO regulator has a unique autosource feature which sources the input supply from either the buck output or the battery. If both the buck and
LDO regulators are enabled, the buck regulator switches the input of the LDO regulator to the output of the buck
to reduce heat. With the buck disabled or the buck output voltage out of regulation (VFB1 less than 91% of Vref),
the buck regulator switches the LDO input automatically to the input voltage.
The LDO regulator of the TPS65320C-Q1 device has a power-good comparator (nRST) that asserts when the
regulated output voltage is less than 92% (typical) of the nominal output voltage.
10
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7.2 Functional Block Diagram
EN1
Shutdown
PWRGD
Thermal
Shutdown
Shutdown
UVLO
Shutdown
Logic
Enable
Threshold
OV
Voltage
Reference
Boot
Charge
Boot
UVLO
Minimum
Clamp
Pulse Skip
Error
Amplifier
Current
Sense
BOOT
PWM
Comparator
FB1
SS
VIN
Logic
UV
SS/TR
EN2
+
PWM Latch
R
Q
+
Logic
S
SW
Slope
Compensation
COMP
OVTO
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Linear Regulator
Control
LDO_OUT
Oscillator
with PLL
LDO Input
Selection
Voltage
Supervisor
+
VIN
±
nRST
0.8 V
GND
RT/CLK
PowerPAD
VIN_LDO
FB2
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7.3 Feature Description
7.3.1 Buck Regulator
7.3.1.1 Fixed-Frequency PWM Control
The TPS65320C-Q1 buck regulator uses an adjustable, fixed-frequency peak current-mode control. An internal
voltage reference compares the output voltage through external resistors on the FB1 pin to an error amplifier
which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The device
compares the error amplifier output to the high-side power-switch current. When the power-switch current
reaches the level set by the COMP voltage, the power switch turns off. The COMP pin voltage increases and
decreases as the output current increases and decreases. The device implements a current-limit by clamping the
COMP pin voltage to a maximum level.
7.3.1.2 Slope Compensation Output
The TPS65320C-Q1 buck regulator adds a compensating ramp to the switch-current signal. This slope
compensation prevents sub-harmonic oscillations. The available peak-inductor current remains constant over the
full duty-cycle range.
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Feature Description (continued)
7.3.1.3 Pulse-Skip Eco-mode™ Control Scheme
The TPS65320C-Q1 buck regulator operates in a pulse-skip mode at light load currents to improve efficiency by
reducing switching and gate-drive losses. The design of the TPS65320C-Q1 buck regulator is such that if the
output voltage is within regulation and the peak switch current at the end of any switching cycle is below the
pulse-skipping-current threshold, the buck regulator enters pulse-skip mode. This current threshold is the current
level corresponding to a nominal COMP voltage, or 720 mV. The current at which entry to the pulse-skip mode
occurs depends on switching frequency, inductor selection, output-capacitor selection, and compensation
network.
In pulse-skip mode, the buck regulator clamps the COMP pin voltage at 720 mV, inhibiting the high-side
MOSFET. Further decreases in load current or in output voltage cannot drive the COMP pin below this clampvoltage level. Because the buck regulator is not switching, the output voltage begins to decay. As the voltagecontrol loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the
high-side MOSFET turns on and a switching pulse initiates on the next switching cycle. The peak current is set
by the COMP pin voltage. The output current recharges the output capacitor to the nominal voltage, then the
peak switch current begins to decrease, and eventually falls below the pulse-skip-mode threshold, at which time
the buck regulator enters Eco-mode again.
For pulse-skip-mode operation, the TPS65320C-Q1 buck regulator senses the peak current, not the average or
load current. Therefore, the load current where the buck regulator enters pulse-skip mode is dependent on the
output inductor value. When the load current is low and the output voltage is within regulation, the buck regulator
enters a sleep mode and draws only 140-µA input quiescent current. The internal PLL remains operating when
the buck regulator is in sleep mode.
7.3.1.4 Dropout Mode Operation and Bootstrap Voltage (BOOT)
The TPS65320C-Q1 buck regulator has an integrated boot regulator and requires a small ceramic capacitor
between the BOOT pin and the SW pin to provide the gate-drive voltage for the high-side MOSFET. The BOOT
capacitor recharges when the high-side MOSFET is off and the low-side diode conducts. The value of this
ceramic capacitor must be 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric and
a voltage rating of 10 V or higher because of the stable characteristics over temperature and over voltage.
To improve drop out, the high-side MOSFET of the TPS65320C-Q1 buck regulator remains on for 7 consecutive
switching cycles, and is forced off during the 8th switching cycle to allow the low-side diode to conduct and
refresh the charge on the BOOT capacitor. Because the current supplied by the BOOT capacitor is low, the highside MOSFET can remain on before it is required to refresh the BOOT capacitor. The effective duty cycle of the
switching regulator under this operation can be higher than the fixed-frequency PWM operation through skipping
switching cycles.
7.3.1.5 Error Amplifier
The buck converter of the TPS65320C-Q1 buck regulator has a transconductance amplifier acting as the error
amplifier. The error amplifier compares the FB1 voltage to the lower of the internal soft-start (SS) voltage or the
internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 310 µS during normal
operation. During the soft-start operation, the transconductance is a fraction of the normal operating gm. When
the voltage of the voltage on the FB1 pin is below 0.8 V and the buck regulator is regulating using an internal SS
voltage, the gm is 70 µS. For frequency compensation, external compensation components (capacitor with series
resistor and an optional parallel capacitor) must be connected between the COMP pin and the GND pin.
7.3.1.6 Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable band-gap circuit.
7.3.1.7 Adjusting the Output Voltage
A resistor divider from the output node to the FB1 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Start with 10 kΩ for the R2 resistor and use Equation 1 to calculate R1. To
improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is
more susceptible to noise, and voltage errors from the FB1 input current are noticeable.
12
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Feature Description (continued)
R1 = R2 ´
VO - 0.8 (V)
0.8 (V)
where
•
VO = buck regulator output voltage
(1)
7.3.1.8 Soft-Start and Tracking Pin (SS/TR)
The TPS65320C-Q1 buck regulator effectively uses the lower voltage of the internal voltage reference or the
SS/TR pin voltage as the reference voltage of the power supply and regulates the output accordingly. A capacitor
on the SS/TR pin to ground implements a soft-start time. The TPS65320C-Q1 buck regulator has an internal
pullup current source of 2 μA that charges the external soft-start capacitor. Equation 2 shows the calculations for
the soft-start time (10% to 90%). The voltage reference (Vref) is 0.8 V and the soft-start current (Iss) is 2 μA. The
soft-start capacitor must remain lower than 10 nF and greater than 1 nF.
t (ms) ´ Iss (µA)
Css (nF) = ss
Vref (V) ´ 0.8
where
•
•
The voltage reference (Vref) is 0.8 V.
The soft-start current (ISS) is 2 µA.
(2)
7.3.1.9 Overload-Recovery Circuit
The TPS65320C-Q1 buck regulator has an overload recovery (OLR) circuit. The OLR circuit soft-starts the output
from the overload voltage to the nominal regulation voltage on removal of the fault condition. The OLR circuit
discharges the SS/TR pin to a voltage slightly greater than the FB1 pin voltage using an internal pulldown of 382
μA when the error amplifier changes to a high voltage from a fault condition. On removal of the fault condition,
the output soft starts from the fault voltage to nominal output voltage.
7.3.1.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS65320C-Q1 buck regulator is adjustable over a wide range from
approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is 0.5 V
(typical) and must have a resistor to ground to set the switching frequency. To determine the timing resistance
for a given switching frequency, use Equation 3 or the curves in Figure 2. To reduce the solution size, the user
typically sets the switching frequency as high as possible. However, consider tradeoffs of the supply efficiency,
maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is 100 ns (typical)
and limits the maximum operating input voltage. The frequency-shift circuit also limits the maximum switching
frequency. The following sections discuss more details of the maximum switching frequency.
206033
RT (kW) = 1.0888
ƒS
(kHz)
(3)
7.3.1.11 Overcurrent Protection and Frequency Shift
The TPS65320C-Q1 buck regulator implements current-mode control, which uses the COMP pin voltage to turn
off the high-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch current and COMP pin
voltage are compared. When the peak-switch current intersects the COMP voltage, the high-side switch turns off.
During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP
pin high, increasing the switch current. Internal clamping of the error-amplifier output functions as a switch
current-limit.
The TPS65320C-Q1 buck regulator also implements a frequency shift. The switching frequency is divided by 8,
4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the FB1 pin. During short-circuit events (particularly with
high-input-voltage applications), the control loop has a finite minimum controllable on-time, and the output has a
low voltage. During the switch on-time, the inductor current ramps to the peak current-limit because of the high
input voltage and minimum on-time. During the switch off-time, the inductor typically does not have enough offtime and output voltage for the inductor to ramp down by the ramp-up amount. The frequency shift effectively
increases the off-time which allows the current to ramp down.
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Feature Description (continued)
7.3.1.12 Selecting the Switching Frequency
The switching frequency that is selected must be the lower value of the two equations, Equation 4 and
Equation 5. Equation 4 is the maximum switching-frequency limitation set by the minimum controllable on-time.
Setting the switching frequency above this value causes the regulator to skip switching pulses. The device
maintains regulation, but pulse-skipping leads to high inductor current and a significant increase in output ripple
voltage.
Use Equation 5 to calculate the maximum switching frequency limit set by the frequency-shift protection. For
adequate output short-circuit protection at high input voltages, set the switching frequency to a value less than
the ƒS(maxshift) frequency. In Equation 5, to calculate the maximum switching frequency one must take into
account that the output voltage decreases from the nominal voltage to 0 volts, and the ƒdiv integer increases from
1 to 8 corresponding to the frequency shift.
æ 1 ö æ (IL ´ Rdc + VO + Vd ) ö
ƒS (max skip) = ç
÷´ç
÷
è t on ø è (VI - IL ´ Rhs + Vd ) ø
where
•
•
•
•
•
•
•
IL = inductor current
Rdc = inductor resistance
VI = maximum input voltage
VO = buck regulator output voltage
Vd = diode voltage drop
Rhs = FET on resistance (127 mΩ, trypical)
ton = controllable on-time (100 ns, typical)
æƒ
ƒS (shift) = ç div
è t on
(4)
ö æ (IL ´ Rdc + VO(SC) + Vd ) ö
÷÷
÷ ´ çç
ø è (VI - IL ´ Rhs + Vd ) ø
where
•
•
VO(SC) = buck regulator output voltage during short-circuit condition
ƒdiv = frequency divide factor (equals 1, 2, 4 or 8)
(5)
In Figure 8 the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is 0 V, the resistance of the inductor is 0.13 Ω, the FET on-resistance is 0.127 Ω, and the diode
voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping.
Switchin Frequency (kHz)
2500
2000
1500
1000
500
(Maxskip)
Skip)
¦fsw
S (max
¦fsw
(Shift)
S (shift)
0
10
20
30
40
50
Input Voltage (V)
VO = 3.3 V
60
C012
IL = 1 A
Figure 8. Maximum Switching Frequency Versus Input Voltage
14
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Feature Description (continued)
7.3.1.13 How to Interface to RT/CLK Pin
The RT/CLK pin synchronizes the buck regulator to an external system clock. To implement the synchronization
feature, connect a square wave to the RT/CLK pin through the circuit network shown in Figure 9. The squarewave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and must have an ontime greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to
2200 kHz. The rising edge of the SW pin synchronizes with the falling edge of the RT/CLK pin signal. Design the
external synchronization circuit in such a way that the device has the default frequency-set resistor connected
from the RT/CLK pin to ground if the synchronization signal turns off. TI recommends using a frequency-set
resistor connected as shown in Figure 9 through a 50-Ω resistor to ground. The resistor must set the switching
frequency close to the external CLK frequency. TI also recommends AC-coupling the synchronization signal
through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces SW
jitter in heavy-load applications when synchronizing to an external clock, and in applications that transition from
synchronizing to RT mode. The first time CLK is pulled above the CLK threshold, the device switches from the
RT resistor frequency to PLL mode. Along with the resulting removal of the internal 0.5-V voltage source, the
CLK pin becomes high-impedance as the PLL starts to lock onto the external signal. Because there is a PLL on
the buck regulator, the switching frequency can be higher or lower than the frequency set with the external
resistor. The buck regulator transitions from the resistor mode to the PLL mode and then increases or decreases
the switching frequency until the PLL locks onto the CLK frequency within 100 ms.
When the buck regulator transitions from the PLL mode to the resistor mode, the switching frequency slows
down from the CLK frequency to 150 kHz, then reapplies the 0.5-V voltage. The resistor then sets the switching
frequency. The switching-frequency divisor changes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the
FB1 pin. The buck regulator implements a digital frequency shift to enable synchronizing to an external clock
during standard start-up and fault conditions.
10 …F
4k
Rfset
RT/CLK
PLL
External
Clock
Source
50
Figure 9. Synchronizing to a System Clock
7.3.1.14 Overvoltage Transient Protection
The TPS65320C-Q1 buck regulator incorporates an overvoltage transient protection (OVTP) circuit to minimize
voltage overshoot when recovering from output fault conditions or strong unload transients on power-supply
designs with low-value output capacitance. For example, with the buck regulator output overloaded, the error
amplifier compares the actual output voltage to the internal reference voltage. If the FB1 pin voltage is lower than
the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the
error amplifier output to a high voltage, thus requesting the maximum output current. On removal of the condition,
the buck regulator output rises and the error-amplifier output transitions to the steady-state duty cycle. In some
applications, the buck regulator output voltage can respond faster than the error-amplifier output can respond
which leads to possible output overshoot. The OVTP feature minimizes the output overshoot when using a lowvalue output capacitor by implementing a circuit to compare the FB1-pin voltage to the OVTP threshold (which is
109% of the internal voltage reference). The FB1 pin voltage exceeding the OVTP threshold disables the highside MOSFET, preventing current from flowing to the output and minimizing output overshoot. The FB1 voltage
dropping lower than the OVTP threshold allows the high-side MOSFET to turn on at the next clock cycle.
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Feature Description (continued)
7.3.1.15 Small-Signal Model for Loop Response
Figure 10 shows an equivalent model for the buck-regulator control loop which can be modeled in a circuitsimulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gmea of 310 μS. Model the error amplifier using an ideal voltage-controlled
current source. Resistor, RO, and capacitor, CO, model the open-loop gain and frequency response of the
amplifier. The 1-mV AC-voltage source between nodes a and b effectively breaks the control loop for the
frequency-response measurements. Plotting c versus a shows the small-signal response of the frequency
compensation. Plotting a versus b shows the small-signal response of the overall loop. Check the dynamic loop
response by replacing RL with a current source that has the appropriate load-step amplitude and step rate in a
time-domain analysis. This equivalent model is only valid for continuous-conduction-mode designs.
SW
VO
Power Stage
gmps = 10.5 A/V
a
b
R1
RESR
FB1
RL
CO
±
COMP
c
C2
R3
C1
Error
Amplifier
CO_ea
RO_ea
+
R1
Vref = 0.8 V
gmea
310 µA/V
Figure 10. Small-Signal Model for Loop Response
7.3.1.16 Simple Small-Signal Model for Peak-Current Mode Control
Figure 11 shows a simple small-signal model that can be used to understand how to design the frequency
compensation. A voltage-controlled current source (duty cycle modulator) supplying current to the output
capacitor and load resistor can approximate the TPS65320C-Q1 buck regulator power stage. Equation 6 shows
the control-to-output transfer function, which consists of a DC gain, one dominant pole, and one ESR zero. The
quotient of the change in switch current divided by the change in COMP pin voltage (node c in Figure 10) is the
power-stage transconductance. The gmps for the TPS65320C-Q1 buck regulator power-stage is 10.5 A/V. Use
Equation 7 to calculate the low-frequency gain of the power stage which is the product of the transconductance
and the load resistance.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load seems problematic at first, but the dominant pole moves with the load current (see
Equation 8). The dashed line in the right half of Figure 11 highlights the combined effect. As the load current
decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same
for the varying load conditions, which makes designing the frequency compensation easier. The type of output
capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation
design. Using high-ESR aluminum-electrolytic capacitors can reduce the number of frequency-compensation
components required to stabilize the overall loop because the phase margin increases from the ESR zero at the
lower frequencies (see Equation 9).
16
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Feature Description (continued)
VO
RESR
VC
Adc
¦P
RL
gmps = 10.5 A/V
CO
¦Z
Figure 11. Simple Small-Signal Model and Frequency Response for Peak-Current Mode
VO
= A dc
VC
æ
s
ç1 +
2π ´ ƒ Z
´è
æ
s
ç1 +
2π
´ ƒP
è
ö
÷
ø
ö
÷
ø
(6)
A dc = gmps ´ RL
ƒP _ mod =
ƒ Z _ mod =
(7)
1
2π ´ RL ´ CO
(8)
1
2π ´ RESR ´ CO
(9)
7.3.1.17 Small-Signal Model for Frequency Compensation
The buck regulator of the TPS65320C-Q1 device uses a transconductance amplifier as the error amplifier.
Figure 12 shows compensation circuits. Implementation of Type 2 circuits is most likely in high-bandwidth powersupply designs. The purpose of loop compensation is to ensure stable operation while maximizing dynamic
performance. Use of the Type 1 circuit is with power-supply designs that have high-ESR aluminum electrolytic or
tantalum capacitors. Equation 10 and Equation 11 show how to relate the frequency response of the amplifier to
the small-signal model in Figure 12. Modeling of the open-loop gain and bandwidth uses RO and CO shown in
Figure 12. See the Typical Application section for a design example with a Type 2A network that has a low-ESR
output capacitor. For stability purposes, the target must have a loop-gain slope that is –20 dB/decade at the
crossover frequency. Also, the crossover frequency must not exceed one-fifth of the switching frequency (120
kHz in the case of a 600-kHz switching frequency).
For dynamic purposes, the higher the bandwidth, the faster the load-transient response. A large DC gain means
high DC-regulation accuracy (DC voltage changes little with load or line variations). To achieve this loop gain, set
the compensation components according to the shape of the control-output bode plot.
Equation 10 through Equation 20 serve as a reference to calculate the compensation components. RO and C1
form the dominant pole (P1). A resistor (R3) and a capacitor (C1) in series to ground work as zero (Z1). In
addition, add a lower-value capacitor (C2) in parallel with R3 to work as an optional pole. This capacitor can filter
noise at switching frequency, and is also required if the output capacitor has high ESR.
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Feature Description (continued)
VO
R1
FB1
±
Vref = 0.8 V
Type 1
COMP
Error
Amplifier
R2
Type 2B
Type 2A
gmea
+
R3
RO
R3
C2
CO
C1
C2
C1
Inside TPS65320C-Q1
Copyright © 2017, Texas Instruments Incorporated
Figure 12. Types of Frequency Compensation
P0
Aol
A0
A1
P1
Z1
P2
BW
Figure 13. Frequency Response of the Type 2 Frequency Compensation
A ol (V/V)
gmea
gmea
=
2π ´ BW (Hz)
RO _ ea =
CO _ ea
P0 =
(10)
(11)
1
2π ´ RO _ ea ´ CO _ ea
(12)
æ
ö
2
ç1 +
÷
2π ´ ƒ Z1 ø
è
EA = A0 ´
æ
ö æ
ö
2
2
ç1 +
÷ ´ ç1 +
÷
2π ´ ƒP1 ø è
2π ´ ƒP2 ø
è
18
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Feature Description (continued)
R2
R1 + R2
R2
|| R3 ´
R1 + R2
A0 = gmea ´ RO _ ea ´
A1 = gmea ´ RO _ ea
P1 =
(14)
(15)
1
2π ´ RO _ ea ´ C1
(16)
1
Z1 =
2π ´ R3 ´ C1
1
P2 =
Type 2A
2π ´ R3 ´ C2
1
P2 =
Type 2B
2π ´ R3 ´ CO _ ea
P2 =
1
2π ´ RO _ ea ´ C2
(17)
(18)
(19)
Type 1
(20)
7.3.2 LDO Regulator
The LDO regulator on the TPS65320C-Q1 device can be used to supply low power consumption rails. The
quiescent current in standby mode is about 45 µA under typical operating condition.
The LDO regulator require both supplies from VIN and VIN_LDO to function. At all times the voltage level of VIN
must be higher or equal to the voltage level of VIN_LDO for the LDO regulator to function properly. The current
capability of the LDO regulator is 280 mA under the full VIN_LDO input range, while V(VIN) ≥ 4 V. When VIN
becomes less than 4 V, the current capability of the LDO regulator decreases.
7.3.2.1 Charge-Pump Operation
The LDO regulator has an internal charge-pump that turns on or off depending on the input voltage. The chargepump switching circuitry does not cause conducted emissions to exceed required thresholds on the input voltage
line. The charge-pump switching thresholds are hysteretic. Figure 14 shows the typical switching thresholds for
the charge pump.
ON
Hysteresis
OFF
8.5
9
VI (V)
Figure 14. Charge-Pump Switching Thresholds
Table 1. Typical Quiescent Current Consumption
LDO IQ
CHARGE PUMP ON
CHARGE PUMP OFF
300-µA
45 µA
7.3.2.2 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation, and the output voltage tracks input minus a drop out
voltage (VDROPOUT). This feature allows for a smaller input capacitor and can possibly eliminate the need to use a
boost convertor during cold-crank conditions.
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7.3.2.3 Adjusting the Output Voltage
A resistor divider from the output node to the FB2 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Referring to the schematics in Figure 21, begin with 10 kΩ as the selected
value for the R6 resistor and use Equation 21 to calculate the value of the R5 resistor.
V(LDO _ OUT) - 0.8 (V)
R5 = R6 ´
0.8 (V)
(21)
To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator
is more susceptible to noise, and voltage errors from the FB2 input current are noticeable.
7.3.3 Thermal Shutdown
The device implements an internal thermal shutdown as protection if the junction temperature exceeds 170°C
(typical). The thermal shutdown forces the buck regulator to stop switching and disables the LDO regulator when
the junction temperature exceeds the thermal trip threshold. Once the junction temperature decreases below
160°C (typical), the device re-initiates the power-up sequence.
7.3.4 Power-Good Output, nRST
The nRST pin is a push-pull output formed by a push-pull stage between LDO_OUT and GND pins. The poweron-reset output asserts low until the output voltage on LDO_OUT exceeds the setting thresholds of 92% (typical)
and the deglitch timer has expired. Additionally, whenever the EN2 pin is low or open, the nRST pin immediately
asserts low regardless of the output voltage. If a thermal shutdown occurs because of excessive thermal
conditions, this pin also asserts low.
7.3.5 Enable and Undervoltage Lockout
The TPS65320C-Q1 device enable pins (EN1 and EN2) are high-voltage-tolerant input pins with an internal
pulldown circuit. A high input activates the device and turns on the regulators.
The TPS65320C-Q1 device has an internal UVLO circuit to shut down the output if the input voltage falls below
an internally-fixed UVLO-falling threshold level. This UVLO circuit ensures that both regulators are not latched
into an unknown state during low-input-voltage conditions. The regulators power up when the input voltage
exceeds the UVLO-rising threshold level.
7.4 Device Functional Modes
7.4.1 Modes of Operation
The buck regulator has two hardware enable pins, and one can turn off either the buck or the LDO by pulling the
enable pin low, as listed in Table 2. One unique feature of the TPS65320C-Q1 buck regulator is the input auto
source of the LDO. With both the buck and the LDO enabled, the LDO receives input from the output of the buck
through the VIN_LDO pin. In this mode, the buck output voltage must be higher than the LDO output voltage.
With the buck disabled and the LDO still enabled, the input of the LDO changes automatically from VIN_LDO to
VIN which is useful for standby operations which need a very low standby current, such as automotive
infotainment, telematics, and other operations. The LDO changes the input when the buck output voltage is out
of regulation (V(FB1) is less than 91% of Vref1).
Table 2. Device Operation Modes
20
BUCK
LDO
EN1
EN2
0
0
Both buck and LDO disabled
0
1
Buck disabled. LDO enabled and LDO input source is from the battery.
1
0
Buck enabled and LDO disabled
1
1
Both buck and LDO enabled and LDO input source is from buck output. Buck output voltage must
be higher than LDO output voltage.
DESCRIPTION
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VIN_LDO
Automotive Battery
VIN_LDO
Automotive Battery
BOOT
VIN
5-V Preregulator
BOOT
5-V Preregulator
VIN
SW
FB1
EN1
KL15 OFF
SW
FB1
EN1
KL15 ON
LDO Input
MUX
KL30 Always ON
LDO Input
MUX
KL30 Always ON
EN2
EN2
LDO_OUT
GND
3.3-V Standby MCU
Regulator
Control
LDO_OUT
GND
FB2
Standby Mode
3.3-V Standby MCU
Regulator
Control
FB2
Full-Running Mode
Figure 15. Example of LDO Auto Source in Standby Condition
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS65320C-Q1 buck regulator operates with a supply voltage of 3.6 V to 36 V. The TPS65320C-Q1 LDO
regulator operates with a supply voltage of 3 V to 20 V V. To reduce power dissipation, TI recommends to use
the output voltage of the buck regulator as the input supply for the LDO regulator. To use the output voltage of
the buck regulator in this way, the selected buck-regulator output voltage must be higher than the selected LDOregulator output voltage.
To optimize the switching performance (such as low jitter) in automotive applications with input voltages that
have wide ranges, TI recommends to operate the device at higher frequencies, such as 2 MHz, which also helps
achieve AM-band compliance requirements (that extends until 1.7 MHz).
8.1.1 Soft-Start Discharge
A potential set of conditions for the TPS65320C-Q1 device can cause the soft-start capacitor to not (fully)
discharge. A runtime condition can shorten the effective discharge time so that the external capacitor is not
adequately discharged.
To determine if a system is impacted by the inadequate soft-start (SS) discharge, evaluate the system to assess
whether or not an event occurred. If no event occurred, systems that always remain on are not affected. This
issue is only triggered by an EN1 pin toggle. Systems where the TPS65320C-Q1 device is completely powered
off are not affected. Systems with several minutes or hours (depending on the selected SS capacitor, see the
Soft-Start Capacitor Selection for the Buck Regulator section) of delay between when the EN1 pin toggles are
not affected.
No corrective action is required if the downstream hardware can handle all of the following:
• VIN-overshoot (up to 1 V was observed, see Figure 16)
• A nonmonotonous ramp (see Figure 17)
• High inrush-current (up to 6 A, see Figure 17)
EN1
SW
VBAT
Fast ramp and
overshoot
SS
3.3-V Output
EN1
Input current
VO
Capacitor not
fully discharged
Capacitor not fully discharged
Figure 16. Partially Discharged SS Capacitor Causing
Overshoot on VO
22
Figure 17. Partially Discharged SS Capacitor Causes
Nonmonotonic Ramp and High Input Currents
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Application Information (continued)
If the system is affected, the following solutions are available:
• Implement an application fix by applying a discharge resistor (at least 2 MΩ) in parallel to the SS capacitor on
the SS pin. For additional information, see the Passive Discharge Through a Resistor in Parallel With the SS
Capacitor section.
NOTE
This resistance discharges the capacitor, but requires a finite time to do so.
•
Implement an application fix by applying an external discharge circuit (such as one with two NPN transistors).
For additional information, see the Active Discharge Through A NPN Transistor section.
No corrective action is required if the off time is long enough to allow the leakage current to discharge SScapacitor, or if the downstream hardware can accept nonmonotonous ramp, overshoot on VO, increased inrushcurrents, or all of these.
8.1.2 Passive Discharge Through a Resistor in Parallel With the SS Capacitor
Implement an application fix by applying a discharge resistor (at least 2-MΩ) in parallel to the SS capacitor on
the SS pin as shown in Figure 18.
SS
10
C1
3300 pF
R1
2 MΩ
12
SS
EN1
COMP
SW
GND
GND
TPS65321QPWPRQ1
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Slow ramp and
no overshoot
VO
Figure 18. Passive Discharge Schematic
Capacitor is
fully discharged
SS
Figure 19. Passive Discharge With 2-MΩ Resistor
The benefits of this option include a simple, rugged solution. However, the disadvantages include the following:
• If maximum resistor values apply (in automotive applications, the maximum is often 100 kΩ), multiple
resistors in series are required to achieve the 2-MΩ minimum value.
• This resistance discharges the capacitor, but requires a finite time to do so. For example, a capacitor
discharge time of 3.3 nF with a 2-MΩ resistor is approximately 30 ms. A capacitor discharge time of 10-nF
with a 2-MΩ resistor is approximately 80 ms. Use Equation 22 to calculate the discharge time of the selected
capacitor. Online tools are available to help with the calculation.
τ=R×C
where
•
•
R is the discharge resistor (2 MΩ).
C is the value of the soft-start capacitor (for example, 3.3 nF or 10 nF).
For adequate discharge, assume approximately 4τ; for example:
tdischarge = 4 × τ = 4 × R × C = 4 × 2 MΩ × 3.3 nF = 26.4 ms
•
A permanent current will flow from the SS-current source through the resistor, increasing the quiescent
current.
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When implementing this solution, calculate the discharge time of the capacitor, and do not re-enable the buckconverter before this time has elapsed. When taking measurements, consider the impedance of the instrument.
For example, a passive Oscilloscope-probehead usually has a 1-MΩ impedance and compromises measurement
accuracy as it significantly contributes to the discharge if probing the SS pin.
8.1.3 Active Discharge Through A NPN Transistor
Implement an active discharge, activated by the EN1 signal as shown in Figure 20. In this solution, the Q1
transistor functions as an inverter and must be supplied by an always-on source, which is VBAT in this case. The
Q2 transistor discharges the SS capacitor.
SS
10
C1
3300 pF
VBAT
Q2
BC817
EN1
Q1
BC817
1
2
100 kΩ
GND
TPS65321QPWPRQ1
2
3
1
R2
COMP
3
R1
100 kΩ
12
SS
GND
GND
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Figure 20. Active Discharge Schematic
The benefits of this option include fast discharge. However, the disadvantages include the following:
• More external components
• Increased quiescent current through the Q1 transistor which can be mitigated by the selected value for R1.
When implementing this solution, the selected transistor must have a leakage current of less than 1 µA when
turned off, and have a high enough forward-voltage drop on Q1 and a low enough turnon voltage on the Q2
transistor to turn on Q2 (therefore bipolar transistors are used instead of MOSFETs). The combination of
resistors, transistors, VBAT-range, and EN1-drive-voltage must be validated (for example, a low value for R1
with a high value for R2 and a low EN1 voltage might not (fully) turn on Q2 and therefore not discharge the SS
capacitor). The a value of 100 kΩ for both resistors proved valid across a wide range of permutations with the
selected BC817-transistors. When taking measurements, consider the impedance of the instrument. For
example, a passive Oscilloscope-probehead usually has a 1-MΩ impedance and compromises measurement
accuracy as it significantly contributes to the discharge if probing the SS pin.
24
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8.2 Typical Application
8.2.1 2-MHzSwitching Frequency, 9-V to 16-V Input, 5-V Output Buck Regulator, 3.3-V Output LDO
Regulator
This example details the design of a high-frequency switching regulator and linear regulator using ceramic output
capacitors.
VIN_LDO
VI = 9 V to 16 V
BOOT
Supply
VIN
C10
100 F
C8
2.2 F
SW
L1
3.3 H
C3
0.1 F
5V
D1
C4
47 F
R1
95.3 k
C5
47 F
FB1
EN1
R2
18.2 k
EN2
C1
R3 5.6 nF
28 k
RT/CLK
R4
52.3 k
COMP
C2
10 pF
SS
C6
3.3 nF
LDO_OUT
3.3 V
R5
95.3 k
GND
C7
10 F
FB2
R6
30.1 k
TPS65320C-Q1
PowerPAD
RST
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Figure 21. TPS65320C-Q1 Design Example With 2-MHz Switching Frequency
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Typical Application (continued)
8.2.1.1 Design Requirements
A few parameters must be known to begin the design process. The determination of these parameters is typically
at the system level. This example begins with the parameters listed in .
Table 3. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, VIN1
9 V to 16 V, nominal 12 V
Output voltage, VREG1 (buck regulator)
5 V ± 2%
Maximum output current, IO_max1
3.2 A
Minimum output current, IO_min1
0.01 A
Transient response, 0.01 A to 0.8 A
3%
Output ripple voltage
1%
Switching frequency, ƒSW
2 MHz
Output voltage, VREG2 (LDO regulator)
3.3 V ± 2%
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Switching Frequency Selection for the Buck Regulator
The first step is to decide on a switching frequency for the regulator. Typically, the user selects the highest
switching frequency possible because this produces the smallest solution size. The high switching frequency
allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a
lower frequency. The selectable switching frequency is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage, and the frequency-shift limitation.
Consider minimum on-time and frequency-shift protection as calculated with Equation 4 and Equation 5. To find
the maximum switching frequency for the regulator, select the lower value of the two results. Switching
frequencies higher than these values result in pulse skipping or the lack of overcurrent protection during a short
circuit. The typical minimum on-time, tON-min, is 100 ns for the TPS65320C-Q1 device. For this example, where
the output voltage is 5 V and the maximum input voltage is 16 V, use a switching frequency of 2000 kHz. Use
Equation 3 to calculate the timing resistance for a given switching frequency. The R4 resistor sets the switching
frequency. A 2-MHz switching frequency requires a 52.45-kΩ resistor (see R4 in Figure 21).
8.2.1.2.2 Output Inductor Selection for the Buck Regulator
Use Equation 23 to calculate the minimum value of the output inductor. The output capacitor filters the inductor
ripple current. Therefore, selecting high inductor-ripple currents impacts the selection of the output capacitor
because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple
current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines
can be used to select this value. KIND is a coefficient that represents the amount of inductor ripple current relative
to the maximum output current.
V max - VO
VO
LO min = I
´
IO ´ KIND
VI max ´ ƒS
(23)
For designs using low-ESR output capacitors such as ceramics, use a value as high as KIND = 0.3. When using
higher-ESR output capacitors, KIND = 0.2 yields better results. In a wide-input voltage regulator, selecting an
inductor ripple current on the larger side is best because it allows the inductor to still have a measurable ripple
current with the input voltage at a minimum.
26
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For this design example, use KIND = 0.3 and the minimum inductor value which is calculated as 2.24 µH. The
nearest standard value would be 2.7 µH. However, in order to support potentially lower switching frequencies or
lower ripple, 3.3 µH was chosen (see L1 in Figure 21). Use Equation 24 to calculate the inductor ripple current
(Iripple). For the output filter inductor, do not to exceed the RMS-current and saturation-current ratings. Use
Equation 25 and Equation 26 to calculate the RMS current (IL-RMS) and the peak inductor (IL-peak).
V ´ (VI max - VO )
Iripple = O
VI max ´ Lo ´ ƒS
(24)
IL -RMS = IO2 +
IL -peak = IO +
1
Iripple2
12
(25)
Iripple
2
(26)
For this design, the RMS inductor current is 3.21 A, the peak inductor current is 3.52 A, and the inductor ripple
current is 0.65 A. The selected inductor is a Coilcraft XAL4030-332MEB, which has a saturation-current rating of
5.5 A and an RMS-current rating of 5 A. As the equation set demonstrates, lower ripple current reduces the
output ripple voltage of the buck regulator but requires a larger value of inductance. Selecting higher ripple
currents increases the output ripple voltage of the buck regulator but allows for a lower inductance value.
8.2.1.2.3 Output Capacitor Selection for the Buck Regulator
Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines
the modulator pole, the output ripple voltage, and how the buck regulator responds to a large change in load
current. Select the output capacitance based on the most stringent of these three criteria. The desired response
to a large change in the load current is the first criterion. The output capacitor must supply the load with current
when the regulator cannot. This situation occurs if the desired hold-up times are present for the buck regulator. In
this case, the output capacitor must hold the output voltage above a certain level for a specified amount of time
after the input power is removed. The regulator is also temporarily unable to supply sufficient output current if a
large, fast increase occurs affecting the current requirements of the load, such as a transition from no load to full
load. The buck regulator usually requires two or more clock cycles for the control loop to notice the change in
load current and output voltage, and to adjust the duty cycle to react to the change. Size the output capacitor to
supply the extra current to the load until the control loop responds to the load change. The output capacitance
must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable
amount of droop in the output voltage. Use Equation 27 to calculate the minimum output capacitance required to
supply the difference in current.
2 ´ DIO
CO >
ƒS ´ DVO
where
•
•
•
ΔIO is the change in the buck-regulator output current
ƒS is the switching frequency of the buck regulator
ΔVO is the allowable change in the buck-regulator output voltage
(27)
For this example, the specified transient load response is a 3% change in VO for a load step from 0.01 A to 0.8
A. For this example, ΔIO = 0.8 – 0.01 = 0.79 A and ΔVO = 0.03 × 5 = 0.15 V. Using these numbers results in a
minimum capacitance of 5.27 µF. This value does not consider the ESR of the output capacitor in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be take into consideration.
The catch diode of the regulator cannot sink current. Therefore any stored energy in the inductor produces an
output-voltage overshoot when the load current rapidly decreases. Also, size the output capacitor to absorb the
energy stored in the inductor when transitioning from a high load current to a lower load current. The excess
energy that is stored in the output capacitor increases the voltage on the capacitor. Size the capacitor to maintain
the desired output voltage during these transient periods.
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Use Equation 28 to calculate the minimum capacitance to keep the output voltage overshoot to a desired value.
CO > LO ´
(IOH2 - IOL 2 )
(Vf 2 - Vi2 )
where
•
•
•
•
•
LO is the output inductance of the buck regulator
IOH is the output current of the buck regulator under heavy load
IOL is the output current of the buck regulator under light load
Vf is the final peak output voltage of the buck regulator
Vi is the initial capacitor voltage of the buck regulator
(28)
For this example, the worst-case load step is from 3.2 A to 0.01 A. The output voltage increases during this load
transition, and the stated maximum in the specification is 3% of the output voltage (see the Electrical
Characteristics table). This makes Vf = 1.03 × 5 = 5.15. Vi is the initial capacitor voltage, which is the nominal
output voltage of 5 V. Using these numbers in Equation 28 yields a minimum capacitance of 22 µF.
Equation 29 calculates the minimum output capacitance needed to meet the output ripple-voltage specification.
Equation 29 yields 0.8 µF.
1
1
CO >
´
8 ´ ƒS VO -ripple
IL -ripple
where
•
•
VO-ripple is the maximum allowable output ripple voltage of the buck regulator
IL-ripple is the inductor ripple current of the buck regulator
(29)
Use Equation 30 to calculate the maximum ESR required for the output capacitor to meet the output voltage
ripple specification. As a result of Equation 30, the ESR should be less than 80 mΩ.
VO -ripple
RESR <
IL -ripple
(30)
The most stringent criterion for the output capacitor is 22 µF of capacitance to keep the output voltage in
regulation during a load transient.
Factor in additional capacitance deratings for aging, temperature, and DC bias which increase this minimum
value. For this example, two 47-µF, 25-V ceramic capacitors are used (see C4 and C5 in Figure 21). Capacitors
generally have limits to the amount of ripple current they can handle without failing or producing excess heat.
Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the
root-mean-square (RMS) value of the maximum ripple current.
Use Equation 31 to calculate the RMS ripple current that the output capacitor must support. For this application,
Equation 31 yields 191 mA.
VO ´ (VI max - VO )
ICO(RMS) <
12 ´ VI max ´ LO ´ ƒS
(31)
8.2.1.2.4 Catch Diode Selection for the Buck Regulator
The TPS65320C-Q1 device requires an external catch diode between the SW pin and GND (see D1 in
Figure 21). The selected diode must have a reverse voltage rating equal to or greater than VImax. The peak
current rating of the diode must be greater than the maximum inductor current. The diode should also have a low
forward voltage. Schottky diodes are typically a good choice for the catch diode because of low forward voltage
of these diodes. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage is. Although the
design example has an input voltage up to 36 V, select a diode with a minimum of 40-V reverse voltage to allow
input voltage transients up to the rated voltage of the TPS65320C-Q1 device.
28
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For the example design, the selection of a Schottky diode is SL44-E3/57 based on the low forward voltage of this
diode. This diode is also available in a larger package size, which has better thermal characteristics. The typical
forward voltage of the SL44-E3/57 is 0.44 V.
Also, select a diode with an appropriate power rating. The diode conducts the output current during the off-time
of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the
output voltage, and the switching frequency. The output current during the off-time, multiplied by the forward
voltage of the diode, equals the conduction losses of the diode. At higher switching frequencies, consider the AC
losses of the diode. The AC losses of the diode are because the charging and discharging of the junction
capacitance and reverse recovery.
8.2.1.2.5 Input Capacitor Selection for the Buck Regulator
The TPS65320C-Q1 device requires a high-quality ceramic input decoupling capacitor (type X5R or X7R) of at
least 3 µF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance
includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input
voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the
TPS65320C-Q1 device. Use Equation 32 to calculate the input ripple current (ICI(RMS)).
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. Minimize the capacitance variations because of temperature by selecting a dielectric material that is
stable over temperature. Designers usually select X5R and X7R ceramic dielectrics for power regulator
capacitors because these capacitors have a high capacitance-to-volume ratio and are fairly stable over
temperature. Also, select the output capacitor with the DC bias taken into consideration. The capacitance value
of a capacitor decreases as the DC bias across a capacitor increases.
This design requires a capacitor with at least a 40-V voltage rating to support the maximum input voltage.
Common standard capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, 63V, or 100 V. For this
design example. The selection for this example is a 100-µF, 63-V bulk capacitance in parallel with a 2.2-µF
ceramic capacitor (see C8 and C10 in Figure 21).
ICI(RMS) = IO max ´
VO
(V min - VO )
´ I
VI min
VI min
(32)
The input-capacitance value determines the input ripple voltage of the regulator. Use Equation 33 to calculate the
input ripple voltage (ΔVI).
I max ´ 0.25
DVI = O
CI ´ ƒS
(33)
Using the design example values, IOmax = 3.2 A, CI = 100 µF, ƒS = 2000 kHz, yields an input ripple voltage of 4
mV and an RMS input ripple current of 1.59 A.
8.2.1.2.6 Soft-Start Capacitor Selection for the Buck Regulator
The soft-start capacitor determines the minimum amount of time required for the output voltage to reach the
nominal programmed value during power up which is useful if a load requires a controlled-voltage slew rate. This
feature is also useful if the output capacitance is large and requires large amounts of current to charge the
capacitor quickly to the output voltage level. The large currents required to charge the capacitor may make the
TPS65320C-Q1 device reach the current limit, or excessive current draw from the input power supply may cause
the input voltage rail to sag. Limiting the output voltage-slew rate solves both of these problems.
The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Use Equation 34 to calculate the minimum soft-start time, tss, required
to charge the output capacitor, CO, from 10% to 90% of the output voltage, VO, with an average load current of
Io(avg).
C ´ VO ´ 0.8
t ss > O
IO(avg)
(34)
In the example, to charge the effective output capacitance of 94 µF up to 5 V while allowing the average output
current to be 3.2 A requires a 0.118 ms soft-start time.
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When the soft-start time is known, use Equation 2 to calculate the soft-start capacitor. For the example circuit,
the soft-start time is not too critical because the output-capacitor value is 2 × 47 µF, which does not require much
current to charge to 5 V. The example circuit has the soft-start time set to an arbitrary value of 1 ms, which
requires a 3.125-nF soft-start capacitor. This design uses the next-larger standard value of 3.3 nF.
8.2.1.2.7 Bootstrap Capacitor Selection for the Buck Regulator
Connect a 0.1-µF ceramic capacitor between the BOOT and SW pins for proper operation. TI recommends using
a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage
rating.
8.2.1.2.8 Output Voltage and Feedback Resistor Selection for the Buck Regulator
The voltage divider of R1 and R2 sets the output voltage. For the design example, the selected value of R2 is
18.2 kΩ, and the calculated value of R1 is 95.3 kΩ. Because of current leakage of the FB1 pin, the current
flowing through the feedback network should be greater than 1 μA to maintain the output-voltage accuracy.
Selecting higher resistor values decreases the quiescent current and improves efficiency at low output currents,
but can introduce noise immunity problems.
8.2.1.2.9 Frequency Compensation Selection for the Buck Regulator
Several possible methods exist to design closed loop compensation for DC-DC converters. The method
presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the buck
regulator. Ignoring the slope compensation usually causes the actual crossover frequency to be lower than the
crossover frequency used in the calculations. This method assumes the crossover frequency is between the
modulator pole and the ESR zero, and that the ESR zero is at least 10 times greater than the modulator pole.
To begin, use Equation 35 to calculate the modulator pole, ƒP_mod, and Equation 36 to calculate the ESR zero,
ƒz_mod.
Im ax
1
ƒP _ mod =
=
2π ´ RL ´ CO 2π ´ VO ´ CO
(35)
ƒ Z _ mod =
1
2π ´ RESR ´ CO
(36)
Use Equation 37 and Equation 38 to calculate an estimate starting point for the crossover frequency, ƒCO, to
design the compensation.
ƒCO = ƒP _ mod ´ ƒ Z _ mod
ƒCO = ƒP _ mod ´
(37)
ƒS
2
(38)
For the example design, ƒP_mod is 1.08 kHz and ƒZ_mod is 564 kHz assuming an ESR of 3 mΩ. Equation 37 is the
geometric mean of the modulator pole and the ESR zero and Equation 38 is the mean of the modulator pole and
the switching frequency. Equation 37 yields 24.7 kHz and Equation 38 results 32.9 kHz. Use the lower value of
Equation 37 or Equation 38 for an initial crossover frequency.
For this example, the target ƒCO value is 24.7 kHz. Next, calculate the compensation components. Use a resistor
in series with a capacitor to create a compensating zero. A capacitor in parallel to these two components forms
the compensating pole.
The total loop gain, which consists of the product of the modulator gain, the feedback voltage-divider gain, and
the error amplifier gain at ƒCO equal to 1. Use Equation 39 to calculate the compensation resistor, R3 (see the
schematic in Figure 21).
æ 2π ´ ƒCO ´ CO
R3 = ç
ç
gmps
è
ö æ
ö
VO
÷´ç
÷ è Vref ´ gmea ø÷
ø
(39)
Assume the power-stage transconductance, gmps, is 10.5 S. The output voltage (VO), reference voltage (Vref),
and amplifier transconductance, (gmea) are 5 V, 0.8 V, and 310 μS, respectively. The calculated value for R3 is
28.01 kΩ. For this design, use a value of 28 kΩ for R3. Use Equation 40 to set the compensation zero to the
modulator pole frequency.
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C1 =
SLVSD50D – MARCH 2016 – REVISED JUNE 2017
1
2π ´ R3 ´ ƒP _ mod
(40)
Equation 38 yields 5.3 nF for compensating capacitor C1 (see the schematic in Figure 21). For this design, select
a value of 5.6 nF for C1.
To implement a compensation pole as needed, use an additional capacitor, C2, in parallel with the series
combination of R3 and C1. Use Equation 41 and Equation 42 to calculate the value of C2 and select the larger
resulting value to set the compensation pole. Type 2B compensation does not use C2 because it would demand
a low ESR of the output capacitor.
C ´ RESR
C2 = O
R3
(41)
1
C2 =
π ´ R3 ´ ƒS
(42)
8.2.1.2.10 LDO Regulator
Depending on the end application, use different values of external components can be used. To program the
output voltage, carefully select the feedback resistors, R5 and R6 (see the schematic in Figure 21). Using smaller
resistors results in higher current consumption, whereas using very large resistors impacts the sensitivity of the
regulator. Therefore selecting feedback resistors such that the sum of R5 and R6 is between 20 kΩ and 200 kΩ
is recommended.
If the desired regulated output voltage is 3.3 V on selecting R6, the value of R5 can be calculated. With Vref = 0.8
V (typical), VO = 3.3 V, and selecting R6 = 30.1 kΩ, the calculated value of R5 is 95.3 kΩ.
An output capacitor for the LDO regulator is required (see C10 in Figure 21) to prevent the output from
temporarily dropping down during fast load steps. TI recommends a low-ESR ceramic capacitor with dielectric of
type X5R or X7R. Additionally, a bypass capacitor can be connected at the output to decouple high-frequency
noise based on the requirements of the end application.
8.2.1.2.11 Power Dissipation
8.2.1.2.11.1 Power Dissipation Losses of the Buck Regulator
Use the following equations to calculate the power dissipation losses for the buck regulator. These losses are
applicable for continuous-conduction-mode (CCM) operation.
1. Conduction loss:
PCON = IO2 × rDS(on) × (VO / VI)
where
•
•
•
IO is the buck regulator output current
VO is the buck regulator output voltage
VI is the input voltage
(43)
2. Switching loss:
PSW = ½ × VI × IO × (tr + tf) × fS
where
•
•
•
tr is the FET switching rise time (tr maximum = 20 ns)
tf is the FET switching fall time (tf maximum = 20 ns)
ƒS is the switching frequency of the buck regulator
(44)
3. Gate drive loss:
PGate = Vdrive × Qg × ƒsw
where
•
•
Vdrive is the FET gate-drive voltage (typically Vdrive = 6 V)
Qg = 1 × 10–9 (nC, typical)
(45)
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8.2.1.2.12 Power Dissipation Losses of the LDO Regulator
PLDO = (VVIN_LDO – V(LDO_OUT)) × I(LDO_OUT)
(46)
8.2.1.2.13 Total Device Power Dissipation Losses and Junction Temperature
1. Supply loss:
PIC = VI × IQ-normal
(47)
2. Total power loss:
PTotal = PCON + PSW + PGate + PLDO + PIC
(48)
For a given operating ambient temperature TA:
TJ = TA + Rth × PTotal
where
•
•
•
•
TJ is the junction temperature in °C
TA is the ambient temperature in °C
Rth is the thermal resistance of package in (°C/W)
PTotal is the total power dissipation (W)
(49)
For a given maximum junction temperature TJ-max = 150°C, the allowed Total power dissipation is given as:
TA-max = TJ-max -Rth × PTotal
(50)
where
•
•
TA-max is the maximum ambient temperature in °C
TJ-max is the maximum junction temperature in °C
(51)
Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the Schottky
diode, and trace resistance that impact the overall efficiency of the regulator.
Figure 22 shows the thermal derating profile of the 14-pin HTSSOP Package With PowerPAD™ . It is important
to consider additional cooling strategies if necessary to maintain the junction temperature of the device below the
maximum junction temperature of 150 °C.
3
Power Dissipation (W)
2.5
2
1.5
1
0.5
0
0
25
50
75
100
125
150
Ambient Temperature (qC)
Figure 22. Thermal Derating Profile ofTPS65320C-Q1 in 14-pin HTSSOP Package With PowerPAD
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8.2.1.3 Application Curves
EN1
Buck_out
200 mV/div
Buck_out
5 V/div
SS
1 V/div
I_load
1 V/div
200 mA/div
I_load
1 A/div
100 µs/div
ƒS = 2 MHz
Buck Output Voltage = 5 V
1 ms/div
Figure 23. Buck Regulator Output at Load Transient
(200 mA to 3 A)
Figure 24. Buck-Regulator Startup Operation
EN2
5 V/div
200 mA/div
I_load
50 mV/div
LDO_out
LDO_out
2 V/div
I_load
200 mA/div
400 µs/div
10 µs/div
Figure 25. LDO Regulator Startup Operation
V(LDO_OUT) = 3.3 V
Figure 26. LDO-Regulator Output at Load Transient
(50 mA to 300 mA)
100
90
80
Efficiency (%)
70
60
50
40
30
20
fS = 300
kHz
fsw
= 300kHz
10
ffsw
= MHz
2MHz
S= 2
0
0.0
1.0
2.0
3.0
4.0
Output Current (A)
C001
Figure 27. Buck Efficiency Versus Output Current
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9 Power Supply Recommendations
The buck regulator is designed to operate from an input voltage supply range between 3.6 V and 36 V. The
linear regulator is designed to operate from an input supply voltage up to 20 V. Both input supplies must be well
regulated. If the input supply connected to the VIN pin is located more than a few inches from the TPS65320CQ1 converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 100 μF is a typical choice.
10 Layout
10.1 Layout Guidelines
TI recommends the guidelines that follow for PCB layout of the TPS65320C-Q1 device.
• Inductor
Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors can also be used, however,
these inductors must have low-EMI characteristics and be located away from the low-power traces and
components in the circuit.
• Input Filter Capacitors
Locate input ceramic filter capacitors close to the VIN pin. TI recommends surface-mount capacitors to
minimize lead length and reduce noise coupling.
• Feedback
Route the feedback trace for minimum interaction with any noise sources associated with the switching
components. TI recommends to place the inductor away from the feedback trace to prevent creating an EMI
noise source.
• Traces and Ground Plane
All power (high-current) traces must be as thick and short as possible. The inductor and output capacitors
must be as close to each other as possible to reduce EMI radiated by the power traces because of high
switching currents. In a two-sided PCB, TI recommends using ground planes on both sides of the PCB to
help reduce noise and ground loop errors. The ground connection for the input capacitors, output capacitors,
and device ground should connect to this ground plane, where the connection between input capacitors and
the catch-diode is the most critical. In a multi-layer PCB, the ground plane separates the power plane (where
high switching currents and components are) from the signal plane (where the feedback trace and
components are) for improved performance. Also, arrange the components such that the switching-current
loops curl in the same direction. Place the high-current components such that during conduction the current
path is in the same direction. This placement prevents magnetic field reversal caused by the traces between
the two half-cycles, and helps reduce radiated EMI.
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10.2 Layout Example
Buck Regulator
Output Capacitor
Power
Ground
VI
Input Capacitors
Buck
Regulator
BOOT
Capacitor
BOOT
LDO
Regulator
Resistor
Feedback
Network
SW
VIN
2
13
GND
VIN_LDO
3
12
COMP
LDO_OUT
4
11
FB1
FB2
5
10
SS
RST
6
9
RT/CLK
EN2
7
8
EN1
Analog Ground Trace
Buck
Regulator
Resistor
Feedback
Network
Buck Regulator
Soft-Start Capacitor
Buck Regulator Switching
Frequency Resistor
Ground Trace
LDO Regulator
Output Capacitor
14
Analog
VO(LDO)
Buck Regulator
Output Inductor
Buck Regulator
Catch Diode
1
Exposed
Thermal Pad
Area
VO(BUCK)
Buck Regulator
Compensation Components
Analog Ground Trace
Figure 28. TPS65320C-Q1 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• CISPR25 Radiated Emissions Using TPS65320-Q1
• Interfacing TPS57xxx-Q1,TPS65320-Q1 Family, and TPS65321-Q1 Devices With Low Impendence External
Clock Drivers
• Low Quiescent Current with Asynchronous Buck Converters at High Temperatures
• TPS65320-Q1 and TPS65320C-Q1 Design Checklist
• TPS65320C-Q1 Auto-Source Feature
• TPS65320C-Q1-EVM User Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following packaging information and addendum reflect the most current data available for the designated
devices. This data is subject to change without notice and revision of this document.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65320CQPWPRQ1
NRND
HTSSOP
PWP
14
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
T65320C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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