TPS65381QDAPRQ1

Product Folder Order Now Technical Documents Tools & Software Support & Community TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 TPS65381-Q1 Multirail Power Supply for Microcontrollers in Safety-Relevant Applications Not Recommended for New Designs 1 Device Overview 1.1 Features 1 • Qualified for Automotive Applications • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B • Multirail Power Supply Supporting Among Others – TI Hercules™ TMS570, C2000™, and Various Functional-Safety Architecture Microcontrollers • Supply Rails – Input voltage range: – 5.8 V to 36 V (CAN, I/O, MCU Core, and Sensor-Supply Regulators Functional) – 4.5 V to 5.8 V (3.3 V I/O and MCU Core Regulators Functional) – 6-V Asynchronous Switch Mode Preregulator With Internal FET, 1.3-A Output Current – 5-V (CAN) Supply Voltage, Linear Regulator With Internal FET, 300-mA Output Current – 3.3-V or 5-V (MCU I/O) Voltage, Linear Regulator With Internal FET, 300-mA Output Current – 0.8-V to 3.3-V Adjustable (MCU Core Voltage), Linear Regulator Controller With External FET – 3.3-V to 9.5-V Adjustable Sensor Supply: Linear Tracking Regulator With Internal FET, 100-mA Output Current, and Protection Against Short-toSupply and Short-to-Ground – Charge Pump: Typically 12 V Above Battery Voltage • Power Supply and System Monitoring – Independent Undervoltage and Overvoltage Monitoring on All Regulator Outputs, Battery Voltage, and Internal Supplies – Independent Voltage References for Regulator References and Voltage Monitoring. VoltageMonitoring Circuitry With Independent Bandgap Reference and Separate Supply Input Pin • • • • • – Self-Check on all Voltage Monitoring (Automatic During Power-Up and After Power-Up Initiated by External MCU) – All Supplies With Internal FETs Protected With Current-Limit and Overtemperature Shutdown Microcontroller (MCU) Interface – Watchdog: Trigger Mode (OPEN/CLOSE Window) or Question and Answer Mode – MCU Error-Signal Monitor For Lock-Step DualCore MCUs Including Hercules™ TMS570, C2000™, and Various Functional-Safety Architecture MCUs Using Pulse-Width Modulation (PWM) Error Output – DIAGNOSTIC State for Performing Device SelfTests, Diagnostics, and External Interconnect Checks – SAFE State for Device and System Protection on Error Event Detection – Clock Monitor for Internal Oscillator – Self-Tests for Analog- and Digital-Critical Circuits Executed With Every Device Power Up or Activated by MCU in DIAGNOSTIC State – CRC on Nonvolatile Memory, Device and Configuration Registers – Reset Circuit and Output Pin for MCU – Diagnostic Output Pin Allowing MCU to Observe Through a Multiplexer Internal Analog and Digital Signals of the Device Serial Peripheral Interface (SPI) – Configuration Registers – Watchdog Question and Answers – Diagnostic Status Readout – Compliant With 3.3-V and 5-V Logic Levels Enable Drive Output for Disabling Safing-Path or External Power-Stages on Detected SystemFailure Wakeup Through IGNITION Pin or CAN WAKEUP Pin Package: 32-Pin HTSSOP PowerPAD™ IC Package 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 1.2 • www.ti.com Applications Safety Automotive Applications – Power Steering: Electrical Power Steering (EPS) and Electro Hydraulic Power Steering (EHPS) – Braking: Anti-Lock Brake System (ABS), Electronic Stability Control (ESC), and Electric Parking Brake – Advanced Driver Assistance Systems (ADAS) – Suspension 1.3 • Industrial Safety Applications – Safety Programmable-Logic Controllers (PLCs) – Safety I/O Control Modules – Test and Measurement – Railway and Subway Signal Control and Safety Modules – Elevator and Escalator Safety Control – Wind Turbine Control Description The TPS65381-Q1 device is a multirail power supply designed to supply microcontrollers (MCUs) in safety-relevant applications, such as those found in automotive and industrial markets. The device supports Texas Instruments’ Hercules™ TMS570 MCU and C2000™ MCU families, and various other MCUs with dual-core lockstep (LS) or loosely-coupled architectures (LC). The TPS65381-Q1 device integrates multiple supply rails to power the MCU, controller area network (CAN), or FlexRay, and an external sensor. An asynchronous-buck switch-mode power-supply converter with an internal FET converts the input supply (battery) voltage to a 6-V preregulator output. This 6-V preregulator supplies the other regulators. The device supports wakeup from IGNITION or wakeup from the CAN transceiver. The integrated, fixed 5-V linear regulator with internal FET can be used for a CAN or FlexRay transceiver supply for example. A second linear regulator, also with an internal FET, regulates to a selectable 5-V or 3.3-V output which, for example, can be use for the MCU I/O voltage. The TPS65381-Q1 device includes an adjustable linear-regulator controller, requiring an external FET and resistor divider, that regulates to an adjustable voltage of between 0.8 V and 3.3 V which may be used for the MCU core supply. The integrated sensor supply can be run in tracking mode or adjustable output mode and includes shortto-ground and short-to-battery protection. Therefore, this regulator can power a sensor outside the module or electronic control unit (ECU). The integrated charge pump provides overdrive voltage for the internal regulators. The charge pump can also be used in a reverse-battery protection circuit by using the charge-pump output to control an external NMOS transistor. This solution allows for a lower minimum-battery-voltage operation compared to a traditional reverse-battery blocking diode when the device must be operational at the lowest possible supply voltages. The device monitors undervoltage and overvoltage on all regulator outputs, battery voltage, and internal supply rails. A second bandgap reference, independent from the main bandgap reference, is used for the undervoltage and overvoltage monitoring, to avoid any drifts in the main bandgap reference from being undetected. In addition, regulator current-limits and temperature protections are implemented. The TPS65381-Q1 device has monitoring and protection functions, which include the following: watchdog with trigger and question and answer modes, MCU error-signal monitor, clock monitoring on internal oscillators, self-check on the clock monitor, cyclic redundancy check (CRC) on nonvolatile memory, a diagnostic output pin allowing the MCU to observe internal analog and digital signals of the device, a reset circuit and output pin for the MCU, and an enable drive output to disable the safing-path or external-power stages on detected faults. A built-in self-test (BIST) monitors the device functionality automatically at power-up. A dedicated DIAGNOSTIC state allows the MCU to check TPS65381-Q1 monitoring and protection functions. The TPS65381-Q1 device is offered in a 32-pin HTSSOP PowerPAD package. 2 Device Overview Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Device Information (1) PART NUMBER PACKAGE TPS65381-Q1 (1) 1.4 HTSSOP (32) BODY SIZE (NOM) 11.00 mm × 6.20 mm For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Diagram 1 VBAT_SAFING 2 VCP SEL_VDD3/5 31 3 CP1 IGN 30 4 CP2 VBATP 29 5 PGND SDN6 28 6 NRES VDD6 27 7 DIAG_OUT 8 NCS 9 SDI 10 SDO 11 SCLK 12 RSTEXT 13 ERROR/WDI 14 CANWU 15 VSFB1 16 VSIN ENDRV 32 VDD6 VDD6 ESR VDD1_G 26 PGND 25 VDD1_SENSE 24 GND 23 VDDIO 22 VDD3/5 21 VDD5 20 GND 19 VTRACK1 18 VSOUT1 17 Copyright © 2016, Texas Instruments Incorporated Figure 1-1. Typical Application Diagram Device Overview Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 3 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Table of Contents 1 2 3 4 Device Overview ......................................... 1 5.4 Device Functional Modes 1.1 Features .............................................. 1 5.5 Register Maps ....................................... 92 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 6.1 Application Information 1.4 Typical Application Diagram .......................... 3 6.2 Typical Application ................................. 116 6.3 System Examples .................................. 124 Revision History ......................................... 4 Pin Configuration and Functions ................... 27 Specifications ........................................... 29 4.1 5 7 8 Absolute Maximum Ratings ......................... 29 ........................................ 4.3 Recommended Operating Conditions ............... 4.4 Thermal Information ................................. 4.5 Electrical Characteristics ............................ 4.6 Timing Requirements ............................... 4.7 Switching Characteristics ........................... 4.8 Typical Characteristics .............................. Detailed Description ................................... 5.1 Overview ............................................ 5.2 Functional Block Diagram ........................... 5.3 Feature Description ................................. 4.2 6 ESD Ratings 29 30 31 9 ........................... 45 Application and Implementation ................... 116 ............................ 116 Power Supply Recommendations ................. 129 Layout ................................................... 129 8.1 Layout Guidelines .................................. 129 8.2 Layout Example .................................... 131 8.3 Power Dissipation and Thermal Considerations ... 132 Device and Documentation Support .............. 134 32 9.1 Device Support..................................... 134 36 9.2 Documentation Support ............................ 134 37 9.3 Receiving Notification of Documentation Updates. 134 38 9.4 Community Resources............................. 134 39 9.5 Trademarks ........................................ 134 39 9.6 Electrostatic Discharge Caution 39 9.7 Glossary............................................ 135 40 ................... 135 10 Mechanical, Packaging, and Orderable Information ............................................. 135 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (May 2016) to Revision G • • • • • • • • • • • • • • • • 4 Page Changed the Features list for Supply rails to show output current instead of current limit. Added general current limit bullet in the FEATURES list ................................................................................................... 1 Added acronym definitions .......................................................................................................... 1 Changed recommended maximum voltage for VBATP and VBAT_SAFING in the Recommended Operating Conditions table ...................................................................................................................... 8 Changed the PIN Function table descriptions to clarify device operation ................................................... 27 Changed the max value for the charge-pump voltages from 52 V to lesser of VBATP + 16V or 52 V with footnote in the ABSOLUTE MAXIMUM RATINGS table ....................................................................... 29 Changed M1.12 and M1.13 Sensor supply feedback and supply voltage by combining in M1.12 with conditions of use for the Sensor supply output and feedback voltage to match how the sensor supply is used. Changed the maximum to 18 V in the ABSOLUTE MAXIMUM RATINGS table ............................................................ 29 Deleted M1.13 Sensor supply output voltage by combining with M1.12 in the ABSOLUTE MAXIMUM RATINGS table ................................................................................................................................... 29 Changed the table note for Absolute Maximum Ratings ...................................................................... 29 Changed changed recommended operating condition descriptions for R1.1, R1.2 and R1.3 to make the operation of device more clear in the Recommended Operating Conditions ............................................... 30 Deleted recommended operating condition R1.3a and R1.3b, VBAT_SAFING impact to device operation was included in R1.2 and R1.3 to make the operation of device more clear in the Recommended Operating Conditions 30 Changed link formats throughout document ..................................................................................... 30 Changed recommended maximum voltage for VBATP and VBAT_SAFING in the Recommended Operating Conditions table ..................................................................................................................... 30 Changed the Thermal Metric table and Derating Profile for Power Dissipation Based on High-K JEDEC PCB in the Thermal Information section. .................................................................................................. 31 Changed application report link ................................................................................................... 31 Changed the Derating Profile for the Power Dissipation in the Thermal Information table and the Power Dissipation and Thermal Considerations section ............................................................................... 31 Deleted R1.3b from the operating conditions in the Electrical Characteristics section since VBAT_SAFING condition R1.3b was merged with R1.2 in the Recommended Operating Conditions, Timing Requirements and Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Switching Characteristics sections ............................................................................................... Changed VDD6, POS 1.1 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS table .... Deleted Hysteresis parameter from TprotVDD6 (POS 1.7) in the ELECTRICAL CHARACTERISTICS table. ........... Changed VDD5, POS 2.1 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS table .... Changed POS 2.3 test condition to Load step 20% to 80% in 5 µs, with CVDD5 = 5 µF for VDD5 output voltage dynamic parameter in the Electrical Characteristics table ..................................................................... Changed PSRR to > 40 dB typical n the Electrical Characteristics for parameter 2.6 ..................................... Deleted Hysteresis parameter from TprotVDD5 (POS 2.13) in the ELECTRICAL CHARACTERISTICS table. ......... Changed all references of VDD3_5 to VDD3/5 for consistency in the datasheet .......................................... Added clarification on VDD6 current limit and duty cycle in the Electrical Characteristics section ....................... Added clarification on IVDD5_limit current limit in the Electrical Characteristics section ...................................... Changed VDD3/5, POS 3.1 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS table .. Changed POS 3.3 into 3.3a for 3.3 V setting and 3.3v for 5 V setting for VDD3/5 output voltage dynamic parameter in the Electrical Characteristics table ................................................................................ Changed POS 3.3a and 3.3b test condition to Load step 20% to 80% in 5 µs, with CVDD3/5 = 5 µF for VDD3/5 output voltage dynamic parameter in the Electrical Characteristics table ................................................... Changed the minimum for POS 3.3a from 3.17 V to 3.15 V, VDD3/5 output voltage dynamic parameter in the Electrical Characteristics table..................................................................................................... Changed PSRR to > 40 dB typical n the Electrical Characteristics for parameter 3.6 ..................................... Deleted Hysteresis parameter from TprotVDD3/5 (POS 3.13) in the ELECTRICAL CHARACTERISTICS table. ........ Changed MAX value of VDD1SENSE(4.2) from 0.816 mV to 0.808 mV in the Electrical Characteristics table .......... Changed VDD1SENSE POS 4.2 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS table ................................................................................................................................... Changed VDD1dyn, POS 4.7, to typical due to dependency on external FET choice in the Electrical Characteristics table ............................................................................................................... Changed the VDD1max, POS 4.8, to specific VDD1 output voltage range for test condition in the Electrical Characteristics table ............................................................................................................... Changed PSRR to > 40 dB typical n the Electrical Characteristics for parameter 4.9 ..................................... Added clarification on IVDD3/5 load current at power up in the Electrical Characteristics section .......................... Added clarification on IVDD3/5_limit current limits in the Electrical Characteristics section ................................... Changed MVVSOUT1 min and max values from –25 and 25 to –35 and 35 in the ELECTRICAL CHARACTERISTICS table ......................................................................................................... Changed VSFB1, POS 5.3 to only volts as units for consistency in the ELECTRICAL CHARACTERISTICS table... Changed Test Condition and PSRR to > 40 dB typical sensor supply to clarify the test in the Electrical Characteristics for parameters 5.6 ................................................................................................ Changed POS 5.11, VSOUT1SH, for clarity of condition for output short circuit voltage range and changed maximum voltage to 18 V in the ELECTRICAL CHARACTERISTICS table ................................................ Deleted Hysteresis parameter from TprotVSOUT1 (POS 5.13) in the ELECTRICAL CHARACTERISTICS table. ....... Changed IVSOUT1_limit, POS 5.14 minimum from 100 mA to 120 mA in the ELECTRICAL CHARACTERISTICS table Added clarification on IVSOUT1 load current and power dissipation in the Electrical Characteristics section ............. Changed min value for VDD3/5_UVhead to 155 mV from 170 mV for 3.3-V setting in the ELECTRICAL CHARACTERISTICS table POS 6.13 ............................................................................................ Changed VDD_UV POS 6.16 units from ratio to mV for consistency in the ELECTRICAL CHARACTERISTICS table ................................................................................................................................... Changed VDD1_OV POS 6.17 MIN from 824 mV to 816 mV in the ELECTRICAL CHARACTERISTICS table ....... Changed VDD1_OV POS 6.17 units from ratio to mV for consistency in the ELECTRICAL CHARACTERISTICS table ................................................................................................................................... Deleted VSOUT1_UV hysteresis parameter (typical), POS 6.19a in the ELECTRICAL CHARACTERISTICS table. . Deleted VSOUT1_OV hysteresis parameter (typical), POS 6.20a in the ELECTRICAL CHARACTERISTICS table. . Changed I_IGN_rev parameter (7.4), -1, from MAX to MIN to match polarity in the ELECTRICAL CHARACTERISTICS table ........................................................................................................ Changed I_CAN_rev parameter (7.8), -1, from MAX to MIN to match polarity in the ELECTRICAL CHARACTERISTICS table ........................................................................................................ Added clarification to POS 10.1, 10.2 and 10.3 by using pin names in parameter field instead of footnote and adding SEL_VDD3/5 pin to 10.1 and 10.2 in the ELECTRICAL CHARACTERISTICS table ............................ Changed tdelayVDD5 max from 2.5 ms to 5 ms in the Timing Requirements table ........................................... Changed tdelayVDD3/5 max from 2.5 ms to 5 ms in the Timing Requirements table ......................................... Changed tdelayVDD1 max from 2.5 ms to 5 ms in the Timing Requirements table ........................................... Changed VBATP_deglitch minimum from 200 µs to 180 µs and maximum from 280 µs to 260 µs in the Timing Requirements table for POS 6.7................................................................................................... Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 32 32 32 32 32 32 32 32 32 32 33 33 33 33 33 33 33 33 33 33 33 33 33 34 34 34 34 34 34 34 35 35 35 35 35 35 35 35 36 36 36 36 36 5 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 6 www.ti.com Changed minimum for tWD_pulse in the ELECTRICAL CHARACTERISTICS table to 14.25 µs from 28 µs .............. Deleted tERROR_WDI_deglitch in the ELECTRICAL CHARACTERISTICS µs ..................................................... Changed min value for thigh(13.3) to 85.7 ns in the ELECTRICAL CHARACTERISTICS table. ......................... Changed format of graph .......................................................................................................... Added clarification of operation in the VDD6 Buck Switch Mode Power Supply section ................................. Added a note to the VSOUT1 register clarifying VSOUT1_EN through RESET state in the VSOUT1 Linear Regulator section .................................................................................................................... Added note in the Wake-Up section to not send WR_CAN_STBY command while CANWU and/or IGN are still high. ................................................................................................................................... Changed WDT_FAIL_CNT and WD_FAIL_CNT to WD_FAIL_CNT[2:0] throughout document ......................... Changed section heading levels from 5.4.1.1 through 5.4.1.20............................................................... Changed the VCP17_OV impact on device behavior in the Voltage Monitoring Overview table and the Internal Errors Signals table. ................................................................................................................ Changed the VCP12_OV the impact on device behavior in the Voltage Monitoring Overview table and the Internal Errors Signals table. ...................................................................................................... Changed the MAIN_BG and VMON_BG UV and OV impact on device behavior in the Voltage Monitoring Overview table and the Internal Errors Signals table. ......................................................................... Changed all _UVN Signal Names in the Internal Error Signals table and Digital MUX section to Nxxx_UV for consistency in datasheet for inverted logic signal names with N at the beginning of the name. ......................... Changed the signal name from VCP_OV to VCP17_OV for D1.7 in the Internal Error Signals table. Also changed the device state from Not changed for NRES and ENDRV to LOW, and State to STANDBY ................ Changed the max deglitch for VDD5_OT, VDD3/5_OT and VSOUT1_OT to 64us in the Internal Error Signals table .................................................................................................................................. Changed the naming convention of EN_VDD5_OT and EN_VDD3/5_OT to NMASK_VDD5_OT and NMASK_VDD3/5_OT to clarify option of these configuration bits throughout the datasheet ............................ Changed the description of VDD5_OT in the Internal Error Signals table for clarity ...................................... Changed the VMON_TRIM_ERR deglitch time minimum from 15 to 5 µs and maximum from 30 to 10 µs in the Internal Error Signals table ........................................................................................................ Changed the VMON_TRIM_ERR device state when flag is set to NRES = LOW from not changed, ENDRV = LOW from not changed and Device State to STANDBY from not changed in the Internal Error Signals table ....... Added clarification footnote to VDD5_CL internal signal in the Internal Error Signals table ............................. Changed Analog BIST Run States diagram for to clarify operation in the Analog Built-In Self-Test section ........... Changed ABIST_UVOV_ERR and ABIST_OV_UV to ABIST_ERR throughout document ............................... Added notes to clarify considerations needed if a manual run of LBIST is done in DIAGNOSTIC or ACTIVE state in the Logic Built-In Self-Test (LBIST) section................................................................................... Added clarification in the Analog Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) sections to clarify operation ..................................................................................................................... Changed paragraphs for VSOUT1, VDD6 and VDD3/5 overtemperature and current limit in the Junction Temperature Monitoring and Current Limiting section to clarify device operation .......................................... Changed the descriptions in the Overtemperature and Overcurrent Protection Overview table to clarify device operation and made naming for thermal shutdown consistent to overtemperature ....................................... Changed Section title to Diagnostic MUX and Diagnostic Output Pin (DIAG_OUT) ....................................... Added clarity to the DIAG_OUT description in the Diagnostic Output Pin DIAG_OUT section........................... Added clarification to the SPI Interface Note for the use of the SPI in a bus while DIAG_OUT MUX is enabled in the Diagnostic Output Pin DIAG_OUT section .................................................................................. Changed values and clarity of AMUX operation and added minimum output resistance in the Analog MUX Selection table ....................................................................................................................... Changed WDT_ signal names to WD_, WD_RES_EN toWD_RST_EN, NMASK_VDD1_OV to NMASK_VDD1_UV_OV, and EN_DRV to ENDRV throughout document .................................................. Changed NRST_EXT_IN to NRES_EXT_IN for consistency with pin name ................................................ Changed WDI/Error to Error/WDI throughout document ....................................................................... Changed the Watchdog Question (Token) Generation image in the Watchdog Timer Configuration for Question and Answer Configuration section ................................................................................................ Changed Figure for Watchdog Answer Calculation in the Question (Token) Generation section to remove FDBK[3:0] impact on Answer-x byte calculation ................................................................................ Changed TOKEN_ERR bit name to ANSWER_ERR to more accurately describe the error the bit indicates throughout the datasheet .......................................................................................................... Changed SEQ_ERR status bit in Table WD_STATUS Bits Versus Possible Watchdog Sequence Events section ... Added a note to clarify impact of changing SAFETY_ERR_PWM_L or SAFETY_ERR_PWM_H while the MCU ESM is running in the MCU Error Signal Monitor (MCU ESM) section ...................................................... Revision History 37 37 37 38 40 43 43 45 47 48 48 48 49 49 50 50 50 50 50 50 52 52 53 54 54 55 56 56 56 57 58 58 61 70 71 72 74 75 Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Added a note to clarify MCU ESM diagnostics in the MCU Error Signal Monitor (MCU ESM) section .................. 76 Added clarification in the MCU Error Signal Monitor (MCU ESM) section................................................... 76 Added clarification for the LOW minimum and maximum duration time for the MCU ESM in the TMS570 Mode section ................................................................................................................................ 76 Changed the time range for HIGH and LOW pulse duration in PWM Mode section from 5 µs to 15 µs (minimum) and 1.28 ms to 3.8 ms (maximum) for consistency along with additional clarifications of operation .................... 78 Added clarification for HIGH and LOW pulse register minimum and maximum pulse timing for the MCU ESM in the PWM Mode section ............................................................................................................. 78 Added a note to clarify MCU ESM to MCU synchronization in the MCU Error Signal Monitor (MCU ESM) PWM Mode section ......................................................................................................................... 79 Added note to clarify uncleared CFG_CRC_ERR impact to state diagram during DIAGNOSTIC state in the list of steps in the Device Configuration Register Protection section ................................................................ 83 Changed the Reset and Enable Circuit image to clarify operation ........................................................... 84 Changed section title from Device Controller State Diagram to Device Operating States and clarified device operating states operation ......................................................................................................... 86 Changed the STANDBY, RESET, DIAGNOSTIC, ACTIVE and SAFE state text descriptions in their sections to clarify device operation. ............................................................................................................ 87 Added clarification in the RESET STATE list .................................................................................... 87 Added clarification on BIST running on exit of RESET State to the RESET STATE section ............................. 88 Added note to clarify considerations needed if a manual run of LBIST is done in the DIAGNOSTIC state in the DIAGNOSTIC state section ........................................................................................................ 89 Added note to clarify considerations needed if a manual run of LBIST is done in the ACTIVE state in the ACTIVE state section ............................................................................................................... 90 Added note to clarify SAFE state time-out possible state transitions due to the SAFE state time-out in the SAFE state section.......................................................................................................................... 91 Added the Power on Reset (NPOR) section to clarify device operation. .................................................... 91 Changed the STAT[2] and STAT[0] descriptions for SPI errors in the Device Status Flag Byte Response table...... 93 Added note to explain additional SPI diagnostics in the Device Status Flag Byte Response section ................... 93 Added SPI Register Write Access Lock (SW_LOCK command) section in the Register Map section ................. 94 Added clarification on which registers are re-initialized to default values after LBIST run in Register Map section .. 95 Added clarification to WR_CAN_STBY that this command is only valid with data 00h in the SPI Command Table .. 95 Deleted note "SPI WR update can occur only in the DIAGNOSTIC and ACTIVE states" for WR_SAFETY_BIST_CTRL command in the SPI Command Table .......................................................... 95 Changed SAFE_CFG_CRC to SAFETY_CFG_CRC throughout the datasheet for consistency of the register name ................................................................................................................................. 96 Changed register bit descriptions in the DEV_CFG2 Register table to clarify device operation ......................... 99 Added clarification on VDD5_UV operation when VDD5_EN = 0 in the VMON_STAT_2 Register .................... 101 Added clarity to note on VDD5_ILIM bit description in the SAFETY_STAT_1 Register table ........................... 102 Changed the D[5] NRES_ERR, LBIST_ERR, ABIST_ERR, LBIST_RUN and ABIST_RUN register descriptions in SAFETY_STAT_3 Register .................................................................................................... 104 Added to the NRES_ERR description in the SAFETY_STAT_3 Register table ........................................... 104 Changed the SPI_ERR[1:0] description in the SAFETY_STAT_4 Register table ......................................... 105 Changed the LOCLK description in the SAFETY_STAT_4 Register table................................................. 105 Changed MCU_ERR bit description inSAFETY_STAT_4 Register table .................................................. 105 Changed WD_ERR bit and NRES_ERR bit description inSAFETY_STAT_4 Register table to clarify operation..... 105 Deleted note "Write update can only occur in the DIAGNOSTIC and ACTIVE states." for WR_SAFETY_BIST_CTRL command in the SAFETY _BIST_CTRL Register ............................................ 107 Changed SAFETY_STATUS_2 to SAFETY_STAT_2 for consistency in the datasheet ................................ 107 Changed NO_ERROR bit description to improve clarity in the SAFETY_CHECK_CTRL Register table ............. 108 Changed ERROR_PIN_FAIL bit description in the SAFETY_ERR_STAT Register table ............................... 110 Changed to clarity the WD_FAIL bit description in the SAFETY_ERR_STAT Register table ........................... 110 Changed ERR_CNT to DEV_ERR_CNT[3:0] throughout datasheet for consistency in naming. ....................... 111 Added clarification on the TOKEN_SEED[3:0] to the description in the WD_TOKEN_FDBCK Register table ....... 113 Changed WD_FAIL_TH description in the WDT_TOKEN_VALUE Register table for consistency ..................... 114 Changed added clarification on clearing of the ANSWER_ERR bit in the WD_STATUS Register table ............. 114 Deleted "This bit is set to 1 when switching between the Trigger and Q&A Mode" and added clarification on how to clear the WD_CFG_CHG bit description in the WD_STATUS Register table ......................................... 114 Changed TIME_OUT bit description in the WD_STATUS Register table to clarify how the bit is cleared. ........... 114 Added ANSWER_EARLY bit operation during trigger mode to the WD_STATUS Register table ..................... 114 Changed the description of VDD_EN in the SENS_CTRL Register table ................................................. 115 Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 7 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 • • • • • • • • • • • • www.ti.com Changed the description of VSOUT1_EN in the SENS_CTRL Register table ............................................ Clarified capacitors, resistor tolerance impact on regulation and monitoring in the Typical Application Diagram .... Clarified resistor tolerance impact on regulation and monitoring in the VDD1 Linear Controller Section .............. Clarified resistor tolerance impact on regulation and monitoring in the Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 6-V Output Tracking VDD3/5 In 3.3-V Mode Section.................................. Clarified resistor tolerance impact on regulation and monitoring in the Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 9-V Output Tracking to 5-V Input from VDD5 Section................................. Clarified resistor tolerance impact on regulation and monitoring in the Alternative Use for VSOUT1 Tracking Linear Regulator, Configured in Non-tracking Mode Providing a 4.5-V Output Section .................................. Changed and clarified the System Examples drawings ...................................................................... Changed and clarified the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Q&A Mode flowchart .............................................................................................................. Changed and clarified the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Trigger Mode flowchart............................................................................................................ Added Power Dissipation and Thermal Considerations in the Layout section ............................................ Added Receiving Notification of Documentation Updates section .......................................................... Changed the Electrostatic Discharge Caution statement..................................................................... Changes from Revision E (July 2015) to Revision F • • • • • • • • • • • • • • • • • • • (1) 8 115 117 119 121 122 123 124 127 128 132 134 134 Page Added clarity to the PIN Function table descriptions ........................................................................... Added clarification in Recommended Operating Conditions that GND = PGND ........................................... Changed (1)maximum VBAT_SAFING to 36 V in the Recommended Operating Conditions table for parameter 1.3a to be consistent with VBATP ................................................................................................ Added VBAT_SAFING input supply voltage range for normal operation RECOMMENDED OPERATING CONDITIONS table ................................................................................................................. Added clarification in statement for the ELECTRICAL CHARACTERISTICS table by adding VBAT_SAFING recommended operating range in addition to VBATP recommended operating range .................................... Changed description of parameter from Test Condition column to a footnote on the parameter in Electrical Characteristics table for parameters 1.2, 1.7, 2.1, 2.13, 3.1, 3.2, 3.13, 4.2, 5.1, 5.2, 5.3, 5.13, 6.4, 6.5, 6.7, 6.22, 6.23 ................................................................................................................................... Added clarification on direct loading of VDD6 in the IVDD6 Electrical Characteristics table ................................ Changed the Test Condition column to parameter description the ELECTRICAL CHARACTERISTICS table for 2.2, 3.1, 3.2, 5.1, 5.3a, 5.4, 9.3 .................................................................................................... Added clarification on resistor divider on regulation tolerance of VDD1 in the VDD1 section of the Electrical Characteristics table ................................................................................................................ Deleted test condition from TJ the Electrical Characteristics table for 5.5 because it is same as overall electrical characteristics table ................................................................................................................ Changed Test Condition for input to sensor supply to VSIN from VBATP in the Electrical Characteristics for parameters 5.6, 5.7, 5.8 ............................................................................................................ Changed the description for indication of VBATP_UV (6.1, 6.2) in the ELECTRICAL CHARACTERISTICS table. .. Added the condition of VBATP = VBAT_SAFING to 6.1, 6.2, 6.3, 6.4, 6.5, 6.8, 6.9, 6.10, 6.11, 6.12, 6.13, 6.14, 6.15, 6.16, 6.17 in the ELECTRICAL CHARACTERISTICS table. .......................................................... Added the condition of VBATP = VBAT_SAFING = 12 V to 7.1, 7.2, 7.3, 7.4, 7.7 and 7.8 the ELECTRICAL CHARACTERISTICS table ......................................................................................................... Changed test condition for the I_IGN parameter (7.4) to 36 V, added clarification that VBATP = VBAT_SAFING = 36 V in the ELECTRICAL CHARACTERISTICS table ...................................................................... Changed test condition for the I_CANWU parameter (7.7) to 36 V, added clarification that VBATP = VBAT_SAFING = 36 V in the ELECTRICAL CHARACTERISTICS table ................................................... Added clarification for Cpump and Cstore connections in the Charge Pump section of the ELECTRICAL CHARACTERISTICS table ......................................................................................................... Changed the Test Condition for NRES output low (paramater 9.1) level from 5mA to 2mA in the ELECTRICAL CHARACTERISTICS table ........................................................................................................ Added clarification in statement for the Timing Requirements table by adding VBAT_SAFING recommended operating range in addition to VBATP recommended operating range ...................................................... 27 30 30 30 32 32 32 32 33 34 34 34 34 35 35 35 35 36 36 The recommended maximum operating voltage for VBATP and VBAT_SAFING is listed as 34 V, just below the overvoltage detection thresholds for VBATP, VBATP_OVrise and VBATP_OVfall. TI recommends enabling overvoltage detection on VBATP (default is enabled, MASK_VBATP_OV = 0). TI also recommends evaluating the thermal and power dissipation of the device in the application and ensure the design has adequate thermal management for operation at the necessary supply voltage level. Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Changed description of parameter from Test Condition column to a footnote on the parameter in the Timing Requirements table for parameters 6.7, 11.1 ................................................................................... 36 Changed to clarify IGNITION and CAN WAKE-UP parameters (7.6 and 7.9) in TIMING REQUIREMENTS table .... 36 Added clarification in statement for the Switching Characteristics table by adding VBAT_SAFING recommended operating range in addition to VBATP recommended operating range ...................................................... 37 Added clarification of resistor divider feedback impact in the VDD1 Linear Regulator section ........................... 41 Changed pin name to VTRACK1 for pin determining tracking or non-tracking mode in VSOUT1 Linear Regulator section describing what occurs after completion of the VDDx ramp-up ..................................................... 42 Added note in the Wake-Up section on how to wake up the device for systems that need to power up and down with the power supply and do not need IGN or CANWU....................................................................... 44 Changed the Power-Up and Power-Down Behavior image for clarity ....................................................... 45 Changed the VDD6 UV bit to D6 from D7 in the Voltage Monitoring Overview table ..................................... 48 Changed the name for VSOUT1 current-limit to VSOUT1_CL in the Internal Error Signals table ...................... 50 Changed all references to the sensor supply to VSOUT1 for consistency .................................................. 50 Changed to clarify ABIST functionality in the Analog Built-In Self-Test (ABIST) section .................................. 52 Changed LBIST coverage in the Logic Built-In Self-Test (LBIST) section ................................................... 53 Changed to clarify LBIST functionality in the Logic Built-In Self-Test (LBIST) section..................................... 53 Changed the impact on device behavior for VSOUT1 thermal protect and over current in the Thermal and Over Current Protect ion Overview table .............................................................................................. 55 Changed the name for VSOUT1 current-limit to VSOUT1_CL in the Digital MUX Selection table ...................... 59 Changed and clarified Watchdog timer text in the Watchdog Timer (WDT) section ...................................... 60 Changed the all references of ERROR/WDTI pin to ERROR/WDI pin for consistency .................................... 61 Added clarification on the watchdog fail counter and reset event requirements in the Watchdog Fail Counter, Status, and Fail Event section ..................................................................................................... 61 Added the Watchdog Sequence section ........................................................................................ 62 Changed and clarified the equations for watchdog WINDOW 1 and WINDOW 2 (tWOW and tWCW) timing Watchdog Sequence section ..................................................................................................... 62 Added the MCU to Watchdog Synchronization section ....................................................................... 63 Added note on TIME_OUT flag not latching during active SPI frame (nCS low) in the Trigger Mode (Default Mode) section ........................................................................................................................ 63 Added clarification of the impact of a bad event on the watchdog sequence in the Trigger Mode Section and updated the images ................................................................................................................ 66 Added note on TIME_OUT flag not latching during active SPI frame (nCS low) in the Q&A Mode section ............ 67 Changed and clarified the watchdog in Q&A mode answer sequence requirements in the Watchdog Q&A Related Definitions section ......................................................................................................... 68 Changed the Watchdog Sequence in Q&A Mode image in the Watchdog Sequence in Q&A Mode section to update the Answer-3, Answer-2, Answer-1 requirements ..................................................................... 69 Added clarification on when the watchdog Markov chain and question counter are re-initialized in the Question (Token) Generation) section ....................................................................................................... 69 Added for clarification the Device Controller State Diagram .................................................................. 86 Changed SAFETY_ERR_STATUS to SAFETY_ERR_STAT so all references to this register are consistent ......... 88 Added clarification on using the DIAG_EXIT_MASK bit for software debug to the end of the DIAGNOSTIC STATE section ....................................................................................................................... 89 Added note to explain conditions leading to inadvert setting of SDO ERROR bit in the Device Status Flag Byte Response section ................................................................................................................... 93 Added clarification on reserved bits (RSV) in the Register Map section .................................................... 95 Changed DEV_STATE to DEV_STAT for Device Status in Register table for consistency ............................... 97 Deleted VSOUT1_ILIM in the SAFETY_STAT_1 Register table and made bit D3 a reserved bit (RSV) .............. 102 Changed VDD_3_5_SEL description in SAFETY_FUNC_CFG Register table ........................................... 109 Changed and clarified the WDT_TOKEN_FDBCK Register table .......................................................... 113 Changed and clarified the WDT_WIN1_CFG Register table ................................................................ 113 Changed and clarified the WDT_WIN2_CFG Register table ................................................................ 113 Changed and clarified the WDT_TOKEN_VALUE Register table .......................................................... 114 Changed and clarified the WDT_STATUS Register table ................................................................... 114 Changed and clarified the WDT_ANSWER Register table .................................................................. 115 Changed and clarified the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Q&A Mode flowchart .............................................................................................................. 127 Added the Software Flowchart for Configuring and Synchronizing the MCU With the Watchdog in Trigger Mode flowchart ............................................................................................................................ 128 Added clarity for VBAT_SAFING in the Power Supply Recommendations section ....................................... 129 Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 9 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Changes from Revision D (May 2015) to Revision E • • • • Changed the maximum UV value for VDD1 from 0.97 to 0.98 in the Voltage Monitoring Overview table. Also updated the VDD output voltage information .................................................................................... Changed the MAX value for VDD1_UVN from 0.97 to 0.98 in the Internal Error Signals table. Also updated the Device State When Flag Is Set cells for VDD1_UVN .......................................................................... Added clarification on the watchdog fail counter and reset event requirements in the Watchdog Enable Function image ................................................................................................................................. Added clarification on the watchdog fail counter and reset event requirements in the Device Controller State Diagram............................................................................................................................... Changes from Revision C (March 2015) to Revision D • • • • • • • • • • • • • • • • • • • • • • • • • 10 48 49 61 86 Page Changed ƒclk_VDD6 POS 1.5 minimum and maximum units from % to kHz for consistency in the ELECTRICAL CHARACTERISTICS table ........................................................................................................ Changed MIN value of VDD1SENSE(4.2) from -2% to -1% in the Electrical Characteristics table ........................ Changed MAX value of VDD1 undervoltage level (6.16) from 0.97 to 0.98 in the Electrical Characteristics table ... Changed description of un-used VDD1 regulator in the VDD1 Linear Regulator section ................................. Added clarification in the NMASK_VDD1_UV_OV description in the DEV_CFG1 Register table........................ Changes from Revision B (July 2014) to Revision C • • • • Page 32 33 35 41 98 Page Changed Applications listed in the Applications Section ........................................................................ 2 Deleted the nominal storage temperature value of 27°C ...................................................................... 29 Changed the Handling Ratings to ESD Ratings and moved Tstg into the Absolute Maximum Ratings table .......... 29 Added clarification notes on output capacitance and ESR for VDD6 in the ELECTRICAL CHARACTERISTICS table ................................................................................................................................... 32 Added the Typical Characteristics section ....................................................................................... 38 Added clarification of ESR needed on VDD6 output capacitance in the Functional Block Diagram ..................... 39 Added clarification on effective output capacitance and ESR in theVDD6 Buck Switch Mode Power Supply section ............................................................................................................................... 40 Added clarification on the IGN and CANWU pins with respect to transients Wake-Up section .......................... 44 Added start-up delay to VCP in the Power-Up and Power-Down Behavior ................................................. 45 Added SPI Interface Note on use of the SPI while DIAG_OUT MUX is enabled in the Diagnostic Output Pin DIAG_OUT section .................................................................................................................. 56 Added clarification on the watchdog fail counter and reset event requirements in the WDT Fail Counter, WDT Status, and WDT Fail Event section .............................................................................................. 61 Changed the RT bits from 4:0 to 6:0 in the TWCW calculation in the WDTI Configuration With an External Trigger Input (Default Mode) section ....................................................................................................... 64 Deleted the RT bits from 4:0 to 6:0 in the TWCW calculation in the Watchdog Token-Response Sequence Run section and changed the second calculation from TWOW to TWCW ............................................................ 68 Changed WDT_ANSW_CNT answer order in Set of 4-Bit WD Token Values and Corresponding 8-Bit Responses table. ................................................................................................................... 73 Changed 4-bit watchdog answer conter to 2-bit watchdog answer counter (WDT_ANSW_CNT) in Watchdog Token-Response Sequence Run and WDT_STATUS Register Updates section . ........................................ 73 Deleted logic BIST activated by MCU in SAFE state in the MCU Error Signal Monitor (MCU ESM) .................... 76 Deleted permanently text for the CRC check in the Device Configuration Register Protection section ................ 81 Changed CRC check to return to step one for continuous check in the Device Configuration Register Protection section ................................................................................................................................ 83 Added clarification on the watchdog fail counter and reset event requirement in the Reset and Enable Circuit image ................................................................................................................................. 84 Added or POST_RUN_RST = 1 & IGN_PWRL = 1 & re-cranking on IGN toGlobal RESET Conditions text bubble of the Device Controller State Diagram image ........................................................................ 86 Added clarification on watchdog fail counter text to the watchdog reset sub-bullet in the RESET STATE list ......... 87 Changed status bit STAT[1] function in Device Status Flag Byte Response table ......................................... 93 Changed data for SW_LOCK and SW_UNLOCK commands, which were reversed in the SPI Command Table ..... 95 Added clarification for watchdog failure in the SAFETY_STAT_2 Register table ......................................... 103 Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com • • • • • • • • • SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Added clarification for watchdog failure in the SAFETY_STAT_4 Register table ......................................... Added ERROR/WDI text to D[5] cleared to description in the SAFETY_ERR_STAT Register table .................. Added watchdog fail counter text to D[4] cleared to description in the SAFETY_ERR_STAT Register table ........ Changed the calculation in the WDT_WIN1_CFG Register table .......................................................... Changed the calculation in the WDT_WIN2_CFG Register table .......................................................... Added the Typical Application section .......................................................................................... Clarified ESR needed on VDD6 output capacitance in the Typical Application Diagram ................................ Added the System Examples section ........................................................................................... Added the Layout section ......................................................................................................... Changes from Revision A (December 2013) to Revision B • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 105 110 110 113 113 116 117 124 129 Page Deleted the phrase safety critical from the document. .......................................................................... 1 Added device name to document title.............................................................................................. 1 Added the following to the document: Device Information table, Power Supply Recommendations section, Layout section,Device and Documentation Support, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................. 2 Changed the pin type for the VDD3/5 pin from I to PWR ...................................................................... 28 Changed the max value for the Charge-pump voltages from 50 to 52 V in the ABSOLUTE MAXIMUM RATINGS table ................................................................................................................................... 29 Added the Handling Ratings table, which now contains the storage temperature and ESD ratings .................... 29 Added added with respect to the GND pin to the condition statement in the RECOMMENDED OPERATING CONDITIONS ........................................................................................................................ 30 Moved operating ambient temperature range from the Absolute Maximum Ratings table to the Recommended Operating Conditions table ......................................................................................................... 30 Changed changed no undervoltage to no NRES event and added VSOUT to the input supply voltage range on VBATP specification in the Recommended Operating Conditions ........................................................... 30 Deleted Thermal Information table notes: all of these notes are included in the IC Package Thermal Metrics application report that is listed in the new table note. .......................................................................... 31 Added the power dissipation image and notes after the Thermal Information table ....................................... 31 Changed condition statement for the ELECTRICAL CHARACTERISTICS table by removing 125°C from the TA temperature range and changingTJ to the maximum operating junction temperature. Removed VBATP range and added reference to R1.2 ...................................................................................................... 32 Deleted letter A from beginning of POS number in the VDD6-BUCK With Internal FET and VDD1 – LDO With External FET sections of the Electrical Characteristics and Timing Requirements table ................................. 32 Changed the parameter name of IVDD6 from output voltage to output current in the Electrical Characteristics table .. 32 Added the test condition to the dVDD5/dt parameter in the ELECTRICAL CHARACTERISTICS table................. 32 Changed the typ value from 3.35 to 3.3 and 5 for the VDD3/5 output voltage parameter in the ELECTRICAL CHARACTERISTICS table ......................................................................................................... 33 Changed the unit from † to V for the 3.3, VDD3/5 output voltage dynamic parameter in the Electrical Characteristics table ................................................................................................................ 33 Changed the parameter of 3.8 in the Electrical Characteristics table from VDD5 to VDD6 ............................... 33 Changed the parameter of A4.11 in the Electrical Characteristics table from VBATP to VDD6 .......................... 33 Changed MVVSOUT1 min and max values from –35 and 35 to –25 and 25 in the Electrical Characteristics table... 34 Changed the max value for temperature range listed in the VdrS1 parameter test condition from 165 to 150 in the Electrical Characteristics table ............................................................................................... 34 Changed the MIN and MAX values of the LdRegVSOUT1 parameter from –25 and 25 to –35 and 35 in the Electrical Characteristics table .................................................................................................... 34 Changed the typical value for the VDD3/5_OV 5-V hysteresis setting from 400 to 140 in the Electrical Characteristics table ................................................................................................................ 35 Added DC condition note to the VSOUT1_UV and VSOUT1_OV parameters in the Electrical Characteristics table .................................................................................................................................. 35 Changed max value for the Rdson_ENDRV_NRES (9.2a) parameter from 86 to 40 in the Electrical characteristics table .. 36 Deleted note reference for the RRSTEXT parameter (9.3) in the Electrical Characteristics table ........................... 36 Changed min value from 300 to 350 for the VENDRV_NRES_TH (9.5) parameter in the ELECTRICAL CHARACTERISTICS table ........................................................................................................ 36 Added note reference and test condition to the VDIGIN_HIGH parameter (10.1) in the ELECTRICAL CHARACTERISTICS table ........................................................................................................ 36 Moved timing and switching characteristics out of the Electrical Characteristics table and into a Timing Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 11 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 12 www.ti.com Requirements and Switching Requirements table (respectively). Also moved the capacitance at CSDO note to the Timing Requirements and Switching Requirements tables .................................................................... Changed the TYP value to the MAX value of the SPI clock frequency parameter for the VDDIO = 5 V test condition in the Electrical Characteristics table ................................................................................. Added image reference to timing and switching requirement parameters .................................................. Changed max value of ttri (13.11) from 25 to 53.3 in the ELECTRICAL CHARACTERISTICS table .................... Added the Overview section to the Detailed Description section ............................................................. Moved block diagram into the Detailed Description section and updated block colors .................................... Changed the OV max value for VDD3/5 (3.3 V) from 3.63 to 3.6 in the Voltage Monitoring Overview table .......... Added nMASK comments to the UV and OV impact on device behavior for VDD1 in the Voltage Monitoring Overview table ....................................................................................................................... Moved the Internal Error Signals table to after the Voltage Monitoring Overview table in the Detailed Description section ............................................................................................................................... Changed the TYP value for the AVDD_UVN signal from 3.81 to 3.6 in the Internal Error Signals table. Also changed the device state from Not changed for NRES and ENDRV to LOW, and for State to STANDBY ............ Changed the TYP value for the VCP12_UVN signal from 7.32 to 7.43 in the Internal Error Signals table ............ Changed the TYP value for the VCP12_OV signal from 14 to 14.2 in the Internal Error Signals table ................ Changed the typ value for VCP_OV from 20 to 21 in the Internal Error Signals table .................................... Changed NUV on signal names to UVN throughout ........................................................................... Changed the MIN value for the LOCLK signal from 0.740.7452 to 0.742 in the Internal Error Signals table .......... Changed the VBATP_OV MIN and MAX values from 29 to 34.7 and 32 to 36.7 (respectively) in the Internal Error Signals table .................................................................................................................. Changed the device state of the VDD3_5_OT bit from STANDBY to include change .................................... Changed the max values for VDD5_CL and VDD3_5_CL from 600 to 650 in the Internal Error Signals table ....... Added the DVDD_UV signal to the Internal Error Signals table ............................................................. Changed ............................................................................................................................. Deleted Watchdog function configuration from the post-BIST-reset initialization list in the Logic Built-In Self-Test (LBIST) section ...................................................................................................................... Changed VCP voltage range from 0.8 to 5.5 to 0.6 to 4 ...................................................................... Replaced the VSFB1 sensor-supply feedback voltage row wit the VSOUT1 sensor-supply voltage row in the Analog MUX Selection Table ...................................................................................................... Changed VSFB1 divide ratio from 4 ± 0.5% to 1 in the Analog MUX Selection table. Also changed the Voltage Range from 1.226 V to 5 V ±2% to 2.5 V to 5 V ............................................................................... Changed the Voltage Range / Accuracy value for both MAIN_BG and VMON_BG from 1.226 to 2.5 V in the Analog MUX Selection table ....................................................................................................... Changed the name bit that must be configured for DIGITAL MUX mode from DIAG_MUX to MUX_CFG in the Digital MUX (DMUX) section ...................................................................................................... Deleted Bits INT_CON[2:0] in DIAG_CFG_CTRL register must be set to 111 list item from the SDO diagnostic check sequence in the MUX interconnect check section ...................................................................... Changed the RT bits from 4:0 to 6:0 in the TWCW calculation in the WDTI Configuration With an External Trigger Input (Default Mode) section ....................................................................................................... Deleted the CLOSE window note from the Possible Cases for Bad Watchdog Event image and updated the image Added + 1 to the duration time program calculations in the Watchdog Token-Response Sequence Run section and changed the second calculation from TWOW to TWCW ...................................................................... Changed the filter time for the ERROR/WDI deglitch from 15-s to 15-µs in the MCU Error Signal Monitor (MCU ESM) section ......................................................................................................................... Changed the low-pulse duration increment from 15-s to 15-µs in the PWM Mode section ............................... Changed the Reset and Enable Circuit figure to reflect overtemperature behavior. ....................................... Added _UV to the NMASK_VDD1_OV name in the Reset and Enable Circuit image .................................... Added _UV to the NMASK_VDD1_OV name in DIAGNOSTIC and ACTIVE state text box of the Device Controller State Diagram image .................................................................................................. Deleted WDT failure text from the first list item in the SAFE State section ................................................. Moved all of the registers into one Register Map section ..................................................................... Changed D0 from 1 to 0 in the DEV_REV Register table ..................................................................... Changed D1 and D0 from 0 to X in the DEV_STATE Register table ........................................................ Changed the deglitched minimum time from 7.7 to 7.5 for the IGN bit description in the DEV_STATE register ...... Changed D7 from RSV and 1 to VDD_3_5_SEL and X in the DEV_CFG1 Register table ............................... Changed D6 from nMASK_VDD_UV and 1 to nMASK_VDD_UV_OV and 0 in the DEV_CFG1 Register table ....... Changed the default value of the NMASK_VDD1_UV_OV bit from 1 to 0 and the VDD1 bit value from 0 to 1 in the DEV_CFG1 Register ........................................................................................................... Revision History 36 37 37 37 39 39 48 48 49 49 49 49 49 49 50 50 50 50 50 50 54 57 57 57 57 60 60 64 66 68 76 78 84 84 86 90 95 96 97 97 98 98 98 Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Changed bit D5 name from MASK_VBAT_OV to MASK_VBATP_OV in the DEV_CFG2 Register table .............. 99 Changed the D[7] description when EN_VDD3/5_OT is set to '0' by removing the SAFETY_STAT_REG1, VDD6 and re-enable text in the DEV_CFG2 Register table. Also changed from when set to '0' to when set to '1' ........... 99 Changed VDD6, clearing, and re-enabling text from the D[7] description when EN_VDD3/5_OT is set to '1' and changed to when set to ''' in the DEV_CFG2 Register table .................................................................. 99 Changed D[3:0] description in the DEV_CFG2 Register table from bits are not read/writable to bits are read/writable ......................................................................................................................... 99 Deleted after SPI read access from the clear to 0 description of each bit in the VMON_STAT_1 Register........... 100 Deleted after SPI read access from the clear to 0 description of each bit in the VMON_STAT_2 Register........... 101 Deleted after SPI read access from the clear to 0 description of each bit in the SAFETY_STAT_1 Register ........ 102 Deleted after SPI read access from the clear to 0 description of each bit in the SAFETY_STAT_2 Register ........ 103 Added description to bit D[4] when set to one 1 when the device is the DIAGNOSTIC state .......................... 103 Changed the name of bit D5 in the SAFETY_STAT_3 register from NRES_IN to NRES_ERR ........................ 104 Changed the D[5] NRES_IN, Reset input status, register description to NRES_ERR, Reset input error and change first description for setting this bit to 1 ................................................................................. 104 Updated cleared to 0 description of the LBIST_ERR bit in the SAFETY_STAT_3 register ............................. 104 Added DIAGNOSTIC state description for setting bit D[3] and D[2] to 1 .................................................. 104 Changed SPI read access to internal NPOR from the LOCLK bit description in the SAFETY_STAT_4 Register ... 105 Changed bit D7 and bit D6 from 1 to 0 in the SAFETY_ERR_CFG Register table ....................................... 106 Changed the SAFETY_STAT4 register bit from D4 to D5 in the ABIST_EN[1:0] descriptions in the SAFETY_BIST_CTRL Register table .......................................................................................... 107 Changed names of protected registers in the CRG_CRC_EN bit description in the SAFETY_CHECK_CTRL Register ............................................................................................................................. 108 Changed monitored to not monitored in the NO_ERROR bit description for setting this bit to 1 in the SAFETY_CHECK_CTRL Register .............................................................................................. 108 Changed CTRL to CFG in the read and write commands of the SAFETY_FUNC_CFG Register ..................... 109 Changed D7 from 0 to 1 in the SAFETY_FUNC_CFG Register table ...................................................... 109 Changed D4 from 1 to 0 in the SAFETY_FUNC_CFG Register table ...................................................... 109 Changed D0 from 0 to X in the SAFETY_FUNC_CFG Register table ..................................................... 109 Updated the WD_RST_EN bit description for setting this bit to 0 in the SAFETY_FUNC_CFG Register ............ 109 Changed 15 seconds to 15 µs in the SAFETY_ERR_PWM_H Register table description .............................. 110 Changed the time reference amount from 15 s to 15 µs in the PWML[7:0] bit description for when ERR_CFG is set to 0 in the SAFETY_ERR_PWM_L Register .............................................................................. 111 Changed 5 seconds to 5 µs in the SAFETY_ERR_PWM_H Register table description ................................. 111 Deleted Note: With configuration 001 setting for INT_CON[2:0] bits text from the SPI_SDO description in the DIAG_CFG_CTRL Register. Also changed the 111 description of the INT_CON[2:0}] from controlling the state of the SPI_SDO output buffer to Not applicable .................................................................................. 112 Included bit 2 to all WDT_FAIL_CNT bit references ......................................................................... 114 Changed command for the WDT_ANSWER Register from Read to Write ................................................ 115 Changed the default setting of VSOUT1_EN from 1 to in the SENS_CTRL Register tabel ............................. 115 Changed Moved the Application Information section into the Application and Implementation section and added product folder references ......................................................................................................... 117 Changes from Original (May 2012) to Revision A • • • • • • • • • • • • • • Page Changed current limit for 6-V pre-regulator from 1.5 A to 1.3 A in the FEATURES list ..................................... Added current limit to the 5-V (CAN) bullet in the FEATURES list ............................................................ Added current limit to the 3.3-V or 5-V MCU I/O Voltage bullet in the FEATURES list .................................... Deleted reverse battery protection bullet from the FEATURES list ............................................................ Changed current limit from 300 mA to 100 mA in the sensor supply bullet in the FEATURES list ....................... Deleted wake-up and enable circuit bullets from the FEATURES list ......................................................... Added Independent to voltage monitoring bullet in the FEATURES list ....................................................... Added Independent Bandgap Reference bullet to the FEATURES list ........................................................ Added Diagnostic Output Pin bullet to the FEATURES list ..................................................................... Added Safing-Pin and IGNITION Pin bullets to the FEATURES list ........................................................... Changed document status from Product Preview to Production Data ......................................................... Added CAN Transceiver sentence to the second paragraph in the DESCRIPTION ........................................ Changed adjustable core voltage range from 0.8 and 2.6 V to 0.8 and 3.3 V in the DESCRIPTION ..................... Added diagnostic output pin and enable output to the list of features listed in the eighth paragraph in the Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 1 1 1 1 1 1 1 1 1 1 1 2 2 13 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 14 www.ti.com DESCRIPTION ........................................................................................................................ 2 Changed to data manual template to include table of contents and section numbers ...................................... 2 Added ADC, VDD6, to Typical Application Diagram ............................................................................. 3 Changed PGND type from input to ground in PIN FUNCTIONS table ....................................................... 27 Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustments ..................................... 29 Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustments ..................................... 29 Added Charge-pump overdrive voltage to the ABSOLUTE MAXIMUM RATINGS table .................................. 29 Deleted DMUXO from Logic I/O voltage list (M1.15) in the ABSOLUTE MAXIMUM RATINGS table ................... 29 Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table ................................................ 29 Changed unit for CDM on corner pins (750) from kV to V in the ABSOLUTE MAXIMUM RATINGS table ............. 29 Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table ................................................ 30 Deleted VDDIO internal pullup diode note from the RECOMMENDED OPERATING CONDITIONS table............. 30 Added values to the current consumption parameter in the RECOMMENDED OPERATING CONDITIONS table ... 30 Changed condition statement for the ELECTRICAL CHARACTERISTICS table by adding TA over junction temperature with up to 150°C ..................................................................................................... 32 Added VDD6ripple parameter to the ELECTRICAL CHARACTERISTICS table ............................................. 32 Added VDD6 output voltage to IVDD6 parameter (A1.2) in the ELECTRICAL CHARACTERISTICS table .............. 32 Changed example to Vdropout6 (A1.3) test condition in the ELECTRICAL CHARACTERISTICS table ................... 32 Changed IVDD6_limit parameter description from current-limit to peak current in the ELECTRICAL CHARACTERISTICS table ......................................................................................................... 32 Changed A1.5 from Fsw_VDD6, switching frequency to ƒclk_VDD6, clock frequency, added note, and deleted test condition from the ELECTRICAL CHARACTERISTICS table. Also added test condition ................................. 32 Changed test condition for DCVDD6 parameter (A1.6) from VBATP > 7 V to 0 main band gap .......................................... 100 Changed name of D6 from VDD3_ILIM to VDD3_5_ILIM in the SAFETY_STAT_1 Register table .................... 102 Added note to D[7] description in the SAFETY_STAT_1 Register table ................................................... 102 Added EEPROM bullet to D[5] description in the SAFETY_STAT_2 Register table ..................................... 103 Added DIAGNOSTIC and ACTIVE State text to D[2:0] default bullet in the SAFETY_STAT_2 Register table ....... 103 Added cleared to text to the D[5] description in the SAFETY_STAT_3 Register table ................................... 104 Changed D7 and D6 from 1 to 0 in the SAFETY_STAT_4 Register table ................................................. 105 Changed name of D0 from TRIM_ERR to TRIM_ERR_VMON in the SAFETY_STAT_4 Register table .............. 105 Added cleared to bullet and note to D[7:6] description in the SAFETY_STAT_4 Register table........................ 105 Changed set to text to include error-signal monitoring in the D[3] description in the SAFETY_STAT_4 Register table ................................................................................................................................. 105 Added ERROR_PIN_FAIL text to D[3] cleared description in the SAFETY_STAT_4 Register table................... 105 Added Watchdog Fail Counter text to the D[2] set to and cleared to descriptions in the SAFETY_STAT_4 Register table....................................................................................................................... 105 Deleted SPI read access from D[1]cleared to description in the SAFETY_STAT_4 Register table ................... 105 Changed SPI read access to NPOR in the D[0]cleared to description in the SAFETY_STAT_4 Register table ..... 105 Changed D4 from 1 to 0 and D1 and D0 from 0 to 1 in the SAFETY_STAT_5 Register table ......................... 106 Changed threshold from max to min for the 0000 setting description in the SAFETY_ERR_CFG Register table ... 106 Changed D7 and D6 from 1 to 0 in the SAFETY_BIST_CTRL Register table ............................................ 107 Changed D3 from LOCLK_EN to RSV in the SAFETY_BIST_CTRL Register table ..................................... 107 Added ACTIVE state bullet to D[7:6] description in the SAFETY_BIST_CTRL Register table .......................... 107 Added DIAGNOSTIC and ACTIVE states to D[5] description in the SAFETY_BIST_CTRL Register table ........... 107 Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Changed D4 from NO_WRST to RSV in the SAFETY_CHECK_CTRL Register table .................................. Added DEV_CFG2 and DEV_CFG1 to D[7] list of protected registers in the SAFETY_CHECK_CTRL Register table ................................................................................................................................. Added device state, ENDRV and NRES to D[6] description in the SAFETY_CHECK_CTRL Register table ......... Changed D[3] from not read/writable to read/writable in the SAFETY_CHECK_CTRL Register table ................ Added ERROR_PIN_FAIL sub-bullet to D[2] descriptionin the SAFETY_CHECK_CTRL Register table ............. Changed D7 from 0 to 1 in the SAFETY_FUNC_CFG Register table ...................................................... Changed D2 from RSV to DIS_NRES_MON in the SAFETY_FUNC_CFG Register table .............................. Changed D0 from 0 to X in the SAFETY_FUNC_CFG Register table ..................................................... Added SAFE state-time sub-bullet to the D[7] description in the SAFETY_FUNC_CFG Register table ............... Changed D[6] description from error-pin to Error-Signal Monitor in the SAFETY_FUNC_CFG Register table ....... Deleted watchdog pin from the D[6] description in the SAFETY_FUNC_CFG Register table .......................... Added note text to the D[4] description in the SAFETY_FUNC_CFG Register table..................................... Added STANDBY state text to the D[4] description in the SAFETY_FUNC_CFG Register table ...................... Deleted enabling/disabling the watchdog bullet from the D[3] description in the SAFETY_FUNC_CFG Register table ................................................................................................................................. Added bullets to the D[2] description in the SAFETY_FUNC_CFG Register table ....................................... Changed D[1] from not read/writable to read/writable in the SAFETY_FUNC_CFG Register table .................... Added READ-ONLY bullet, RESET STATE sub-bullet, and connected and not-connected text to the D[0] description in the SAFETY_FUNC_CFG Register table ...................................................................... Added ERROR/WDI and SAFE state text to the D[5] set to description in the SAFETY_ERR_STAT Register table ................................................................................................................................. Added WD_RST_EN text to D[4] set to description in the SAFETY_ERR_STAT Register table ....................... Added watchdog fail counter text to D[4] cleared to description in the SAFETY_ERR_STAT Register table ......... Added equation and oscillator text to the SAFETY_ERR_PWM_H Register table description ......................... Changed D4, D2, and D0 from 0 to 1 in the SAFETY_ERR_PWM_L Register description ............................. Added equations and oscillator text to the SAFETY_ERR_PWM_H Register table description ........................ Changed D4 from 1 to 0 in theSAFETY_PWD_THR_CFG Register table ................................................. Changed _THR to PWD names for D3:D0 in theSAFETY_PWD_THR_CFG Register table ........................... Changed D7, D5, and D3 from 1 to 0 in the SAFETY_CFG_CRC Register table ........................................ Changed D4 from 0 to 1 in the SAFETY_CFG_CRC Register table ....................................................... Changed D[7] description from high-impedance to tri-stated in the DIAG_CFG_CTRL Register table ................ Added SDO diagnostics from D[1:0] description to the D[6] description in the DIAG_CFG_CTRL Register table ... Changed D2 from 1 to 0 in the WDT_TOKEN_FDBCK Register table .................................................... Added bullets to the D[7:4] description in the WDT_TOKEN_FDBCK Register table ................................... Added new TOKEN seed bullet and sub-bullets to the D[3:0] description in the WDT_TOKEN_FDBCK Register table ................................................................................................................................. Changed D6:D0 from 0 to 1 in the WDT_WIN1_CFG Register table ...................................................... Changed D4:D3 from 0 to 1 in the WDT_WIN2_CFG Register table ....................................................... Changed D7 from 0 to 1 in the WDT_TOKEN_VALUE Register table ..................................................... Changed MCU sub-bullet from D[7] description to replace Q&A sub-bullet in the D[3:0] description of the WDT_TOKEN_VALUE Register table .......................................................................................... Changed D7:D6 from 0 to 1 in the WDT_STATUS Register table .......................................................... Changed D7:DF from RSV to WD_WRONG_CFG in the WDT_STATUS Register table ............................... Changed set to text of the D[5] description in the WDT_STATUS Register table ........................................ Changed D[4] note from recommendation to clear bit to remains set to 1 in the SENS_CTRL Register table ...... Changed Typical Application Diagram image .................................................................................. Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 108 108 108 108 108 109 109 109 109 109 109 109 109 109 109 109 109 110 110 110 110 111 111 111 111 111 111 112 112 113 113 113 113 113 114 114 114 114 114 115 117 19 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Changes from Original (July 2016) to Revision A • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 20 Page Changed current limit for 6-V pre-regulator from 1.5 A to 1.3 A in the FEATURES list ..................................... 1 Added current limit to the 5-V (CAN) bullet in the FEATURES list ............................................................ 1 Added current limit to the 3.3-V or 5-V MCU I/O Voltage bullet in the FEATURES list .................................... 1 Deleted reverse battery protection bullet from the FEATURES list ............................................................ 1 Changed current limit from 300 mA to 100 mA in the sensor supply bullet in the FEATURES list ....................... 1 Deleted wake-up and enable circuit bullets from the FEATURES list ......................................................... 1 Added Independent to voltage monitoring bullet in the FEATURES list ....................................................... 1 Added Independent Bandgap Reference bullet to the FEATURES list ........................................................ 1 Added Diagnostic Output Pin bullet to the FEATURES list ..................................................................... 1 Added Safing-Pin and IGNITION Pin bullets to the FEATURES list ........................................................... 1 Changed document status from Product Preview to Production Data ......................................................... 1 Added CAN Transceiver sentence to the second paragraph in the DESCRIPTION ........................................ 2 Changed adjustable core voltage range from 0.8 and 2.6 V to 0.8 and 3.3 V in the DESCRIPTION ..................... 2 Added diagnostic output pin and enable output to the list of features listed in the eighth paragraph in the DESCRIPTION ........................................................................................................................ 2 Changed to data manual template to include table of contents and section numbers ...................................... 2 Added ADC, VDD6, to Typical Application Diagram ............................................................................. 3 Changed PGND type from input to ground in PIN FUNCTIONS table ....................................................... 27 Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustments ..................................... 29 Changed POS numbers in ABSOLUTE MAXIMUM RATINGS table for adjustments ..................................... 29 Added Charge-pump overdrive voltage to the ABSOLUTE MAXIMUM RATINGS table .................................. 29 Deleted DMUXO from Logic I/O voltage list (M1.15) in the ABSOLUTE MAXIMUM RATINGS table ................... 29 Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table ................................................ 29 Changed unit for CDM on corner pins (750) from kV to V in the ABSOLUTE MAXIMUM RATINGS table ............. 29 Deleted TJ min value of –40 from ABSOLUTE MAXIMUM RATINGS table ................................................ 30 Deleted VDDIO internal pullup diode note from the RECOMMENDED OPERATING CONDITIONS table............. 30 Added values to the current consumption parameter in the RECOMMENDED OPERATING CONDITIONS table ... 30 Changed condition statement for the ELECTRICAL CHARACTERISTICS table by adding TA over junction temperature with up to 150°C ..................................................................................................... 32 Added VDD6ripple parameter to the ELECTRICAL CHARACTERISTICS table ............................................. 32 Added VDD6 output voltage to IVDD6 parameter (A1.2) in the ELECTRICAL CHARACTERISTICS table .............. 32 Changed example to Vdropout6 (A1.3) test condition in the ELECTRICAL CHARACTERISTICS table ................... 32 Changed IVDD6_limit parameter description from current-limit to peak current in the ELECTRICAL CHARACTERISTICS table ......................................................................................................... 32 Changed A1.5 from Fsw_VDD6, switching frequency to ƒclk_VDD6, clock frequency, added note, and deleted test condition from the ELECTRICAL CHARACTERISTICS table. Also added test condition ................................. 32 Changed test condition for DCVDD6 parameter (A1.6) from VBATP > 7 V to 0 main band gap .......................................... 100 Changed name of D6 from VDD3_ILIM to VDD3_5_ILIM in the SAFETY_STAT_1 Register table .................... 102 Added note to D[7] description in the SAFETY_STAT_1 Register table ................................................... 102 Added EEPROM bullet to D[5] description in the SAFETY_STAT_2 Register table ..................................... 103 Added DIAGNOSTIC and ACTIVE State text to D[2:0] default bullet in the SAFETY_STAT_2 Register table ....... 103 Added cleared to text to the D[5] description in the SAFETY_STAT_3 Register table ................................... 104 Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Changed D7 and D6 from 1 to 0 in the SAFETY_STAT_4 Register table ................................................. Changed name of D0 from TRIM_ERR to TRIM_ERR_VMON in the SAFETY_STAT_4 Register table .............. Added cleared to bullet and note to D[7:6] description in the SAFETY_STAT_4 Register table........................ Changed set to text to include error-signal monitoring in the D[3] description in the SAFETY_STAT_4 Register table ................................................................................................................................. Added ERROR_PIN_FAIL text to D[3] cleared description in the SAFETY_STAT_4 Register table................... Added Watchdog Fail Counter text to the D[2] set to and cleared to descriptions in the SAFETY_STAT_4 Register table....................................................................................................................... Deleted SPI read access from D[1]cleared to description in the SAFETY_STAT_4 Register table ................... Changed SPI read access to NPOR in the D[0]cleared to description in the SAFETY_STAT_4 Register table ..... Changed D4 from 1 to 0 and D1 and D0 from 0 to 1 in the SAFETY_STAT_5 Register table ......................... Changed threshold from max to min for the 0000 setting description in the SAFETY_ERR_CFG Register table ... Changed D7 and D6 from 1 to 0 in the SAFETY_BIST_CTRL Register table ............................................ Changed D3 from LOCLK_EN to RSV in the SAFETY_BIST_CTRL Register table ..................................... Added ACTIVE state bullet to D[7:6] description in the SAFETY_BIST_CTRL Register table .......................... Added DIAGNOSTIC and ACTIVE states to D[5] description in the SAFETY_BIST_CTRL Register table ........... Changed D4 from NO_WRST to RSV in the SAFETY_CHECK_CTRL Register table .................................. Added DEV_CFG2 and DEV_CFG1 to D[7] list of protected registers in the SAFETY_CHECK_CTRL Register table ................................................................................................................................. Added device state, ENDRV and NRES to D[6] description in the SAFETY_CHECK_CTRL Register table ......... Changed D[3] from not read/writable to read/writable in the SAFETY_CHECK_CTRL Register table ................ Added ERROR_PIN_FAIL sub-bullet to D[2] descriptionin the SAFETY_CHECK_CTRL Register table ............. Changed D7 from 0 to 1 in the SAFETY_FUNC_CFG Register table ...................................................... Changed D2 from RSV to DIS_NRES_MON in the SAFETY_FUNC_CFG Register table .............................. Changed D0 from 0 to X in the SAFETY_FUNC_CFG Register table ..................................................... Added SAFE state-time sub-bullet to the D[7] description in the SAFETY_FUNC_CFG Register table ............... Changed D[6] description from error-pin to Error-Signal Monitor in the SAFETY_FUNC_CFG Register table ....... Deleted watchdog pin from the D[6] description in the SAFETY_FUNC_CFG Register table .......................... Added note text to the D[4] description in the SAFETY_FUNC_CFG Register table..................................... Added STANDBY state text to the D[4] description in the SAFETY_FUNC_CFG Register table ...................... Deleted enabling/disabling the watchdog bullet from the D[3] description in the SAFETY_FUNC_CFG Register table ................................................................................................................................. Added bullets to the D[2] description in the SAFETY_FUNC_CFG Register table ....................................... Changed D[1] from not read/writable to read/writable in the SAFETY_FUNC_CFG Register table .................... Added READ-ONLY bullet, RESET STATE sub-bullet, and connected and not-connected text to the D[0] description in the SAFETY_FUNC_CFG Register table ...................................................................... Added ERROR/WDI and SAFE state text to the D[5] set to description in the SAFETY_ERR_STAT Register table ................................................................................................................................. Added WD_RST_EN text to D[4] set to description in the SAFETY_ERR_STAT Register table ....................... Added watchdog fail counter text to D[4] cleared to description in the SAFETY_ERR_STAT Register table ......... Added equation and oscillator text to the SAFETY_ERR_PWM_H Register table description ......................... Changed D4, D2, and D0 from 0 to 1 in the SAFETY_ERR_PWM_L Register description ............................. Added equations and oscillator text to the SAFETY_ERR_PWM_H Register table description ........................ Changed D4 from 1 to 0 in theSAFETY_PWD_THR_CFG Register table ................................................. Changed _THR to PWD names for D3:D0 in theSAFETY_PWD_THR_CFG Register table ........................... Changed D7, D5, and D3 from 1 to 0 in the SAFETY_CFG_CRC Register table ........................................ Changed D4 from 0 to 1 in the SAFETY_CFG_CRC Register table ....................................................... Changed D[7] description from high-impedance to tri-stated in the DIAG_CFG_CTRL Register table ................ Added SDO diagnostics from D[1:0] description to the D[6] description in the DIAG_CFG_CTRL Register table ... Changed D2 from 1 to 0 in the WDT_TOKEN_FDBCK Register table .................................................... Added bullets to the D[7:4] description in the WDT_TOKEN_FDBCK Register table ................................... Added new TOKEN seed bullet and sub-bullets to the D[3:0] description in the WDT_TOKEN_FDBCK Register table ................................................................................................................................. Changed D6:D0 from 0 to 1 in the WDT_WIN1_CFG Register table ...................................................... Changed D4:D3 from 0 to 1 in the WDT_WIN2_CFG Register table ....................................................... Changed D7 from 0 to 1 in the WDT_TOKEN_VALUE Register table ..................................................... Changed MCU sub-bullet from D[7] description to replace Q&A sub-bullet in the D[3:0] description of the WDT_TOKEN_VALUE Register table .......................................................................................... Changed D7:D6 from 0 to 1 in the WDT_STATUS Register table .......................................................... Changed D7:DF from RSV to WD_WRONG_CFG in the WDT_STATUS Register table ............................... Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 105 105 105 105 105 105 105 105 106 106 107 107 107 107 108 108 108 108 108 109 109 109 109 109 109 109 109 109 109 109 109 110 110 110 110 111 111 111 111 111 111 112 112 113 113 113 113 113 114 114 114 114 25 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 • • • 26 www.ti.com Changed set to text of the D[5] description in the WDT_STATUS Register table ........................................ 114 Changed D[4] note from recommendation to clear bit to remains set to 1 in the SENS_CTRL Register table ...... 115 Changed Typical Application Diagram image .................................................................................. 117 Revision History Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 3 Pin Configuration and Functions The pin configuration drawing in this section is not to scale. For package dimensions, see the mechanical data in Section 10. DAP Package 32-Pin HTSSOP With PowerPAD™ Top View VBAT_SAFING 1 32 ENDRV VCP 2 31 SEL_VDD3/5 CP1 3 30 IGN CP2 4 29 VBATP PGND 5 28 SDN6 NRES 6 27 VDD6 DIAG_OUT 7 26 VDD1_G NCS 8 25 PGND 24 VDD1_SENSE Thermal SDI 9 SDO 10 23 GND SCLK 11 22 VDDIO RSTEXT 12 21 VDD3/5 ERROR/WDI 13 20 VDD5 CANWU 14 19 GND VSFB1 15 18 VTRACK1 VSIN 16 17 VSOUT1 Pad Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 VBAT_SAFING PWR Battery (supply) input for monitoring (VMON) and BG2 functions (must be reverse protected), should be connected to VBATP 2 VCP PWR Charge-pump output voltage 3 CP1 PWR Charge-pump external capacitor, high-voltage side 4 CP2 PWR Charge-pump external capacitor, low-voltage side 5 PGND GND Ground (power) 6 NRES O Cold reset output signal for the microcontroller (MCU) (active-low, internal pullup, open drain output) 7 DIAG_OUT O Diagnostic output pin for diagnostic MUX. Internal analog (AMUX) and digital (DMUX) signal connection to MCU ADC and digital IO 8 NCS I SPI chip select (active-low, internal pullup) 9 SDI I SPI serial data IN (internal pulldown) 10 SDO O SPI serial data OUT 11 SCLK I SPI clock (internal pull down) 12 RSTEXT I Configuration pin to set reset extension time through a resistor to GND Pin Configuration and Functions Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 27 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Pin Functions (continued) PIN NO. NAME TYPE DESCRIPTION 13 ERROR/WDI I Error input signal from the MCU while using the MCU ESM (with the watchdog in Q&A Mode), trigger input for the watchdog in trigger mode (MCU ESM not used). This pin is edge triggered. 14 CANWU I Wake-up input from CAN transceiver, other transceiver or other source. Wake-up request latched with CANWU_L. (internal pulldown) 15 VSFB1 I Feedback input reference for sensor supply regulator (VSOUT1) 16 VSIN PWR Input supply voltage for the sensor-supply regulator (VSOUT1) 17 VSOUT1 PWR Output voltage for the VSOUT1 sensor-supply regulator 18 VTRACK1 I 19 GND GND Ground (analog) Tracking input reference for sensor-supply regulator (VSOUT1) (internal pulldown) 23 GND GND Ground (analog) 20 VDD5 PWR VDD5 regulator output voltage 21 VDD3/5 PWR VDD3/5 regulator output voltage 22 VDDIO PWR I/O supply input for pins to and from the MCU 24 VDD1_SENSE I 25 PGND GND 26 VDD1_G O 27 VDD6 PWR VDD6 switch mode regulator feedback input and supply input for integrated VDD5 and VDD3/5 regulators 28 SDN6 PWR Switching node for VDD6 switch mode regulator 29 VBATP PWR Battery (supply) voltage (must be reverse protected), main power supply input for device 30 IGN I Wake-up input from ignition (key) or other source (internal pulldown) 31 SEL_VDD3/5 I Input selects voltage level for VDD3/5 regulator (SEL_VDD3/5 pin open: 3.3-V regulation from VDD3/5; SEL_VDD3/5 pin to GND: 5-V regulation from VDD3/5) 32 ENDRV O Enable output signal for peripherals (for example, motor-driver IC), safing path output (internal pullup, open drain output) — Thermal pad — Place thermal vias to large ground plane and connect to GND and PGND pins. 28 Reference input for VDD1 regulator (feedback) and input for UV/OV monitoring of VDD1 regulator Ground (power) Gate drive of external FET for VDD1 regulator Pin Configuration and Functions Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 4 Specifications 4.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) (2) POS M1.1 Protected-battery voltage VBATP, VBAT_SAFING, VSIN (3) MIN MAX UNIT –0.3 40 V –0.3 lesser of VBATP + 16 or 52 V M1.2 Charge-pump voltage VCP, CP1 M1.3 Charge-pump pumping capacitor voltage CP2 –0.3 40 V M1.3a Charge-pump overdrive voltage VCP (3)-VBATP –0.3 16 V M1.4 VDD6 switching-node voltage SDN6 –0.3 40 V M1.5 VDD6 output voltage VDD6 –0.3 40 V M1.6 VDD5 output voltage VDD5 –0.3 7 V M1.7 VDD3/5 output voltage VDD3/5 –0.3 7 V M1.8 VDD1_G voltage VDD1_G –0.3 15 V M1.10 VDD1_SENSE voltage VDD1_SENSE –0.3 7 V M1.11 Sensor supply tracking voltage VTRACK1 –0.3 40 V M1.12 Sensor supply output and feedback voltage VSOUT1, VSFB1 –2 18 V M1.14 Analog/digital reference output voltage DIAG_OUT –0.3 7 V VDDIO, ERROR/WDI, ENDRV, NRES, NCS, SDI, SDO, SCLK, RSTEXT –0.3 7 V SEL_VDD3/5 –0.3 40 V –7 40 V –0.3 40 V 150 °C 150 °C M1.15 Logic I/O voltage M1.16 M1.17 IGN wakeup IGN M1.18 CAN wakeup CANWU M1.19 Operating virtual junction temperature, TJ (4) Storage temperature, Tstg –65 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) (3) All voltage values are with respect to the network ground pin unless otherwise noted. VCP and CP1 are output pins, no external voltage should be applied to these pins. Absolute Maximum ratings for these pins are what may appear on the pins. VSOUT1 is connected to VSFB1 directly (for unity gain) or through resistor divider (tracking mode gain or non-tracking mode output voltage adjusting). In case of a short to supply fault, the voltage on VSOUT1 is equal to the supply to the device (VBATP, VBAT_SAFING, and VSIN where VSIN is connected to VBATP as it's supply instead of VDD6) and VSFB1 voltage will follow VSOUT1 based on the use case, directly (for unity gain) or via resistor divider (tracking mode gain or non-tracking mode output voltage adjusting). (4) 4.2 ESD Ratings POS. VALUE M1.21 Human body model (HBM), per AEC Q100-002 (1) M1.20 M1.22 M1.23 (1) V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 All pins except VSOUT1 (17) and VSFB1 (15) ±2000 On sensor supply pins VSOUT1 (17) and VSFB1 (15) ±4000 Corner pins (1, 16, 17, and 32) ±750 All pins ±500 UNIT V AEC Q100-002 indicates that HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 Specification. Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 29 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 4.3 www.ti.com Recommended Operating Conditions Over operating temperature range and with respect to the GND and PGND (GND = PGND) pins (unless otherwise noted) POS MIN MAX UNIT –40 125 °C 5.8 (3) V 5.8 34 (5) V R1.3 Input supply voltage on VBATP after initial power up, functional operation during low input supply voltage events, (POS 6.1, VBATP_UVoff): (1) (6) • The device remains functional. Some rails can be in dropout or undervoltage depending on actual input supply and the configuration of the specific regulator. • VDD6 is in dropout mode (100% duty cycle). • VDD3/5 configured for 5-V output can be in dropout. If the output reaches VDD3/5_UV threshold, the device transitions to the RESET state because of a VDD3/5 undervoltage event. If VDD3/5 is configured for 3.3-V output it remains functional. • VDD5 can be in dropout. If the output reaches VDD5_UV threshold, the device indicates the undervoltage event through the VDD5_UV status bit. • VSOUT1 may be in dropout depending on configuration, if output reaches VSOUT1_UV threshold the device indicates the undervoltage event through the VSOUT1_UV status bit. 4.5 5.8 V R1.4 VDDIO supply-voltage range 3.3 5 V R1.5 Current consumption in standby mode (all regulator outputs disabled) IGN = 0 V, CANWU = 0 V, 5.8 V ≤ VBAT ≤ 20 V for TJ < 85°C or 5.8 V ≤ VBAT ≤ 14 V tor TJ = 125°C 75 µA M1.20a Operating ambient temperature, TA R1.1 Minimum input supply voltage on VBATP for initial power up (POS 6.2, VBATP_UVon) (1) (2) R1.2 Input supply voltage on VBATP (1) (2) (4) • To support operation when VBATP is between 5.8 V and 7 V, the device remains functional. Some rails can be in dropout or undervoltage depending on actual input supply and the configuration of the specific regulator. • VDD6 can be in dropout mode (100% duty cycle) • VDD3/5 configured for 5-V output can be in dropout. If the output reaches VDD3/5_UV threshold, the device transitions to the RESET state because of a VDD3/5 undervoltage event. If VDD3/5 is configured for 3.3-V output it remains functional. • VDD5 can be in dropout. If output reaches the VDD5_UV threshold, the device indicates the undervoltage event through the VDD5_UV status bit. • VSOUT1 can be in dropout depending on configuration. If output reaches VSOUT1_UV threshold, the device indicates the undervoltage event through the VSOUT1_UV status bit. (1) (2) (3) (4) VBATP should be connected to VBAT_SAFING. VBAT_SAFING has a supply high enough to power the VMON block and internal rail AVDD_VMON above AVDD_VMON_UV. The device may power up when VBATP is less than 5.8 V, but it will always power up when VBATP is 5.8V or greater, while VBAT_SAFING has a supply high enough to power the VMON block and internal rail AVDD_VMON above AVDD_VMON_UV. Under slow VBAT ramp-down and when VDD3/5 rail is configured as a 5-V rail, the NRES output can be pulled low when VBAT is at approximately 6.3 V. This occurs because of an undervoltage transient on the VDD3/5 rail. Under slow VBAT ramp-up and when VDD3/5 rail is configured as a 5-V rail, the NRES output can be pulled low when VBAT is at approximately 6.6 V. This occurs because of an undervoltage transient on VDD3/5 rail. Under similar conditions, undervoltage transients are observed on VDD5 and VSOUT1 rails (refer to Device Behavior Under Slow VBAT Ramp-Up and Ramp-Down). (5) The recommended maximum operating voltage for VBATP and VBAT_SAFING is listed as 34 V, just below the overvoltage detection thresholds for VBATP, VBATP_OVrise and VBATP_OVfall. TI recommends enabling overvoltage detection on VBATP (default is enabled, MASK_VBATP_OV = 0). TI also recommends evaluating the thermal and power dissipation of the device in the application and ensure the design has adequate thermal management for operation at the necessary supply voltage level. (6) The device will remain on if VBATP drops from 5.8V down to VBATP_UVoff threshold or another voltage monitor detects an undervotlage on a specific rail and changes the device state. VBAT_UVoff can be detected at 4.5 V but could be detected as low as 4.2 V. VBAT_SAFING has a supply high enough to power the VMON block and internal rail AVDD_VMON above AVDD_VMON_UV. 30 Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com 4.4 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Thermal Information TPS65381-Q1 THERMAL METRIC (1) DAP (HTSSOP) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 26.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 14.1 °C/W RθJB Junction-to-board thermal resistance 6 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 6.2 °C/W Junction-to-case (bottom) thermal resistance 0.5 °C/W RθJC(bot) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 3 Power Dissipation (W) 2.85 1.9 0.95 25 50 75 100 125 150 Ambient Temperature (°C) (1) (2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TAmax) is dependent on the maximum-operating junction temperature (TJmax), the maximum power dissipation of the device in the application (PDmax), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TAmax = TJmax – (RθJA × PDmax). Maximum power dissipation is a function of TJmax, RθJA, and TA. The maximum-allowable power dissipation at any allowable ambient temperature is PD = (TJmax – TA) / RθJA. Figure 4-1. Derating Profile for Power Dissipation Based on High-K JEDEC PCB Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 31 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 4.5 www.ti.com Electrical Characteristics Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and with VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted) POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD6-BUCK WITH INTERNAL FET AN CVDD6 Value of output ceramic capacitor (1) AN LVDD6 Value of inductor 1.1 VDD6 VDD6 output voltage Average DC value excluding ripple and load transients, VBAT > 7 V, 0 < IVDD6 < 1.3 A, including dc line and load regulation, temperature drift, and long-term drift where VBAT = VBATP = VBAT_SAFING 1.1a VDD6ripple VDD6 ripple voltage Peak-to-peak, ensured by design VBATP = VBAT_SAFING = 14 V, L = 33 µH, C = 22 µF 1.2 ESR range 100 mΩ to 300 mΩ (2) IVDD6 VDD6 output current IVDD5 + IVDD3/5 + IVDD1+ IVSOUT1 1.3 Vdropout6 VDD6 output dropout voltage Vdropout6 = (VBATP – SDN6) 1.4 IVDD6_limit Peak current out of SDN6 pin (4) 1.5 ƒclk_VDD6 Clock Frequency 1.6 DCVDD6 ton/tperiod 1.7 TprotVDD6 Temperature protection threshold (7) 22 47 22 33 5.4 6 IVDD6 = 1.3 A (example: RDS(on) = 0.46 Ω) 1.5 (5) 396 0 < IVDD6 < 1.3 A VDD6 enters dropout mode (100% duty cycle) for VBATP < 7 V 6.6 200 (3) 440 µF µH V mV 1.3 A 0.6 V 2.5 A 484 kHz 7% (6) 100% 175 210 °C 5 µF VDD5 – LDO WITH INTERNAL FET AN CVDD5 Value of output ceramic capacitor ESR range 0 mΩ to 100 mΩ 2.1 VDD5 VDD5 output voltage (8) 0 < IVDD5 < 300 mA 2.2 IVDD5 VDD5 output current, including load from the internal resistor of 660 Ω (typical) 2.3 VDD5dyn VDD5 output voltage dynamic Load step 20% to 80% in 5 µs, with CVDD5 = 5 µF VDD5max Maximum VDD5 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs 2.5 Vdropout5 VDD5 output dropout voltage Vdropout5 = (VDD6 – VDD5) 2.6 PSRRVDD5 Power supply rejection ratio 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp, CVDD5 = 5 μF, 0 < IVDD5 < 300 mA 2.4 1 4.9 5.1 V 300 mA 5.15 V CVDD5 = 5 µF, IVDD5 < 300 mA 5.5 V IVDD5 < 300 mA 0.3 V 4.85 5 5 > 40 dB 2.7 LnRegVDD5 Line regulation (IVDD5 constant) 0 < IVDD5 < 300 mA, 8 V < VBATP < 19 V 2.8 LdRegVDD5 Load regulation (VDD6 constant) 0 < IVDD5 < 300 mA, 8 V < VBATP < 19 V 2.9 TmpCoVDD5 Temperature drift Normalized to 25°C value 2.11 dVDD5/dt dV/dt at VDD5 at startup Between 10% and 90% of VDD5 end-value 5 50 2.13 TprotVDD5 Temperature protection threshold (9) 175 210 °C 2.14 IVDD5_limit Current-limit (10) 350 650 mA (1) (2) (3) (4) –25 25 mV –25 25 mV –0.5% 0.5% V/ms Capacitance is effective capacitance after derating for operating voltage, temperature, and lifetime. ESR is total effective series resistance of the capacitors and if necessary added series resistor. IVDD6 is the load current from VDD5, VDD3/5, VDD1 and VSOUT1 on VDD6 regulator; VDD6 is not recommended to be loaded directly for applications or peripherals that cannot operate with wider tolerance and ripple since VDD6 is a pre-regulator. However, LDOs or DCDC conv erters may be connected directly as along as the total load current on VDD6, IVDD6, does not exceed the specification for VDD6 load current. VDD6 current limit is based on the peak current through SDN6 switch, it will not directly correspond to an average current limit. (5) Actual switching on SND6 depends on whether output voltage on VDD6 is above or below hysteretic PWM comparator threshold at the moment of the rising edge of the Fclk_VDD6 clock. If no switching is needed when the risking edge of the Fclk_VDD6 clock occurs, SDN6 will not switch on. SDN6 turn off is determined by the hysteretic PWM comparator threshold, when the actual VDD6 voltage is above the threshold SDN6 will turn off. (6) When the VDD6 control loop turns the SDN6 switch on at the rising edge of a fclk_VDD6 clock cycle, SDN6 will remain on with a minimum duty cycle of 7%. However, if the control loop skips a clock cycle the duty cycle will be 0% for that fclk_VDD6 clock cycle. (7) Protection of VDD6, shared with VDD3/5 overtemperature protection. (8) VDD5 output regulation includes line and load regulation, temperature drift. (9) Protection of VDD5. In case of detected overtemperature, only VDD5 will be switched off. (10) IVDD5_limit current limit has snap back behavior. During a short circuit condition, a transient current higher than the maximum will occur until the current limit snaps back into the specified range. 32 Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Electrical Characteristics (continued) Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and with VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted) POS PARAMETER TEST CONDITIONS MIN TYP MAX 3.234 3.3 3.366 4.9 5 5.1 UNIT VDD3/5 – LDO WITH INTERNAL FET AN CVDD3/5 Value of output ceramic capacitor VDD3/5 VDD3/5 output voltage, SEL_VDD3/5 pin: open = 3.3 V setting, ground = 5 V setting 3.1a 3.1b ESR range 0 mΩ to 100 mΩ 1 3.3-V Setting 0 < IVDD3/5 < 300 mA VDD3/5 output current, including load from the internal resistor of 440 Ω (typ.) for 3.3 V setting or 660 Ω (typ.) for 5 V setting (11) VDD3/5dyn VDD3/5 output voltage dynamic VDD3/5max Maximum VDD3/5 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs CVDD3/5 = 5 µF, IVDD3/5 < 300 mA 3.5 Vdropout3/5 VDD3/5 output dropout voltage Vdropout3/5 = (VDD6–VDD3/5) IVDD3/5 < 300 mA 3.6 PSRRVDD3/5 Power-supply rejection ratio 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp CVDD3/5 = 5 μF, 0 < IVDD3/5 < 300 mA 3.3a 3.3b 3.4 300 Load step 20% to 80% in 5 µs, with 3.3-V Setting CVDD3/5 = 5 µF 5-V Setting 3.7 LnRegVDD3/5 Line regulation (IVDD3 constant) 0 < IVDD3/5 < 300 mA, 8 V < VBATP < 19 V 3.8 LdRegVDD3/5 Load regulation (VDD6 constant) 0 < IVDD3/5 < 300 mA 8 V < VBATP < 19 V 3.9 TmpCoVDD3/5 Temperature drift Normalized to 25°C value 3.11 dVDD35/dt dV/dt at VDD3/5 at start-up Between 10% and 90% of VDD3/5 end-value TprotVDD3/5 Temperature protection threshold 3.14 IVDD3/5_limit Current-limit (13) 3.15 Ipu_SEL_VDD3/5 Pullup current on SEL_VDD3/5 pin 3.15 3.3 3.43 4.85 5 5.15 mA V 3.3-V Setting 3.6 5-V Setting 5.5 V 0.3 > 40 –25 V dB 25 mV mV –25 25 –0.5% 0.5% 3.3-V Setting 3 30 5-V Setting 5 50 175 210 °C 350 650 mA 20 µA V/ms (12) 3.13 µF V 5-V Setting IVDD3/5 3.2 5 VDD1 – LDO WITH EXTERNAL FET AN Vgs(th) Gate threshold voltage, external FET ID = 1 mA AN Ciss Gate capacitance, external FET VGS = 0 V AN Qgate Gate Charge, external FET VGS = 0 V to 10 V AN gfs Forward transconductance, external FET ID = 50 mA AN CVDD1 Value of output ceramic capacitor ESR range 0 mΩ to 100 mΩ 4.1 VDD1 VDD1 output voltage, depends on external resistive divider (14) 0.3 3 V 3200 pF 70 nC 5 40 µF 0.8 3.3 V 0.4 4.2 VDD1SENSE VDD1 reference voltage 4.2a VDD1SENSE_BIAS Bias current of VDD1SENSE 4.3 IVDD1 VDD1 output current Minimum current realized with external resistive divider 4.4 VDD1G VDD1_G output voltage Referenced to GND 4.5 VDD1G_off VDD1_G voltage in OFF condition 20 µA into VDD1_G pin 0.3 V 4.6 I_VDD1G VDD1_G DC load current 200 µA 4.7 VDD1dyn VDD1 output voltage dynamic 4.8 VDD1max 10 mA < IVDD1 < 600 mA 0.792 S 0.808 V –6.6 –10 µA 10 600 mA 15 V Load step 10% to 90% in 1 μs, with CVDD1 = 40 μF (15) Maximum VDD1 output voltage during VBATP step from 5.5 V to 13.5 V within 10 μs CVDD1 > 6 µF, IVDD1< 600 mA ± 4% VDD1 = 0.8-V output 0.898 VDD1 = 1.23-V output 1.287 VDD1 = 3.3-V output 3.435 4.9 PSRRVDD1 Power-supply rejection ratio 50 < f < 20 kHz, VBATP = 10 V, U = 4 Vpp, CVDD1 = 10 μF, 10 mA < IVDD1 < 600 mA 4.10 LnRegVDD1 Line regulation on VDD1_SENSE (IVDD1 constant) 10 mA < 4.11 LdRegVDD1 Load regulation on VDD1_SENSE (VDD6 constant) 10 mA < IVDD1 < 600 mA, 8 V < VBATP < 19 V IVDD1< 0.8 600 mA, 8 V < VBATP < 19 V > 40 V dB –7 7 mV –7 7 mV (11) Less than 50% of maximum loading of IVDD3/5 should be placed on the VDD3/5 regulator before NRES goes high during device power up. (12) Protection of VDD3/5, treated as global overtemperature (shutdown for all regulators). (13) IVDD3/5_limit current limit has snap back behavior. During a short circuit condition, a transient current higher than the maximum will occur until the current limit snaps back into the specified range. (14) VDD1 regulation including line and load regulation, temperature drift and long-term drift. Does not include tolerance of resistor divider to set VDD1 output voltage. (15) VDD1dyn will depend on external FET choice Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 33 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Electrical Characteristics (continued) Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and with VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted) POS PARAMETER TEST CONDITIONS 4.12 TmpCoVDD1 Temperature drift Normalized to 25°C value 4.14 dVDD1/dt dV/dt at VDD1_SENSE at start-up MIN TYP MAX UNIT –0.5% 0.5% Between 10% and 90% of VDD1 end-value 0.8 8 V/ms ESR range 0 mΩ to 100 mΩ 0.5 10 µF 3.3 9.5 V 35 mV VSOUT1 – LDO WITH PROTECTED INTERNAL FET AN CVSOUT1 Value of output ceramic capacitor 5.1 VSOUT1 VSOUT1 output voltage, depends on external resistive divider and tracking or non-tracking mode 5.2 MVVSOUT1 For tracking mode: Matching output error MVVSOUT1 = (VTRACK1 – VSFB1) (16) 0 < IVSOUT1 < 100 mA –35 5.3 VSFB1 For non-tracking mode: VSOUT1 reference voltage (17) 10 mA < IVSOUT1 < 100 mA 2.45 2.5 2.55 V 5.3a VTRACK1th Threshold for selecting tracking/non-tracking mode (VTRACK1 > VTRACK1th_max V for tracking mode, VTRACK1 < VTRACK1th_min V non-tracking mode) 1.1 1.2 1.3 V 5.3b VTRACK1pd Internal pulldown resistance on VTRACK1 pin 5.4 IVSOUT1 VSOUT1 output current, including internal resistor to dissipate minimum current (18) 5.5 VdrS1 VSOUT1 dropout voltage VdrS1 = (VSIN-VSOUT1) 0 < IVSOUT1 < 100 mA 100 kΩ 100 mA 0.75 V 5.6 PSRRVSOUT1 Power-supply rejection ratio With VTRACK1 = GND, VSOUT1 = 4.5V, 50 < f < 20 kHz, VSIN = 10 V, U = 4 Vpp CVSOUT1 = 1 μF, 0 < IVSOUT1 < 100 mA, 5.7 LnRegVSOUT1 Line regulation (IVSOUT1 constant) 0 < IVSOUT1 < 100 mA, 8 V < VSIN < 19 V –25 25 mV 5.8 LdRegVSOUT1 Load regulation (VSIN constant) 0 < IVSOUT1 < 100 mA, 8 V < VSIN < 19 V –35 35 mV 5.9 TmpCoVSOUT1 Temperature drift Normalized to 25°C value –0.5% 0.5% 5.11 VSOUT1SH Output short circuit voltage range VSOUT1 (VSFB1 configured for regulation) (19) –2 18 V 5.12 –IVSIN Output reverse current VSOUT1 = 14 V and VBATP = 0 V, regulator switched off 20 mA 5.13 TprotVSOUT1 Temperature protection threshold (20) 175 210 °C 5.14 IVSOUT1_limit Current-limit 120 500 mA > 40 dB VOLTAGE MONITORING 6.1 VBATP_UVoff VBATP and VBAT_SAFING level for indication by VBAT_UV comparitor (21) VBATP = VBAT_SAFING 4.2 4.5 V 6.2 VBATP_UVon VBATP and VBAT_SAFING level for indication by VBAT_UV comparitor (21) VBATP = VBAT_SAFING 5.4 5.8 V 6.3 VBATP_UVhys Undervoltage hysteresis VBATP = VBAT_SAFING 1.1 1.4 V 6.4 VBATP_OVrise VBATP level for setting VBAT_OV flag (22) VBATP = VBAT_SAFING 34.7 36.7 V 6.5 VBATP_OVfall VBATP level for clearing VBAT_OV flag (23) VBATP = VBAT_SAFING 34.4 36.3 V VDD5 undervoltage level VBATP = VBAT_SAFING 4.5 4.85 Hysteresis VBATP = VBAT_SAFING VDD5 undervoltage headroom (VDD5act – VDD5_UVact) VBATP = VBAT_SAFING 200 VDD5 overvoltage level VBATP = VBAT_SAFING 5.2 Hysteresis VBATP = VBAT_SAFING VDD5 overvoltage headroom (VDD5_OVact – VDD5act) VBATP = VBAT_SAFING 6.8 V VDD5_UV 6.8a 6.9 VDD5_UVhead 6.10 140 mV mV 5.45 V VDD5_OV 6.10a 6.11 VDD5_OVhead 140 200 mV mV (16) Referenced to VTRACK1 input, including long-term and temperature drift. (17) VSOUT1 including line and load regulation, temperature drift and long-term drift. (18) VSOUT1 maximum power dissipation for the internal FET must not exceed 0.6 W to avoid overtemperature. Special consideration must be taken for output voltages greater than 5 V and when VBATP is used to supply VSIN instead of VDD6. (19) VSOUT1 is connected to VSFB1 directly (for unity gain) or through resistor divider (tracking mode gain or non-tracking mode output voltage adjusting). In case of a short to supply fault, the voltage on VSOUT1 is equal to the supply to the device (VBATP, VBAT_SAFING, and VSIN where VSIN is connected to VBATP as it's supply instead of VDD6) and VSFB1 voltage will follow VSOUT1 based on the use case, directly (for unity gain) or via resistor divider (tracking mode gain or non-tracking mode output voltage adjusting). (20) Protection of VSOUT1 Sensor Supply. Only VSOUT1 switch-offs off. (21) VBATP_UVoff and VBATP_UVon are the threshold levels for VBATP where UV will be indicated by the VBAT_UV bit in VMON_STAT_1 register. The VBATP level that will allow device power up is outlined by R1.1. (22) Brings device into the RESET state and sets flag in SPI (23) Clears flag in SPI 34 Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Electrical Characteristics (continued) Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and with VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted) POS PARAMETER TEST CONDITIONS 3.3-V setting 6.12 VDD3/5 undervoltage level MIN TYP MAX 3 3.17 4.5 4.85 VBATP = VBAT_SAFING UNIT V 5-V setting VDD3/5_UV 6.12a 6.13 Hysteresis VDD3/5_UVhead 3.3-V setting 100 5-V setting 140 VBATP = VBAT_SAFING VDD3/5 undervoltage headroom (VDD3/5act – VDD3/5_UVact) VBATP = VBAT_SAFING VDD5_3 overvoltage level VBATP = VBAT_SAFING 6.14 mV 3.3-V setting 155 5-V setting 200 3.3-V setting 3.43 3.6 5.2 5.5 mV V 5-V setting VDD3/5_OV Hysteresis 3.3-V setting 100 5-V setting 140 VBATP = VBAT_SAFING 6.14a mV 3.3-V setting 170 5-V setting 200 VDD3/5 undervoltage headroom (VDD3/5_OVact – VDD3/5act) VBATP = VBAT_SAFING VDD1 undervoltage level VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) 6.16a Hysteresis VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) 6.17 VDD1 overvoltage level VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) Hysteresis VBATP = VBAT_SAFING. Sensed on VDD1_SENSE pin. Relative thresholds are with respect to nominal 800-mV VDD1SENSE (Pos 4.2) 6.15 VDD3/5_UVhead 6.16 VDD1_UV mV 752 784 10 816 mV mV 848 mV VDD1_OV 6.17a 9 mV Sensed on VSFB1 pin. Relative thresholds (ratio) are: 6.19 VSOUT1_UV VSOUT1 undervoltage level • For non-tracking mode, with respect to nominal 2.5-V VSFB1 (Pos 5.3) • For tracking mode, with respect to voltage applied on VTRACK1 pin • In tracking mode, VSOUT1_UV comparator output is valid for VTRACK1 DC condition 0.88 0.94 VSOUT 1 1.06 1.12 VSOUT 1 Sensed on VSFB1 pin. Relative thresholds (ratio) are: 6.20 VSOUT1_OV VSOUT1 overvoltage level • For non-tracking mode, with respect to nominal 2.5-V VSFB1 (Pos 5.3) • For tracking mode, with respect to voltage applied on VTRACK1 pin • In tracking mode, VSOUT1_OV comparator output is valid for VTRACK1 DC condition VDD6 undervoltage level (24) 6.22 5.2 5.4 V VDD6_UV 6.22a Hysteresis 115 VDD6 overvoltage level (24) 6.23 7.8 mV 8.2 V VDD6_OV 6.23a Hysteresis 115 mV IGNITION AND CAN WAKE-UP 7.1 IGN_WUP IGN wake-up threshold (25) VBATP = VBAT_SAFING =12 V 2 3 7.2 CAN_WUP CAN wake-up threshold (25) VBATP = VBAT_SAFING =12 V 2 3 7.3 WUP_hyst Wake-up hysteresis VBATP = VBAT_SAFING =12 V 50 200 mV 7.4 I_IGN IGN pin forward leakage current IGN pin at 36 V, VBATP = VBAT_SAFING = 12V 50 µA 7.5 I_IGN_rev IGN reverse current IGN at –7 V, VBATP = VBAT_SAFING =12 V 7.7 I_CANWU CANWU pin forward leakage current CANWU pin at 36 V, VBATP = VBAT_SAFING = 12V 7.8 I_CAN_rev CANWU reverse current CANWU at –0.3 V, VBATP = VBAT_SAFING =12 V –1 V V mA 50 µA mA CHARGE PUMP AN Cpump Pumping capacitor (between CP1 and CP2) AN Cstore Storage capacitor (between VCP and VBATP) 10 8.1 VCPon VCP output voltage in on-state VBATP > 5.8 V 8.2 ICP External load Load coming from RGS of Reverse Battery Protection nF 100 VBATP + 4 nF VBATP + 15 V 100 µA (24) Information in SPI register only (25) For device wake up, VBATP and VBAT_SAFING must be operating range, Recommended Operating Conditions R1.1 and R1.3a, and then a level on either IGN or CANWU to allow the device to start up, especially when VBATP and VBAT_SAFING are ramping. Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 35 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Electrical Characteristics (continued) Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and with VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted) POS 8.3 PARAMETER fCP TEST CONDITIONS Charge-pump switching frequency MIN TYP MAX UNIT 225 250 275 kHz RESET AND ENABLE OUTPUTS 9.1 VNRES_ENDRV_L NRES / ENDRV low-output level 9.2 RNRES_ENDRV_PULLUP NRES / ENDRV internal pullup resistance With external 2-mA open-drain current 9.2a RDS(on)_ENDRV_NRES RDS(on) NRES/ENDRV pulldown transistor 9.3 RRSTEXT Value of external reset extension resistor, in case of open-connect, device stays in RESET state (26) 9.5 VENDRV_NRES_TH ENDRV and NRES input readback logic 1 threshold 3 Read-back muxed to DIAG_OUT pin 0 22 350 400 0.2 V 6 kΩ 40 Ω kΩ 450 mV DIGITAL INPUT / OUTPUT VDIGIN_HIGH Digital input, high level for NCS, SDI, SCLK, ERROR/WDI and SEL_VDD3/5 10.2 VDIGIN_LOW Digital input, low level for NCS, SDI, SCLK, ERROR/WDI and SEL_VDD3/5 10.3 VDIGIN_HYST Digital input hysteresis for NCS, SCI, SCLK and ERROR/WDI (27) 10.1 2 V 0.8 0.1 10.4 RDIAGOUT_AMUX Output resistance at DIAG_OUT pin in AMUX mode BG1 selected on AMUX, < 200 nA current in or out of DIAG_OUT pin 10.5 VDIGOUT_HIGH Digital output, high level (28) IOUT = –2 mA (out of pin) 10.6 VDIGOUT_LOW Digital output, low level (28) IOUT = 2 mA (into pin) V V 15 VDDIO – 0.2 kΩ V 0.2 V SERIAL PERIPHERAL INTERFACE 13.12 RPULL_UP Internal pullup resistor on NCS input pin 40 70 100 kΩ 13.13 RPULL_DOWN Internal pulldown resistor on SDI and SCLK input pins 40 70 100 kΩ (26) The maximum resistance recommend for RSTEXT to ground is 120 kΩ. (27) SEL_VDD3/5 is sampled and latched at device power up hysteresis, VDIGIN_HYST , does not apply. (28) For pins SDO and DIAG_OUT in DMUX mode. 4.6 Timing Requirements Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in the Section 4.3) (unless otherwise noted) POS MIN NOM MAX UNIT VDD5 – LDO WITH INTERNAL FET 2.12 tdelayVDD5 VDD5 voltage stabilization delay Maximum delay between rising edge on CANWU pin until VDD5 reaches the end-value within 2% 5 ms Maximum delay after CANWU wakeup for VDD3/5 output to settle 5 ms Maximum delay after CANWU wakeup for VDD1 output to settle 5 ms 260 µs VDD3/5 – LDO WITH INTERNAL FET 3.12 tVDD3/5 VDD3/5 voltage stabilization delay VDD1 – LDO WITH EXTERNAL FET 4.15 tdelayVDD1 VDD1 voltage stabilization delay VOLTAGE MONITORING 6.7 VBATP_deglitch VBATP undervoltage and overvoltage monitor deglitch time 6.18 VDDx_deglitch VDDx undervoltage and overvoltage monitor deglitch time 10 40 µs 6.21 VSOUT1_deglitch VSOUT1 undervoltage and overvoltage monitor deglitch time 10 40 µs 180 240 (1) IGNITION AND CAN WAKE-UP (IGN AND CANWU) 7.6 IGN_deg IGN deglitch filter time 7.5 22 ms 7.9 CANWU_deg CANWU deglitch filter time 100 350 µs RESET AND ENABLE OUTPUTS 9.4 tRSTEXT(22kΩ) Reset extension delay 22 kΩ 4.05 4.5 4.95 ms 9.4a tRSTEXT(0kΩ) Reset extension delay 0 kΩ 0.98 1.4 1.89 ms INTERNAL SYSTEM CLOCK (1) 36 240 µs for VBAT-UV deglitch and 260 µs for VBAT-OV deglitch Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Timing Requirements (continued) Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in the Section 4.3) (unless otherwise noted) POS 11.1 ƒSysclk System clock frequency MIN NOM MAX UNIT 3.8 4 4.2 MHz 14.25 30 32 µs (2) WINDOW WATCHDOG 12.2 Deglitch time on ERROR/WDI pin for watchdog-trigger input signal tWD_pulse SERIAL PERIPHERAL INTERFACE TIMING (3) 5 (4) VDDIO = 3.3 V 13.1 ƒSPI SPI clock (SCLK) frequency tSPI SPI clock period 13.3 thigh High time: SCLK logic high duration 85.7 ns 13.4 tlow Low time: SCLK logic low duration 45 ns 13.5 tsucs Setup time NCS: time between falling edge of NCS and rising edge of SCLK 45 ns 13.7 tsusi Setup time at SDI: setup time of SDI before the falling edge of SCLK 15 ns 13.9 thcs Hold time: time between the falling edge of SCLK and rising edge of NCS 45 ns thlcs SPI transfer inactive time (time between two transfers) during which NCS must remain high 788 ns 13.2 13.10 (2) (3) (4) MHz VDDIO = 5 V 6 VDDIO = 3.3 V 200 VDDIO = 5 V 167 ns See Figure 4-2 The system clock is also used to derive the clock for the watchdog timer, so the system clock tolerance also impacts the watchdog-timer tolerance. Capacitance at CSDO = 100 pF MAX SPI Clock tolerance is ±10% 4.7 Switching Characteristics Over operating ambient temperature TA = –40°C to the maximum-operating junction temperature TJ = 150°C, and VBATP = VBAT_SAFING in the recommended operating range (see R1.2 in Section 4.3) (unless otherwise noted) POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 53.3 ns 85.7 ns 53.3 ns Serial Peripheral Interface Timing (1) 13.6 td1 Delay time: time delay from falling edge of NCS to SDO transitioning from tri-state to 0 13.8 td2 Delay time: time delay from rising edge of SCLK to data valid at SDO 13.11 ttri Tri-state delay time: time between rising edge of NCS and SDO in tri-state (1) See Figure 4-2 0 Capacitance at CSDO = 100 pF NCS thlcs thcs tsucs SCLK tsucs thigh tlow SDI tsusi tsusi SDO td1 td2 ttri td1 td2 Figure 4-2. SPI Timing Parameters Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 37 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com 3.5 VDD-VOH (VDDIO 3.3 V) VOL (VDDIO 3.3 V) VDD-VOH (VDDIO 5 V) VOL (VDDIO 5 V) 3 VOH / VOL (V) 2.5 2 1.5 1 0.5 0 0 5 10 15 20 25 IOH / IOL (mA) 30 35 40 C001 Figure 4-3. SPI SDO Buffer Source and Sink Current 4.8 Typical Characteristics 100 90 80 Efficiency (%) 70 60 50 40 30 20 10 VBAT = 7 V VBAT = 13.8 V VBAT = 28 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 Load Current (A) D001 Figure 4-4. VDD6 BUCK Efficiency 38 Specifications Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 5 Detailed Description 5.1 Overview The device integrates an asynchronous-buck switch mode power-supply converter with an internal FET that converts the input battery voltage to a 6-V preregulator output, which supplies the integrated regulators. A fixed 5-V linear regulator with an internal FET is integrated to be used as, for example, a CAN supply. A second linear regulator, also with an internal FET, regulates the 6 V to a selectable 5-V or 3.3-V MCU I/O voltage. A linear regulator controller with an external FET and resistor-divider regulates the 6 V to an externally adjustable core voltage of between 0.8 V and 3.3 V. A linear regulator with two different modes of operation (tracking mode and non-tracking mode) with adjustable voltage between 3.3 V and 9.5 V can be used as a supply for external sensor. The device monitors undervoltage and overvoltage on all regulator outputs, battery voltage, and internal supply rails. A second band-gap reference, independent from the main band-gap reference used for regulation circuit, is used for undervoltage and overvoltage monitoring. In addition, regulator current-limits and temperature protections are implemented. The device supports wakeup from IGNITION or wakeup from a CAN transceiver. 5.2 Functional Block Diagram VDD6 6V KL30 (Battery) VDD5 5 V, 300 mA VDD3/5 3.3 or 5 V, 300 mA VDD1 0.8 to 3.3 V, 600 mA Schottky VBATP VDD6 VDD1_G VDD1_SENSE VDD3/5 SEL_VDD3/5 VDD5 VDD6 SDN6 CP1 VBATP Schottky CP2 VCP ESR GND or NoConnect GND VDD6 LDO Internal FET Buck Internal FET Charge Pump LDO Internal FET LDO Controller VBAT_SAFING VBATP VBATP or VDD6 3.3 to 9.5 V, 100 mA Bias and Internal Supply VSIN VSOUT1 Bandgap Reference 1 Voltage Monitoring Bandgap Reference 2 RES Ext Sensor LDO Protected Int. B2B FET Oscillator 1 VSFB1 TJ Oscillator Overtemperature Monitor shutdown EEPROM CRC RSTEXT Digital State Machine VTRACK1 Monitoring and Protection IGN NCS SDI SDO WakeUp CANWU Reference/Bias SPI Interface SCLK Diagnostics MCU ERROR Monitor (ESM) or Window Watchdog VDDIO Power Supply Q&A Watchdog ERROR/WDI Bandgap 1 Bandgap 2 Reset and Enable ENDRV Diagnostics NRES DIAG_OUT Analog Mux VDD5, VDD3/ 5 or GND VDD5 or VDD3/5 Copyright © 2017, Texas Instruments Incorporated Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 39 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 5.3 5.3.1 www.ti.com Feature Description VDD6 Buck Switch-Mode Power Supply The purpose of the VDD6 buck switch-mode power supply is to reduce the power dissipation inside the device as a preregulator. The VDD6 supply regulates from the battery voltage (main supply) range to 6 V. The VDD6 output is used as the input voltage for the VDD5, VDD3/5, VDD1, and can also be used for VSOUT1 regulator depending on the required VSOUT1 output voltage. The VDD6 supply is intended as a preregulator, therefore the output accuracy of VDD6 is less than the other integrated regulators. The VDD6 current capability is set to supply the VDD5, VDD3/5, VDD1, and VSOUT1 regulators at their respective maximum output currents. Power dissipation and thermal analysis should be performed to ensure the PCB design and thermal management can support the required power dissipation in the application. This switch-mode power supply operates with fixed-frequency adaptive on-time control PWM. The control loop is based on a hysteretic comparator. The internal N-channel MOSFET is turned on at the beginning of each cycle if the sensed voltage on the VDD6 pin is below the hysteretic comparator threshold. When the MOSFET is turned on, it is on for a minimum of 7% duty cycle (7% of fclk_VDD6). This MOSFET is turned off when the hysteretic comparator detects a voltage on the VDD6 pin above the threshold. The VDD6 regulator may skip pulses if the output voltage remains above the hysteretic comparator when the clock edge occurs. When the MOSFET is turned off, the external Schottky diode recirculates the energy stored in the inductor for the remainder of the switching period. The VDD6 regulator enters dropout mode (100% duty cycle) for a supply voltage below approximately 7 V on the VBATP pin. The internal MOSFET is protected from excessive power dissipation by a current-limit circuit. The VDD6 regulator also shares an overtemperature protection circuit with the VDD3/5 regulator. When overtemperature is detected by this circuit, the device transitions to the STANDBY state (all regulators switched off). Because the control loop of the VDD6 regulator is based on a hysteretic comparator, the effective capacitance on the output, and effective series resistance (ESR) of the output capacitance must be considered. The effective capacitance of the output capacitors at the operating voltage (6 V, DC bias derating), tolerance, temperature range, and lifetime must meet the effective capacitance range for VDD6 (CVDD6). The capacitor supplier should provide the necessary derating data to calculate the effective capacitance. The hysteretic comparator also requires a specified ESR to ensure balanced operation. Typically low-ESR ceramic capacitors are used for the output, so an external resistor is required to bring the total ESR into the specified ESR range for the CVDD6. A general guideline to achieve balanced operation is RESR = L / (15 × CEffective). Using a higher-effective output capacitance allows for a lower ESR, which leads to lower-voltage ripple. Additionally, the inductance influences the system: using a lower inductance value allows for lower ESR, however, the peak inductor current will be higher. 5.3.2 VDD5 Linear Regulator The VDD5 pin is a regulated supply of 5 V ±2% overtemperature and battery supply range. A low-ESR ceramic capacitor is required for loop stabilization. This capacitor must be placed close to the pin of the device. This output is protected against shorts to ground by a current-limit. This output also limits outputvoltage overshoot during power up and during line or load transients. On an initial IGN or CANWU power cycle, the soft-start circuit on this regulator is initiated, which is typically from 1 ms to 2 ms. This output can require a larger output capacitor to ensure that during load transients the output does not drop below the required regulation specifications. The internal MOSFET is protected from excess power dissipation with junction-overtemperature protection. In case of an overtemperature condition in the VDD5 pin, only the VDD5 regulator switches off by clearing bit D4 in the SENS_CTRL register. To re-enable the VDD5 pin, bit D4 in the SENS_CTRL register must be set again. 40 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com 5.3.3 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 VDD3/5 Linear Regulator The VDD3/5 pin is a regulated supply of 3.3 V or 5 V ±2% overtemperature and battery supply range. The output voltage level is selected with the SEL_VDD3/5 pin (open pin selects 3.3 V, grounded pin selects 5 V). The state of this selection pin is sampled and latched directly at the first initial IGN or CANWU power cycle. When latched, any change in the state of this selection pin after the first initial IGN or CANWU power cycle does not change the initially selected state of the VDD3/5 regulator. A low-ESR ceramic capacitor is required for loop stabilization. This capacitor must be placed close to the pin of the device. This output is protected against shorts to ground by a current-limit. This output also limits output-voltage overshoot during power up or during line or load transients. On an initial IGN or CANWU power cycle, the soft-start circuit on this regulator is initiated, which is typically from 1 ms to 2 ms. This output may require a larger output capacitor to ensure that during load transients the output does NOT drop below the required regulation specifications. The internal MOSFET is protected from excess power dissipation with a current-limit circuit and junction overtemperature protection. In case of an overtemperature in the VDD3/5 pin, the TPS65381-Q1 device enters the STANDBY state (all regulators switched-off). 5.3.4 VDD1 Linear Regulator The VDD1 pin is an adjustable regulated supply from 0.8 V to 3.3 V. This regulator uses a ±2% reference (VDD1SENSE). The tolerance of the external feedback resistor divider resistors have an impact to the overall VDD1 regulation tolerance. To reduce on-chip power consumption, an external power NMOS is used. The regulation loop and the command gate drive are integrated. TI recommends applying a resistor with a value of 100 kΩ to 1 MΩ between the gate and source of the external power NMOS. The VDD1 gate output is limited to prevent gate-source overvoltage stress during power up or during line or load transients. On an initial IGN or CANWU power cycle, the soft-start circuit on this regulator is initiated, which is typically from 1 ms to 2 ms. This soft-start is meant to prevent any voltage overshoot at start-up. The VDD1 output may require larger output capacitor to ensure that during load transients the output does not drop below the required regulation specifications. The VDD1 LDO has no current-limit and no overtemperature protection for the external NMOS FET. Therefore, supplying the VDD1 pin from the VDD6 pin is recommended (see Section 5.2). In this way, the VDD6 pin current-limit acts as current-limit for the VDD1 pin and the power dissipation is limited also. To avoid damage in the external NMOS FET, selecting the current rating of the VDD1 pin well above the maximum-specified VDD6 current-limit is recommended. If the VDD1 regulator is not used, leave the VDD1_G and VDD1_SENSE pins open. An internal pullup device on the VDD1_SENSE pin detects the open connection and pulls up the VDD1_SENSE pin. This forces the regulation loop to bring the VDD1_G output down. This mechanism also masks the VDD1_OV flag in VMON_STAT_2 register and therefore the ENDRV pin action from a VDD1 overvoltage (OV) condition is also masked. These actions are equivalent to clearing the NMASK_VDD1_UV_OV bit in the DEV_CFG1 register to 0. This internal pullup device on the VDD1_SENSE pin also prevents a real VDD1 overvoltage on the MCU core supply in case of an open connection to the VDD1_SENSE pin, as it brings the VDD1_G pin down. Therefore, in this situation, the VDD1 output voltage is 0 V. By default, VDD1 monitoring is disabled. If the VDD1 pin is used in the application, TI recommends to set the NMASK_VDD1_UV_OV bit in the DEV_CFG1 register to 1 when the device is in the DIAGNOSTIC state. This setting enables driving and extending the reset to the external MCU when a VDD1 undervoltage event is detected. Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 41 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 5.3.5 www.ti.com VSOUT1 Linear Regulator The VSOUT1 regulator is a regulated supply with two separate modes: tracking mode and non-tracking mode. The mode selection occurs with the VTRACK1 pin. When the voltage applied on the VTRACK1 pin is above 1.2 V, the VSOUT1 pin is in tracking mode. When the VTRACK1 pin is shorted to ground, the VSOUT1 regulator is in non-tracking mode. This mode selection occurs during the first ramp-up of the VDDx rails and is latched after the first VDDx ramp-up is complete. Therefore, after completion of the VDDx ramp-up, any change on the VTRACK1 pin no longer affects the selected tracking or non-tracking mode. In tracking mode, the VSOUT1 regulator tracks the input reference voltage on the VTRACK1 pin with a gain factor determined by the external resistive divider. The tracking offset between the VTRACK1 and VSFB1 pins is ±35 mV. This mode allows, for instance, the VSOUT1 output voltage to be 5 V while tracking the VDD3 (3.3-V) supply. In unity-gain feedback, the VSOUT1 output voltage can directly follow the VDD5 pin or the VDD3 pin. In non-tracking mode, the VSOUT1 output voltage is proportional to a fixed reference voltage of 2.5 V at the VSFB1 pin, with a gain factor determined by the external resistive divider. This mode allows the VSOUT1 pin to be any factor of the internal reference voltage. Both in tracking and non-tracking mode, the VSOUT1 output voltage must be 3.3 V or higher. The VSOUT1 regulator can track the VDD3/5 pin in 3.3-V setting within the specified limits. The VSOUT1 regulator has a separate input supply to reduce the internal power dissipation. For an output voltage of 3.3 V or 5 V, for instance, the VDD6 supply can be used as the input supply. For an output voltage greater than 5 V, the VBATP pin can be used as the input supply. The maximum power dissipation for the internal FET must not exceed 0.6 W to avoid overtemperature (thermal shutdown). A low-ESR ceramic capacitor is required for loop stabilization; this capacitor must be placed close to the pin of the device. This supply limits output-voltage overshoot during power up or during line or load transients. This supply rail is intended for going outside the ECU and therefore is protected against shorts to external chassis ground by a current-limit. The supply rail can be shorted externally within the specified short circuit voltages, VSOUT1SH. If the output can be shorted to voltages outside the specified short circuit voltage range, additional external protection is required. The VSOUT1 regulator is disabled by default on start-up. After the NRES pin release, the MCU can enable the VSOUT1 regulator through a SPI command by setting bit D0 in the SENS_CTRL register. After this SPI command, the soft-start circuit on this regulator is initiated, which is typically from 1 ms to 2 ms. This output may require a larger output capacitor to ensure that during load transients the output does NOT drop below the required regulation specifications. Regardless of tracking or non-tracking mode, the VSFB1 pin is ramped to the desired value after completion of the soft start. The internal MOSFET is protected from excess power dissipation with a current-limit circuit and junctionovertemperature protection. In case of an overtemperature condition in the VSOUT1 pin, only the VSOUT1 regulator is switched off by clearing bit 0 in the SENS_CTRL register. To re-enable the VSOUT1 pin, first bit 2 in the SAFETY_STAT 1 register must be cleared on read-out, and afterwards bit 0 in the SENS_CTRL register must be set again. The VSOUT1 pin voltage can be observed by the ADC input of the MCU through the DIAG_OUT pin (see Section 5.4.9), which allows the detection of a short to any other supply prior to enabling the VSOUT1 LDO. 42 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 NOTE The VSOUT1_EN bit is in the SENS_CTRL register which is only reinitialized by a power-on reset (NPOR) event and not a transition through the RESET state. If the VSOUT1_EN bit was previously set to 1, it remains set to 1 and the VSOUT1 regulator remains enabled after events that cause a transition to the RESET state. In a fault case that would cause an undervoltage or overvoltage on the VSOUT1 pin, when a BIST runs automatically on the transition from the RESET to the DIAGNOSTIC state, the VSOUT1_UV or VSOUT1_OV condition during the BIST run would cause the device to go to the SAFE state because of the detected ABIST_ERR. 5.3.6 Charge Pump The charge pump is used to generate an overdrive voltage from the VBATP supply that is used for driving the gates of the internal NMOS FETs in the VDDx and VSOUT1 supply rails. The charge pump is a hysteretic architecture, when the VCP voltage is high enough, the CP_OV bit sets and the charge pump stops pumping until the VCP voltage drops below the threshold, the CP_OV bit clears and the charge pump starts pumping again. The charge pump overdrive is provided internally to the device through the linear regulators, VCP12 and VCP17. Furthermore, this overdrive voltage can drive the gate of an external NMOS FET acting as reverse-battery protection. Such reverse-battery protection allows for lower battery voltage operation compared to a traditional reverse battery-blocking diode. When using the charge pump (VCP) to drive the gate of an NMOS for reverse battery protection, a series resistance of about 10 kΩ must be connected between the VCP pin and the gate of the NMOS FET (see Section 5.2). This series resistance is required to limit any current out of the VCP pin when the gate of the NMOS FET is driven to a negative voltage, because the absolute maximum rating of the VCP pin is limited to –0.3 V because of a parasitic reverse diode to the substrate (ground). The charge pump requires two external capacitors, one pumping capacitor (Cpump) and one storage capacitor (Cstore). To have sufficient overdrive voltage out of the charge pump even at low battery voltage, the external load current on the VCP pin must be less than 100 µA. 5.3.7 Wake-Up The TPS65381-Q1 device has two wake-up pins: IGN and CANWU. Both pins have a wake-up threshold level from 2 V to 3 V, and a hysteresis from 50 mV to 200 mV. The IGN wake-up pin is level-sensitive and is deglitched with the IGN_deg deglitch (filter) time. The TPS65381-Q1 device provides a power-latch function (POST_RUN) for this IGN pin, allowing the MCU to decide when to power down the TPS65381-Q1 device through SPI command. For this, the MCU must set the IGN power-latch bit 4 (IGN_PWRL) in the SPI SAFETY_FUNC_CFG register, and read the unlatched status of the deglitched (filtered) IGN pin on the SPI register, DEV_STAT, bit 0 (IGN). To enter the STANDBY state, the MCU must clear the IGN_PWRL bit. For this, the TPS65381-Q1 device must be in the DIAGNOSTIC state because this SPI register is only writable in the DIAGNOSTIC state. The IGN_PWRL bit is also cleared after a detected CANWU wake-up event. Furthermore, the TPS65381-Q1 device provides an optional transition to the RESET state after a detected IGN wake-up during POST_RUN (see Figure 5-2). The CANWU pin is level sensitive and is deglitched with CANWU_deg (filter) time. The deglitched (filtered) CANWU wake-up signal is latched, into CANWU_L, allowing the MCU to decide when to power down the TPS65381-Q1 device through the WR_CAN_STBY SPI command. NOTE The WR_CAN_STBY command should not be written to the device while the CANWU pin or IGN pin is still high. The device starts to transition to the STANDBY state and immediately transitions to the RESET state because of the wake-up request received on the CANWU or IGN pin. The registers are reinitialization according to post LBIST (because of a RESET transition) or according to NPOR (because of a STANDBY transition). Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 43 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Both the IGN and CANWU pins are high voltage pins. If the pins are connected to lines with transients, the application should provide proper filtering and protection to ensure the pins stay within the specified voltage range. NOTE If the application does not require wake up from IGN (ignition or KL15) or wake up from CANWU (a CAN or other transceiver), but the device should wake up any time power is supplied, one method is to connect the IGN pin to the VBATP pin (and VBAT_SAFING) through a 10-kΩ or greater series resistor. When the VBATP supply is turned on, the IGN pin also goes high and allows the device to wake up (power up) as soon as the voltage levels allow the release of NPOR circuits for the VBATP and VBAT_SAFING pins, and the IGN pin is high. 5.3.8 Reset Extension During a power-up event, the TPS65381-Q1 device releases the reset to the external MCU through the NRES pin with a certain delay time (reset extension time) after the VDD3/5 and VDD1 pins have crossed the respective undervoltage thresholds. This reset extension time is externally configurable with a resistor between the RESEXT pin and ground. When shorting the RESEXT pin to ground, the minimum reset extension time is typically 1.4 ms. For a 22kΩ external resistor, the typical reset extension time is 4.5 ms. 44 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com 5.4 5.4.1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Device Functional Modes Power-Up and Power-Down Behavior Figure 5-1 shows the power-up and power-down behavior. IGN 7.5-ms (min) to 22-ms (max) deglitch time 7.5-ms (min) to 22-ms (max) deglitch time OR CANWU Min.350-µs pulse width SPI OR WR_CAN _STBY x x 1-ms (typical) start-up delay VCP < 200-µs start-up time VBATP + 12 V VCP is turned-off approximately 5 ms after NRES is driven low VCP_UV VBATP - Vdiode Note: The actual rampdown time of VCP depends on external load conditions VDD6 6V VDD6 is turned-off approximately 5 ms after NRES is driven low VDD6_UV level VDD5, VDD3/5, VDD1 Note: Device turns off all internal biasing for low-Iq when NRES is driven LOW 3 V 010b 0111b D3.9 DFT Signal reserved for production test 010b 1000b D3.10 NVBAT_UV VBAT undervoltage comparator (inverted) 010b 1001b D3.11 VBATP_OV VBAT overvoltage comparator 010b 1010b D3.12 VDD5_OT VDD5 overtemperature 010b 1011b D3.13 VDD3/5_OT VDD3/5 overtemperature 010b 1100b D3.14 VSOUT1_OT VSOUT1 overtemperature 010b 1101b D3.15 VDD5_CL VDD5 current-limit 010b 1110b D3.16 VDD3_CL VDD3 current-limit 010b 1111b Table 5-8. Digital MUX Selection Table – Group 4 SIGNAL NUMBER SIGNAL NAME DESCRIPTION CHANNEL GROUP DIAG_MUX_SEL [6:4] CHANNEL NUMBER DIAG_MUX_SEL [3:0] D4.1 RSV Reserved, logic 0 011b 0000b D4.2 VSOUT1_CL VSOUT1 current-limit 011b 0001b D4.3 NVSOUT1_UV VSOUT1 undervoltage comparator (inverted) 011b 0010b D4.4 VSOUT1_OV VSOUT1 overvoltage comparator 011b 0011b D4.5 NDVDD_UV DVDD undervoltage comparator (inverted) 011b 0100b D4.6 DVDD_OV DVDD overvoltage comparator 011b 0101b D4.7 RSV Reserved 011b 0110b D4.8 VS_TRK_MODE VSOUT1 in track-mode indication 011b 0111b D4.9 VMON_TRIM_ERR VMON trim error 011b 1000b D4.10-16 RSV Reserved 011b 1001b-1111b CHANNEL GROUP DIAG_MUX_SEL [6:4] CHANNEL NUMBER DIAG_MUX_SEL [3:0] 0000b Table 5-9. Digital MUX Selection Table – Group 5 SIGNAL NUMBER SIGNAL NAME DESCRIPTION D5.1 RSV Reserved, logic 0 111b D5.2 TI_TEST_MODE TI production test mode indication 111b 0001b D5.3-16 DFT Signal reserved for production test 111b 0010b-1111b Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 59 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com A diagnostic check at the SDO digital-output pin is also possible in DMUX mode. For this diagnostic check, the following sequence is required: 1. The MUX_CFG[1:0] configuration must be set to 01b for DIGITAL MUX mode. 2. The SPI NCS must be kept HIGH. 3. The state of the SDO pin is controlled by the SPI_SDO bit (bit D6 in the DIAG_CFG_CTRL register). During this SDO check at the SDO pin, the DIAG_OUT pin is kept low if no signal from the Digital MUX Selection table is selected. 5.4.9.3 Diagnostic MUX Output State (by MUX_OUT bit) For a diagnostic interconnect check between the DIAG_OUT pin and the MCU analog-digital input pin, the state of the DIAG_OUT pin is controlled with the SPI bit, MUX_OUT, in the DIAG_CFG_CTRL register. To use this mode, the MUX_CFG[1:0] bits must be set to 00b in the DIAG_CFG_CTRL register. 5.4.9.4 MUX Interconnect Check For performing a diagnostic interconnect check at the digital input pins (ERROR/WDI, NCS, SDI, and SCLK), the MUX_CFG[1:0] bits in the DIAG_CFG_CTRL register must be set to 11b. The INT_CON[2:0] bits in the DIAG_CFG_CTRL register can select which of these digital inputs to be multiplexed to the DIAG_OUT pin (see the description of DIAG_CFG_CTRL register in Section 5.5.1). 5.4.10 Watchdog Timer (WD) The watchdog monitors the correct operation of the MCU. This watchdog requires specific triggers, or messages, from the MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic level of the ENDRV pin with the ENABLE_DRV bit when the watchdog detects correct operation of the MCU. When the watchdog detects incorrect operation of the MCU, the device pulls the ENDRV pin low. This ENDRV pin can be used in the application as a control signal to deactivate the power output stages, for example a motor driver, in case of incorrect operation of the MCU. This function is consequently referred to as the watchdog-enabled function. The watchdog has two different modes, which are defined as follows: Trigger mode: In trigger mode, the MCU applies a trigger (pulse) on the ERROR/WDI pin to send the required watchdog event for trigger mode. The watchdog operates in trigger mode as the default mode when the device goes from the RESET state to the DIAGNOSTIC state. The MCU error signal monitor (ESM) should not be used when the watchdog operates in trigger mode. Question-answer mode (Q&A mode): In Q&A mode, the MCU sends watchdog answers through SPI. To select the Q&A mode, the MCU must set the WD_CFG bit (bit 5) in the safety-function configuration register (SAFETY_FUNC_CFG) while in the DIAGNOSTIC state. When the watchdog operates in Q&A mode, the MCU error signal monitor (ESM) may be used. 5.4.11 Watchdog Fail Counter, Status, and Fail Event The watchdog includes a watchdog fail counter (WD_FAIL_CNT[2:0]) which increments because of bad events or decrements because of good events. When the value of the watchdog fail counter is 5 or more, the watchdog status is out-of-range and the ENDRV pin is low (the watchdog-enabled function is disabled). When the watchdog fail counter is 4 or less, the watchdog status is in-range and the watchdog no longer disables the watchdog-enabled function. In this case, the device pulls up the ENDRV pin when the ENABLE_DRV control bit (in the SAFETY_CHECK_CTRL register) is set and when the device detects no other errors that impact the level of the ENDRV pin. The watchdog fail counter operates independently of the state of the watchdog reset configuration bit (bit 3), WD_RST_EN, in the SAFETY_FUNC_CFG register. 60 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 The watchdog fail counter responds as follows: • A good event decrements the fail counter by one, down to the minimum of zero. • A bad event increments the fail counter by one, up to the maximum of seven. • A time-out event increases the fail counter by one, up to the maximum of seven, and sets the TIME_OUT flag (WD_STATUS register, bit 1). The definitions of good event, bad event and time-out event are listed Section 5.4.14 and Section 5.4.15. VDDIO 4.5 k ENABLE_DRV Bit (SAFETY_CHECK_CTRL Register) SPI Bus or ERROR/WDI Pin Watchdog Event (Trigger or Q&A Mode) ENDRV Pin ENABLE_DRV Watchdog Status WD_FAIL_CNT[2:0] > 4 Good Event (-1) Watchdog Fail Counter Bad Event (+1) WD_RST_EN Bit (SAFETY_FUNC_CFG Register) Watchdog Status WD_FAIL_CNT[2:0] = 7 + 1 Go to RESET State WD_RST_EN Status Figure 5-5. Watchdog Impact on ENDRV and RESET Table 5-10. Watchdog Status for Range of the Watchdog Fail Counter Value WATCHDOG FAIL COUNTER WD_FAIL_CNT[2:0] The watchdog status is based on the WD_FAIL_CNT[2:0] value. 000b THROUGH 100b Watchdog in-range 101b THROUGH 111b Watchdog is out-of-range 111b If the WD_RST_EN bit is set to 1, the NRES pin is pulled low, the device is in the RESET state on next "bad" or "timeout" event to the watchdog The watchdog fail counter is initialized to a count of 5 when the device enters the DIAGNOSTIC state (after going through the RESET state) and when the device transitions from the DIAGNOSTIC state to the ACTIVE state. When the watchdog fail counter reaches a count of 7, another bad event does not change the counter: the counter remains at 7. However, if the watchdog reset is enabled (WD_RST_EN bit in the SAFETY_FUNC_CFG register is set to 1), on the next bad event or time-out event (7 + 1) the device enters the RESET state and resets the MCU by pulling the NRES pin low. In the RESET state, the watchdog fail counter reinitializes to 5. If the watchdog fail counter is at seven when the WD_RST_EN bit is set to 1, the device immediately enters the RESET state without requiring another bad event or time-out event. Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 61 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com 5.4.12 Watchdog Sequence Each watchdog sequence begins with a Window 1 followed by a Window 2. The MCU can program the time periods of Window 1 (tWIN1) and Window 2 (tWIN2) with the WD_WIN1_CFG and WD_WIN2_CFG registers respectively when the device is in the DIAGNOSTIC state. When the device goes from the RESET state to the DIAGNOSTIC state, the watchdog sequence begins with the default tWIN1 and tWIN2 time periods. Use Equation 1 and Equation 2 to calculate the minimum and maximum values for the tWIN1 time period. Use Equation 3 and Equation 4 to calculate the minimum and maximum values for the tWIN2 time period. tWIN1_MIN = [(RT[6:0] – 1) × 0.55 × 0.95] ms where • The bits RT[6:0] are located in the WD_WIN1_CFG SPI register. (1) tWIN1_MAX = (RT [6:0] × 0.55 × 1.05) ms where • The bits RT[6:0] are located in the WD_WIN1_CFG SPI register. (2) tWIN2_MIN = [(RW[4:0] + 1) × 0.55 × 0.95] ms where • The bits RW[4:0] are located in the WD_WIN2_CFG SPI register. (3) tWIN2_MAX = [(RW[4:0] + 1) × 0.55 × 1.05] ms where • The bits RW[4:0] are located in the WD_WIN2_CFG SPI register. (4) If the MCU stops sending events, or stops feeding the watchdog during the watchdog sequence, the watchdog considers this lack of response from the MCU a time-out event (no response event). This sets the TIME_OUT status bit (bit 1 in the WD_STATUS register) and increments the watchdog fail counter. Immediately following a time-out event the next watchdog sequence is started. Based on the Window 1 and Window 2 time periods, the watchdog sequence and time-out time periods are calculated as follows: tSEQUENCE_MIN = tTIMEOUT_MIN = tWIN1_MIN + tWIN2_MIN tSEQUENCE_MAX = tTIMEOUT_MAX = tWIN1_MAX + tWIN2_MAX (5) (6) The watchdog uses the internal system clock of the device (±5% accuracy) as a time reference for creating the 0.55-ms watchdog time step. WINDOW 1 may be up to one 0.55-ms watchdog time step shorter than programmed as indicated by Equation 1. NOTE Because of the uncertainty in the Window 1 and Window 2 time periods, TI recommends using settings for Window 1 and Window 2 of two or higher. Window 2 could be set as low as one, assuming Window 1 is set to six or lower. The response from the MCU should be targeted to the mid point of known timing for Window 2. As Window 1 setting is increased above six, the device system-clock tolerance (±5%) becomes large compared to a setting of one in Window 2 not allowing for a known time range for a response in Window 2, so Window 2 setting must be scaled with Window 1 to allow timing margin. 62 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 5.4.13 MCU to Watchdog Synchronization To synchronize the MCU with the watchdog sequence, the MCU can write to either the WIN1_CFG or WIN2_CFG registers to start a new watchdog sequence. After a write access to the WIN1_CFG or WIN2_CFG register by the MCU (even when these registers are locked or when the device is in the ACTIVE or the SAFE state), the device immediately starts a new watchdog sequence and increments the watchdog fail counter. Therefore a write access to the WD_WIN1_CFG or WD_WIN2_CFG register only takes effect in this new watchdog sequence. When the MCU is synchronized with the watchdog sequence, a good event from the MCU immediately starts a new watchdog sequence. In this way, the MCU stays synchronized with the watchdog sequence. See Figure 6-11 for an example software flowchart of how to synchronize the MCU with the TPS65381-Q1 watchdog. 5.4.14 Trigger Mode (Default Mode) When the device goes from the RESET state to the DIAGNOSTIC state, the watchdog operates in trigger mode (default). The first watchdog sequence begins with the default tWIN1 and tWIN2 time periods. The watchdog receives the triggers from the MCU on the ERROR/WDI pin. A rising edge on the ERROR/WDI pin, followed by a falling edge on the ERROR/WDI pin after more than the required pulse time, tWD_pulse(max) (32 μs), is a trigger. Even a waveform with a longer duration high than low is counted as a trigger if the rising and falling edges meet this requirement. Window 1, called a CLOSE window, is the first window in the watchdog sequence. A trigger received in Window 1 is a bad event and ends Window 1, starts a new watchdog sequence and sets ANSWER_EARLY flag. Window 2, called an OPEN window, follows Window 1. At a minimum, Window 2 lasts until a trigger is received. At a maximum, Window 2 lasts until the programmed tWIN2 time. A trigger received in Window 2 (OPEN) is a good event. A new watchdog sequence begins immediately after the watchdog receives a trigger in Window 2. If the MCU stops sending triggers during the watchdog sequence, the watchdog considers this lack of response from the MCU a time-out event (no response event). This sets the TIME_OUT status bit (bit 1 in the WD_STATUS register) and increments the watchdog fail counter. Immediately following a time-out event a new watchdog sequence is started. The TIME_OUT flag can be useful for the MCU software to resynchronize the watchdog trigger pulse events to the required device watchdog timing. When resynchronizing in this way, the MCU detects the TIME_OUT flag being set. The TIME_OUT flag being set indicates the time-out event and the start of a new watchdog sequence. The MCU should send the trigger with timing so the trigger is in Window 2 (OPEN) of this new watchdog sequence. NOTE If an active SPI frame (nCS is low) is present when the time-out event occurs, TIME_OUT flag is not latched (set) in the WD_STATUS register, but the watchdog counter still increments. Because the TIME_OUT flag is not latched, this impacts resynchronization ability of the MCU and status monitoring. It is recommended to use synchronization procedure outlined in section Section 5.4.13. the fail the the In trigger mode, the watchdog uses a deglitch filter with the tWD_pulse filter time and an internal system clock to create the internally generated watchdog pulse (see Figure 5-6 and Figure 5-7). The rising edge of the trigger on the ERROR/WDI pin must occur at least the tWD_pulse(max) time before the end of Window 2 (OPEN) to generate a good event. Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 63 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com The window duration times of Window 1 (CLOSE) and Window 2 (OPEN) are programmed through the WD_WIN1_CFG and WD_WIN2_CFG registers when the device is in the DIAGNOSTIC state. In trigger mode, the window duration time are as follows: tWCW_MIN (Trigger mode) = tWIN1_MIN where • WCW is a watchdog CLOSE window (7) tWCW_MAX (Trigger mode) = tWIN1_MAX where • WCW is a watchdog CLOSE window (8) tWOW_MIN (Trigger mode) = tWIN2_MIN where • WOW is a watchdog OPEN window (9) tWOW_MIN (Trigger mode) = tWIN2_MIN where • WOW is a watchdog OPEN window (10) Use Equation 1 and Equation 2 to calculate the minimum and maximum values for the tWIN1 = tWCW time period. Use Equation 3 and Equation 4 to calculate the minimum and maximum values for the tWIN2 = tWOW time period. Writing a new Window 1 or Window 2 time to the WD_WIN1_CFG or WD_WIN2_CFG register immediately begins a new watchdog sequence and increments the watchdog fail counter. A new watchdog sequence is started by a write even when WD_WIN1_CFG register and the WD_WIN2_CFG SPI register are locked because the device is not in DIAGOSTIC state or the SPI command SW_LOCK is blocking a write update to the register values. The watchdog trigger event is considered a good-event if received during a Window 2 (OPEN) window, and is considered a bad-event if received during Window 1 (CLOSE) window. A good-event ends the current watchdog sequence and starts a new watchdog sequence, therefore the MCU and device watchdog timing stay synchronized. A good-event, bad-event, time-out event, power-up event, or power-down event ends the current watchdog sequence and starts a new watchdog sequence. 64 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 RESET Extension BIST Run Time (Conf. With Time RESEXT) t = tWIN1 t < tWIN2 t = t WIN1 t < t WIN2 NRES (Reset to MCU) Decrement WD_FAIL_CNT[2:0] WD_FAIL_CNT[2:0]=4 WD_FAIL_CNT[2:0]=5 Watchdog Windows WINDOW 1 (CLOSE) WINDOW 2 (OPEN) Decrement WD_FAIL_CNT[2:0] WD_FAIL_CNT[2:0]=3 WINDOW 2 (OPEN) WINDOW 1 (CLOSE) Start New Watchdog Sequence WINDOW 1 (CLOSE) Start New Watchdog Sequence A A t > tWD_pulse t > tWD_pulse Trigger on ERROR/WDI Pin tWD_pulse tWD_pulse tWD_pulse tWD_pulse Internally Generated Watchdog Pulse Note: The deglitch time of the WD trigger on ERROR/WDI is tWD_pulse. tWD_pulse (min) = 28 µs and tWD_pulse (max) = 32 µs The rising edge of the external trigger signal must be no later than 32 µs before WINDOW 2 ends to ensure the deglitched signal occurs within WINDOW 2. A. Note: The external trigger signal may start in WINDOW 1, as long as the rising edge of the internally generated watchdog pulse (derived from the deglitched trigger on ERROR/WDI pin) is in WINDOW 2. When a good event is received in Window 2, 1 system clock-cycle (250 ns, typical) later the next watchdog sequence begins. Therefore the actual length of Window 2 depends on when the MCU sends the good event. Figure 5-6. Example Cases for Good-Events in Trigger Mode Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 65 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 NRES (Reset to MCU) RESET Extension BIST Run Time Time (Conf. With RSTEXT) www.ti.com t = tWIN1 RESET Extension Time (Conf. With RSTEXT) t = tWIN2 BIST Run Time t = t WIN1 or t < t WIN1 WD_FAIL_CNT[2:0]=5 WD_FAIL_CNT[2:0]=5 Watchdog Windows WINDOW 1 (CLOSE) WINDOW 2 (OPEN) WINDOW 1 (CLOSE) NRES = LOW When WD_FAIL_CNT[2:0] = 7+1 and WD_RST_EN = 1B A WINDOW 1 (CLOSE) Start New Watchdog Sequence Increment WD_FAIL_CNT[2:0] WD_FAIL_CNT[2:0]=6 C Increment WD_FAIL_CNT[2:0] WD_FAIL_CNT[2:0]=6 t > tWD_pulse Trigger on ERROR/WDI Pin tWD_pulse tWD_pulse Internally Generated Watchdog Pulse Case No. 1: Time-Out Event NRES (Reset to MCU) RESET Extension Time (Conf. With RSTEXT) BIST Run Time Watchdog Windows Case No. 2: Watchdog Trigger Event During WINDOW 1 (CLOSE) NRES = HIGH When WD_FAIL_CNT[2:0] = 7 AND WD_RST_EN = 0 or 1B t = t WIN1 or t < t WIN1 NRES = HIGH When WD_FAIL_CNT[2:0] = 7 + 1 AND WD_RST_EN = 0B t = t WIN1 t = t WIN2 t = t WIN1 t = t WIN2 WINDOW 1 (CLOSE) WINDOW 2 (OPEN) WINDOW 1 (CLOSE) WINDOW 2 (OPEN) WD_FAIL_CNT[2:0]=5 WINDOW 1 (CLOSE) Start New Watchdog Sequence t > tWD_pulse C Trigger on ERROR/WDI Pin tWD_pulse WINDOW 1 (CLOSE) Start New Watchdog Sequence Start New Watchdog Sequence Increment WD_FAIL_CNT[2:0] WD_FAIL_CNT[2:0]=6 t < tWD_pulse A Increment WD_FAIL_CNT[2:0] WD_FAIL_CNT[2:0]=7 A WD_FAIL_CNT[2:0] remains at 7 while WD_RST_EN = 0B WD_FAIL_CNT[2:0]=7 tWD_pulse Internally Generated Watchdog Pulse Case No. 2: Watchdog Trigger Event During WINDOW1 (CLOSE) Case No. 3: Too Short Trigger Signal Causes Time-Out Event Case No. 4: Time-Out Event Note: The deglitch time of the WD trigger on ERROR/WDI is tWD_pulse. tWD_pulse (min) = 28 µs and tWD_pulse (max) = 32 µs Any external trigger signal that his high longer than 32 µs will be deglitched and propagate into the watchdog as the Internally Generated Watchdog Pulse. A. B. C. When a time-out event occurs, 1 system clock-cycle (250 ns, typical) later, the next watchdog sequence begins. WD_RST_EN = 0 per default. To enable a reset from the watchdog once WD_FAIL_CNT[2:0] = 7 +1, WD_RST_EN must be set to 1. The notation WD_FAIL_CNT[2:0] = 7 +1 means the next (+ 1) bad event or time-out event if WD_FAIL_CNT[2:0] = 7 while WD_RST_EN = 1 will cause a transition to the RESET state. However, when WD_RST_EN = 0, the WD_FAIL_CNT[2:0] counter does not increment past 7 and the watchdog does not cause a transition to the RESET state. When a bad event is received in Window 1, 1 system clock-cycle (250 ns, typical) later the next watchdog sequence begins. Therefore the actual length of Window 1 depends on when the MCU sends the bad event. Figure 5-7. Example Cases for Bad-Event and Time-out Events in Trigger Mode 66 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 5.4.15 Q&A Mode Setting the WD_CFG bit in the SAFETY_FUNC_REG register to 1 when the device is in the DIAGNOSTIC state configures the watchdog for Q&A (question and answer) mode. In Q&A mode, the device provides a question (or TOKEN) for the MCU in the WD_TOKEN_VALUE register. The MCU performs a fixed series of arithmetic operations on the question to calculate the required 32-bit answer. This answer is split into four answer bytes or responses. The MCU writes these answer bytes through SPI one byte at a time into the WD_ANSWER register. The device verifies that the MCU returned the answer bytes within the specified timing windows, and that the answer bytes are correct. A good event occurs when the MCU sends the correct answer bytes calculated for the current question within the correct watchdog window and in the correct order. A bad event occurs when one of the events that follows occur: • The MCU sends the correct answer bytes, but not in the correct watchdog window. • The MCU sends incorrectly calculated answer bytes. • The MCU returns correct answer bytes in the wrong order (sequence). If the MCU stops sending answer bytes during the watchdog sequence, the watchdog considers this lack of response from the MCU a time-out event (no response event). This sets the TIME_OUT status bit (bit 1 in the WD_STATUS register) and increments the watchdog fail counter. Immediately following a time-out event a new watchdog sequence is started. The TIME_OUT flag can be useful for the MCU software to resynchronize the watchdog answer timing to the required device watchdog timing. When resynchronizing in this way, the MCU detects the TIME_OUT flag being set. The TIME_OUT flag being set indicates the time-out event and the start of a new watchdog sequence. The MCU should send the answer bytes with timing so they will be in the correct windows of the new watchdog sequence. NOTE If an active SPI frame (nCS is low) is present when the time-out event occurs, TIME_OUT flag is not latched (set) in the WD_STATUS register, but the watchdog counter is still incremented. Because the TIME_OUT flag is not latched this impacts resynchronization ability of the MCU and status monitoring. It is recommended to use synchronization procedure outlined in section Section 5.4.13. the fail the the NOTE In Q&A mode, each watchdog sequence starts with Window 1 (OPEN) followed by Window 2 (CLOSE). The OPEN and CLOSE references for Q&A mode are reversed with respect to those of trigger mode, but the order of the Window 1 and Window 2 is the same as are the registers containing the setting for each window, WD_WIN1_CFG and WD_WIN2_CFG. 5.4.15.1 Watchdog Q&A Related Definitions The Q&A mode definitions are: Question (Token) The question (token) is a 4-bit word (see Section 5.4.15.3). The watchdog provides the question (token) to the MCU when the MCU reads the question (TOKEN[3:0]) from the WD_TOKEN_VALUE register. The MCU can request each new question (token) at the start of the watchdog sequence, but this is not required to calculate the answer. The MCU can also generate the question by implementing the question generation circuit as shown in Figure 5-9. Nevertheless, the answer and, therefore the answer bytes, are always based on the question generated inside the watchdog of the device. So, if the MCU generates a wrong question and gives answer bytes calculated from a wrong question, the watchdog detects a bad event. A new question (token) is generated only when a good event occurred in the previous watchdog sequence causing the token counter (internal counter) to increment and generate Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 67 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com a new question (token) as shown in figure Figure 5-9. Answer (Response) The answer (response) is a 32-bit word that is split into four answer bytes or responses: Answer-3 (WD_TOKEN_RESP_3), Answer-2 (WD_TOKEN_RESP_2), Answer-1 (WD_TOKEN_RESP_1), and Answer-0 (WD_TOKEN_RESP_0). The watchdog receives an answer byte when the MCU writes to the watchdog answer register (the WD_ANSW[7:0] bits in the WD_ANSWER register). For each question, the watchdog requires four correct answer bytes from the MCU in the correct timing and order (sequence). Answer-3, Answer-2, and Answer-1 can be in Window 1 or Window 2 in the correct order, and Answer-0 must be in Window 2 to be detected as a good event. 5.4.15.2 Watchdog Sequence in Q&A Mode The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte, Answer-0 (WD_TOKEN_RESP_0), or after a time-out event. A new watchdog sequence starts after the previous watchdog sequence ends. The window duration times of Window 1 (OPEN) and Window 2 (CLOSE) are programmed through the WD_WIN1_CFG and WD_WIN2_CFG registers when the device is in the DIAGNOSTIC state. In Q&A mode, the window duration time are as follows: tWOW_MIN (Q&A mode) = tWIN1_MIN where • WOW is a watchdog OPEN window (11) tWOW_MAX (Q&A mode) = tWIN1_MAX where • WOW is a watchdog OPEN window (12) tWCW_MIN (Q&A mode) = tWIN2_MIN where • WCW is a watchdog CLOSE window (13) tWCW_MIN (Q&A mode) = tWIN2_MIN where • WCW is a watchdog CLOSE window (14) Use Equation 1 and Equation 2 to calculate the minimum and maximum values for the tWIN1 = tWOW time period. Use Equation 3 and Equation 4 to calculate the minimum and maximum values for the tWIN2 = tWCW time period. Writing a new Window 1 or Window 2 time to the WD_WIN1_CFG or WD_WIN2_CFG register immediately begins a new watchdog sequence and increments the watchdog fail counter. A new watchdog sequence is started by a write even when WD_WIN1_CFG register and the WD_WIN2_CFG SPI register are locked because the device is not in DIAGOSTIC state or the SPI command SW_LOCK is blocking a write update to the register values. 68 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 WINDOW 1 (OPEN) WINDOW 2 (CLOSE) Programmed through WD_WIN1_CFG register t = tWIN1 Programmed through WD_WIN2_CFG register t = tWIN2 The first three correct answer bytes (responses) may be scheduled in WINDOW 1 or WINDOW 2. The first three answer bytes must be in the correct order (sequence): x Answer-3 (WD_TOKEN_RESP_3) followed by x Answer-2 (WD_TOKEN_RESP_2) followed by x Answer-1 (WD_TOKEN_RESP_1) The fourth answer byte, Answer-0 (WD_TOKEN_RESP_0) must be provided in WINDOW 2. After the MCU writes the fourth answer byte (Answer-0) to the WD_ANSWER register, the watchdog generates the next question (token) after which next watchdog sequence begins. After WINDOW 1 time elapses, WINDOW 2 begins. The MCU needs to write the answer bytes (responses) to WD_ANSWER register. Question SPI Commands MCU Reads Question(1) Q* Answer MCU Provides Answer(2) 3* 2* 1* 0* NCS pin 1 Internal Clock Cycle (250 ns) to Generate New Question for (Q&A [n + 1]) Q&A [n] Q&A [n + 1] WATCHDOG SEQUENCE Q* = RD_WD_TOKEN_VALUE 3* = Answer-3 to WR_WD_ANSWER 2* = Answer-2 to WR_WD_ANSWER 1* = Answer-2 to WR_WD_ANSWER 0* = Answer-0 to WR_WD_ANSWER (1) (2) The MCU is not required to read the question (token). The MCU can begin giving the correct answer bytes Answer-3, Answer-2, Answer-1, anywhere in Window 1 or Window 2. The new question (token) is generated and a new watchdog sequence started within 1 system clock cycle after the final Answer-0 as long as the answer was a good event. A bad event or time-out event causes a new watchdog sequence to start, however a new question (token) is not generated. The MCU can put other SPI commands in-between the WR_WD_ANSWER commands (even rerequesting the question). These SPI commands have no influence on the detection of a good event, as long as the four correct answer bytes are in the correct order, and the fourth correct answer byte is provided in Window 2. Figure 5-8. Watchdog Sequence in Q&A Mode 5.4.15.3 Question (Token) Generation The watchdog uses a 4-bit token counter (TOKEN_CNT[3:0] bits in Figure 5-9), and a 4-bit Markov chain to generate a 4-bit question (token). The MCU can read this question in the WD_TOKEN_VALUE register, TOKEN[3:0] bits. The watchdog generates a new question when the token counter increments, which only occurs when the watchdog detects a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event. The watchdog does not generate a new question for a watchdog sequence that starts after the MCU writes to the WD_WIN1_CFG or WD_WIN2_CFG registers. The token counter provides a clock pulse to the Markov chain when it transitions from 1111b to 0000b. The question counter and the Markov chain are set to the singular default value of 0000b when the device completes the LBIST (either a manual LBIST run or the automotive LBIST run initiated on the transition from the RESET to DIAGNOSTIC state). To leave the singular point, the feedback logic combination is implemented. Figure 5-9 shows the logic combination for the question (token) generation. The question is in the WD_TOKEN_VALUE register, TOKEN[3:0] bits. The logic combination of the token counter with the WD_ANSW_CNT[1:0] status bits (in the WD_STATUS register) generates the reference answer bytes as shown in Figure 5-9. Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 69 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com 4-bit LFSR Polynomial Equation1 FDBK[2:1] = 2E¶00: FDBK[2:1] = 2E¶01: FDBK[2:1] = 2E¶10 : FDBK[2:1] = 2E¶11: y = x4 + x3 + 1 (Default Value) y = x4 + x2 + 1 y = x3 + x2 + 1 y = x4 + x3 + x2 + 1 Equivalent for Default LFSR Polynomial (Default FDBK value) Bit 3 0 Bit 2 Q 0 D Flip Flop Bit 1 Q D 0 Flip Flop Bit 0 Q D 0 Q Flip Flop D Flip Flop good event and TOKEN_CNT[3:0] = 4'b1111 4-bit SEED Value Loaded when the device goes to the RESET state ( Programmable Through TOKEN_SEED[3:0] ) ( Default Value 4'b00001 ) 00 01 10 TOKEN[0] 11 Token Counter (Default = 4'b0000) Good Event INCR + 1 trigger CNT [0] TOKEN_ CNT[0] CNT [1] TOKEN_ CNT[1] CNT [2] TOKEN_ CNT[2] CNT [3] TOKEN_ CNT[3] TOKEN_ CNT[1] TOKEN_ CNT[3] TOKEN_ CNT[2] TOKEN_ CNT[1] Bit 3 Bit 2 Bit 3 Bit 3 TOKEN_ CNT[3] TOKEN_ CNT[2] TOKEN_ CNT[3] TOKEN_ CNT[3] Bit 0 Bit 1 Bit 0 Bit 0 TOKEN_ CNT[0] TOKEN_ CNT[1] TOKEN_ CNT[0] TOKEN_ CNT[0] Bit 2 Bit 0 Bit 1 Bit 2 TOKEN_ CNT[2] TOKEN_ CNT[0] TOKEN_ CNT[1] TOKEN_ CNT[2] Bit 0 Bit 1 Bit 2 SEED 1 0 0 0 Bit 3 0 1 1 0 0 0 2 0 1 0 0 3 0 0 1 0 4 1 0 0 1 5 1 1 0 0 6 0 1 1 0 7 1 0 1 1 8 0 1 0 1 9 1 0 1 0 10 1 1 0 1 11 1 1 1 0 12 1 1 1 1 13 0 1 1 1 14 0 0 1 1 15 0 0 0 1 00 01 10 11 00 01 TOKEN[1] 10 11 00 01 10 11 00 01 TOKEN[2] 10 Question Order 1 to 15 Bit 1 Bit 3 Bit 2 Bit 1 11 00 01 10 11 Default question order with default TOKEN_SEED[3:0] and FDBK[3:0] values 00 01 TOKEN[3] 10 11 00 01 10 11 Feedback settings controllable through FDBK [3:2] setting in WD_TOKEN_FDBK register (default value 0x0) (1) A value of 0000b is a special seed and equates to 0001b, including the default loading of 0000b during power up. Figure 5-9. Watchdog Question (Token) Generation 70 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 TOKEN [0] Reference-Answer-x [0] X = 3, 2, 1, 0 WD_ANSW_CNT [1] ( from WD_STATUS register ) TOKEN [3] TOKEN [0] Reference-Answer-x [1] X = 3, 2, 1, 0 TOKEN [2] TOKEN [1] WD_ANSW_CNT [1] ( from WD_STATUS register ) TOKEN [0] Reference-Answer-x [2] X = 3, 2, 1, 0 TOKEN [3] TOKEN [1] WD_ANSW_CNT [1] ( from WD_STATUS register ) Reference-Answer-x [3] TOKEN [2] X = 3, 2, 1, 0 TOKEN [0] TOKEN [3] WD_ANSW_CNT [1] ( from WD_STATUS register ) TOKEN [1] Reference-Answer-x [4] X = 3, 2, 1, 0 WD_ANSW_CNT [0] ( from WD_STATUS register ) TOKEN [3] Reference-Answer-x [5] X = 3, 2, 1, 0 WD_ANSW_CNT [0] ( from WD_STATUS register ) TOKEN [0] Reference-Answer-x [6] X = 3, 2, 1, 0 WD_ANSW_CNT [0] ( from WD_STATUS register ) TOKEN [2] Reference-Answer-x [7] X = 3, 2, 1, 0 WD_ANSW_CNT [0] ( from WD_STATUS register ) Calculated Answer-x byte Figure 5-10. Watchdog Answer Calculation Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 71 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com 5.4.15.4 Answer Comparison and Reference Answer The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], in the WD_STATUS register counts the number of received answer bytes and controls the generation of the reference Answer-x byte as shown in Figure 5-10. At the start of each watchdog sequence, the default value of the WD_ANSW_CNT[1:0] is 11b to indicate that the watchdog expects the MCU to write Answer-3 (WD_RESP_3) in the WD_ANSWER register. 5.4.15.4.1 Sequence of the 2-bit Watchdog Answer Counter The sequence of the 2-bit, watchdog answer counter, WD_ANSW[1:0], is as follows for each counter value: • WD_ANSW_CNT[1:0] = 11b: – The watchdog calculates reference Answer-3 – A write access occurs: the MCU writes Answer-3 (WD_TOKEN_RESP_3) byte in the WD_ANSWER register. – The watchdog compares the reference Answer-3 with the Answer-3 byte in the WD_ANSWER register. – The watchdog decrements the WD_ANSW_CNT[1:0] bits to 10b and updates the ANSWER_ERR flag bit. • WD_ANSW_CNT[1:0] = 10b: – The watchdog calculates reference Answer-2 – A write access occurs: the MCU writes Answer-2 (WD_TOKEN_RESP_2) byte in the WD_ANSWER register. – The watchdog compares the reference Answer-2 with the Answer-2 byte in the WD_ANSWER register. – The watchdog decrements the WD_ANSW_CNT[1:0] bits to 01b and updates the ANSWER_ERR flag bit. • WD_ANSW_CNT[1:0] = 01b: – The watchdog calculates reference Answer-1 – A write access occurs: the MCU writes Answer-1 (WD_TOKEN_RESP_1) byte in the WD_ANSWER register. – The watchdog compares the reference Answer-1 with the Answer-1 byte in the WD_ANSWER register. – The watchdog decrements the WD_ANSW_CNT[1:0] bits to 00b and updates the ANSWER_ERR flag bit. • WD_ANSW_CNT[1:0] = 00b: – The watchdog calculates reference Answer-0 – A write access occurs: the MCU writes Answer-0 (WD_TOKEN_RESP_0) byte in the WD_ANSWER register. – The watchdog compares the reference Answer-0 with the Answer-0 byte in the WD_ANSWER register. – The watchdog updates the ANSWER_ERR flag bit. – The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 11b. 72 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Table 5-11. Set of Questions (Tokens) and Corresponding Answer Bytes Using Default Setting of WD_TOKEN_FDBK Register QUESTION (TOKEN) IN WD_TOKEN_VALUE REGISTER WD ANSWER (TO BE WRITTEN INTO WD_ANSW REGISTER) Answer-3 (WD_TOKEN_ RESP_3) Answer-2 (WD_TOKEN_ RESP_2) Answer-1 (WD_TOKEN_ RESP_1) Answer-0 (WD_TOKEN_ RESP_0) TOKEN [3:0] WD_ANSW_CNT [1:0] = 11b WD_ANSW_CNT [1:0] = 10b WD_ANSW_CNT [1:0] = 01b WD_ANSW_CNT [1:0] = 00b 0h FFh 0Fh F0h 00h 1h B0h 40h BFh 4Fh 2h E9h 19h E6h 16h 3h A6h 56h A9h 59h 4h 75h 85h 7Ah 8Ah 5h 3Ah CAh 35h C5h 6h 63h 93h 6Ch 9Ch 7h 2Ch DCh 23h D3h 8h D2h 22h DDh 2Dh 9h 9Dh 6Dh 92h 62h Ah C4h 34h CBh 3Bh Bh 8Bh 7Bh 84h 74h Ch 58h A8h 57h A7h E8h Dh 17h E7h 18h Eh 4Eh BEh 41h B1h Fh 01h F1h 0Eh FEh 5.4.15.5 Watchdog Q&A Mode Sequence Events and WD_STATUS Register Updates The watchdog sequence events are as follows for the different scenarios listed: • A good event occurs when all answer bytes are correct in value (the ANSWER_ERR bit is cleared to 0) and timing. For such a good event, then the events that follow occur: – The watchdog fail counter, WD_FAIL_CNT[2:0], decrements by one. – The token counter increments by one, causing a new question (token) to be generated. – The SEQ_ERR bit resets. – The ANSWER_EARLY bit resets. • A bad event occurs when all answer bytes are correct in value (the ANSWER_ERR bit is cleared to 0) but not in correct timing. For such a bad event, then the events that follow occur: – The watchdog fail counter, WD_FAIL_CNT[2:0], increments by one. – The token counter does not change, thus the question (token) does not change. – The SEQ_ERR bit is set. – The ANSWER_EARLY bit is set. • A bad event occurs when one or more of the answer bytes are not correct in value (the ANSWER_ERR bit is set to 1) but in correct timing. For such a bad event, then the events that follow occur: – The watchdog fail counter, WD_FAIL_CNT[2:0], increments by one. – The token counter does not change, thus the question (token) does not change. – The SEQ_ERR bit is set – The ANSWER_EARLY bit is reset Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 73 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 • • • www.ti.com A bad event occurs when one or more of the answer bytes are not correct in value (the ANSWER_ERR status bit is set to 1) and not in correct timing. For such a bad event, then the events that follow occur: – The watchdog fail counter, WD_FAIL_CNT[2:0], increments by one – The token counter does not change, thus the question (token) does not change. – The SEQ_ERR bit is set. – The ANSWER_EARLY bit is set. In case a time-out event occurs, then the events that follow occur: – The watchdog fail counter, WD_FAIL_CNT[2:0], increments by one. – The token counter does not change, thus the question (token) does not change. – The TIME_OUT bit is set. In case the MCU writes to registers WD_WIN1_CFG or WD_WIN2_CFG, the events that follow occur: – The watchdog fail counter, WD_FAIL_CNT[2:0], increments by one. – The WD_CFG_CHG bit is set. Table 5-12. WD_STATUS Bits Versus Possible Watchdog Sequence Events WATCHDOG SEQUENCE EVENTS All MCU Answer Bytes Correct? Answer-0 Arrived During WINDOW 2 (CLOSE) Yes Yes WD_STATUS REGISTER BITS Answer-0 Arrived During WINDOW 1 (OPEN) Time-out Occurred While Waiting for Answer? WINDOW 1 or WINDOW 2 Duration Changed? Yes No No No 0 0 0 0 No Yes No No 0 0 0 1 No Yes No No No 0 1 0 0 No No Yes No No 0 1 0 1 Yes (first 3 Answer-x) No No Yes No 0 0 1 0 No No No Yes No 0 1 1 0 — — — — Yes 1 0 0 0 74 Detailed Description WD_CFG_ CHG SEQ_ERR TIME_OUT ANSWER_ EARLY Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 5.4.16 MCU Error Signal Monitor (MCU ESM) This block monitors the external MCU error conditions signaled from the MCU to the device through the ERROR/WDI input pin. The MCU ESM is configurable to monitor two different signaling options depending which functional safety architecture MCU family is being monitored and how the specific MCU family indicates on the error or fault output pin improper operation. The MCU ESM mode is selected through the ERROR_CFG bit in the SAFETY_FUNC_CFG register. In TMS570 mode the ESM detects a low-pulse signal with a programmable low-pulse duration threshold (see Section 5.4.16.1). This mode is selected when the ERROR_CFG bit is set to 1. In PWM mode the ESM detecting a PWM signal with a programmable frequency and duty cycle (see Section 5.4.16.2). This mode is selected when the ERROR_CFG bit is cleared to 0 (default). PWM mode can be used as an external clock-monitor function. The MCU ESM is deactivated by default. To activate it, clear the NO_ERROR bit to 0 in the SAFETY_CHECK_CTRL register. NOTE Activating the MCU ESM is only recommended when the watchdog is configured in Q&A mode, otherwise the ERROR/WDI pin is used both for watchdog trigger input and MCU error signaling. The low-signaling duration threshold (for TMS570 mode) or the expected PWM low-pulse duration (for PWM mode) is set through the SAFETY_ERR_PWM_L register. The expected PWM high-pulse duration (for PWM mode) is set through the SAFETY_ERR_PWM_H register. A detected MCU signaling error is indicated when the ERROR_PIN_FAIL bit in the SAFETY_ERR_STAT register is set to 1. NOTE An update to a SAFETY_ERR_PWM_x register (only possible in the DIAGNOSTIC state) has an immediate effect. Therefore, if the MCU writes a new value to the SAFETY_ERR_PWM_x register which is less than the value of the current pulse-duration counter value, the MCU ESM immediately detects an error condition on the ERROR/WDI pin. The pulse duration counter then reinitializes to 0 and sets the ERROR_PIN_FAIL bit to 1. When the TPS65381-Q1 device is in the DIAGNOSTIC state, the MCU can emulate a signaling error (emulated fault-injection) for a diagnostic check of the error-signal monitor by checking the status of the ERROR_PIN_FAIL bit while the NO_ERROR bit is cleard to 0 (MCU ESM enabled) without a transition to the SAFE state. Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 75 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com NOTE To perform an MCU ESM diagnostic check of the pin while in the DIAGNOSTIC state the following procedure can be used. The ERROR/WDI pin is edge triggered. 1. Clear the ERROR_PIN_FAIL bit by clearing it to 0 in the SAFETY_ERR_STAT register. 2. Verify the ERROR_PIN_FAIL bit is not reset to 1 when the MCU ESM is enabled. 3. Inject a failure on the ERROR/WDI pin specific to the MCU ESM mode of operation. 4. Verify the ERROR_PIN_FAIL bit is set to 1 and the ENDRV pin is low even if the ENABLE_DRV bit is set to 1. 5. Remove the injected failure. 6. Write 0 to clear the ERROR_PIN_FAIL bit. 7. Confirm the ERROR_PIN_FAIL bit was cleared by reading back the SAFETY_ERR_STAT register. 8. Confirm the ENDRV pin returned HIGH when the ENABLE_DRV bit is set to 1, assuming no other conditions exist that block ENDRV from being HIGH (see Figure 5-14). When the TPS65381-Q1 device is in the ACTIVE state, a detected MCU signaling error causes a transition to the SAFE state. A dedicated 4-bit error counter, the DEV_ERR_CNT[3:0] bits in the SAFETY_ERR_STAT register, counts the transitions from the ACTIVE state to the SAFE state. The module is covered by the logic BIST (LBIST). 5.4.16.1 TMS570 Mode An error condition is detected when the ERROR/WDI pin remains low longer than the programmed amount of time set by the SAFETY_ERR_PWM_L register. The programmable time range is 5 µs to 1.28 ms (typical), with 5-µs steps (±5%). The SAFETY_ERR_PWM_L register must be set to the desired value based on the maximum required time for the TMS570 MCU to detect an error or fault and to potentially recover from or correct the error or fault. The LOW duration time is as follows: tTMS570_LOW_MIN = (PWML[7:0]) × 5 µs × 0.95 tTMS570_LOW_MAX= (PWML[7:0] + 1) × 5 µs × 1.05 (15) (16) Use Equation 15 and Equation 16 to calculate the minimum and maximum values for the LOW duration, tTMS570_LOW. Figure 5-11 shows the error-detection case scenarios. NOTE The SAFETY_ERR_PWM_L register (PWML[7:0]) should be configured with a minimum of 1 (01h) in the register. The low-pulse monitoring on the ERROR/WDI pin is implemented as follows: • When the NO_ERROR bit is cleared to 0, every falling edge on the ERROR/WDI pin reinitializes the low-pulse duration counter to 0 within one system clock-cycle (250 ns ±5%). • After reinitialization, the low-pulse counter restarts one system clock-cycle (250 ns ±5%). • The low-pulse duration counter increases every 5 µs (with ±5% accuracy) as long as the ERROR/WDI pin is low. A rising edge on the ERROR/WDI pin stops the low-pulse duration counter. • When low-pulse duration counter is equal to the SAFETY_ERR_PWM_L register setting, an error is detected. The ERROR_PIN_FAIL bit in the SAFETY_ERR_STAT register is set within one system clock cycle (250 ns ± 5%) after detecting an MCU signaling error. When the device is in the ACTIVE state, a transition to the SAFE state occurs after one more system clock-cycle. 76 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 MCU ERROR Pin Reset Request MCU Issues ERROR Pin Reset Request When Recovers From Detected Failure or After Correcting Detected Failure TMS570 ERROR Pin Output to ERROR/WDI Case No. 1: Error event occurred, but MCU recovered or corrected the failure in the allowed time interval by sending ERROR pin reset request which returned the input to ERROR/WDI high. Device State ACTIVE Allowed MCU Response Time to ERROR Event TMS570 ERROR Pin Output to ERROR/WDI Case No. 2: Error event occurred and MCU did NOT recover and/or was not able to correct the problem within the allowed time interval t 0 tTMS570_LOW SAFETY_PWM_ERR_L (PWML[7:0]) Low-Pulse Counter Started Internal Error Event Trigger Device State ACTIVE SAFE Figure 5-11. Error Detection Case Scenarios in TMS570 Mode Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 77 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com 5.4.16.2 PWM Mode An error condition is detected when one of the following occurs on the ERROR/WDI pin: • The ERROR/WDI pin high-pulse duration exceeds the threshold value programmed by the PWM_H register. • The ERROR/WDI pin low-pulse duration exceeds the threshold value programmed by the PWM_L register. The MCU ESM does NOT detect an MCU signaling error on the ERROR/WDI pin if both of the following occurs: • The ERROR pin high-pulse duration is less than the threshold value programmed by the PWM_H register. • The ERROR pin low-pulse duration is less than the threshold value programmed by the PWM_L register. The programmable time range for the expected HIGH and LOW pulse duration is 15 µs to 3.8 ms (typical), with 15-µs resolution steps (±5%). The HIGH and LOW pulse duration times are programmed through the SAFETY_ERR_PWM_H and SAFETY_ERR_PWM_L registers when the device is in the DIAGNOSTIC state. The pulse duration time are as follows: tPWM_HIGH_MIN = (PWMH[7:0]) × 15 µs × 0.95 tPWM_HIGH_MAX = (PWMH[7:0] + 1) × 15 µs × 1.05 tPWM_LOW_MIN = (PWML[7:0]) × 15 µs × 0.95 tPWM_LOW_MAX= (PWML[7:0] + 1) × 15 µs × 1.05 (17) (18) (19) (20) Use Equation 17 and Equation 18 to calculate the minimum and maximum values for the HIGH pulse duration, tPWM_HIGH. Use Equation 19 and Equation 20 to calculate the minimum and maximum values for the LOW pulse duration, tPWM_LOW. NOTE The SAFETY_ERR_PWM_H (PWMH[7:0]) and SAFETY_ERR_PWM_L (PWML[7:0]) register should be configured with a minimum of 1 (01h) in the registers. The monitoring of the high-pulse duration and low-pulse duration is implemented as follows: LOW pulse monitoring: • Every falling edge on the ERROR/WDI pin, or setting the NO_ERROR bit from 1 to 0 when the ERROR/WDI pin is low, reinitializes the low-pulse duration counter to 0 within one system clock-cycle (250 ns ±5%). • After reinitialization, the low-pulse counter restarts after one system clock-cycle (250 ns ±5%). • The low-pulse duration counter increases every 15 µs (±5%) while the ERROR/WDI pin remains low. • When the low-pulse duration counter is equal to the SAFETY_ERR_PWM_L register setting, an error is detected. HIGH pulse monitoring: • Every rising edge on the ERROR/WDI pin, or setting the NO_ERROR bit from 1 to 0 when the ERROR/WDI pin is high, reinitializes the high-pulse duration counter to 0 within one system clock-cycle (250 ns ±5%). • After reinitialization, the high-pulse counter restarts after one system clock-cycle (250 ns ±5%). • The high-pulse duration counter increases every 15 µs (with ± 5% accuracy) while the ERROR/WDI pin remains high. • When the high-pulse duration counter is equal to the SAFETY_ERR_PWM_H register setting, an error is detected. 78 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 NOTE The ERROR/WDI pin is edge triggered, to synchronize the MCU to the MCU ESM module, while in the DIAGNOSTIC state the MCU should start sending the desired PWM signal. On the first falling or rising edge the MCU ESM detects the edge and starts the internal timers in sync with the edge so the MCU and MCU ESM are synchronized. The MCU ESM resynchronizes to the MCU on every rising and falling edge. While in the DIAGNOSTIC state, when synchronization has occurred the ERROR_PIN_FAIL flag should be cleared. The ERROR_PIN_FAIL bit in the SAFETY_ERR_STAT register is set within one system clock cycle (250 ns ±5%) after detecting an MCU signaling error. When the device is in the ACTIVE state, a transition to the SAFE state occurs after one more system clock-cycle. Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 79 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com tPWM_HIGH SAFETY_PWM_ERR_H (PWMH[7:0]) tPWM_HIGH SAFETY_PWM_ERR_H (PWMH[7:0]) tPWM_LOW SAFETY_PWM_ERR_L (PWML[7:0]) ERROR Signal from MCU on ERROR/WDI Low-Pulse Counter Stopped, High-Pulse Counter started tHIGH High-Pulse Counter Stopped, Low-Pulse Counter started tPWM_LOW SAFETY_PWM_ERR_L (PWML[7:0]) Low-Pulse Counter Stopped, High-Pulse Counter started tLOW High-Pulse Counter Stopped, Low-Pulse Counter started Low-Pulse Counter Stopped, High-Pulse Counter started tHIGH tLOW Internal Error Event Trigger Device State ACTIVE Case No. 1: MCU sends PWM Error signal with correct timing tPWM_HIGH SAFETY_PWM_ERR_H (PWMH[7:0]) ERROR Signal from MCU on ERROR/WDI Low-Pulse Counter Stopped, High-Pulse Counter started tHIGH Internal Error Event Trigger Device State ACTIVE SAFE Case No. 2: MCU PWM Error Signal HIGH Pulse Duration Exceeds Time Configured in SAFETY_PWM_ERR_H Register tPWM_HIGH SAFETY_PWM_ERR_H (PWMH[7:0]) tPWM_LOW SAFETY_PWM_ERR_L (PWML[7:0]) ERROR Signal from MCU on ERROR/WDI High-Pulse Counter Stopped, Low-Pulse Counter started Low-Pulse Counter Stopped, High-Pulse Counter started tHIGH tLOW Internal Error Event Trigger Device State ACTIVE SAFE Case No. 3: MCU PWM Error Signal LOW Pulse Duration Exceeds Time Configured in SAFETY_PWM_ERR_L Register Figure 5-12. Error Detection Case Scenarios in PWM Mode 80 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 5.4.17 Device Configuration Register Protection This function offers a mechanism to help protect safety SPI-mapped registers by means of SPI writeaccess protection and CRC check. The register access protection includes two distinctive features: • A register cannot be written after write-access lock protection is set. The lock is cleared by software or by a power-on reset. • CRC protection for configuration registers. A CRC occurs on safety data after a SPI write updates to verify the SPI register contents are correctly programmed. The CRC controller is a diagnostic module, which performs the CRC to verify the integrity of the SPI-mapped register space. A signature representing the content of the safety registers is obtained when the content is read into the CRC controller. The responsibility of the CRC controller is to calculate the signature for a set of data and then compare the calculated signature value against a predetermined good-signature value. The predetermined CRC signature value is stored in the SAFETY_CFG_CRC register. The external MCU uses the SAFETY_CHECK_CTRL register to enable a CRC check and the SAFETY_STAT_2 register to monitor the status. When enabled, a CRC check on the configuration registers is performed. In case of a detected signature error, the CFG_CRC_ERR flag is set in the SAFETY_STAT_2 SPI register. The device state and the ENDRV pin state remain unchanged. In case of a detected checksum error with the TPS65381-Q1 device in the DIAGNOSTIC state, clearing the CFG_CRC_EN bit to 0 brings the TPS65381-Q1 device into the SAFE state (the ENDRV pin is pulled low). A standard CRC-8 polynomial is used: X8 + X2 + X1 + 1 The CRC monitor test is covered by a logic BIST. A • • • • • • • • • • 64-bit string is protected by CRC. The following registers are protected: SAFETY_FUNC_CFG DEV_REV SAFETY_PWD_THR_CFG SAFETY_ERR_CFG WD_TOKEN_FDBK WD_WIN2_CFG WD_WIN1_CFG SAFETY_ERR_PWM_L DEV_CFG2 DEV_CFG1 (only bit number 6) Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 81 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com Table 5-13 lists the CRC bus structure. Table 5-13. CRC Bus Structure REGISTER NAME 64-BIT BUS ORDERING SAFETY_FUNC_CFG [6:0] [63:57] DEV_REV [7:0] [56:49] SAFETY_PWD_THR_CFG [3:0] [48:45] SAFETY_ERR_CFG [7:0] [44:37] WD_TOKEN_FDBK [7:0] [36:29] WD_WIN2_CFG [4:0] [28:24] WD_WIN1_CFG [6:0] [23:17] SAFETY_ERR_PWM_L [7:0] [16:9] DEV_CFG2 [7:0] [8:1] DEV_CFG1 [6] 0 In the external MCU, the CRC calculation must be performed byte-wise, starting with the lowest byte of the 64-bit bus ordering value. The most significant bit is first in the bit order. The resulting CRC of one calculation is the seed value for the next calculation. The initial seed value is FFh. The CRC result of the eighth byte-wise calculation is the CRC signature value, which must be stored in the SAFETY_CFG_CRC register (see Figure 5-13). 64-Bit Bus Ordering Value: 63 0 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Flip-Flop the Preload Value (Seed Value) Byte 0, Byte 1, Byte 2, Byte 3, Byte 4, Byte 5, Byte 6, Byte 7 1 Q D 1 Q Flip Flop Bit 7 D Flip Flop Bit 6 1 Q D Flip Flop Bit 5 1 Q D 1 Q Flip Flop Bit 4 D Flip Flop Bit 3 1 Q 1Q D Flip Flop Bit 2 D Flip Flop Bit 1 1Q D Flip Flop Bit 0 Figure 5-13. CRC Calculation Logic Table 5-14 lists some CRC calculation examples. Table 5-14. CRC Calculation Examples 82 64-BIT BUS ORDERING VALUE CRC-8 RESULT 0000 0000 0000 0000h DBh FFFF FFFF FFFF FFFFh 0Ch 0A0A 0505 0A0A 0505h D4h 0505 0A0A 0505 0A0Ah 17h A0A0 5050 A0A0 5050h 2Bh 0A23 E000 18FE 7B80h 1Bh Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com SLVSBC4G – MAY 2012 – REVISED JUNE 2017 In case the CRC controller detects a signature error on the configuration registers, care must be used when performing an EEPROM CRC afterwards. In case of a detected signature error in the configuration registers, the device reports an EEPROM signature error when the CFG_CRC_EN bit in the SAFETY_CHECK_CTRL register is cleared to 0 first before performing the EEPROM CRC by setting the EE_CRC_CHK bit in the SAFETY_BIST_CTRL register to 1, even when the EEPROM bits do not have an error. Therefore, when performing an EEPROM CRC after a CRC on the configuration registers, the steps must always occur in the following order: 1. Calculate CRC8 in the MCU and store it in the SAFETY_CFG_CRC register. 2. Set the CFG_CRC_EN bit in the SAFETY_CHECK_CTRL register to 1 to perform a CRC on the configuration registers. 3. After the SPI command sets the CFG_CRC_EN bit to 1 (for example, after rising edge on NCS), wait at least 2.1 µs for the configuration register to complete the CRC. 4. Read the results of the configuration register CRC in the SAFETY_STAT_2 register, bit CFG_CRC_ERR. If continuous CRC on the configuration register must be performed, clear the CFG_CRC_EN bit in the SAFETY_CHECK_CTRL register to 0 and repeat beginning with Step 1. If the CRC on the EEPROM registers must be performed, proceed to Step 5. NOTE A correct EEPROM CRC afterwards (as described in Step 5) clears this CFG_CRC_ERR bit. Therefore, TI recommends reading out this CFG_CRC_ERR bit before performing the EEPROM CRC. 5. Set the EE_CRC_CHK bit in the SAFETY_BIST_CTRL register to 1 to perform the CRC on the EEPROM registers. 6. After the SPI command sets the EE_CRC_CHK bit to 1 (for example, after rising edge on NCS), wait at least 811 µs for the EEPROM CRC to finish. 7. Completion of the EERPOM CRC is observed by reading the EE_CRC_CHK bit. When the EEPROM CRC is complete, this EE_CRC_CHK bit is cleared to 0. 8. Clear the CFG_CRC_EN bit in the SAFETY_CHECK_CTRL register to 0 9. Read the results of the EEPROM CRC in the SAFETY_STAT_2 register, bit EE_CRC_ERR. 10. Go back to Step 1. NOTE Returning to Step 1 is not required; returning to Step 2 is also an option. NOTE While in the DIAGNOSTIC state, a check can be performed to confirm the CFG_CRC_ERR bit is set to 1 on a mismatch between the value stored in the SAFETY_CFG_CRC register and the value that is calculated from the configuration registers covered by the CRC8. If the CFG_CRC_EN is cleared while the CFG_CRC_ERR bit is set to 1, then the device transitions to the SAFE state, set the EE_CRC_ERR bit and clear the CFG_CRC_EN bit. To avoid this transition to the SAFE state, the CFG_CRC_ERR bit must be cleared by running the EEPROM CRC by setting the EE_CRC_CHK bit. While the EPPROM CRC is running, the EE_CRC_ERR bit is set. Assuming the EEPROM CRC was good, both the EE_CRC_ERR and CFG_CRC_ERR bits are cleared. To check if the CFG_CRC_ERR bit is 0 for a matching CRC, the matching CRC value should be stored in the SAFETY_CFG_CRC register. Then the CFG_CRC_EN bit must be cleared to 0 and set again to 1 which reruns the CRC on the configuration registers, resulting in the CFG_CRC_ERR bit being 0. Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 83 Not Recommended for New Designs TPS65381-Q1 SLVSBC4G – MAY 2012 – REVISED JUNE 2017 www.ti.com 5.4.18 Enable and Reset Driver Circuit Figure 5-14 shows the reset and enable circuit. NRES_ERR To DIAG_OUT Through DMUX VDD5_OT NMASK_VDD5_OT VDDIO VDD3/5_UV ~ 4.5 NŸ VDD1_UV NMASK_VDD1_UV_OV NRES RESET State and Global RESET Conditions STANDBY State and Global STANDBY Conditions •1 POST_RUN_RST IGN_PWRL Re-cranking on IGN WD_FAIL_CNT[2:0] = 7 + 1 WD_RST_EN VDDIO VBATP_OV MASK_VBATP_OV ~ 4.5 NŸ VDD1_OV VDD5_OV VDD3/5_OV ENDRV NMASK_VDD1_UV_OV WD_FAIL_CNT[2:0] > 4 SAFE State ABIST_RUN or LBIST_RUN (ACTIVE State or DIAGNOSTIC State) STANDBY State •1 ENABLE_DRV Bit Type Status or Monitoring Event or Flag User Configurable Input Bit ENDRV_ERR Figure 5-14. Reset and Enable Circuit The ENDRV pin features a read-back circuit to compare the external ENDRV level with the internally applied ENDRV level. This feature detects any possible failure in the ENDRV pullup or pulldown components. A failure is detected by the MCU through the ENDRV_ERR bit (bit 1 in the SAFETY_STAT_4 register). The ENDRV pin is pulled low for the ABIST duration time (approximately 300 µs) when activating the ABIST function after the ENDRV output is turned on and driven high. This is part of ENDRV diagnostics to validate all monitoring functions that disable the ENDDRV output and confirm that the ENDRV output is controllable by using the ENDRV read-back path. The NRES pin features a readback of the external NRES level. The value is read on the DIAG_OUT pin and NRES_ERR bit (bit 5 in the SAFETY_STAT_3 register).. For both the ENDRV pin and the NRES pin, the logic read-back threshold level is typically 400 mV. Figure 5-15 shows the timing-response diagram for the NRES and ENDRV pins to any VDDx undervoltage or overvoltage condition. 84 Detailed Description Copyright © 2012–2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65381-Q1 Not Recommended for New Designs TPS65381-Q1 www.ti.com VDD3/5 or VDD1 Undervoltage Condition SLVSBC4G – MAY 2012 – REVISED JUNE 2017 Hysteresis t1 Required Signal De-glitch Time t1 < Signal De-Glitch Time t2 t2 > Signal De-Glitch Time Required Signal De-glitch Time NRES NRES Extension Time After WD_FAIL_CNT Signal De-Glitch Time Required Signal De-glitch Time NRES ENDRV When WD_FAIL_CNT