TPS65835RKPT

Product Folder Sample & Buy Tools & Software Technical Documents Support & Community TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 TPS65835 Advanced PMU With Integrated MSP430 for Active Shutter 3D Glasses 1 Device Overview 1.1 – – – – Features • Power Management Core – Linear Charger • Three Charger Phases: Pre-Charge, Fast Charge, and Charge Termination • LED Current Sinks for Power Good and Charger Status Indication – Low-Dropout Regulator (LDO) Supply for External Modules & Integrated MSP430 Power – Boost Converter • Adjustable Output Voltage: 8 V to 16 V – Full H-Bridge Analog Switches • Internally Controlled by MSP430 Core for System Functions • MSP430 Core – Ultralow Power Consumption • Active Mode: 280 µA at 1 MHz, 2.2 V • Standby Mode: 0.5 µA • Off Mode (RAM Retention): 0.1 µA 1 1.2 – – – – Five Power-Saving Modes 16-Bit RISC Architecture 16-kB Flash Two 16-Bit Timer_A Modules with Three Capture/Compare Registers 10-Bit 200-ksps A/D Converter with Internal Reference, Sample-and-Hold, and Autoscan Universal Serial Communications Interface, Supports IrDA Encode/Decode and Synchronous SPI • Enhanced UART Supporting Auto Baudrate Detection (LIN) • IrDA Encoder and Decoder • Synchronous SPI • I2C Serial Onboard Programming • No External Programming Voltage Needed • Programmable Code Protection by Security Fuse For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144) Applications Active Shutter 3D Glasses 1.3 Description The TPS65835 is a power management unit (PMU) for active shutter 3D glasses consisting of a power management core and an MSP430 microcontroller. The power management core has an integrated power path, linear charger, LDO, boost converter, and full H-bridge analog switches for left and right shutter operation in a pair of active shutter 3D glasses. The MSP430 core supports the synchronization and communications from an IR, RF, or other communications module through the integrated universal serial communications and timer interfaces for operation of the H-bridge switches on the power management core. Device Information (1) (1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS65735 VSON (32) 4.00 mm x 4.00 mm For more information, see Section 10, Mechanical Packaging and Orderable Information. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 1.4 www.ti.com Block Diagram Figure 1-1. TPS65835 Simplified Functional Block Diagram 2 Device Overview Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Table of Contents 1 2 3 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 1 1.3 Description ............................................ 1 1.4 Block Diagram ........................................ 2 5 6 Revision History ......................................... 3 Terminal Configuration and Functions .............. 4 .......................................... 4 3.2 Pin Functions ......................................... 5 Specifications ............................................ 7 4.1 Absolute Maximum Ratings .......................... 7 4.2 ESD Ratings .......................................... 7 4.3 Power-On Hours (POH) .............................. 7 4.4 Recommended Operating Conditions ................ 8 4.5 Thermal Information .................................. 8 4.6 Electrical Characteristics ............................. 9 4.7 Quiescent Current ................................... 12 4.8 Typical Characteristics .............................. 12 Detailed Description ................................... 13 5.1 Overview ............................................ 13 3.1 4 5.2 Pin Diagram 7 8 9 Functional Block Diagram ........................... 13 ................................. ........................... 5.5 MSP430 CORE ..................................... Application and Implementation .................... 6.1 Application Information .............................. 6.2 Typical Application .................................. Power Supply Recommendations .................. Layout .................................................... 8.1 Layout Guidelines ................................... 8.2 Layout Example ..................................... Device and Documentation Support ............... 9.1 Device Support ...................................... 9.2 Community Resources .............................. 9.3 Trademarks.......................................... 9.4 Electrostatic Discharge Caution ..................... 9.5 Glossary ............................................. 5.3 Feature Description 5.4 Device Functional Modes 13 26 27 52 52 52 58 58 58 58 59 59 59 59 59 59 10 Mechanical, Packaging, and Orderable Information .............................................. 59 10.1 Packaging Information .............................. 59 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2011) to Revision A • Page Added ESD Ratings table, Typical Characteristics section, Detailed Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................................................. 1 Revision History Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 3 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 3 Terminal Configuration and Functions 3.1 Pin Diagram A. Pins 10 and 40 = N/C. No internal connection; connect to main system ground. Figure 3-1. 40-Pin RKP VQFN (Top View) 4 Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 3.2 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Pin Functions Table 3-1. Pin Functions PIN NO. NAME I/O DESCRIPTION POWER MANAGEMENT CORE (PMIC) DGND - PMIC Digital Ground (1) 5 LCLP O H-Bridge Output for Left LC Shutter, Positive Terminal 6 LCLN O H-Bridge Output for Left LC Shutter, Negative Terminal 7 LCRP O H-Bridge Output for Right LC Shutter, Positive Terminal 8 LCRN O H-Bridge Output for Right LC Shutter, Negative Terminal 11 BST_OUT O Boost Output 12 BST_SW I Boost Switch Node 14 PGNDBST — 15 BST_FB I 18 ISET I/O 19 TS I 22 BAT I/O Charger Power Stage Output and Battery Voltage Sense Input 23 SYS O Output Terminal to System 26 VIN I AC or USB Adapter Input 27 VLDO O LDO Output 28 VLDO_SET I Sets LDO Output Voltage (see Table 5-2) 29 AGND — 33 SWITCH I Switch Input for Device Power On/Off 35 SW_SEL I Selects Type of Switch Connected to SWITCH Pin (see Table 5-6) 36 PSDA I/O I2C Data Pin (only used for TI debug and test) GROUND PIN IN APPLICATION 37 PSCL I/O I2C Clock Pin (only used for TI debug and test) GROUND PIN IN APPLICATION 38 nCHG_STAT O Open-drain Output, Charger Status Indication CONNECT TO GROUND IF FUNCTION IS NOT USED 4 PMIC Boost Power Ground (1) Boost Feedback Node Fast-Charge Current Setting Resistor Pin for 10-kΩ NTC Thermistor Connection FLOAT IF THERMISTOR / TS FUNCTION IS NOT USED PMIC Analog Ground (1) MSP430 MICROCONTROLLER 1 P2.1/ TA1.1 I/O General-purpose digital I/O pin Timer1_A, capture: CCI1A input, compare: Out1 output 2 P2.2/ TA1.1 I/O General-purpose digital I/O pin Timer1_A, capture: CCI1B input, compare: Out1 output 3 P3.3/ TA1.2 I/O General-purpose digital I/O pin Timer1_A, compare: Out2 output 9 P3.5/ TA0.1 I/O General-purpose digital I/O pin Timer0_A, compare: Out0 output 13 P1.6/ TA0.1/ A6/ CA6/ UCB0SOMI/ UCB0SCL/ TDI/TCLK I/O General-purpose digital I/O pin Timer0_A, compare: Out1 output ADC10 analog input A6 Comparator_A+, CA6 input USCI_B0 slave out/master in SPI mode USCI_B0 SCL I2C clock in I2C mode JTAG test data input or test clock input during programming and test 16 P1.7/ A7/ CA7/ CAOUT/ UCB0SIMO/ UCB0SDA/ TDO/TDI I/O General-purpose digital I/O pin ADC10 analog input A7 Comparator_A+, CA7 input Comparator_A+, output USCI_B0 slave in/master out in SPI mode USCI_B0 SDA I2C data in I2C mode JTAG test data output terminal or test data input during programming and test (2) 17 nRST/ NMI/ SBWTDIO I/O Reset Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test (1) (2) MSP430 ground and grounds for PMIC (Power Management Core) are connected internally. TDO or TDI is selected via JTAG instruction. Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 5 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 3-1. Pin Functions (continued) PIN NO. NAME I/O DESCRIPTION 20 TEST/ SBWTCK I 21 P2.7/ XOUT I/O General-purpose digital I/O pin Output terminal of crystal oscillator (3)) 24 P2.6/ XIN/ TA0.1 I/O General-purpose digital I/O pin XIN, Input terminal of crystal oscillator TA0.1, Timer0_A, compare: Out1 output 25 DVSS — MSP430 Ground reference (1) 30 P1.1/ TA0.0/ UCA0RXD/ UCA0SOMI/ A1/ CA1 I/O General-purpose digital I/O pin Timer0_A, capture: CCI0A input, compare: Out0 output USCI_A0 receive data input in UART mode USCI_A0 slave data out/master in SPI mode ADC10 analog input A1 Comparator_A+, CA1 input 31 P1.2/ TA0.1/ UCA0TXD/ UCA0SIMO/ A2/ CA2 I/O General-purpose digital I/O pin Timer0_A, capture: CCI1A input, compare: Out1 output USCI_A0 transmit data output in UART mode USCI_A0 slave data in/master out in SPI mode ADC10 analog input A2 Comparator_A+, CA2 input 32 P1.3/ ADC10CLK/ A3 VREF-/VEREF-/ CA3/ CAOUT I/O General-purpose digital I/O pin ADC10, conversion clock output ADC10 analog input A3 ADC10 negative reference voltage Comparator_A+, CA3 input Comparator_A+, output 34 P1.4/ SMCLK/ UCB0STE UCA0CLK/ A4 VREF+/VEREF+/ CA4 TCK I/O General-purpose digital I/O pin SMCLK signal output USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10 analog input A4 ADC10 positive reference voltage Comparator_A+, CA4 input JTAG test clock, input terminal for device programming and test I/O General-purpose digital I/O pin Timer0_A, compare: Out0 output USCI_B0 clock input/output USCI_A0 slave transmit enable ADC10 analog input A5 Comparator_A+, CA5 input JTAG test mode select, input terminal for device programming and test N/C — All N/C pins are not connected internally (package to die). They should be connected to the main system ground. Thermal PAD — There is an internal electrical connection between the exposed thermal pad and the AGND ground pin of the device. The thermal pad must be connected to the same potential as the AGND pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. AGND pin must be connected to ground at all times. P1.5/ TA0.0/ UCB0CLK/ UCA0STE/ A5/ CA5/ TMS 39 Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test MISCELLANEOUS AND PACKAGE 10, 40 41 (3) 6 If P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Terminal Configuration and Functions Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 4 Specifications 4.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Input voltage on all pins (except for VIN, BST_OUT, BST_SW, BST_FB, VLDO, LCLP, LCLN, LCRP, LCRN, AGND, DGND, PGNDBST, and MSP430 Core pins) with respect to AGND –0.3 7 V VIN with respect to AGND –0.3 28 V BST_OUT, BST_SW with respect to PGNDBST –0.3 18 V BST_FB with respect to PGNDBST, VLDO with respect to DGND –0.3 3.6 V MSP430 Core Pins –0.3 4.1 V 0 60 °C TA Operating free-air temperature TJ Junction temperature Tstg Storage temperature (1) (2) (3) Electrical characteristics ensured 0 85 Functionality ensured (3) 0 105 –55 150 ESD Ratings VALUE Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 VESD 4.3 See (1) (2) (3) (4) (5) °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted. Device has a thermal shutdown feature implemented that shuts down at 105°C 4.2 (1) (2) °C Electrostatic discharge (1) UNIT ±1000 Charged Device Model (CDM), per JESD22-C101 (2) ±250 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Power-On Hours (POH) (1) (2) (3) (4) OPERATING CONDITION NOMINAL CVDD VOLTAGE (V) JUNCTION TEMPERATURE (Tj) LIFETIME POH (5) 100% OPP 1.1 –40 to 105 °C 100 K 120% OPP 1.2 –40 to 105 °C 100 K 166% OPP 1.35 –40 to 105 °C 49 K This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. Notations in this table cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and conditions for TI semiconductor products. POH represent device operation under the specified nominal conditions continuously for the duration of the calculated lifetime. Specifications Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 7 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 4.4 www.ti.com Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT CHARGER / POWER PATH 28 (1) V 200 mA 10 µF 0 2 µH 2.5 6.4 V 100 mA 10 µF VVIN Voltage at charger input pin 3.7 IVIN Input current at VIN pin CVIN Capacitor on VIN pin LVIN Inductance at VIN pin VSYS Voltage at SYS pin ISYS(OUT) Output current at SYS pin CSYS Capacitor on SYS pin 0.1 VBAT Voltage at BAT pin 2.5 6.4 V CBAT Capacitor on BAT pin 4.7 10 µF REXT(nCHG_STAT) Resistor connected to nCHG_STAT pin to limit current into pin 320 0.1 2.2 4.7 Ω BOOST CONVERTER / H-BRIDGE SWITCHES VIN(BST_SW) Input voltage for boost converter VBST_OUT Output voltage for boost converter 2.5 6.5 V 8 16 V CBST_OUT Boost output capacitor 3.3 10 µF LBST_SW (2) Inductor connected between SYS and BST_SW pins 4.7 10 (3) µH 1 10 µF 0.4 V 4.7 LDO CVLDO External decoupling cap on pin VLDO POWER MANAGEMENT CORE CONTROL (LOGIC LEVELS FOR GPIOs) VIL(PMIC) GPIO low level (BST_EN, CHG_EN, SW_SEL, VLDO_SET and to switch H-Bridge inputs to a low, 0, level) VIH(PMIC) GPIO high level (BST_EN, CHG_EN, SW_SEL, VLDO_SET and to switch H-Bridge inputs to a high, 1, level) (1) (2) (3) 1.2 V VIN pin has 28 V ESD protection See Section 5.3.4 for information on boost converter inductor selection. Design optimized for boost operation with 10 µH inductor 4.5 Thermal Information TPS65835 THERMAL METRIC RKP (VQFN) UNIT 40 PINS RθJA Junction-to-ambient thermal resistance (1) 38.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance (2) 26.5 °C/W RθJB Junction-to-board thermal resistance (3) 9.8 °C/W (4) ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter (5) 9.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance (6) 3.5 °C/W (1) (2) (3) (4) (5) (6) 8 The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Specifications Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 4.6 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3.3 3.45 UNIT BATTERY CHARGER POWER PATH VUVLO(VIN) Undervoltage lockout at power VVIN: 0 V → 4 V path input, VIN pin 3.2 VHYS-UVLO(VIN) Hysteresis on UVLO at power path input, VIN pin VVIN: 4 V → 0 V 200 300 VIN-DT Input power detection threshold Input power detected if: (VVIN > VBAT + VIN-DT); VBAT = 3.6 V VVIN: 3.5 V → 4 V 40 140 VHYS-INDT Hysteresis on VIN-DT VBAT = 3.6 V VVIN: 4 V → 3.5 V 20 VOVP Input over-voltage protection threshold VVIN: 5 V → 7 V 6.4 VHYS-OVP Hysteresis on OVP VVIN: 11 V → 5 V VDO(VIN-SYS) VIN pin to SYS pin dropout voltage VVIN – VSYS ISYS = 150 mA (including IBAT) VVIN = 4.35 V VBAT = 3.6 V 350 mV VDO(BAT-SYS) BAT pin to SYS pin dropout voltage VBAT – VSYS ISYS = 100 mA VVIN = 0 V VBAT > 3 V 150 mV IVIN(MAX) Maximum power path input current at pin VIN VVIN = 5 V VSUP(ENT) Enter battery supplement mode VSYS ≤ (VBAT - 40 mV) V VSUP(EXIT) Exit battery supplement mode VSYS ≥ (VBAT - 20 mV) V VSUP(SC) Output short-circuit limit in supplement mode 250 VO(SC) Output short-circuit detection threshold, power-on 0.9 V mV mV mV 6.6 6.8 105 V mV 200 mA mV V BATTERY CHARGER VVIN = 5 V No load on SYS pin VBAT > VBAT(REG) ICC Active supply current into VIN pin IBAT(SC) Source current for BAT pin short-circuit detection VBAT(SC) BAT pin short-circuit detection threshold 1.6 1.8 2.0 VBAT(REG) Battery charger output voltage –1% 4.20 1% VLOWV Pre-charge to fast-charge transition threshold 2.9 3.0 3.1 ICHG Charger fast charge current range ICHG = KISET / RISET KISET Battery fast charge current set factor ICHG = KISET / RISET IPRECHG Pre-charge current ITERM Charge current value for ICHG = 100 mA termination detection threshold 2 1 VVIN = 5 V VBAT(REG) > VBAT > VLOWV VVIN = 5 V IVIN(MAX) > ICHG ICHG = 100 mA No load on SYS pin, thermal loop not active. 5 mA Submit Documentation Feedback Product Folder Links: TPS65835 V V V 100 mA –20% 450 20% AΩ 0.07 × ICHG 0.10 × ICHG 0.15 × ICHG mA 7 10 15 Specifications Copyright © 2011–2016, Texas Instruments Incorporated mA mA 9 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER VRCH Recharge detection threshold IBAT(DET) Sink current for battery detection tCHG Charge safety timer (18000 seconds = 5 hours) tPRECHG Pre-charge timer (1800 seconds = 30 minutes) VDPPM DPPM threshold ILEAK(nCHG) Leakage current for nCHG_STAT pin RDSON(nCHG) On resistance for nCHG_STAT MOSFET switch IMAX(nCHG) Maximum input current to nCHG_STAT pin TEST CONDITIONS MIN TYP MAX VBAT below nominal charger voltage, VBAT(REG) 55 100 170 1 UNIT mV mA 18000 s 1800 s VBAT + 100 mV V VnCHG_STAT = 4.2 V CHG_EN = LOW (Charger disabled) 100 20 60 50 nA Ω mA BATTERY CHARGER NTC MONITOR ITSBIAS TS pin bias current VCOLD 0°C charge threshold for 10kΩ NTC (β = 3490) VHYS(COLD) Low temperature threshold hysteresis VHOT 50°C charge threshold for 10kΩ NTC (β = 3490) VHYS(HOT) High temperature threshold hysteresis Battery charging and battery / NTC temperature increasing 75 µA 2100 mV 300 mV 300 Battery charging and battery / NTC temperature decreasing mV 30 mV BATTERY CHARGER THERMAL REGULATION TJ(REG_LOWER) Charger lower thermal regulation limit 75 TJ(REG_UPPER) Charger upper thermal regulation limit 95 TJ(OFF) Charger thermal shutdown temperature 105 TJ(OFF-HYS) Charger thermal shutdown hysteresis 20 °C °C °C °C LDO IMAX(LDO) ISC(LDO) Maximum LDO output current, VVLDO = 2.2 V VSYS = 4.2 V VVIN = 0 V VLDO_SET = 0 V 30 mA Maximum LDO output current, VVLDO = 3.0 V VSYS = 4.2 V VVIN = 0 V VLDO_SET = VSYS 30 mA Short circuit current limit 30 VVLDO LDO output voltage VLDO_SET = LOW (VLDO_SET pin connected to DGND) 3.7 V ≤ VVIN ≤ 6.5 V ILOAD(LDO) = –10 mA VVLDO LDO output voltage VLDO_SET = HIGH (VVLDO_SET = VSYS) 3.7 V ≤ VVIN ≤ 6.5 V ILOAD(LDO) = –10 mA VDO(LDO) LDO Dropout voltage VVIN - VLDO when in dropout ILOAD(LDO) = –10 mA 10 Specifications 2.13 2.91 100 mA 2.2 2.27 V 3.0 3.09 V 200 mV Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER PSRR TEST CONDITIONS MIN TYP MAX Line regulation 3.7 V ≤ VVIN ≤ 6.5 V ILOAD(LDO) = –10 mA –1% 1% Load regulation VVIN = 3.5 V 0.1 mA ≤ ILOAD(LDO) ≤ –10 mA –2% 2% Power supply rejection ratio at 20 KHz, ILOAD(LDO) = 10 mA VDO(LDO) = 0.5 V CVLDO = 10 µF UNIT 45 dB BOOST CONVERTER IQ(BST) Boost operating quiescent current Boost Enabled, BST_EN = High IOUT(BST) = 0 mA (boost is not switching) VBAT = 3.6 V RDSON(BST) Boost MOSFET switch onresistance VIN(BST) = 2.5 V ISW(MAIN) = 200 mA ILKG(BST_SW) Leakage into BST_SW pin (includes leakage into analog h-bridge switches) BST_EN signal = LOW (Boost disabled) VBST_SW = 4.2 V No load on BST_OUT pin ISWLIM(BST) Boost MOSFET switch current limit VDIODE(BST) Voltage across integrated boost diode during normal operation VREF(BST) Boost reference voltage on BST_FB pin 1.17 1.2 1.23 VREFHYS(BST) Boost reference voltage hysteresis on BST_FB pin 2% 2.5% 3.2% TON(BST) Maximum on time detection threshold 5 6.5 8 TOFF(BST) Minimum off time detection threshold 1.4 1.75 2.1 TSHUT(BST) Boost thermal shutdown threshold 105 TSHUT-HYS(BST) Boost thermal shutdown threshold hysteresis 20 100 2 4.5 µA 0.8 1.2 Ω 90 nA 150 BST_EN signal = HIGH VBST_SW = 16.0 V IBST_OUT = –2 mA 200 1.0 mA V V µs µs °C °C FULL H-BRIDGE ANALOG SWITCHES IQ(HSW) Operating quiescent current for h-bridge switches RDSON(HSW) H-bridge switches on resistance TDELAY(HSW-H) H-bridge switch propagation delay, input switched from low to high state. VHBxy = 0 V → VVLDO 100 ns H-bridge switch propagation delay, input switched from high to low state. VHBxy = VVLDO → 0 V 100 ns TDELAY(HSW-L) 5 20 40 µA Ω POWER MANAGEMENT CORE CONTROLLER VIL(PMIC) Low logic level for logic IO logic level decreasing: signals on power management VSYS → 0 V core IIN = 1 mA (BST_EN, CHG_EN, SLEEP, HBR1, HBR2, HBL1, HBL2) VIH(PMIC) High logic level for signals on power management core (BST_EN, CHG_EN, SLEEP, HBR1, HBR2, HBL1, HBL2) IO logic level increasing: 0 V → VSYS IIN = 1 mA 0.4 1.2 V Specifications Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 V 11 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VGOOD(LDO) Power fault detection threshold VVLDO decreasing VGOOD_HYS(LDO) Power fault detection hysteresis VVLDO increasing MIN VBATCOMP 4.7 MAX 1.96 50 VBAT = 4.2 V VVLDO = 2.2 V COMP pin voltage (scaled down battery voltage) TYP UNIT V mV 1.85 VBAT = 2.5 V VVLDO = 2.2 V 1.10 VBAT = 4.2 V VVLDO = 3.0 V 1.90 VBAT = 3.3 V VVLDO = 3.0 V 1.50 V Quiescent Current over operating free-air temperature range (unless otherwise noted) PARAMETER IQ(SLEEP) IQ(ACTIVE) 4.8 TYP MAX UNIT Power management core quiescent current in sleep mode at 25° C VBAT = 3.6 V VVIN = 0 V No load on LDO CHG_EN, BST_EN grounded BST_FB = 300 mV Power management core in sleep mode / device 'off' TEST CONDITIONS 8.6 10.5 µA Power management core quiescent current in active mode at 25° C VBAT = 3.6 V VVIN = 0 V Boost enabled but not switching, Hbridge in grounded state No load on LDO Power management core in active mode 39 53.5 µA Typical Characteristics VIN = 5 V 15-mA Load on LDO 1-mA Load on Boost VIN = 5 V Figure 4-1. Startup 12 MIN 15-mA Load on LDO 1-mA Load on Boost Figure 4-2. Shutdown Specifications Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5 Detailed Description 5.1 Overview The TPS65835 integrates a linear charger, Boost Converter and an MSP430 to create a PMIC for active shutter 3D glasses. 5.2 Functional Block Diagram Figure 5-1. TPS65835 Simplified Functional Block Diagram 5.3 5.3.1 Feature Description System Operation The system must complete the power up routine before it enters normal operating mode. The specific system operation depends on the setting defined by the state of the SW_SEL pin. The details of the system operation for each configuration of the SW_SEL pin are contained in this section. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 13 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.3.1.1 www.ti.com System Power Up Figure 5-2. System Power Up State Diagram 14 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 5.3.1.2 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 System Operation Using Push Button Switch Figure 5-3. Push Button State Diagram Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 15 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.3.1.3 www.ti.com System Operation Using Slider Switch Figure 5-4. System Operation Using Slider Switch 16 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 5.3.2 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Linear Charger Operation This device has an integrated Li-Ion battery charger and system power path management feature targeted at space-limited portable applications. The architecture powers the system while simultaneously and independently charging the battery. This feature reduces the number of charge and discharge cycles on the battery, allows for proper charge termination, and enables the system to run with a defective or absent battery pack. It also allows instant system turn-on even with a totally discharged battery. The input power source for charging the battery and running the system can be an AC adapter or USB port connected to the VIN pin as long as the input meets the device operating conditions outlined in this datasheet. The power-path management feature automatically reduces the charging current if the system load increases. Note that the charger input, VIN, has voltage protection up to 28 V. 5.3.2.1 Battery and TS Detection To detect and determine between a good or damaged battery, the device checks for a short circuit on the BAT pin by sourcing IBAT(SC) to the battery and monitoring the voltage on the BAT pin. While sourcing this current if the BAT pin voltage exceeds VBAT(SC), a battery has been detected. If the voltage stays below the VBAT(SC) level, the battery is presumed to be damaged and not safe to charge. The device will also check for the presence of a 10-kΩ NTC thermistor attached to the TS pin of the device. The check for the NTC thermistor on the TS pin is done much like the battery detection feature described previously. The voltage on the TS pin is compared against a defined level and if it is found to be above the threshold, the NTC thermistor is assumed to be disconnected or not used in the system. To reduce the system quiescent current, the NTC thermistor temperature sensing function is only enabled when the device is charging and when the thermistor has been detected. Figure 5-5. Thermistor Detection and Circuit 5.3.2.2 Battery Charging The battery is charged in three phases: conditioning pre-charge, constant-current fast charge (current regulation), and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is exceeded. Figure 5-6 shows what happens in each of the three charge phases: Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 17 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Figure 5-6. Battery Charge Phases In the pre-charge phase, the battery is charged with the pre-charge current that is scaled to be 10% of the fast-charge current set by the resistor connected to the ISET pin. Once the battery voltage crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage reaches VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off as the battery approaches full charge. When the battery current reaches ITERM, the charger indicates charging is done by making the nCHG_STAT pin high impedance. Note that termination detection is disabled whenever the charge rate is reduced from the set point because of the actions of the thermal loop, the DPM loop, or the VIN(LOWV) loop. 5.3.2.2.1 Pre-charge The value for the pre-charge current is set to be 10% of the charge current that is set by the external resistor, RISET. Pre-charge current is scaled to lower currents when the charger is in thermal regulation. 5.3.2.2.2 Charge Termination In the fast charge state, once VBAT ≥ VBAT(REG), the charger enters constant voltage mode. In constant voltage mode, the charge current will taper until termination when the charge current falls below the I(TERM) threshold (typically 10% of the programmed fast charge current). Termination current is not scaled when the charger is in thermal regulation. When the charging is terminated, the nCHG_STAT pin will be high impedance (effectively turning off any LED that is connected to this pin). 5.3.2.2.3 Recharge Once a charge cycle is complete and termination is reached, the battery voltage is monitored. If VBAT < VBAT(REG) - VRCH, the device determines if the battery has been removed. If the battery is still present, then the recharge cycle begins and will end when VBAT ≥ VBAT(REG). 5.3.2.2.4 Charge Timers The charger in this device has internal safety timers for the pre-charge and fast charge phases to prevent potential damage to either the battery or the system. The default values for these timers are found as follows: Pre-charge timer = 0.5 hours (30 minutes) and Fast charge timer = 5 hours (300 minutes). 18 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 During the fast charge phase, the following events may increase the timer durations: 1. The system load current activates the DPM loop which reduces the available charging current 2. The input current is reduced because the input voltage has fallen to VIN(LOW) 3. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG) During each of these events, the internal timers are slowed down proportionately to the reduction in charging current. If the pre-charge timer expires before the battery voltage reaches VLOWV, the charger indicates a fault condition. 5.3.2.3 Charger Status (nCHG_STAT Pin) The nCHG_STAT pin is used to indicate the charger status by an externally connected resistor and LED circuit. The pin is an open drain input and the internal switch is controlled by the logic inside of the charger. This pin may also be connected to a GPIO of the system MCU to indicate charging status. The table below details the status of the nCHG_STAT pin for various operating states of the charger. Table 5-1. nCHG_STAT Functionality CHARGING STATUS 5.3.3 nCHG_STAT FET / LED Pre-charge / Fast Charge / Charge Termination ON Recharge OFF OVP OFF SLEEP OFF LDO Operation The power management core has a low dropout linear regulator (LDO) with variable output voltage capability. This LDO is used for supplying the microcontroller and may be used to supply either an external IR or RF module, depending on system requirements. The LDO can supply a continuous current of up to 30 mA. The output voltage (VVLDO) of the LDO is set by the state of the VLDO_SET pin. See Table 5-2 for details on setting the LDO output voltage. Table 5-2. VLDO_SET Functionality 5.3.3.1 VLDO_SET STATE VLDO OUTPUT VOLTAGE (VVLDO) Low (VLDO_SET < VIL(PMIC)) 2.2 V High (VLDO_SET > VIH(PMIC)) 3.0 V LDO Internal Current Limit The internal current limit feature helps protect the LDO regulator during fault conditions. During current limit, the output sources a fixed amount of current, defined in the Electrical Characteristics table. The voltage on the output in this stage can not be regulated and will be VOUT = ILIMIT × RLOAD. The pass transistor integrated into the LDO will dissipate power, (VIN - VOUT) × ILIMIT, until the device enters thermal shutdown. In thermal shutdown the device will enter the SLEEP / POWER OFF state which means that the LDO will then be disabled and shut off. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 19 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.3.4 www.ti.com Boost Converter Operation The boost converter in this device is designed for active shutter 3D glasses. This load is typically a light load where the average current is 2 mA or lower and the peak current out of a battery is limited in operation. This asynchronous boost converter operates with a minimum off time / maximum on time for the integrated low side switch, these values are specified in the Electrical Characteristics table of this datasheet. The peak output voltage from the boost converter is adjustable and set by using an external resistor divider connected between BST_OUT pin, BST_FB pin, and ground. The peak output voltage is set by choosing resistors for the feedback network such that the voltage on the BST_FB pin is VREF(BST) = 1.2 V. See Section 6.2.1.2.1 for more information on calculating resistance values for this feedback network. 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) The efficiency curves for various input voltages over the typical 3D glasses load range (2 mA and lower) are shown below. All curves are for a target VOUT of 16 V. For output voltages less than 16 V, a higher efficiency at each operating input voltage should be expected. Note that efficiency is dependent upon the external boost feedback network resistance, the inductor used, and the type of load connected. 60 50 40 60 50 40 30 30 20 20 10 VIN = 3.0 V 10 VOUT = 16.0 V VIN = 3.0 V 0 0.01 0.1 Output Current (mA) 1 VIN = 3.7 V 0 0.01 2 G000 VOUT = 16 V VIN = 3.7 V 100 100 90 90 80 80 70 70 60 50 40 20 VIN = 4.2 V 10 VOUT = 16.0 V 1 2 VIN = 5.5 V 0 0.01 G000 VOUT = 16 V VIN = 5.5 V Figure 5-9. Boost Efficiency vs IOUT 5.3.4.1 40 30 0.1 Output Current (mA) G000 VOUT = 16 V 50 20 VIN = 4.2 V 0 0.01 2 60 30 10 1 Figure 5-8. Boost Efficiency vs IOUT Efficiency (%) Efficiency (%) Figure 5-7. Boost Efficiency vs IOUT VOUT = 16.0 V 0.1 Output Current (mA) VOUT = 16.0 V 0.1 Output Current (mA) 1 2 G000 VOUT = 16 V Figure 5-10. Boost Efficiency vs IOUT Boost Thermal Shutdown An internal thermal shutdown mode is implemented in the boost converter that shuts down the device if the typical junction temperature of 105°C is exceeded. If the device is in thermal shutdown mode, the main switch of the boost is open and the device enters the SLEEP / POWER OFF state. 20 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 5.3.4.2 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Boost Load Disconnect When the boost is disabled (BST_EN = LOW), the H-bridge is automatically placed into the OFF state. In the OFF state the high side H-bridge switches are open and the low side switches of the H-bridge are closed. The OFF state grounds and discharges the load, potentially prolonging the life of the LC shutters by eliminating any DC content (see Section 5.3.5.1 for more information regarding the H-bridge states). The disconnection of the load is done with the H-Bridge and can be seen in the next figure (Figure 5-11). Figure 5-11. Boost Load Disconnect An advantage to this topology for disconnecting the load is that the boost output capacitor is charged to approximately the SYS voltage level, specifically VSYS - VDIODE(BST), when the boost is disabled. This design ensures that there is not a large in-rush current into the boost output capacitor when the boost is enabled. The boost operation efficiency is also increased because there is no load disconnect switch in the boost output path. A load disconnect switch would decrease efficiency because of the resistance that it would introduce. 5.3.5 Full H-Bridge Analog Switches The TPS65835 has two integrated full H-bridge analog switches that are connected to GPIO ports on the MSP430 and can be controlled by the MSP430 core for various system functions. There is an internal level shifter that manages the input signals to the H-Bridge switches. 5.3.5.1 H-Bridge Switch Control The H-Bridge switches are controlled by the MSP430 core for system operation - specifically to control charge polarity on the LCD shutters. Depending on the state of the signals from the MSP430 core, the HBridge will be put into 4 different states. These states are: • OPEN: All Switches Opened • CHARGE+: Boost Output Voltage Present on Pins LCLP or LCRP • CHARGE-: Boost Output Voltage Present on Pins LCLN or LCRN • GROUNDED: High side switches are opened and low side switches are closed Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 21 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com If CHARGE+ state is followed by the CHARGE- state, the voltage across the capacitor connected to the H-Bridge output terminals will be reversed. The system automatically switches to the GROUNDED state when the boost is disabled by the BST_EN pin. For more details, see Section 5.3.1. Table 5-3. H-Bridge States from Inputs H-Bridge STATE HBx2 [HBL2 & HBR2] HBx1 [HBL1 & HBR1] 0 0 OPEN 0 1 CHARGE + 1 0 CHARGE - 1 1 GROUNDED Figure 5-12. H-Bridge States Figure 5-13. H-Bridge States from Oscilloscope 22 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 5.3.6 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Power Management Core Control The power management core is controlled with external pins that can set system behavior by their status along with internal connections to GPIOs from the MSP430. The internal connections to the GPIOs from the MSP430 can be modified through the code implemented in the MSP430. 5.3.6.1 SLEEP / Power Control Pin Function The internal SLEEP signal between the power management device and the MSP430 can be used to control the power down behavior of the device. This has multiple practical applications such as a watchdog implementation for the communication between the sender (TV) and the receiver (3D glasses) or different required system on and off times; typically when the push-button press timing for an off event is a few seconds in length, programmable by software in the system MCU. If there is a requirement that the push-button press for system on and off events are different, the SLEEP signal must be set to a logic high value (VSLEEP > VIH(PMIC)) upon system startup. This implementation allows the device to power down the system on the falling edge of the SLEEP signal (when: VSLEEP < VIL(PMIC)). Figure 5-14. SLEEP Signal to Force System Power Off 5.3.6.2 COMP Pin Functionality The COMP pin is used to output a scaled down voltage level related to the battery voltage for input to the comparator of the MSP430. Applications for this COMP feature could be to generate an interrupt on the MSP430 when the battery voltage drops under a threshold and the device can then be shut down or indicate to the end user with an LED that the battery requires charging. Figure 5-15. COMP Pin Internal Connection Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 23 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 5-4. Scaling Resistors for COMP Pin Function (VVLDO = 2.2 V) SCALING RESISTORS FOR COMP PIN FUNCTION VALUE RBSCL1 3.0 MΩ RBSCL2 2.36 MΩ Table 5-5. Scaling Resistors for COMP Pin Function (VVLDO = 3.0 V) SCALING RESISTORS FOR COMP PIN FUNCTION VALUE RBSCL1 3.0 MΩ RBSCL2 2.48 MΩ Using the designed values in Table 5-4 or Table 5-5, the voltage on the COMP pin will be: VCOMP = 0.5 × VVLDO + 300 mV. This ensures that the COMP pin voltage will be close to half of the LDO output voltage plus the LDO dropout voltage of the device. The COMP pin can also be used as an input to ADC channel A0 of the integrated MSP430 microcontroller. This is useful if greater measurement accuracy or increased functionality is desired from this function. 5.3.6.3 SW_SEL Pin Functionality The SW_SEL pin is used to select what type of switch is connected to the SWITCH pin of the device. Selection between a push-button and a slider switch can be made based on the state of this pin. Table 5-6. SW_SEL Settings SW_SEL STATE TYPE OF SWITCH SELECTED Low (VSW_SEL < VIL(PMIC)) Slider Switch High (VSW_SEL > VIH(PMIC)) Push-button When the push button switch type is selected, the device will debounce the SWITCH input with a 32-ms timer for both the ON and OFF events and either power on or off the device. Using the push-button switch function, the ON and OFF timings are equal; tON = tOFF. If the system requirements are such that the on and off timings should be different, tON ≠ tOFF, then refer to the following section for the correct system setup: Section 6.2.1.2.2.When the slider switch operation is selected, the SWITCH pin must be externally pulled up to the SYS voltage with a resistor and the output connected to the slider switch. When the SWITCH pin is pulled to ground, the device will turn on and enter the power up sequence. 5.3.6.4 SWITCH Pin The SWITCH pin behavior is defined by the SW_SEL pin (Section 5.3.6.3) which defines the type of switch that is connected to the system; either a slider switch or push-button. 5.3.6.5 Slider Switch Behavior If a slider switch is connected in the system then the system power state and VLDO output (which powers the internal MSP430) is defined by the state of the slider switch. If the slider is in the off position than the SWITCH pin should be connected to the SYS pin. If the slider is in the on position than the SWITCH pin should be connected to ground. Figure 5-16 details the system operation using the slider switch configuration. 24 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Figure 5-16. SWITCH, Slider Power On-Off Behavior 5.3.6.6 Push-Button Switch Behavior The system is powered on or off by a push-button press after a press that is greater than 32 ms. The following figures (Figure 5-17 and Figure 5-18) show the system behavior and the expected VLDO output during the normal push-button operation where the ON and OFF press timings are the same value, tON = tOFF. Figure 5-17. SWITCH, Push-button Power On Behavior Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 25 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Figure 5-18. SWITCH, Push-Button Power Off Behavior 5.4 5.4.1 Device Functional Modes SLEEP State If the device is in the SLEEP State or Device IDLE mode, the Sleep control supervisor and the battery charger/power path remain active. The Boost and LDO are disabled. 5.4.2 NORMAL Operating Mode Once the system completes the power up routine, it enters the normal operating mode. The specific system operation is set by the SW_SEL pin. 26 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 5.5 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 MSP430 CORE 5.5.1 5.5.1.1 MSP430 Electrical Characteristics MSP430 Recommended Operating Conditions MIN VCC Supply voltage VSS Supply voltage (1) (2) MAX 1.8 3.6 During flash programming/erase 2.2 3.6 0 Processor frequency (maximum MCLK frequency using the USART module) (1) (2) fSYSTEM NOM During program execution UNIT V V VCC = 1.8 V, Duty cycle = 50% ± 10% dc 6 VCC = 2.7 V, Duty cycle = 50% ± 10% dc 12 VCC = 3.3 V, Duty cycle = 50% ± 10% dc 16 MHz The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. Legend : System Frequency - MHz 16 MHz Supply voltage range, during flash memory programming 12 MHz Supply voltage range, during program execution 6 MHz 1.8 V Note: 2.7 V 2.2 V Supply Voltage - V 3.3 V 3.6 V Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 5-19. Safe Operating Area 5.5.1.2 Active Mode Supply Current Into VCC Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER IAM,1MHz (1) (2) Active mode (AM) current at 1 MHz TEST CONDITIONS TA fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 0 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 VCC MIN TYP 2.2 V 230 3V 330 MAX 420 UNIT µA All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 27 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.5.1.3 www.ti.com Typical Characteristics, Active Mode Supply Current (Into VCC) 5.0 4.0 Active Mode Current − mA Active Mode Current − mA f DCO = 16 MHz 4.0 3.0 f DCO = 12 MHz 2.0 f DCO = 8 MHz 1.0 TA = 85 °C 3.0 TA = 25 °C VCC = 3 V 2.0 TA = 85 °C TA = 25 °C 1.0 f DCO = 1 MHz 0.0 1.5 2.0 2.5 3.0 3.5 VCC = 2.2 V 4.0 VCC − Supply Voltage − V Figure 5-20. Active Mode Current vs VCC, TA = 25°C 5.5.1.4 0.0 0.0 4.0 8.0 12.0 16.0 f DCO − DCO Frequency − MHz Figure 5-21. Active Mode Current vs DCO Frequency Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2) PARAMETER TA VCC Low-power mode 0 (LPM0) current(3) fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25°C 2.2 V 56 µA ILPM2 Low-power mode 2 (LPM2) current(4) fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 22 µA ILPM3,LFXT1 Low-power mode 3 (LPM3) current(4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 0.7 1.5 µA ILPM3,VLO Low-power mode 3 current, (LPM3)(4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 0.5 0.7 µA 0.5 Low-power mode 4 (LPM4) current(5) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 0.1 ILPM4 0.8 1.7 ILPM0,1MHz TEST CONDITIONS 25°C 85°C 2.2 V MIN TYP MAX UNIT µA (1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. (3) Current for brownout and WDT clocked by SMCLK included. (4) Current for brownout and WDT clocked by ACLK included. (5) Current for brownout included. 28 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 5.5.1.5 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Typical Characteristics, Low-Power Mode Supply Currents 3.00 2.50 2.75 2.25 ILPM4 – Low-Power Mode Current – µA ILPM3 – Low-Power Mode Current – µA over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 2.50 2.25 2.00 1.75 1.50 Vcc = 3.6 V 1.25 Vcc = 3 V 1.00 Vcc = 2.2 V 0.75 0.50 Vcc = 1.8 V 0.25 0.00 -40 0 -20 40 20 60 1.75 1.50 1.25 Vcc = 3.6 V 1.00 Vcc = 3 V 0.75 Vcc = 2.2 V 0.50 0.25 0.00 -40 80 Vcc = 1.8 V -20 0 20 40 60 80 TA – Temperature – °C Figure 5-23. LPM4 Current vs Temperature TA – Temperature – °C Figure 5-22. LPM3 Current vs Temperature 5.5.1.6 2.00 Schmitt-Trigger Inputs, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) MIN 3V RPull Pull-up/pull-down resistor For pull-up: VIN = VSS For pull-down: VIN = VCC CI Input capacitance VIN = VSS or VCC 5.5.1.7 VCC TYP MAX 0.45 VCC 0.75 VCC 1.35 2.25 UNIT V 0.25 VCC 0.55 VCC 3V 0.75 1.65 3V 0.3 1 V 3V 20 50 kΩ 35 5 V pF Leakage Current, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) TEST CONDITIONS (1) (2) High-impedance leakage current VCC MIN 3V MAX UNIT ±50 nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is disabled. 5.5.1.8 Outputs, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOH High-level output voltage I(OHmax) = –6 mA (1) 3V VCC – 0.3 V VOL Low-level output voltage I(OLmax) = 6 mA (1) 3V VSS + 0.3 V (1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 29 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.5.1.9 www.ti.com Output Frequency, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fPx.y Port output frequency (with load) Px.y, CL = 20 pF, RL = 1 kΩ (1) fPort_CLK Clock output frequency Px.y, CL = 20 pF (2) (1) (2) VCC (2) MIN TYP MAX UNIT 3V 12 MHz 3V 16 MHz A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 5.5.1.10 Typical Characteristics, Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 50 VCC = 2.2 V P1.7 TA = 25°C 25 TA = 85°C 20 15 10 5 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 30 0 0.5 1 1.5 2 40 TA = 85°C 30 20 10 2.5 VOL − Low-Level Output Voltage − V Figure 5-24. Typical Low-Level Output Current vs Low-Level Output Voltage 0 0.5 1 1.5 2 2.5 3 3.5 VOL − Low-Level Output Voltage − V Figure 5-25. Typical Low-Level Output Current vs Low-Level Output Voltage 0 0 VCC = 2.2 V P1.7 I OH − Typical High-Level Output Current − mA I OH − Typical High-Level Output Current − mA TA = 25°C 0 0 −5 −10 −15 TA = 85°C −20 TA = 25°C −25 0 0.5 VCC = 3 V P1.7 −10 −20 −30 TA = 85°C −40 TA = 25°C −50 1 1.5 2 2.5 VOH − High-Level Output Voltage − V Figure 5-26. Typical High-Level Output Current vs High-Level Output Voltage 30 VCC = 3 V P1.7 0 0.5 1 1.5 2 2.5 3 3.5 VOH − High-Level Output Voltage − V Figure 5-27. Typical High-Level Output Current vs High-Level Output Voltage Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 5.5.1.11 Pin-Oscillator Frequency – Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER foP1.x Port output oscillation frequency foP2.x Port output oscillation frequency foP2.6/7 Port output oscillation frequency foP3.x Port output oscillation frequency (1) (2) TEST CONDITIONS VCC P1.y, CL = 10 pF, RL = 100 kΩ (1) (2) MIN TYP 3V P1.y, CL = 20 pF, RL = 100 kΩ (1) (2) MAX UNIT 1400 kHz 900 P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ (1) (2) 1800 P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ (1) (2) 3V 1000 P2.6 and P2.7, CL = 20 pF, RL = 100 kΩ (1) (2) 3V 700 P3.y, CL = 10 pF, RL = 100 kΩ (1) (2) 1800 P3.y, CL = 20 pF, RL = 100 kΩ (1) (2) 1000 kHz kHz kHz A resistive divider with two 0.5-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 5.5.1.12 Typical Characteristics, Pin-Oscillator Frequency 1.50 VCC = 3.0 V 1.35 fosc − Typical Oscillation Frequency − MHz fosc − Typical Oscillation Frequency − MHz 1.50 1.20 1.05 P1.y 0.90 P2.0 ... P2.5 0.75 P2.6, P2.7 0.60 0.45 0.30 0.15 0.00 VCC = 2.2 V 1.35 1.20 1.05 P1.y 0.90 P2.0 ... P2.5 0.75 P2.6, P2.7 0.60 0.45 0.30 0.15 0.00 10 50 100 10 CLOAD − External Capacitance − pF 50 100 CLOAD − External Capacitance − pF One output active at a time. Figure 5-28. Typical Oscillating Frequency vs Load Capacitance One output active at a time. Figure 5-29. Typical Oscillating Frequency vs Load Capacitance 5.5.1.13 POR/Brownout Reset (BOR) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC(start) See Figure 5-30 dVCC/dt ≤ 3 V/s V(B_IT–) See Figure 5-30 through Figure 5-32 dVCC/dt ≤ 3 V/s Vhys(B_IT–) See Figure 5-30 dVCC/dt ≤ 3 V/s td(BOR) See Figure 5-30 t(reset) Pulse length needed at RST/NMI pin to accepted reset internally (1) VCC MIN TYP MAX 0.7 × V(B_IT--) 2.2 V UNIT V 1.35 V 140 mV 2000 µs 2 µs The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) + Vhys(B_IT–)is ≤ 1.8 V. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 31 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com VCC Vhys(B_IT−) V(B_IT−) VCC(star t) 1 0 t d(BOR) Figure 5-30. POR/Brownout Reset (BOR) vs Supply Voltage 5.5.1.14 Typical Characteristics, POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw − Pulse Width − µs 1 ns t pw − Pulse Width − µs Figure 5-31. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) − V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 t f = tr 0 0.001 1 1000 tf tr t pw − Pulse Width − µs t pw − Pulse Width − µs Figure 5-32. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal 32 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.5.1.15 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC Supply voltage TEST CONDITIONS VCC MIN TYP MAX RSELx < 14 1.8 3.6 RSELx = 14 2.2 3.6 RSELx = 15 3 3.6 UNIT V fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3V 0.06 0.14 MHz fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3V 0.07 0.17 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3V 0.15 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3V 0.21 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3V 0.30 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3V 0.41 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3V 0.58 fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3V 0.54 fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3V 0.80 fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3V 1.6 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3V 2.3 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3V 3.4 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3V fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3V 4.30 fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3V 6.00 fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3V fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 3V 1.35 ratio SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 3V 1.08 ratio Measured at SMCLK output 3V 50% Duty cycle MHz 1.06 MHz 1.50 MHz 4.25 MHz 7.30 MHz 9.60 MHz 8.60 13.9 MHz 12.0 18.5 MHz 16.0 26.0 MHz 7.8 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 33 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 5.5.1.16 Calibrated DCO Frequencies, Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC MIN TYP MAX 1-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V 0°C to 85°C 3V –3% ±0.5% 3% 1-MHz tolerance over VCC BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V 30°C 1.8 V to 3.6 V –3% ±2% 3% 1-MHz tolerance overall BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V –40°C to 85°C 1.8 V to 3.6 V –6% ±3% 6% 8-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V 0°C to 85°C 3V –3% ±0.5% 3% 8-MHz tolerance over VCC BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V 30°C 2.2 V to 3.6 V –3% ±2% 3% 8-MHz tolerance overall BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V –40°C to 85°C 2.2 V to 3.6 V –6% ±3% 6% 12-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V 0°C to 85°C 3V –3% ±0.5% 3% 12-MHz tolerance over VCC BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V 30°C 2.7 V to 3.6 V –3% ±2% 3% 12-MHz tolerance overall BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V –40°C to 85°C 2.7 V to 3.6 V –6% ±3% 6% 16-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V 0°C to 85°C 3V –3% ±0.5% 3% 16-MHz tolerance over VCC BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V 30°C 3.3 V to 3.6 V –3% ±2% 3% 16-MHz tolerance overall BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V –40°C to 85°C 3.3 V to 3.6 V –6% ±3% 6% (1) 34 TEST CONDITIONS UNIT This is the frequency change from the measured frequency at 30°C over temperature. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.5.1.17 Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tDCO,LPM3/4 DCO clock wake-up time from LPM3/4 (1) tCPU,LPM3/4 CPU wake-up time from LPM3/4 (2) (1) (2) VCC BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz MIN TYP 3V MAX UNIT 1.5 µs 1/fMCLK + tClock,LPM3/4 The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. 5.5.1.18 Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4 DCO Wake Time − µs 10.00 RSELx = 0...11 RSELx = 12...15 1.00 0.10 0.10 1.00 10.00 DCO Frequency − MHz Figure 5-33. DCO Wake-Up Time From LPM3 vs DCO Frequency Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 35 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 5.5.1.19 Crystal Oscillator, XT1, Low-Frequency Mode over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER (1) TEST CONDITIONS fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 LF mode OALF Oscillation allowance for LF crystals Integrated effective load capacitance, LF mode (2) CL,eff XTS = 0, LFXT1Sx = 0 or 1 10000 32768 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF 200 1 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 Oscillator fault frequency, LF mode (3) XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4) UNIT Hz 50000 Hz kΩ XTS = 0, XCAPx = 0 fFault,LF (4) 1.8 V to 3.6 V MAX 32768 500 LF mode (3) TYP XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF Duty cycle (2) MIN 1.8 V to 3.6 V XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz (1) VCC 2.2 V 30% 2.2 V 10 50% pF 70% 10000 Hz To • • • • • • • improve EMI on the XT1 oscillator, the following guidelines should be observed. Keep the trace between the device and the crystal as short as possible. Design a good ground plane around the oscillator pins. Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. 5.5.1.20 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TA VCC MIN 4 fVLO VLO frequency –40°C to 85°C 3V dfVLO/dT VLO frequency temperature drift –40°C to 85°C 3V 25°C 1.8 V to 3.6 V dfVLO/dVCC VLO frequency supply voltage drift 36 Detailed Description TYP MAX 12 20 UNIT kHz 0.5 %/°C 4 %/V Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.5.1.21 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fTA Timer_A input clock frequency SMCLK, duty cycle = 50% ± 10% tTA,cap Timer_A capture timing TA0, TA1 MIN TYP MAX fSYSTEM 3V UNIT MHz 20 ns 5.5.1.22 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fUSCI USCI input clock frequency fmax,BITCLK Maximum BITCLK clock frequency (equals baudrate in MBaud) (1) tτ (1) (2) UART receive deglitch time VCC MIN SMCLK, duty cycle = 50% ± 10% (2) TYP MAX fSYSTEM 3V 2 3V 50 UNIT MHz MHz 100 600 ns The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their width should exceed the maximum specification of the deglitch time. 5.5.1.23 USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-34 and Figure 5-35) PARAMETER TEST CONDITIONS VCC MIN SMCLK, duty cycle = 50% ± 10% TYP MAX UNIT fSYSTEM MHz fUSCI USCI input clock frequency tSU,MI SOMI input data setup time 3V 75 ns tHD,MI SOMI input data hold time 3V 0 ns tVALID,MO SIMO output data valid time UCLK edge to SIMO valid, CL = 20 pF 3V 20 ns 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 5-34. SPI Master Mode, CKPH = 0 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 37 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,MI tSU,MI SOMI tHD,MO tVALID,MO SIMO Figure 5-35. SPI Master Mode, CKPH = 1 5.5.1.24 USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-36 and Figure 5-37) PARAMETER TEST CONDITIONS VCC MIN TYP MAX STE lead time, STE low to clock 3V tSTE,LAG STE lag time, Last clock to STE high 3V tSTE,ACC STE access time, STE low to SOMI data out 3V 50 ns tSTE,DIS STE disable time, STE high to SOMI high impedance 3V 50 ns tSU,SI SIMO input data setup time 3V 15 ns tHD,SI SIMO input data hold time 3V 10 ns tVALID,SO UCLK edge to SOMI valid, CL = 20 pF SOMI output data valid time tSTE,LEAD 3V 50 UNIT tSTE,LEAD ns 10 ns 50 75 ns tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tSTE,ACC tHD,SO tVALID,SO tSTE,DIS SOMI Figure 5-36. SPI Slave Mode, CKPH = 0 38 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tHD,MO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 5-37. SPI Slave Mode, CKPH = 1 5.5.1.25 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-38) PARAMETER TEST CONDITIONS fUSCI USCI input clock frequency fSCL SCL clock frequency VCC MIN TYP SMCLK, duty cycle = 50% ± 10% 3V fSCL ≤ 100 kHz 0 MAX UNIT fSYSTEM MHz 400 kHz 4.0 tHD,STA Hold time (repeated) START 3V tSU,STA Setup time for a repeated START tHD,DAT Data hold time 3V 0 ns tSU,DAT Data setup time 3V 250 ns tSU,STO Setup time for STOP 3V 4.0 µs tSP Pulse width of spikes suppressed by input filter 3V 50 fSCL > 100 kHz fSCL ≤ 100 kHz tSU,STA tHD,STA 4.7 3V fSCL > 100 kHz µs 0.6 µs 0.6 tHD,STA 100 600 ns tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 5-38. I2C Mode Timing Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 39 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 5.5.1.26 Comparator_A+ over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT I(DD) (1) CAON = 1, CARSEL = 0, CAREF = 0 3V 45 µA I(Refladder/ CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at CA0 and CA1 3V 45 µA Common–mode input voltage CAON = 1 3V V(Ref025) (Voltage at 0.25 VCC node) / VCC PCA0 = 1, CARSEL = 1, CAREF = 1, No load at CA0 and CA1 3V 0.24 V(Ref050) (Voltage at 0.5 VCC node) / VCC PCA0 = 1, CARSEL = 1, CAREF = 2, No load at CA0 and CA1 3V 0.48 V(RefVT) See Figure 5-39 and Figure 5-40 PCA0 = 1, CARSEL = 1, CAREF = 3, No load at CA0 and CA1, TA = 85°C 3V 490 mV 3V ±10 mV 3V 0.7 mV 120 ns 1.5 µs RefDiode) V(IC) (2) V(offset) Offset voltage Vhys Input hysteresis t(response) Response time (low-high and high-low) (1) (2) CAON = 1 TA = 25°C, Overdrive 10 mV, Without filter: CAF = 0 0 VCC-1 V 3V TA = 25°C, Overdrive 10 mV, With filter: CAF = 1 The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.y) specification. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together. 5.5.1.27 Typical Characteristics – Comparator_A+ 650 650 VCC = 2.2 V V(RefVT) – Reference Voltage – mV V(RefVT) – Reference Voltage – mV VCC = 3 V 600 Typical 550 500 450 400 -45 Typical 550 500 450 400 -5 15 35 55 75 95 TA – Free-Air Temperature – °C Figure 5-39. V(RefVT) vs Temperature, VCC = 3 V 40 600 -25 115 -45 -5 15 35 55 75 95 TA – Free-Air Temperature – °C Figure 5-40. V(RefVT) vs Temperature, VCC = 2.2 V Detailed Description -25 115 Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Short Resistance – kW 100 VCC = 1.8 V VCC = 2.2 V VCC = 3 V 10 VCC = 3.6 V 1 0 0.2 0.4 0.6 0.8 1 VIN/VCC – Normalized Input Voltage – V/V Figure 5-41. Short Resistance vs VIN/VCC 5.5.1.28 10-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC Analog supply voltage VSS = 0 V VAx Analog input voltage(2) All Ax terminals, Analog inputs selected in ADC10AE register IADC10 ADC10 supply current(3) fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0 IREF+ Reference supply current, reference buffer disabled(4) fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0 fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0 TA VCC 3V 25°C 3V MIN TYP MAX UNIT 2.2 3.6 V 0 VCC V 0.6 mA 0.25 25°C 3V mA 0.25 IREFB,0 fADC10CLK = 5.0 MHz, Reference buffer supply ADC10ON = 0, REFON = 1, (4) current with ADC10SR = 0 REF2_5V = 0, REFOUT = 1, ADC10SR = 0 25°C 3V 1.1 mA IREFB,1 fADC10CLK = 5.0 MHz, Reference buffer supply ADC10ON = 0, REFON = 1, (4) current with ADC10SR = 1 REF2_5V = 0, REFOUT = 1, ADC10SR = 1 25°C 3V 0.5 mA CI Input capacitance Only one terminal Ax can be selected at one time 25°C 3V RI Input MUX ON resistance 0 V ≤ VAx ≤ VCC 25°C 3V 27 1000 pF Ω (1) The leakage current is defined in the leakage current table with Px.y/Ax parameter. (2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. (3) The internal reference supply current is not included in current consumption parameter IADC10. (4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 41 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 5.5.1.29 10-Bit ADC, Built-In Voltage Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IVREF+ ≤ 1 mA, REF2_5V = 0 VCC,REF+ Positive built-in reference analog supply voltage range IVREF+ ≤ 1 mA, REF2_5V = 1 VREF+ Positive built-in reference voltage ILD,VREF+ Maximum VREF+ load current VREF+ load regulation IVREF+ ≤ IVREF+max, REF2_5V = 0 IVREF+ ≤ IVREF+max, REF2_5V = 1 MIN TYP IVREF+ = 500 µA ± 100 µA, Analog input voltage VAx ≉ 1.25 V, REF2_5V = 1 UNIT V 2.9 3V 1.41 1.5 1.59 2.35 2.5 2.65 3V IVREF+ = 500 µA ± 100 µA, Analog input voltage VAx ≉ 0.75 V, REF2_5V = 0 MAX 2.2 ±1 V mA ±2 3V LSB ±2 VREF+ load regulation response time IVREF+ = 100 µA→900 µA, VAx ≉ 0.5 × VREF+, Error of conversion result ≤ 1 LSB, ADC10SR = 0 3V 400 ns CVREF+ Maximum capacitance at pin VREF+ IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1 3V 100 pF TCREF+ Temperature coefficient IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA 3V ±100 ppm/ °C tREFON Settling time of internal reference voltage to 99.9% VREF IVREF+ = 0.5 mA, REF2_5V = 0, REFON = 0 → 1 3.6 V 30 µs tREFBURST Settling time of reference buffer to 99.9% VREF IVREF+ = 0.5 mA, REF2_5V = 1, REFON = 1, REFBURST = 1, ADC10SR = 0 3V 2 µs 5.5.1.30 10-Bit ADC, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER VEREF+ Positive external reference input voltage range (2) TEST CONDITIONS UNIT VEREF– ≤ VEREF+ ≤ VCC – 0.15 V, SREF1 = 1, SREF0 = 1 (3) 1.4 3 0 1.2 V 1.4 VCC V ΔVEREF Differential external reference input voltage range, ΔVEREF = VEREF+ – VEREF– VEREF+ > VEREF– Static input current into VEREF– MAX VCC VEREF+ > VEREF– IVEREF– TYP 1.4 Negative external reference input voltage range (4) Static input current into VEREF+ MIN VEREF+ > VEREF–, SREF1 = 1, SREF0 = 0 VEREF– IVEREF+ VCC V (5) 0 V ≤ VEREF+ ≤ VCC, SREF1 = 1, SREF0 = 0 3V ±1 0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V, SREF1 = 1, SREF0 = 1(3) 3V 0 0 V ≤ VEREF– ≤ VCC 3V ±1 µA µA (1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. (2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. (3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1. (4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. (5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 42 Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 5.5.1.31 10-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC ADC10SR = 0 MIN TYP MAX 0.45 6.3 0.45 1.5 fADC10CLK ADC10 input clock frequency For specified performance of ADC10 linearity parameters fADC10OSC ADC10 built-in oscillator frequency ADC10DIVx = 0, ADC10SSELx = 0, fADC10CLK = fADC10OSC 3V 3.7 6.3 ADC10 built-in oscillator, ADC10SSELx = 0, fADC10CLK = fADC10OSC 3V 2.06 3.51 tCONVERT Conversion time tADC10ON Turn-on settling time of the ADC (1) ADC10SR = 1 3V UNIT MHz MHz µs 13 × ADC10DIV × 1/fADC10CLK fADC10CLK from ACLK, MCLK, or SMCLK: ADC10SSELx ≠ 0 (1) 100 ns The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled. 5.5.1.32 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integral linearity error 3V ±1 LSB ED Differential linearity error 3V ±1 LSB EO Offset error 3V ±1 LSB EG Gain error 3V ±1.1 ±2 LSB ET Total unadjusted error 3V ±2 ±5 LSB TYP MAX UNIT Source impedance RS < 100 Ω 5.5.1.33 10-Bit ADC, Temperature Sensor and Built-In VMID over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ISENSOR Temperature sensor supply current (1) TCSENSOR TEST CONDITIONS VCC REFON = 0, INCHx = 0Ah, TA = 25°C ADC10ON = 1, INCHx = 0Ah (2) 3V 60 3V 3.55 tSensor(sample) Sample time required if channel 10 is selected (3) ADC10ON = 1, INCHx = 0Ah, Error of conversion result ≤ 1 LSB 3V IVMID Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh 3V VMID VCC divider at channel 11 ADC10ON = 1, INCHx = 0Bh, VMID ≉ 0.5 × VCC 3V tVMID(sample) Sample time required if channel 11 is selected (5) ADC10ON = 1, INCHx = 0Bh, Error of conversion result ≤ 1 LSB 3V (1) (2) (3) (4) (5) MIN µA mV/°C 30 µs (4) 1.5 1220 µA V ns The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah). The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV] The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). No additional current is needed. The VMID is used during sampling. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 43 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 5.5.1.34 Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 7 mA 10 ms (1) tCPT Cumulative program time tCMErase Cumulative mass erase time 2.2 V/3.6 V 2.2 V/3.6 V 20 104 Program/erase endurance ms 105 cycles tRetention Data retention duration TJ = 25°C tWord Word or byte program time (2) 30 tFTG tBlock, Block program time for first byte or word (2) 25 tFTG Block program time for each additional byte or word (2) 18 tFTG Block program end-sequence wait time (2) 6 tFTG Mass erase time (2) 10593 tFTG Segment erase time (2) 4819 tFTG 0 tBlock, 1-63 tBlock, End tMass Erase tSeg (1) (2) Erase 100 years The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). 5.5.1.35 RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage TEST CONDITIONS (1) MIN CPU halted MAX 1.6 UNIT V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. 5.5.1.36 JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MAX UNIT fSBW Spy-Bi-Wire input frequency PARAMETER 2.2 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V 0.025 15 µs tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) 2.2 V 1 µs tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V 100 µs (2) 2.2 V 0 2.2 V 25 fTCK TCK input frequency RInternal Internal pulldown resistance on TEST (1) (2) TEST CONDITIONS VCC MIN TYP 15 60 5 MHz 90 kΩ Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. 5.5.1.37 JTAG Fuse over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TEST for fuse blow IFB Supply current into TEST during fuse blow tFB (1) 44 TA = 25°C MIN 6 Time to blow fuse MAX 2.5 UNIT V 7 V 100 mA 1 ms Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 5.5.2 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 MSP430 Core Operation NOTE For support and specific questions related to the MSP430 in the TPS65835 device, please refer to TI's E2E PMU forum and post relevant questions to the forum at the following link: TI E2E PMU Forum. Please format your posting as follows: • Title: TPS65835 "specific topic" • Body: Question, with supporting code and oscilloscope screen captures if applicable. 5.5.2.1 Description The MSP430 integrated into the TPS65835 is from the MSP430x2xx family of ultralow-power microcontrollers. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1␣s. The list of the peripherals and modules included in this MSP430 are as follows: • Up to 16 MHz CPU • 16 kB Flash Memory • 512 B RAM • Basic Clock Module – Internal Frequencies up to 16 MHz with one Calibrated Frequency – Internal Very-Low-Power Low-Frequency (LF) Oscillator – 32 kHz Crystal Support – External Digital Clock Source • 10-Bit ADC – 200-ksps Analog-to-Digital (A/D) Converter with Internal Reference, Sample-and-Hold, and Autoscan • Comparator A+ (Comp_A+) – For Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion • Timer0_A3 and Timer1_A3 – Up to Two 16-Bit Timer_A with Three Capture/Compare Registers • Watchdog WDT+ • USCI A0, Universal Serial Communication Interface – Enhanced UART Supporting Auto Baudrate Detection (LIN) – IrDA Encoder and Decoder – Synchronous SPI – I2C • USCI B0, Universal Serial Communication Interface – Synchronous SPI – I2C • JTAG / Spy-By-Wire Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 45 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Figure 5-42. MSP430 Functional Block Diagram 5.5.2.2 Accessible MSP430 Pins There are a number of internal pins connected between the MSP430 core and the power management core as well as external pins on the MSP430. Internal pins are not available externally but can be controlled by the MSP430 core in various ways. A table describing all available MSP430 pin functions (Table 5-7) along with a block diagram detailing the MSP430 core and the pin connectivity (see Figure 542) has been made available. Table 5-7. Internally Connected Pins: MSP430 to Power Management Core POWER MANAGEMENT CORE PIN MSP430 CORE PIN VLDO AVCC / DVCC Voltage supplied by LDO on power management core, connected to MSP430 power management module Enabled by SWITCH pin input COMP P1.0 / A0 / CA0 Scaled down voltage of the BAT pin. Connected to Comparator_A+ channel CA0 or ADC channel A0 of the MSP430 To use COMP and Comp_A+ module function of the MSP430, the pin must be configured properly DO NOT CONFIGURE THIS PIN AS A GPIO AND PULL THIS PIN UP OR DOWN, THIS WILL INCREASE THE OPERATING CURRENT OF THE DEVICE BST_EN P3.2 Enable pin for the boost on the power management core, ACTIVE HIGH CHG_EN P3.1 Enable pin for the charger on the power management core, ACTIVE HIGH SLEEP P3.0 Can put entire device into SLEEP state dependent upon system events, e.g., extended loss of IR or RF synchronization (1) HBL1 P2.0 Control pin 1 for left frame of active shutter glasses HBL2 P2.3 Control pin 2 for left frame of active shutter glasses HBR1 P2.4 Control pin 1 for right frame of active shutter glasses HBR2 P2.5 Control pin 2 for right frame of active shutter glasses (1) 46 FUNCTIONALITY Note that the SLEEP signal can not be used to wake the system if it is already in the SLEEP state since the LDO used to power the MSP430 would be disabled in this state. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Table 5-8. Externally Available MSP430 Pins PIN NAME I/O FUNCTIONALITY I/O General-purpose digital I/O pin Timer0_A, capture: CCI0A input, compare: Out0 output USCI_A0 receive data input in UART mode USCI_A0 slave data out/master in SPI mode ADC10 analog input A1 Comparator_A+, CA1 input I/O General-purpose digital I/O pin Timer0_A, capture: CCI1A input, compare: Out1 output USCI_A0 transmit data output in UART mode USCI_A0 slave data in/master out in SPI mode ADC10 analog input A2 Comparator_A+, CA2 input I/O General-purpose digital I/O pin ADC10, conversion clock output ADC10 analog input A3 ADC10 negative reference voltage Comparator_A+, CA3 input Comparator_A+, output I/O General-purpose digital I/O pin SMCLK signal output USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10 analog input A4 ADC10 positive reference voltage Comparator_A+, CA4 input JTAG test clock, input terminal for device programming and test I/O General-purpose digital I/O pin Timer0_A, compare: Out0 output USCI_B0 clock input/output USCI_A0 slave transmit enable ADC10 analog input A5 Comparator_A+, CA5 input JTAG test mode select, input terminal for device programming and test I/O General-purpose digital I/O pin Timer0_A, compare: Out1 output ADC10 analog input A6 Comparator_A+, CA6 input USCI_B0 slave out/master in SPI mode USCI_B0 SCL I2C clock in I2C mode JTAG test data input or test clock input during programming and test P1.7/ A7/ CA7/ CAOUT/ UCB0SIMO/ UCB0SDA/ TDO/TDI I/O General-purpose digital I/O pin ADC10 analog input A7 Comparator_A+, CA7 input Comparator_A+, output USCI_B0 slave in/master out in SPI mode USCI_B0 SDA I2C data in I2C mode JTAG test data output terminal or test data input during programming and test (1) P2.1/ TA1.1 I/O General-purpose digital I/O pin Timer1_A, capture: CCI1A input, compare: Out1 output P2.2/ TA1.1 I/O General-purpose digital I/O pin Timer1_A, capture: CCI1B input, compare: Out1 output P2.6/ XIN/ TA0.1 I/O General-purpose digital I/O pin XIN, Input terminal of crystal oscillator TA0.1, Timer0_A, compare: Out1 output P2.7/ XOUT I/O General-purpose digital I/O pin Output terminal of crystal oscillator (2)) P3.3/ TA1.2 I/O General-purpose digital I/O pin Timer1_A, compare: Out2 output P3.5/ TA0.1 I/O General-purpose digital I/O pin Timer0_A, compare: Out0 output P1.1/ TA0.0/ UCA0RXD/ UCA0SOMI/ A1/ CA1 P1.2/ TA0.1/ UCA0TXD/ UCA0SIMO/ A2/ CA2 P1.3/ ADC10CLK/ A3 VREF-/VEREF-/ CA3/ CAOUT P1.4/ SMCLK/ UCB0STE UCA0CLK/ A4 VREF+/VEREF+/ CA4 TCK P1.5/ TA0.0/ UCB0CLK/ UCA0STE/ A5/ CA5/ TMS P1.6/ TA0.1/ A6/ CA6/ UCB0SOMI/ UCB0SCL/ TDI/TCLK (1) (2) TDO or TDI is selected via JTAG instruction. If P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 47 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 5-8. Externally Available MSP430 Pins (continued) PIN NAME I/O FUNCTIONALITY nRST/ NMI/ SBWTDIO I Reset Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/ SBWTCK I Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test DVSS N/A 5.5.2.3 MSP430 ground reference MSP430 Port Functions and Programming Options This section details the programming options that are available for each of the pins that are accessible on the MSP430. Table 5-9. Internal MSP430 Pin Functions and Programming Options PIN NAME (P_.x) (1) MSP430 CONTROL BITS / SIGNALS x P1.0/ A0/ P1.x (I/O) 0 CA0 P2.0/ FUNCTION 0 0 0 X 1 (y = 0) 0 CA0 X X X 0 1 (y = 0) I: 0; O: 1 0 0 — — 1 1 0 — — I: 0; O: 1 0 0 — — 1 1 0 — — I: 0; O: 1 0 0 — — 1 1 0 — — I: 0; O: 1 0 0 — — P2.x (I/O), HBL1 internal signal Timer1_A3.TA0 P2.4/ P2.x (I/O), HBR1 internal signal TA1.2 Timer1_A3.TA2 P2.5/ P2.x (I/O), HBR2 internal signal TA1.2 Timer1_A3.TA2 P3.0/ P3.x (I/O), SLEEP signal P3.1/ 1 Timer0_A3.TA2 P3.x (I/O), CHG_EN signal, ACTIVE HIGH TA1.2 Timer1_A3.TA2 P3.2/ P3.x (I/O), BST_EN signal, ACTIVE HIGH TA1.2 (1) (2) 48 2 0 0 TA1.0 0 CAPD.y X P2.3/ TA0.2 ADC10AE.x INCH.x=1 X P2.x (I/O), HBL2 internal signal 5 P_SEL2.x I: 0; O: 1 Timer1_A3.TA0 4 P_SEL.x A0 TA1.0 3 P_DIR.x (2) Timer1_A3.TA2 1 1 0 — — I: 0; O: 1 0 0 — — 1 1 0 — — I: 0; O: 1 0 0 — — 1 1 0 — — I: 0; O: 1 0 0 — — 1 1 0 — — Example: To program port P2.0, the appropriate control bits and MSP430 signals would need to be referenced as P2DIR.0, P2SEL.0, and P2SEL2.0. X = don't care, — = not applicable Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Table 5-10. External MSP430 Port 1 Functions and Programming Options PIN NAME (P1.x) (1) MSP430 CONTROL BITS / SIGNALS x FUNCTION (2) P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x INCH.x=1 CAPD.y I: 0; O: 1 0 0 0 0 P1.1/ P1.x (I/O) TA0.0/ TA0.0 1 1 0 0 0 TA0.CCI0A 0 1 0 0 0 UCA0RXD from USCI 1 1 0 0 UCA0SOMI 0 UCA0RXD/ UCA0SOMI/ 1 from USCI 1 1 0 A1/ A1 X X X 1 (y = 1) 0 CA1/ CA1 X X X 0 1 (y = 1) Pin Osc Capacitive sensing X 0 1 0 0 P1.2/ P1.x (I/O) I: 0; O: 1 0 0 0 0 TA0.1/ TA0.1 1 1 0 0 0 TA0.CCI1A 0 1 0 0 0 UCA0TXD from USCI 1 1 0 0 UCA0SIMO from USCI 1 1 0 0 UCA0TXD/ UCA0SIMO/ 2 A2/ A2 X X X 1 (y = 2) 0 CA2/ CA2 X X X 0 1 (y = 2) Pin Osc Capacitive sensing X 0 1 0 0 P1.3/ P1.x (I/O) I: 0; O: 1 0 0 0 0 ADC10CLK/ ADC10CLK 1 1 0 0 0 A3 X X X 1 (y = 3) 0 VREF- X X X 1 0 VEREF-/ VEREF- X X X 1 0 CA3 CA3 X X X 0 1 (y = 3) Pin Osc Capacitive sensing X 0 1 0 0 P1.4/ P1.x (I/O) I: 0; O: 1 0 0 0 0 SMCLK/ SMCLK 1 1 0 0 0 UCB0STE/ UCB0STE from USCI 1 1 1 (y = 4) 0 UCA0CLK/ UCA0CLK from USCI 1 1 1 (y = 4) 0 VREF+/ VREF+ X X X 1 0 0 A3/ VREF-/ VEREF+/ 3 4 VEREF+ X X X 1 A4/ A4 X X X 1 (y = 4) 0 CA4/ CA4 X X X 0 1 (y = 4) TCK/ TCK (JTAG Mode = 1) X X X 0 0 Pin Osc Capacitive sensing X 0 1 0 0 P1.5/ P1.x (I/O) I: 0; O: 1 0 0 0 0 TA0.0/ TA0.0 1 1 0 0 0 UCB0CLK/ UCB0CLK from USCI 1 1 0 0 UCA0STE/ UCA0STE from USCI 1 1 0 0 A5 X X X 1 (y = 5) 0 CA5/ CA5 X X X 0 1 (y = 5) TMS/ TMS (JTAG Mode = 1) X X X 0 0 Pin Osc Capacitive sensing X 0 1 0 0 A5/ (1) (2) 5 Example: To program port P1.1, the appropriate control bits and MSP430 signals would need to be referenced as P1DIR.1, P1SEL.1, and P1SEL2.1. X = don't care Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 49 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 5-10. External MSP430 Port 1 Functions and Programming Options (continued) PIN NAME (P1.x) (1) MSP430 CONTROL BITS / SIGNALS x FUNCTION (2) P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x INCH.x=1 CAPD.y I: 0; O: 1 0 0 0 0 1 1 0 0 0 P1.6/ P1.x (I/O) TA0.1/ TA0.1 UCB0SOMI/ UCB0SOMI from USCI 1 1 0 0 UCB0SCL/ UCB0SCL from USCI 1 1 0 0 A6 X X X 1 (y = 6) 0 CA6/ CA6 X X X 0 1 (y = 6) TDI/TCLK/ TDI/TCLK (JTAG Mode = 1) X X X 0 0 Pin Osc Capacitive sensing X 0 1 0 0 P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0 0 UCB0SIMO/ UCB0SIMO from USCI 1 1 0 0 UCB0SDA/ UCB0SDA from USCI 1 1 0 0 A7/ A7 X X X 1 (y = 7) 0 A6/ 6 7 CA7/ CA7 X X X 0 1 (y = 7) CAOUT/ CAOUT 1 1 0 0 0 TDO/TDI/ TDO/TDI (JTAG Mode = 1) X X X 0 0 Pin Osc Capacitive sensing X 0 1 0 0 Table 5-11. External MSP430 Port 2 Functions and Programming Options PIN NAME (P2.x) (1) x FUNCTION P2.1/ P2.x (I/O) TA1.1/ Timer1_A3.CCI1A 1 MSP430 CONTROL BITS / SIGNALS (2) P2DIR.x P2SEL.x P2SEL2.x I: 0; O: 1 0 0 0 1 0 Timer1_A3.TA1 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.2/ P2.x (I/O) I: 0; O: 1 0 0 TA1.1/ Timer1_A3.CCI1B 0 1 0 2 Timer1_A3.TA1 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.6/ P2.x (I/O) I: 0; O: 1 0 0 XIN, LFXT1 Oscillator Input 0 1 0 Timer0_A3.TA1 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.7/ P2.x (I/O) I: 0; O: 1 0 0 XOUT/ XOUT, LFXT1 Oscillator Output 1 1 0 Capacitive sensing X 0 1 XIN/ 6 TA0.1/ 7 Pin Osc (1) (2) 50 Example: To program port P2.1, the appropriate control bits and MSP430 signals would need to be referenced as P2DIR.1, P2SEL.1, and P2SEL2.1. X = don't care Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Table 5-12. External MSP430 Port 3 Functions and Programming Options PIN NAME (P3.x) (1) x P3.3/ FUNCTION P3.x (I/O) TA1.1/ 3 Timer1_A3.TA2 Pin Osc Capacitive sensing P3.5/ P3.x (I/O) TA1.1/ 5 Pin Osc (1) (2) MSP430 CONTROL BITS / SIGNALS (2) P3DIR.x P3SEL.x P3SEL2.x I: 0; O: 1 0 0 1 1 0 X 0 1 I: 0; O: 1 0 0 Timer0_A3.TA2 1 1 0 Capacitive sensing X 0 1 Example: To program port P3.3, the appropriate control bits and MSP430 signals would need to be referenced as P3DIR.3, P3SEL.3, and P3SEL2.3. X = don't care 5.5.2.4 Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: • Active mode (AM) • Low-power mode 2 (LPM2) – All clocks are active – CPU is disabled – MCLK and SMCLK are disabled • Low-power mode 0 (LPM0) – DCO's dc-generator remains enabled – CPU is disabled – ACLK remains active – ACLK and SMCLK remain active, MCLK is disabled • Low-power mode 3 (LPM3) • Low-power mode 1 (LPM1) – CPU is disabled – CPU is disabled – MCLK and SMCLK are disabled – ACLK and SMCLK remain active, MCLK – DCO's dc-generator is disabled is disabled – ACLK remains active – DCO's dc-generator is disabled if DCO • Low-power mode 4 (LPM4) not used in active mode – CPU is disabled – ACLK is disabled – MCLK and SMCLK are disabled – DCO's dc-generator is disabled – Crystal oscillator is stopped 5.5.2.5 MSP430x2xx User's Guide To view the user's guide for the MSP430 integrated into this device, see MSP430x2xx Family User's Guide. The list of peripherals found in this MSP430 is listed in the section: Section 5.5.2.1. Detailed Description Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 51 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 6 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 6.1 Application Information This PMIC is designed specifically for active shutter 3D glasses. 6.2 Typical Application 6.2.1 Active Shutter 3D Glasses Figure 6-1. TPS65835 Applications Schematic 6.2.1.1 Design Requirements The design parameters are located in Table 6-1. 52 Application and Implementation Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Table 6-1. Design Parameters 6.2.1.2 PARAMETER EXAMPLE Input Voltage, VIN 3.7 to 6.4 V Input Voltage, Vbat BAT 2.5 to 6.4 V Output Voltage, LDO VLDO 2.2 (default) or 3.0 V Output Voltage Boost, BST_OUT 8 to 16 V, 10 V default Charge Current Ichg=Kiset/Riset 5 to 100 mA, 70 mA default Input Voltage Low VIL (BST_EN, CHG_EN, SW_SEL, VLDO, HBRx, HBLx) 0.4 V Input Voltage High VIH (BST_EN, CHG_EN, SW_SEL, VLDO, HBRx, HBLx) 1.2 V Detailed Design Procedure 6.2.1.2.1 Boost Converter Application Information 6.2.1.2.1.1 Setting Boost Output Voltage To set the boost converter output voltage of this device, two external resistors that form a feedback network are required. The values recommended below (in Table 6-2) are given for a desired quiescent current of 5 µA when the boost is enabled and switching. See Figure 6-2 for the detail of the applications schematic that shows the boost feedback network and the resistor names used in the table below. SYS L BST_SW BST_OUT BST_OUT RFB1 P BST_FB RFB2 P Figure 6-2. Boost Feedback Network Schematic Table 6-2. Recommended RFB1 and RFB2 Values (for IQ(FB) = 5 µA) (1) TARGETED VBST_OUT RFB1 (1) RFB2 (1) 8V 1.3 MΩ 240 kΩ 10 V 1.8 MΩ 240 kΩ 12 V 2.2 MΩ 240 kΩ 14 V 2.4 MΩ 240 kΩ 16 V 3.0 MΩ 240 kΩ Resistance values given in closest standard value (5% tolerance, E24 grouping). These resistance values can also be calculated using the following information. To start, it is helpful to target a quiescent current through the boost feedback network while the device is operating (IQ(FB)). When the boost output voltage and this targeted quiescent current is known, the total feedback network resistance can be found. The value for RFB2 can be found by using the boost feedback pin voltage (VFB = 1.2 V, see Section 4.6) and IQ(FB) using Equation 1: RFB1 + RFB2 = VBST_OUT / IQ(FB) (1) Application and Implementation Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 53 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com RFB2 = (1.2 V) / IQ(FB) (2) To find RFB1, simply subtract the RFB2 from RFB(TOT) as shown in Equation 3. RFB1 = RFB(TOT) - RFB2 (3) 6.2.1.2.1.2 Boost Inductor Selection The selection of the boost inductor and output capacitor is very important to the performance of the boost converter. The boost has been designed for optimized operation when a 10 µH inductor is used. Smaller inductors, down to 4.7 µH, may be used but there will be a slight loss in overall operating efficiency. A few inductors that have been tested and found to give good performance can be found in the following list. Recommended 10-µH inductors: • TDK VLS201612ET-100M (10 µH, IMAX = 0.53 A, RDC = 0.85 Ω) • Taiyo Yuden CBC2016B100M (10 µH, IMAX = 0.41 A, RDC = 0.82 Ω) 6.2.1.2.1.3 Boost Capacitor Selection The recommended minimum value for the capacitor on the boost output, BST_OUT pin, is 4.7 µF. Values that are larger can be used with the measurable impact being a slight reduction in the boost converter output voltage ripple while values smaller than this will result in an increased boost output voltage ripple. Note that the voltage rating of the capacitor should be sized for the maximum expected voltage at the BST_OUT pin. 6.2.1.2.2 Bypassing Default Push-Button SWITCH Functionality If the SWITCH pin functionality is not required to power on and off the device because of different system requirements (SWITCH timing requirements of system will be controlled by the internal MSP430), then the feature can be bypassed. The following diagram shows the connections required for this configuration. Figure 6-3. Bypassing Default TPS65835 Push Button SWITCH Timing In a system where a different push-button SWITCH off timing is required, the SLEEP pin is used to control the power off of the device. After system power up, the MCU must force the SLEEP pin to a high state (VSLEEP > VIH(PMIC)). Once the SWITCH push-button is pressed to shut the system down, a timer in the MCU should be active and counting the desired tOFF time of the device. Once this tOFF time is detected, the MCU can assert the SLEEP signal to a logic low level (VSLEEP < VIL(PMIC)). It is on the falling edge of the SLEEP signal where the system will be powered off (see Figure 6-4). 54 Application and Implementation Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Figure 6-4. SWITCH Press and SLEEP Signal to Control System Power Off Application and Implementation Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 55 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 6.2.1.2.3 MSP430 Programming In order to program the integrated MSP430 in the TPS65835 device, ensure that the programming environment supports the TPS65835 device. 6.2.1.2.3.1 Code To Setup Power Functions This section will detail a basic code to control the MSP430 in the TPS65835 and how to configure the power functions and control the power die. Please reference Table 5-9 for the details on configuring the MSP430 pins. Note that "//" is a comment and this code was written using Code Composer Studio in C. // SETUP H-BRIDGE PINS P2DIR |= (BIT5 + BIT4 + BIT3 + BIT0); P2REN |= (BIT5 + BIT4 + BIT3 + BIT0); // Set PxDIR to 1 for outputs // Enable pull-up/pull-down resistors on outputs // SETUP SLEEP, CHG_EN, AND BST_EN P3DIR |= (BIT2 + BIT1 + BIT0); P3REN |= (BIT2 + BIT1 + BIT0); // Set PxDIR to 1 for outputs // Enable pull-up/pull-down resistors on outputs The previous code setup the power pins for outputs, now they must be controlled with MSP430 code. Refer to the following code to perform initial setup and to control the power functions (SLEEP, CHG_EN, and BST_EN): P3OUT &= ~BIT0; // P3OUT |= BIT0; // Set SLEEP mode signal low; SLEEP Function is disabled // Set SLEEP mode signal high (sleep control via MSP430) // P3OUT &= ~BIT1; P3OUT |= BIT1; // Set CHG_EN signal low (disable charger) // Set CHG_EN signal high (enable charger) // P3OUT &= ~BIT2; P3OUT |= BIT2; // Set BST_EN low (disable boost) // Set BST_EN high (enable boost) The H-Bridge pins can be controlled in a similar manner (see Section 5.3.5.1). The following code is only meant to cover each H-Bridge mode of operation and the appropriate code needed to put it in that state: 56 // BOTH SIDES IN OPEN STATE P2OUT &= ~(BIT3 + BIT0); P2OUT &= ~(BIT5 + BIT4); // HBL2 = 0, HBL1 = 0 // HBR2 = 0, HBR1 = 0 // BOTH SIDES IN GROUNDED STATE P2OUT |= BIT3 + BIT0; P2OUT |= BIT5 + BIT4; // HBL2 = 1, HBL1 = 1 // HBR2 = 1, HBR1 = 1 // LEFT SIDE IN CHARGE+ STATE P2OUT &= ~BIT3; P2OUT |= BIT0; // HBL2 = 0, HBL1 = 1 // LEFT SIDE IN CHARGE- STATE P2OUT |= BIT3; P2OUT &= ~BIT0; // HBL2 = 1, HBL1 = 0 // RIGHT SIDE IN CHARGE+ STATE P2OUT &= ~BIT5; P2OUT |= BIT4; // HBR2 = 0, HBR1 = 1 // RIGHT SIDE IN CHARGE- STATE P2OUT |= BIT5; P2OUT &= ~BIT4; // HBR2 = 1, HBR1 = 0 Application and Implementation Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com 6.2.1.3 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 Application Curves Vbat = –3.2 V 1-mA Load on Boost Vbat = 3.6 V No Load 0.5 µs/div Figure 6-6. Switchnode Figure 6-5. Boost Output Ripple Application and Implementation Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 57 TPS65835 SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 7 Power Supply Recommendations An DC Input Voltage range of 3.7 to 6.4 V is required on VIN and a range of 2.5 V to 6.4 V is required on BAT. VIN requires a 2.2-µF capacitor. SYS requires a 4.7-µF capacitor. BAT requires a 10-µF capacitor. VLDO requires a 2.2-µF capacitor. 8 Layout 8.1 Layout Guidelines The layout is an important step in the design process. Proper function of the device demands careful attention to the PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor performance including stability issues as well as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitors must be placed as close as possible to the IC pins as well as the inductor and output capacitor. Keep the common path to the ground pins which return the small signal components and the high current of the output capacitors as short as possible in order to avoid ground noise. 8.2 Layout Example VSYS Cin Cout L PGNDBST Figure 8-1. Boost Layout 58 Layout Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65835 TPS65835 www.ti.com SLVSAF6A – JUNE 2011 – REVISED JANUARY 2016 9 Device and Documentation Support 9.1 9.1.1 Device Support Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 9.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 9.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 9.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 9.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information 10.1 Packaging Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2011–2016, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: TPS65835 59 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS65835RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 65835 TPS65835RKPT ACTIVE VQFN RKP 40 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 65835 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of