TPS65950BZXN

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 TPS65950 Integrated Power Management and Audio Codec – Silicon Revision 1.2 1 Device Overview 1.1 Features 1 • Power: – Three Efficient Step-down Converters • VDD1: TPS65950A2 with 1.2 A and TPS65950A3 with 1.4 A (for 1-GHz Speed) • VDD2: 600 mA • VIO: 700 mA – 10 External Linear LDOs for Clocks and Peripherals – SmartReflex™ Dynamic Voltage Management • Audio: – Voice Codec – 15-Bit Linear Codec (8 and 16 kHz) – Differential Input Main and Submicrophones – Differential Headset Microphone Input – Auxiliary/FM Input (Mono or Stereo) – Differential 32-Ω Speaker and 16-Ω Headset Drivers (External Predrivers for Class D) – 8-Ω Stereo Class-D Drivers – Pulse Code Modulation (PCM) and TDM Interfaces – Bluetooth® Interface – Automatic Level Control (ALC) – Digital and Analog Mixing – 16-Bit Linear Audio Stereo DAC (96, 48, 44.1, and 32 kHz, and Derivatives) – 16-Bit Linear Audio Stereo ADC (48, 44.1, and 32 kHz, and Derivatives) – Digital Microphone Inputs – Carkit 1.2 • • • Charger: – Li-ion, Li-on Polymer, and Cobalt-NickelManganese Charger – Supports Charging with AC-Regulated Charger (Maximum 7 V), USB Host Devices, Mobile Computing Promotion Consortium (MCPC) Devices, USB Chargers, and Carkit Chargers (Maximum 7 V) – Backup Battery Charger • USB: – USB 2.0 OTG-Compliant HS Transceivers – 12-Bit ULPI – USB Power Supply (5-V CP for VBUS) – CEA-2011: OTG Transceiver Interface Specification – CEA-936A: Mini-USB Analog Carkit Interface Specification – MCPC ME-Universal Asynchronous Receiver/Transmitter (UART) GL-006 Specification • Additional Features: – LED Driver Circuit for Two External LEDs – 10-Bit MADC with 3 to 8 External Inputs – RTC and Retention Modules – HS Inter-Integrated Circuit (I2C) Serial Control – Thermal Shutdown and Hot-Die Detection – Keypad Interface (up to 8 × 8) – External Vibrator (Vibrator) Control – 19 GPIO Devices – 0.4-mm Pitch, 209 Pin, 7-mm × 7-mm Package Applications Smart Phones Tablets • • Industrial Handheld Systems 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 1.3 www.ti.com Description The TPS65950 device is a highly integrated power-management and audio coder/decoder (codec) integrated circuit (IC) that supports the power and peripheral requirements of the OMAP™ application processors. The device contains power management, an audio codec, a universal serial bus (USB) highspeed (HS) transceiver, an AC/USB charger, light-emitting diode (LED) drivers, an analog-to-digital converter (ADC), a real-time clock (RTC), and embedded power control. The power portion of the device contains three buck converters, two controllable by a dedicated SmartReflex class-3 interface, multiple low-dropout (LDO) regulators, an embedded power controller (EPC) to manage the power-sequencing requirements of OMAP, and an RTC and backup module. The RTC can be powered by a backup battery when the main supply is not present, and the device contains a coin-cell charger to recharge the backup battery as needed. The USB module provides a HS 2.0 on-the-go (OTG) transceiver suitable for direct connection to the OMAP universal transceiver macrocell interface (UTMI) + low pin interface (ULPI) with an integrated charge pump (CP) and full support for the carkit Consumer Electronics Association (CEA)-936A specification. The Li-ion battery charger supports charging from AC chargers, USB host devices, USB chargers, or carkits. The device automatically detects the type of charger and provides hardware-controlled linear charging with AC chargers, USB chargers, and carkits, in addition to software-controlled charging for all charger types. The audio codec in the device includes five digital-to-analog converters (DACs) and two ADCs to provide multiple voice channels and stereo downlink channels that can support all standard audio sample rates through several inter-IC sound (I2S)/time division multiplexing (TDM) format interfaces. The audio output stages on the device include stereo headset amplifiers, two integrated class-D amplifiers providing stereo differential outputs, predrivers for line outputs, and an earpiece amplifier. The input audio stages include three differential microphone inputs, stereo line inputs, and interface for digital microphones. Automatic and programmable gain control is available with all necessary digital filtering, side-tone functions, and popnoise reduction. The device also provides auxiliary modules, including LED drivers, an ADC, a keypad interface, and general-purpose inputs/outputs (GPIOs). The LED driver can power two LED circuits to illuminate a panel or provide user indicators. The drivers also provide pulse width modulation (PWM) circuits to control the illumination levels of the LEDs. The ADC monitors signals entering the device, such as supply and charging voltages, and has multiple external ADC inputs for system use. The keypad interface implements a built-in scanning algorithm to decode hardware-based key presses and reduce software use. Multiple GPIOs can be used as interrupts when they are configured as inputs. Table 1-1. Device Information (1) PART NUMBER TPS65950ZXN (1) 2 PACKAGE (PIN) BODY SIZE nFBGA (209) 7.00 mm × 7.00 mm For more information, see , Mechanical Packaging and Orderable Information. Device Overview Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com 1.4 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Functional Block Diagram Figure 1-1 is a block diagram of the TPS65950 device. Device Digital signal(s) Audio RX amplifiers Mic amplifiers Analog volume control D/A converters A/D converters Differential vibrator Carkit preamplifiers Analog signal(s) Interface subchip(D) Audio PLL PIH AUDIO analog Digital mic interface Analog and digital mic bias Clocks Clock generator I2C A pad I2C B pad TAP OCP Clk In/Out Wrapper digital Card Det1 GPIO Audio and voice filters (RX and TX paths) + Vibrator control Bluetooth interface PCM (2) PCM interface PCM (4) TDM/I2S interface TDM (4) SIH Card Det2 GPIO pad AUDIO digital TAP Audio subchip (A-D) TAP TAP Clocks Clocks Clocks SIH_INT OCP OCP SR TAP OCP SIH_INT OCP RTC Felica Vibrator control (D) PMC slave Smart Reflex Slave OCP wrapper 13 MHz/32 kHz Power digital RTC 32 kHz Clock slicer Power control (BBS-backup Thermal monitor system OTG module USB precharge module USB2.0 transceiver ULPI (12) UART(2) USB subchip (A-D) BERDATA Auxiliary subchip (A-D) BCI digital Keypad (D) Power analog USB power supply BERCLK TAP Shundan Clocks SIH OCP PMC master SIH_INT SIH_INT USB digital (ULPI/ registers interrupts CEA and MCPC carkit) Analog carkit interfaces RC oscillator BCITOP Precharge loop Main loop Precharge PM Main DAC Precharge status Main aux Shifters BCI analog LEDTOP Power provider Power references (LDOs-DCDCs) (Vref-Iref-BandGap) VRRTC-UVLO) LED digital MADC digital state-machine LED analog Power subchip (A-D) LedSync MADC analog (SAR-Vref) MADCTOP StartADC 032-003 Figure 1-1. TPS65950 Functional Block Diagram Device Overview Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 3 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Table of Contents 1 2 3 Device Overview ......................................... 1 5.1 Power Module ....................................... 33 1.1 Features .............................................. 1 5.2 Real-Time Clock and Embedded Power Controller . 65 1.2 Applications ........................................... 1 5.3 Audio/Voice Module ................................. 66 1.3 Description ............................................ 2 5.4 USB HS 2.0 OTG Transceiver ...................... 99 1.4 Functional Block Diagram ............................ 3 5.5 Battery Interface Revision History ......................................... 5 Terminal Configuration and Functions .............. 6 5.6 MADC .............................................. 125 5.7 LED Drivers ........................................ 128 .......................................... 6 3.2 Ball Characteristics ................................... 7 3.3 Signal Description ................................... 12 Specifications ........................................... 19 4.1 Absolute Maximum Ratings ......................... 19 4.2 Handling Ratings .................................... 19 4.3 Recommended Operating Conditions ............... 19 4.4 Digital I/O Electrical Characteristics................. 20 5.8 Keyboard ........................................... 129 3.1 4 4.5 4.6 4.7 5 4 Corner Balls Thermal Resistance Characteristics for ZXN Package ............................................. 22 Minimum Voltages and Associated Currents ....... 23 Timing Requirements and Switching Characteristics....................................... 24 Detailed Description ................................... 33 6 ................................... 113 5.9 Clock Specifications................................ 130 5.10 Debouncing Time .................................. 142 5.11 External Components .............................. 143 Device and Documentation Support .............. 149 6.1 Device Support..................................... 149 6.2 Documentation Support ............................ 150 6.3 Community Resources............................. 150 6.4 Trademarks ........................................ 150 6.5 Electrostatic Discharge Caution 6.6 Export Control Notice .............................. 151 6.7 Glossary............................................ 151 6.8 Additional Acronyms ............................... 151 Table of Contents ................... 151 Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (January 2011) to Revision F • • • • • • • Page Changed data sheet to new TI standards. ........................................................................................ 1 Added Section 1.2, Applications .................................................................................................... 1 Changed Introduction to Section 1.3, Description ................................................................................ 2 Added Table 1-1, Device Information .............................................................................................. 2 Changed ESD Specifications to Section 4.2, Handling Ratings .............................................................. 19 Added Section 4.5, Thermal Resistance Characteristics ...................................................................... 22 Added Section 6, Device and Documentation Support ....................................................................... 149 Revision History Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 5 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com 3 Terminal Configuration and Functions Figure 3-1 shows the ball locations for the 209-ball plastic ball grid array (PBGA) package and is used with Table 3-1 to locate signal names and ball grid numbers. 032-088 Figure 3-1. PBGA Bottom View 3.1 Corner Balls The four corner balls (see the following list) are not usable for functional pins: • Test • TestV1 • Test.RESET • TestV2 The eight corner adjacent balls are: • RFID.EN • UART1.TXD • JTAG.TDI/BERDATA • JTAG.CLK/BERCLK • PCM.VFS • PCM.VDX • PCM.VDR • PCM.VCK 6 Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com 3.2 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Ball Characteristics Table 3-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list describes the column headings in Table 3-1: 1. Ball: Ball number(s) associated with each signal(s) 2. Pin Name: Names of all the signals that are multiplexed on each ball 3. A/D: Analog or digital signal 4. Type: Terminal type when a particular signal is multiplexed on the terminal – I = Input – O = Output – OD = Open drain 5. Reference Level: Voltage applied to the I/O cell (see the power module and battery charger interface [BCI] chapters for values). 6. PU/PD: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled through software. 7. Min = Minimum value 8. Typ = Typical value 9. Max = Maximum value 10. Buffer Strength: Drive strength of the associated output buffer Table 3-1. Ball Characteristics Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] H4 ADCIN0 A I/O VINTANA1.OUT J3 ADCIN1 A I/O VINTANA1.OUT G3 ADCIN2 A I VINTANA2.OUT P5 VCCS A I VBAT + 0.2 N5 VAC A Power VACCHARGER P4 VBATS A I VBAT N4 PCHGAC A I VACCHARGER N6 PCHGUSB A I VBUS N2 VPRECH A O VPRECH N1 BCIAUTO A I VPRECH P6 ICTLUSB1 A O VBUS P1 ICTLUSB2 A O VCCS N7 ICTLAC1 A O VACCHARGER P2 ICTLAC2 A O VCCS R5 VBAT A Power VBAT GPIO0/CD1 D I/O IO_1P8 JTAG.TDO D I/O IO_1P8 GPIO1/CD2 D I/O IO_1P8 JTAG.TMS D I IO_1P8 GPIO2 D I/O IO_1P8 Test1 D I/O IO_1P8 GPIO15 D I/O IO_1P8 Test2 D I/O IO_1P8 GPIO6 D I/O IO_1P8 PWM0 D O IO_1P8 Test3 D I/O IO_1P8 P12 N12 L4 P13 M4 PU[6] (kΩ) PD[6] (kΩ) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 Buffer Strength (mA)[10] 8 8 2 75 100 202 59 100 144 156 220 450 59 100 144 2 2 2 156 220 450 59 100 144 2 2 75 100 202 59 100 144 4 2 Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 7 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Table 3-1. Ball Characteristics (continued) Pin Name[2] Reference Level RL[5] PU[6] (kΩ) PD[6] (kΩ) Buffer Strength (mA)[10] A/D [3] Type[4] GPIO7 D I/O IO_1P8 VIBRA.SYNC D I IO_1P8 PWM1 D O IO_1P8 4 Test4 D I/O IO_1P8 2 START.ADC D I IO_1P8 C13 SYSEN D OD/I IO_1P8 C6 CLKEN D O IO_1P8 D7 CLKEN2 D O IO_1P8 G10 CLKREQ D I IO_1P8 F10 INT1 D O IO_1P8 2 F9 INT2 D O IO_1P8 2 A13 NRESPWRON D O IO_1P8 2 B13 NRESWARM D I IO_1P8 2 A11 PWRON D I VBAT B14 NC P7 NSLEEP1 D I IO_1P8 G9 NSLEEP2 D I IO_1P8 D13 CLK256FS (1) D O IO_1P8 VMODE1 D I IO_1P8 Ball[1] N14 J9 F8 Min[7] BOOT0 A/D I/O VBAT J11 BOOT1 A/D I/O VBAT A10 REGEN D OD VBAT H8 MSECURE D I IO_1P8 N16 VREF A Power VREF N15 AGND A Power GND GND I2C.SR.SDA D I/O IO_1P8 VMODE2 D I IO_1P8 I2C.SR.SCL D I/O D4 I2C.CNTL.SDA D D5 I2C.CNTL.SCL D R1 PCM.VCK T2 Max[9] Min Typ Max 2 75 K11 Typ[8] 4.7 100 7.35 202 59 100 144 10 2 2 2 60 100 146 2 5.5 8 12 2 2.5 3.4 12 IO_1P8 2.5 3.4 12 I/O IO_1P8 2.5 3.4 12 I IO_1P8 2.5 3.4 12 D I/O IO_1P8 2 PCM.VDR D I/O IO_1P8 2 T15 PCM.VDX D I/O IO_1P8 2 R16 PCM.VFS D I/O IO_1P8 2 L3 I2S.CLK D I/O IO_1P8 2 K6 I2S.SYNC D I/O IO_1P8 2 K4 I2S.DIN D I IO_1P8 2 K3 I2S.DOUT D O IO_1P8 2 E2 MIC.MAIN.P A I MICBIAS1.OUT F2 MIC.MAIN.M A I MICBIAS1.OUT MIC.SUB.P A I MICBIAS2.OUT DIG.MIC.0 A I VMIC1.OUT MIC.SUB.M A I MICBIAS2.OUT NC C4 2 D6 G2 H2 (1) 8 DIG.MIC.1 A I VMIC2.OUT E3 HSMIC.P A I VINTANA2.OUT F3 HSMIC.M A I VINTANA2.OUT D10 VBAT.LEFT A Power VBAT D9 VBAT.LEFT A Power VBAT B9 IHF.LEFT.P A O VBAT B10 IHF.LEFT.M A O VBAT C10 GND.LEFT A Power GND GND C9 GND.LEFT A Power GND GND D12 VBAT.RIGHT A Power VBAT To avoid reflection on this pin caused by impedance mismatch, a serial resistance (Rs) of 33 Ω must be added. Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Table 3-1. Ball Characteristics (continued) Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] D11 VBAT.RIGHT A Power VBAT B11 IHF.RIGHT.P A O VBAT B12 IHF.RIGHT.M A O VBAT C12 GND.RIGHT A Power GND GND C11 GND.RIGHT A Power GND GND A6 EAR.P A O VINTANA2.OUT A7 EAR.M A O VINTANA2.OUT B4 HSOL A O VINTANA2.OUT PreDriv.LEFT A O VINTANA2.OUT VMID A Power VINTANA2.OUT HSOR A O VINTANA2.OUT PreDriv.RIGHT A O VINTANA2.OUT ADCIN7 A I VINTANA2.OUT F1 AUXL A I VINTANA2.OUT G1 AUXR A I VINTANA2.OUT MICBIAS1.OUT A Power VINTANA2.OUT VMIC1.OUT A Power VINTANA2.OUT MICBIAS2.OUT A Power VINTANA2.OUT VMIC2.OUT A Power VINTANA2.OUT E4 VHSMIC.OUT A Power VINTANA2.OUT D3 MICBIAS.GND Power GND GND PU[6] (kΩ) PD[6] (kΩ) Min[7] Typ[8] Max[9] Min Typ Max 4.7 7.4 10 5.9 7 8.3 Buffer Strength (mA)[10] B7 B5 B8 D1 D2 J4 / J6 /J7 / AVSS1 J8 / E5 A Power GND GND R10 AVSS2 A Power GND GND M15 AVSS3 A Power GND GND C7 AVSS4 A Power GND GND B1 UART1.TXD D OD External 1.8 to 3.3 V GPIO8 D I IO_1P8 UART1.RXD D I IO_1P8 RTSO/ CLK64K.OUT/ BERCLK.OUT D OD VUSB.3P1 ADCIN5 A I VINTANA2.OUT CTSI/ BERDATA.OUT D OD/CMOS/I/O VUSB.3P1 ADCIN3 A I VINTANA2.OUT TXAF A I VUSB.3P1 ADCIN4 A I VINTANA2.OUT RXAF A O VUSB.3P1 ADCIN6 A I VINTANA2.OUT 2 D8 N11 P11 2 4.7 7.4 10 162 280 414 2 N8 N9 L10 MANU D I VUSB.3P1 N10 32KCLKOUT D O IO_1P8 P16 32KXIN A I IO_1P8 P15 32KXOUT A O IO_1P8 A14 HFCLKIN A I IO_1P8 R12 HFCLKOUT D O IO_1P8 R8 VBUS A Power VBUS T10 DP/UART3.RXD A I/O VBUS 2 T11 DN/UART3.TXD A I/O VBUS 2 R11 ID A I/O VBUS 2 L15 UCLK D I IO_1P8 16 STP D I IO_1P8 GPIO9 D I/O IO_1P8 2 DIR D O IO_1P8 16 GPIO10 D I/O IO_1P8 L14 16 75 L13 75 100 100 202 202 59 59 100 100 144 144 2 Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 9 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Table 3-1. Ball Characteristics (continued) Pin Name[2] Ball[1] A/D [3] Type[4] Reference Level RL[5] PU[6] (kΩ) PD[6] (kΩ) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 Buffer Strength (mA)[10] NXT D O IO_1P8 GPIO11 D I/O IO_1P8 2 DATA0 D I/O IO_1P8 16 UART4.TXD D I IO_1P8 DATA1 D I/O IO_1P8 UART4.RXD D O IO_1P8 2 DATA2 D I/O IO_1P8 16 UART4.RTSI D I IO_1P8 DATA3 D I/O IO_1P8 UART4.CTSO D O IO_1P8 GPIO12 D I/O IO_1P8 DATA4 D I/O IO_1P8 GPIO14 D I/O IO_1P8 2 DATA5 D I/O IO_1P8 16 GPIO3 D I/O IO_1P8 2 DATA6 D I/O IO_1P8 16 GPIO4 D I/O IO_1P8 2 DATA7 D I/O IO_1P8 16 GPIO5 D I/O IO_1P8 A/D I VBAT M13 16 K14 16 K13 J14 J13 G14 G13 100 140 60 100 140 75 100 202 59 100 144 75 100 202 59 100 144 16 75 F13 75 T16 TEST.RESET T1 TESTV1 A I/O VBAT A16 TESTV2 A I/O VINTANA2.OUT A1 TEST D I IO_1P8 A15 JTAG.TDI/ BERDATA D I IO_1P8 B16 JTAG.TCK/ BERCLK D I IO_1P8 R7 CP.IN A Power VBAT/VBUS T7 CP.CAPP A O CP.CAPP T6 CP.CAPM A O CP.CAPM R6 CP.GND A Power GND GND R9 VBAT.USB A Power VBAT P9 VUSB.3P1 A Power VUSB.3P1 L1 VAUX12S.IN A Power VBAT M2 VAUX1.OUT A Power VAUX1.OUT VAUX2.OUT M3 VAUX2.OUT A Power H15 VPLLA3R.IN A Power VBAT K16 VRTC.OUT A Power VRTC.OUT H14 VPLL1.OUT A Power VPLL1.OUT J15 VSDI.CSI.OUT A Power VSDI.CSI.OUT G16 VAUX3.OUT VAUX3.OUT A Power B2 VAUX4.IN A Power VBAT B3 VAUX4.OUT A Power VAUX4.OUT C1 VMMC1.IN A Power VBAT C2 VMMC1.OUT A Power VMMC1.OUT A3 VMMC2.IN A Power VBAT A4 VMMC2.OUT A Power VMMC2.OUT K2 VSIM.OUT A Power VSIM.OUT P8 VINTUSB1P5. OUT A Power VINTUSB1P5.OUT P10 VINTUSB1P8. OUT A Power VINTUSB1P8.OUT K1 VDAC.IN A Power VBAT L2 VDAC.OUT A Power VDAC.OUT K15 VINT.IN A Power VBAT H3 VINTANA1.OUT A Power VINTANA1.OUT 16 16 75 F14 10 16 60 100 100 100 Terminal Configuration and Functions 202 202 202 59 59 100 100 144 144 59 100 144 30 50 70 60 100 146 2 Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Table 3-1. Ball Characteristics (continued) Ball[1] Pin Name[2] A/D [3] Type[4] Reference Level RL[5] J2 VINTANA2.OUT A Power VINTANA2.OUT B6 VINTANA2.OUT A Power VINTANA2.OUT L16 VINTDIG.OUT A Power VINTDIG.OUT E15 VDD1.IN A Power VBAT E14 VDD1.IN A Power VBAT D14 VDD1.IN A Power VBAT D16 VDD1.SW A O VBAT D15 VDD1.SW A O VBAT C14 VDD1.SW A O VBAT E13 VDD1.FB A I C16 VDD1.GND A Power GND GND C15 VDD1.GND A Power GND GND B15 VDD1.GND A Power GND GND R13 VDD2.IN A Power VBAT VBAT P14 VDD2.IN A Power N13 VDD2.FB A I T13 VDD2.SW A O VBAT R14 VDD2.SW A O VBAT T14 VDD2.GND A Power GND GND R15 VDD2.GND A Power GND GND P3 VIO.IN A Power VBAT R4 VIO.IN A Power VBAT N3 VIO.FB A I R3 VIO.SW A O VBAT T4 VIO.SW A O VBAT R2 VIO.GND A Power GND GND T3 VIO.GND A Power GND GND M14 BKBAT A Power VBACK C8 IO.1P8 A Power IO_1P8 H13 / H9 / DGND H10 / H11 A Power GND GND LEDGND A Power GND GND GPIO13 D I/O IO_1P8 LEDSYNC D I IO_1P8 LEDA A OD VBAT VIBRA.P A OD VBAT LEDB A OD VBAT VIBRA.M A OD VBAT G8 KPD.C0 D OD IO_1P8 F16 G11 PU[6] (kΩ) PD[6] (kΩ) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 Buffer Strength (mA)[10] F15 G15 H7 KPD.C1 D OD IO_1P8 G6 KPD.C2 D OD IO_1P8 F7 KPD.C3 D OD IO_1P8 G7 KPD.C4 D OD IO_1P8 F4 KPD.C5 D OD IO_1P8 H6 KPD.C6 D OD IO_1P8 G4 KPD.C7 D OD IO_1P8 K9 KPD.R0 D I IO_1P8 8 10 12 K8 KPD.R1 D I IO_1P8 8 10 12 L8 KPD.R2 D I IO_1P8 8 10 12 K7 KPD.R3 D I IO_1P8 8 10 12 L9 KPD.R4 D I IO_1P8 8 10 12 J10 KPD.R5 D I IO_1P8 8 10 12 K10 KPD.R6 D I IO_1P8 8 10 12 L7 KPD.R7 D I IO_1P8 8 10 12 Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 11 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Table 3-1. Ball Characteristics (continued) Pin Name[2] Ball[1] C3 C5 A2 3.3 A/D [3] Type[4] GPIO16 D I/O IO_1P8 BT.PCM.VDR D I/O IO_1P8 DIG.MIC.CLK0 D O IO_1P8 GPIO17 D I/O IO_1P8 BT.PCM.VDX D I/O IO_1P8 DIG.MIC.CLK1 D O IO_1P8 RFID.EN D O VMMC2.OUT PU[6] (kΩ) Reference Level RL[5] PD[6] (kΩ) Min[7] Typ[8] Max[9] Min Typ Max 75 100 202 59 100 144 75 100 202 59 100 144 Buffer Strength (mA)[10] Signal Description Table 3-2 lists the signals on the TPS65950; some signals are available on multiple pins. Table 3-2. Signal Description Signal Name Module ADC Charger GPIOs/ JTAG START. ADC 12 Type(1) Description Configuration By Default After Reset Released Ball Signal (1) Type Internal Pull or Not Unused Features(2) ADCIN0 Battery type I/O H4 ADCIN0 I GND ADCIN1 Battery temperature I/O J3 ADCIN1 I GND ADCIN2 General-purpose (GP) ADC input I G3 ADCIN2 I GND VCCS Charge current sensing I P5 VCCS I Cap to GND(3) VAC Charge device input voltage Power N5 VAC Power GND VBATS Charge current sensing I P4 VBATS I Cap to GND(3) PCHGAC ac precharge sense signal. Used also for EEPROM I N4 PCHGAC I GND PCHGUSB USB precharge sense signal I N6 PCHGUSB I GND VPRECH Precharge regulator output O N2 VPRECH O Cap to GND(3) BCIAUTO Linear charge specific boot mode I N1 BCIAUTO I GND ICTLUSB1 USB power device control O P6 ICTLUSB1 O Floating ICTLUSB2 USB power device control O P1 ICTLUSB2 O Floating ICTLAC1 ac power device control O N7 ICTLAC1 O Floating ICTLAC2 ac power device control O P2 ICTLAC2 O Floating VBAT Battery voltage sensing Power R5 VBAT Power VBAT GPIO0/CD1 GPIO0/card detection 1 I/O JTAG.TDO JTAG test data output I/O P12 GPIO0 I PD Floating GPIO1/CD2 GPIO1/card detection 2 I/O JTAG.TMS JTAG test mode state N12 GPIO1 I PD Floating GPIO2 GPIO2 I/O Test1 Test1 pin used in test mode only I/O L4 GPIO2 I PD Floating GPIO15 GPIO15 I/O Test2 Test2 pin used in test mode only I/O P13 GPIO15 I PD Floating GPIO6 GPIO6 I/O PWM0 Pulse width driver 0 O M4 GPIO6 I PD Floating Test3 Test3 pin used in test mode only (controlled by JTAG) I/O GPIO7 GPIO7 I/O VIBRA.SYNC Vibrator on-off synchronization I PWM1 Pulse width driver O N14 GPIO7 I PD Floating Test4 Test4 pin used in test mode only (controlled by JTAG) I/O START.ADC ADC conversion request START.ADC I I I J9 Terminal Configuration and Functions GND Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Table 3-2. Signal Description (continued) Signal Name Module CONTROL VREF 2 IC SmartReflex I2C PCM TDM ANA.MIC Headset microphone Type(1) Description Configuration By Default After Reset Released Ball (1) Signal Type Internal Pull or Not SYSEN System enable output OD/I C13 SYSEN OD CLKEN Clock enable O C6 CLKEN O CLKEN2 Clock enable 2 O D7 CLKEN2 O CLKREQ Clock request I G10 CLKREQ I INT1 Output interrupt line 1 O F10 INT1 O Floating INT2 Output interrupt line 2 O F9 INT2 O Floating NRESPWRON Output control the NRESPWRON of the application processor O A13 NRESPWRON O Floating NRESWARM Input, detect user action on the reset button I B13 NRESWARM I GND PWRON Input, detect a control command to start or stop the system I A11 PWRON I VBAT NC Not connected B14 NC NSLEEP1 Sleep request from device 1 P7 NSLEEP1 NSLEEP2 Sleep request from device 2 I G9 NSLEEP2 I GND CLK256FS Control for 256 × FS CLK output O D13 CLK256FS O Floating VMODE1 Digital voltage scaling linked with VDD1 I F8 VMODE1 I GND BOOT0 Boot pin 0 I K11 BOOT0 I PD BOOT1 Boot pin 1 I J11 BOOT1 I PD N/A REGEN Enable signal for external LDO OD A10 REGEN OD PU Floating MSECURE Security and digital rights management I H8 MSECURE VREF Reference voltage Power N16 AGND Analog ground for reference voltage Power GND NC Not connected I2C.SR.SDA SmartReflex I2C data VMODE2 Digital voltage scaling linked with VDD2 I2C.SR.SCL SmartReflex I2C data I/O I2C.CNTL.SDA GP I2C data I2C.CNTL.SCL GP I2C clock PCM.VCK I PU Unused Features(2) Floating Floating Floating PD GND Floating I GND N/A I N/A VREF Power N/A N15 AGND Power GND GND C4 Signal not functional(4) D6 VMODE2 I/O D4 I2C.CNTL.SDA I/O PU I/O D5 I2C.CNTL.SCL I/O PU Data clock (voice port) I/O R1 PCM.VCK I/O PCM.VDR Data receive (voice port) I/O T2 PCM.VDR I/O GND PCM.VDX Data transmit (voice port) I/O T15 PCM.VDX I/O Floating PCM.VFS Frame synchronization (voice port) I/O R16 PCM.VFS I/O Floating I2S.CLK Clock signal (audio port) I/O L3 I2S.CLK I/O Floating I2S.SYNC Synchronization signal (audio port) I/O K6 I2S.SYNC I/O Floating I2S.DIN Data receive (audio port) I K4 I2S.DIN I GND I2S.DOUT Data transmit (audio port) O K3 I2S.DOUT O Floating MIC.MAIN.P Main microphone left input (P) I E2 MIC.MAIN.P I Cap to GND MIC.MAIN.M Main microphone left input (M) I F2 MIC.MAIN.M I Cap to GND MIC.SUB.P Main microphone right input (P) I DIG.MIC.0 Digital microphone 0 input data I G2 MIC.SUB.P I Cap to GND MIC.SUB.M Main microphone right input (M) I DIG.MIC.1 Digital microphone 1 input data I H2 MIC.SUB.M I Cap to GND HSMIC.P Headset microphone input (P) I E3 HSMIC.P I Cap to GND HSMIC.M Headset microphone input (M) I F3 HSMIC.M I Cap to GND I/O Floating I I GND N/A N/A Floating Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 13 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Table 3-2. Signal Description (continued) Module Hands-free Signal Name AUX input VMIC BIAS Signal (1) Type Internal Pull or Not Unused Features(2) Battery voltage input Power D10 VBAT.LEFT Power Battery voltage input Power D9 VBAT.LEFT Power VBAT IHF.LEFT.P Hands-free speaker output left (P) O B9 IHF.LEFT.P O Floating IHF.LEFT.M Hands-free speaker output left (M) VBAT O B10 IHF.LEFT.M O Floating C10 GND.LEFT Power GND GND Power GND GND GND.LEFT GND Power GND GND.LEFT GND Power GND C9 GND.LEFT VBAT.RIGHT Battery voltage input Power D12 VBAT.RIGHT Power VBAT VBAT.RIGHT Battery voltage input Power D11 VBAT.RIGHT Power VBAT GND.RIGHT GND Power GND C12 GND.RIGHT Power GND GND GND.RIGHT GND Power GND C11 GND.RIGHT Power GND GND IHF.RIGHT.P Hands-free speaker output right (P) O B11 IHF.RIGHT.P O Floating IHF.RIGHT.M Hands-free speaker output right (M) O B12 IHF.RIGHT.M O Floating EAR.P Earpiece output differential output (P) O A6 EAR.P O Floating EAR.M Earpiece output differential output (M) O A7 EAR.M O Floating HSOL Differential/single-ended headset left output O B4 HSOL O Floating PreDriv.LEFT Predriver output left P for external class-D amplifier O B7 VMID Power Floating VMID Pseudo-ground for headset output Power HSOR Differential/single-ended headset right output (P) O B5 HSOR O Floating PreDriv.RIGHT Predriver output right P for external class-D amplifier O B8 ADCIN7 I GND ADCIN7 GP ADC input 7 I AUXL Auxiliary audio input left I F1 AUXL I Cap to GND AUXR Auxiliary audio input right I G1 AUXR I Cap to GND MICBIAS1. OUT Analog microphone bias 1 Power D1 MICBIAS1.OUT Power Floating VMIC1.OUT Digital microphone power supply 1 Power MICBIAS2. OUT Analog microphone bias 2 Power D2 MICBIAS2.OUT Power Floating VMIC2.OUT Digital microphone power supply 2 Power VHSMIC.OUT Headset microphone bias Power E4 VHSMIC.OUT Power Floating Dedicated ground for microphones Power GND D3 MICBIAS.GND Power GND GND Power GND GND AVSS1 AVSS2 Power GND Analog ground AVSS3 AVSS4 14 Configuration By Default After Reset Released VBAT.LEFT MICBIAS.GND Headset UART Ball VBAT.LEFT Earpiece Headset Type(1) Description UART1.TXD Headset UART transmit data OD GPIO8 GPIO8 I/O UART1.RXD Headset universal asynchronous receiver/transmitter (UART) receive data/switch detection I J4/J6/ J7/J8/E5 AVSS1 R10 AVSS2 M15 AVSS3 C7 AVSS4 B1 UART1.TXD D8 GPIO8 Terminal Configuration and Functions OD PU Floating I PD Floating Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Table 3-2. Signal Description (continued) Signal Name Module Type(1) Description Ready-to-send output/ 64-kHz output clock/ Bit error ratio (BER) clock out in test mode ADCIN5 GP ADC input 5 CTSI/ BERDATA.OUT Clear-to-send input/ BERDATAOUT in test mode ADCIN3 GP ADC input 3 OD/ CMOS/ I/O I GP ADC input 4 I RXAF ULPI Unused Features(2) N11 RTSO/ CLK64K.OUT/ BERCLK.OUT OD Floating P11 CTSI/ BERDATA.OUT OD GND N8 TXAF I Cap to GND N9 RXAF O Floating I TXAF USB PHY OD Type Internal Pull or Not I MCPC Clock (1) Signal RTSO/ CLK64K.OUT/ BERCLK.OUT ADCIN4 Configuration By Default After Reset Released Ball O ADCIN6 GP ADC input 6 I MANU Manufacturer pin I L10 MANU I 32KCLKOUT Buffered output of the 32-kHz digital clock O N10 32KCLKOUT O Floating 32KXIN Input of the 32-kHz oscillator I P16 32KXIN I N/A 32KXOUT Output of the 32-kHz oscillator O P15 32KXOUT O Floating HFCLKIN Input of the digital (or sine) HS clock I A14 HFCLKIN I N/A HFCLKOUT HS clock output O R12 HFCLKOUT VBUS VBUS power rail Power R8 VBUS DP/ UART3.RXD USB data P/USB carkit receive data/UART3 receive data I/O T10 DN/ UART3.TXD USB data N/USB carkit transmit data/UART3 transmit data I/O ID USB ID UCLK STP GPIO9 GPIO9 DIR HS USB direction O GPIO10 GPIO10 I/O NXT HS USB next O GPIO11 GPIO11 I/O DATA0 HS USB Data0 I/O UART4.TXD UART4.TXD DATA1 HS USB Data1 I/O UART4.RXD UART4.RXD O DATA2 HS USB Data2 I/O UART4.RTSI UART4.RTSI DATA3 HS USB Data3 UART4.CTSO UART4.CTSO O GPIO12 GPIO12 I/O DATA4 HS USB Data4 I/O GPIO14 GPIO14 I/O DATA5 HS USB Data5 I/O GPIO3 GPIO3 I/O DATA6 HS USB Data6 I/O GPIO4 GPIO4 I/O DATA7 HS USB Data7 I/O GPIO5 GPIO5 I/O PU Floating O Floating Power N/A DP/UART3.RXD I/O N/A T11 DN/UART3.TXD I/O N/A I/O R11 ID I/O Connected to VRUSB3V1 HS USB clock I L15 UCLK O Floating HS USB stop I L14 STP I L13 DIR O Floating M13 NXT O Floating K14 DATA0 O Floating K13 DATA1 O Floating J14 DATA2 O Floating J13 DATA3 O Floating G14 DATA4 O Floating G13 DATA5 O Floating F14 DATA6 O Floating F13 DATA7 O Floating I/O I I PU Floating I/O Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 15 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Table 3-2. Signal Description (continued) Signal Name Module Test USB CP Type(1) Description Configuration By Default After Reset Released Ball Signal Test.RESET Reset T2 device (except power state-machine) TestV1 Analog test TestV2 Analog test I (1) Type Test.RESET I/O T1 TestV1 I/O Floating I/O A16 TestV2 I/O Floating Test Selection between JTAG mode and application mode for JTAG/GPIOs (with PU or PD) I A1 Test I JTAG.TDI/ BERDATA JTAG.TDI/BERDATA I A15 JTAG.TDI/ BERDATA I GND JTAG.TCK/ BERCLK JTAG.TCK/BERCLK I B16 JTAG.TCK/ BERCLK I GND CP.IN CP input voltage Power R7 CP.IN Power VBAT CP.CAPP CP flying capacitor P O T7 CP.CAPP O Floating CP.CAPM CP flying capacitor M O Floating Power GND GND T6 CP.CAPM R6 CP.GND PD Unused Features(2) T16 O I Internal Pull or Not PD GND Floating CP.GND CP ground Power GND VBAT.USB VBAT.USB USB LDOs (VINTUSB1P5, VINTUSB1P8, VUSB.3P1) VBAT Power R9 VBAT.USB Power VBAT USB.LDO VUSB.3P1 USB LDO output Power P9 VUSB.3P1 Power N/A VAUX12S.IN VAUX1/VAUX2/VSIM LDO input voltage Power L1 VAUX12S.IN Power VBAT VAUX1.OUT VAUX1 LDO output voltage Power M2 VAUX1.OUT Power Floating VAUX2.OUT VAUX2 LDO output voltage Power M3 VAUX2.OUT Power Floating VPLLA3R VPLLA3R.IN Input for VPLL1, VPLL2, VAUX3, VRTC LDOs Power H15 VPLLA3R.IN Power VBAT VRTC VRTC.OUT VRTC internal LDO output (internal use only) Power K16 VRTC.OUT Power N/A VPLL1 VPLL1.OUT LDO output voltage Power H14 VPLL1.OUT Power Floating VPLL2 VSDI.CSI.OUT Output voltage of the regulator Power J15 VSDI.CSI.OUT Power Floating VAUX3 VAUX3.OUT VAUX3 LDO output voltage Power G16 VAUX3.OUT Power Floating VAUX4.IN VAUX4 LDO input voltage Power B2 VAUX4.IN Power VBAT VAUX4.OUT VAUX4 LDO output voltage Power B3 VAUX4.OUT Power Floating VMMC1.IN VMMC1 LDO input voltage Power C1 VMMC1.IN Power VBAT VMMC1.OUT VMMC1 LDO output voltage Power C2 VMMC1.OUT Power Floating VMMC2.IN VMMC2 LDO input voltage Power A3 VMMC2.IN Power VBAT VMMC2.OUT VMMC2 LDO output voltage Power A4 VMMC2.OUT Power Floating VSIM VSIM.OUT VSIM LDO output voltage Power K2 VSIM.OUT Power Floating VINTUSB1 P5 VINTUSB1P5. OUT VINTUSB1P5 internal LDO output (internal use only) Power P8 VINTUSB1P5. OUT Power Floating VINTUSB1 P8 VINTUSB1P8. OUT VINTUSB1P8 internal LDO output (internal use only) Power P10 VINTUSB1P8. OUT Power Floating VDAC.IN Input for VDAC, VINTANA1, and VINTANA2 LDOs Power K1 VDAC.IN Power VBAT VDAC.OUT Output voltage of the regulator Power L2 VDAC.OUT Power Floating VINT VINT.IN Input for VINTDIG LDO Power K15 VINT.IN Power VBAT VINTANA1 VINTANA1. OUT VINTANA1 internal LDO output (internal use only) Power H3 VINTANA1.OUT Power N/A VINTANA2. OUT VINTANA2 internal LDO output (internal use only) Power J2 VINTANA2.OUT Power N/A VINTANA2. OUT VINTANA2 internal LDO output (internal use only) Power B6 VINTANA2.OUT Power N/A VINTDIG.OUT VINTDIG internal LDO output (internal use only) Power L16 VINTDIG.OUT Power N/A VAUX1 VAUX2 VAUX4 VMMC1 VMMC2 Video DAC VINTANA2 VINTDIG 16 Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Table 3-2. Signal Description (continued) Module Signal Name Type(1) Description Ball Configuration By Default After Reset Released Signal (1) Type Internal Pull or Not Unused Features(2) VDD1.IN VDD1 DC-DC input voltage Power E15 VDD1.IN Power VBAT VDD1.IN VDD1 DC-DC input voltage Power E14 VDD1.IN Power VBAT VDD1.IN VDD1 DC-DC input voltage Power D14 VDD1.IN Power VBAT VDD1.SW VDD1 DC-DC switch O D16 VDD1.SW O Floating VDD1.SW VDD1 DC-DC switch O D15 VDD1.SW O Floating VDD1.SW VDD1 DC-DC switch O C14 VDD1.SW O Floating VDD1.FB VDD1 DC-DC output voltage (feedback) I E13 VDD1.FB I GND VDD1.GND VDD1 DC-DC ground Power GND C16 VDD1.GND Power GND GND VDD1.GND VDD1 DC-DC ground Power GND C15 VDD1.GND Power GND GND VDD1.GND VDD1 DC-DC ground Power GND B15 VDD1.GND Power GND GND VDD2.IN VDD2 DC-DC input voltage Power R13 VDD2.IN Power VBAT VDD2.IN VDD2 DC-DC input voltage Power P14 VDD2.IN Power VBAT VDD2.FB VDD2 DC-DC output voltage (feedback) I N13 VDD2.FB I GND VDD2.SW VDD2 DC-DC switch O T13 VDD2.SW O Floating VDD2.SW VDD2 DC-DC switch O R14 VDD2.SW O Floating VDD2.GND VDD2 DC-DC ground Power GND T14 VDD2.GND Power GND GND VDD2.GND VDD2 DC-DC ground Power GND R15 VDD2.GND Power GND GND VIO.IN VIO DC-DC input voltage Power P3 VIO.IN Power VBAT VIO.IN VIO DC-DC input voltage Power R4 VIO.IN Power VBAT VIO.FB VIO DC-DC output voltage (feedback) I N3 VIO.FB I GND VIO.SW VIO DC-DC switch O R3 VIO.SW O Floating VIO.SW VIO DC-DC switch O T4 VIO.SW O Floating VIO.GND VIO DC-DC ground Power GND R2 VIO.GND Power GND GND VIO.GND VIO DC-DC ground Power GND T3 VIO.GND Power GND GND Backup battery BKBAT Backup battery Power M14 BKBAT Power GND Digital VDD IO.1P8 TPS65950 I/O input Power C8 IO.1P8 Power N/A Power GND GND GND VDD1 VDD2 VIO Digital ground LED driver DGND Digital ground Power GND LEDGND LED driver ground Power GND GPIO13 GPIO13 LEDSYNC LED synchronization input LEDA LED leg A VIBRA.P H-bridge vibrator P LEDB LED leg B VIBRA.M H-bridge vibrator M H13 / H9 / H10 / DGND H11 F16 LEDGND Power GND G11 GPIO13 I OD F15 Signal not functional(4) Floating OD G15 Signal not functional(4) Floating I/O I PD Floating Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 17 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Table 3-2. Signal Description (continued) Module Keypad Bluetooth/ digital microphone RFID Signal Name Type(1) Description Ball Configuration By Default After Reset Released Signal (1) Type Internal Pull or Not Unused Features(2) KPD.C0 Keypad column 0 OD G8 KPD.C0 OD Floating KPD.C1 Keypad column 1 OD H7 KPD.C1 OD Floating KPD.C2 Keypad column 2 OD G6 KPD.C2 OD Floating KPD.C3 Keypad column 3 OD F7 KPD.C3 OD Floating KPD.C4 Keypad column 4 OD G7 KPD.C4 OD Floating KPD.C5 Keypad column 5 OD F4 KPD.C5 OD Floating KPD.C6 Keypad column 6 OD H6 KPD.C6 OD Floating KPD.C7 Keypad column 7 OD G4 KPD.C7 OD KPD.R0 Keypad row 0 I K9 KPD.R0 I PU Floating KPD.R1 Keypad row 1 I K8 KPD.R1 I PU Floating KPD.R2 Keypad row 2 I L8 KPD.R2 I PU Floating KPD.R3 Keypad row 3 I K7 KPD.R3 I PU Floating KPD.R4 Keypad row 4 I L9 KPD.R4 I PU Floating KPD.R5 Keypad row 5 I J10 KPD.R5 I PU Floating KPD.R6 Keypad row 6 I K10 KPD.R6 I PU Floating KPD.R7 Keypad row 7 I L7 KPD.R7 I PU Floating GPIO16 Bluetooth PCM receive data I/O BT.PCM.VDR GPIO16 I/O C3 GPIO16 I PD Floating DIG.MIC.CLK0 Digital microphone clock 0 O GPIO17 GPIO17 BT.PCM.VDX Bluetooth PCM transmit data C5 GPIO17 I PD Floating DIG.MIC.CLK1 Digital microphone clock 1 O RFID.EN Enable for the radio frequency identification (RFID) device O A2 RFID.EN O I/O Floating Floating (1) I = Input; O = Output; OD = Open drain (2) This column provides the connection when the associated feature is not used or not connected. When there is a pin muxing, not all functions on the muxed pin are used. But even if a function is not used, the Default Configuration column applies. Connection criteria: – Analog pins: – For input: GND – For output: Floating (except VPRECH is connected to GND) – For I/O if input by default: GND (except for audio features input: capacitor to ground with a 100-nF typical value capacitor) – Digital pins: – For input: GND (except keypad and STP are left floating) – For input and pullup: Floating – For output: Floating – For I/O and pullup: Floating N/A (not applicable): When the associated feature is mandatory for good functioning of the TPS65950. (3) The VPRECH, VBATS, and VCCS signals must be connected to each other and with the CPRECH capacitor to GND (see Section 5.5.2.3, Configuration with BCI Not Used). (4) Signal not functional indicates that no signal is presented on the pad after a release reset. 18 Terminal Configuration and Functions Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 4 Specifications 4.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Parameter Test Conditions Max Unit 2.1 4.5 V 0.0 1.0*Supply V Storage temperature range –55 125 °C Ambient temperature range –40 85 °C 105 °C 105 °C Main battery supply voltage (1) Voltage on any input Where supply represents the voltage applied to the power supply pin associated with the input Junction temperature (TJ) Handling Ratings Tstg MIN MAX UNIT –45 150 °C Internal pins –1 1 External pins (2) –2 2 –500 500 Storage temperature range VESD 4.3 –40 The product can tolerate voltage spikes of 5.2 V for a total duration of 10 milliseconds. 4.2 (1) (2) (3) Typ At 1.4W (Theta JB 11°C/W 2S2P board) Junction temperature (TJ) for parametric compliance (1) Min Electrostatic discharge (ESD) performance: Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 (1) Charged Device Model (CDM), per JESD22-C101 (3) All pins kV V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. List of external pins: VAC, VBUS, DP/UART3.RXD, DN/UART3.TXD, ID, VPLL1.OUT, VMMC1.OUT, VMMC2.OUT, VSIM.OUT. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Parameter Min Typ Max Unit 2.7 (1) 3.6 4.5 V Backup battery supply voltage 1.8 3.2 3.3 V Ambient temperature range –40 85 °C Main battery supply voltage (1) 2.7 V is the minimum threshold for the battery at which the device will turn OFF. However, the minimum voltage at which the device will power ON is 3.2 V ±100 mV (if PWRON does not have a switch and is connected to VBAT) considering battery plug as the device switch on event. If PWRON has a switch then 3.2 V is the minimum for the device to turn ON. Specifications Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 19 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Digital I/O Electrical Characteristics (1) 4.4 VOL (V) VOH (V) VIL (V) VIH (V) Min Max Min Max Min Max Min Max Max Freq (MHz) 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2 START.ADC 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6 16.7 16.7 SYSEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL CLKEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 CLKEN2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 CLKREQ 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 INT1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 INT2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL NRESPWRON 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL NRESWARM 0 0.45 RL–0.45 RL 0 0.35×RL 0 Pin Name Load (pF) Rise Fall Time (ns) Output Mode Time (ns) GPIO0/CD1 JTAG.TDO GPIO0/CD2 JTAG.TMS GPIO2 Test1 GPIO15 Test2 GPIO16 PWM0 Test3 GPIO17 VIBRA.SYNC PWM1 Test4 PWRON 5.2 5.2 30 33.3 33.3 30 33.3 33.3 33.3 33.3 30 33.3 33.3 3 30 33.3 33.3 RL 3 30 33.3 33.3 0.65×RL RL 3 30 33.3 33.3 0.35×1.8V 0.65×1.8V VBAT 3 33.3 33.3 NSLEEP1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3 NSLEEP2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3 CLK256FS 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 12.288 16.3 16.3 VMODE1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3 BOOT0 0 RL 3 33.3 33.3 BOOT1 0 RL 3 33.3 33.3 REGEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3 MSECURE 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3 I2C.SR.SDA 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 VMODE2 0 0.45 0 0.35×RL 0.65×RL RL 3.4 29.4 29.4 I2C.SR.SCL 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 10.0 10.0 I2C.CNTL.SDA 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 I2C.CNTL.SCL 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 10.0 10.0 PCM.VCK 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 33.0 PCM.VDR 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 100.0 PCM.VDX 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 33.0 PCM.VFS 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 33.0 33.0 I2S.CLK 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6.5 30 33.0 33.0 I2S.SYNC 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6.5 30 33.0 33.0 I2S.DIN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.25 30 33.0 33.0 I2S.DOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.25 30 29.0 29.0 UART1.TXD 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.0 33.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0 RL–0.45 RL 30 30 Up to 400 Up to 400 GPIO8 UART1.RXD (1) • • • • • 20 RL: Reference level voltage applied to the I/O cell VOL: Low-level output voltage VOH: High-level output voltage VIL: Low-level input voltage VIH: High-level input voltage Specifications Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Digital I/O Electrical Characteristics(1) (continued) VOL (V) VOH (V) VIL (V) VIH (V) Min Max Min Max Min Max Min Max Max Freq (MHz) RTSO/CLD64K.OUT/ BERCLK.OUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.0 33.0 CTSI/BERDATA.OUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.0 33.0 MANU 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0 32KCLKOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.032 30 16 16 HFCLKOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 38.4 30 2.6 2.6 UCLK 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 60 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0 Test.RESET 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0 Test 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 29.0 29.0 JTAG.TDI/ BERDATA 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0 JTAG.TCK/ BERDATA 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.35×RL KPD.C0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL KPD.C1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL KPD.C2 0 0.45 RL–0.45 RL 0 0.35×RL KPD.C3 0 0.45 RL–0.45 RL 0 KPD.C4 0 0.45 RL–0.45 RL KPD.C5 0 0.45 RL–0.45 KPD.C6 0 0.45 KPD.C7 0 KPD.R0 Pin Name Load (pF) Rise Fall Time (ns) Output Mode Time (ns) STP GPIO9 DIR GPIO10 NXT GPIO11 DATA0 UART4.TXD DATA1 UART4.RXD DATA2 UART4.RTSI DATA3 UART4.CTSO GPIO12 DATA4 GPIO14 DATA5 GPIO3 DATA6 GPIO4 DATA7 GPIO5 30 GPIO13 3 30 33.3 33.3 RL 0.033 30 29.0 29.0 RL 0.033 30 29.0 29.0 0.65×RL RL 0.033 30 29.0 29.0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 KPD.R1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 KPD.R2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 KPD.R3 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 KPD.R4 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 KPD.R5 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 KPD.R6 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 KPD.R7 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8 GPIO16 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3 DIG.MIC.CLK0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 2.4 30 41.7 41.7 LEDSYNC Specifications Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 21 TPS65950 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 www.ti.com Digital I/O Electrical Characteristics(1) (continued) VOL (V) VOH (V) VIL (V) VIH (V) Min Max Min Max Min Max Min Max Max Freq (MHz) BT.PCM.VDX 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 100.0 GPIO17 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3 DIG.MIC.CLK1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 2.4 30 41.7 41.7 BT.PCM.VDX 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 1 30 100.0 100.0 Pin Name Load (pF) Rise Fall Time (ns) Output Mode Time (ns) RFID.EN 4.5 Thermal Resistance Characteristics for ZXN Package °C/W (1) (2) AIR FLOW (m/s) (3) NAME DESCRIPTION RΘJC Junction-to-case (top) 12.9 0.00 RΘJB Junction-to-board 11.2 0.00 RΘJA (High k PCB) Junction-to-free air 37.6 0.00 PsiJT Junction-to-package top 0.2 0.00 PsiJB Junction-to-board 9.5 0.00 (1) (2) (3) 22 °C/W = degrees Celsius per watt. These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements m/s = meters per second. Specifications Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65950 TPS65950 www.ti.com 4.6 SWCS032F – OCTOBER 2008 – REVISED JULY 2014 Minimum Voltages and Associated Currents Category Pin and Module VBAT pin name VDD_VPLLA3R_IN_6POV Internal module supplied 340 1.0 / 1.2 / 1.3 / 1.8 / 2.8 / 3.0 Maximum (2.7, output voltage selected + 250 mV) VPLL2 (LDO) 100 0.7 / 1.0 / 1.2 / 1.3 / 1.5 / 1.8 / 1.85 / 2.5 / 2.6 / 2.8 / 2.85 / 3.0 / 3.15 Maximum (2.7, output voltage selected + 250 mV) VAUX3 (LDO) 200 1.5 / 1.8 / 2.5 / 2.8 / 3.0 Maximum (2.7, output voltage selected + 250 mV) VDD1 core (DCDC)