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TPS72325-Q1, TPS72301-Q1
SLVSAJ4C – SEPTEMBER 2010 – REVISED OCTOBER 2017
TPS723xx-Q1
200-mA Low-Noise, High-PSRR, Negative-Output, Low-Dropout Linear Regulators
1 Features
3 Description
•
•
The TPS723xx-Q1 family of low-dropout (LDO)
negative voltage regulators offers an ideal
combination of features to support low-noise
applications. This device is capable of operating with
input voltages from –10 V to –2.7 V. The TPS72325Q1 regulator is stable with small, low-cost ceramic
capacitors, and includes enable (EN) and noisereduction (NR) functions. Internal detection and
shutdown logic provide thermal short-circuit and
overcurrent protection. High PSRR (65 dB at 1 kHz)
and low noise (60 μVRMS) make the TPS723xx-Q1
ideal for low-noise applications.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Ultralow Noise: 60 μVRMS Typical
High PSRR: 65 dB Typical at 1kHz
Low Dropout Voltage:
280 mV Typical at 200 mA, 2.5 V
Available in –2.5 V and Adjustable
(–1.2 V to –10 V) Versions
Stable With a 2.2-μF Ceramic Output Capacitor
Less Than 2-μA Typical Quiescent Current in
Shutdown Mode
2% Overall Accuracy
(Line, Load, Temperature)
Thermal and Overcurrent Protection
SOT23-5 (DBV) Package
Operating Junction Temperature Range:
–40°C to 125°C
Device Information(1)
PART NUMBER
PACKAGE
TPS723xx-Q1
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
SPACE
2 Applications
•
•
•
•
•
The TPS723xx-Q1 uses a precision voltage reference
to achieve 2% overall accuracy over load, line, and
temperature variations. Available in a small SOT23-5
package, the TPS723xx-Q1 specification covers the
full temperature range of –40°C to 125°C.
Optical Drives
Optical Networking
Noise-Sensitive Circuitry
GaAs FET Gate Bias
Video Amplifiers
Typical Application Circuit
2
IN
OUT
5
2.2 mF
2.2 mF
On
+1.5 V
GND
-1.5 V
3
EN
NR
Off
On
4
10 nF
GND
1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS72325-Q1, TPS72301-Q1
SLVSAJ4C – SEPTEMBER 2010 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
3
3
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Power Dissipation Ratings ........................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
8
Device and Documentation Support.................. 11
8.1
8.2
8.3
8.4
8.5
8.6
9
Related Links .......................................................... 11
Receiving Notification of Documentation Updates.. 11
Community Resources............................................ 11
Trademarks ............................................................. 11
Electrostatic Discharge Caution .............................. 11
Glossary .................................................................. 11
Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2012) to Revision C
Page
•
Added Device Information table, ESD Ratings table, Pin Configuration and Functions section, Feature Description
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Added AEC-Q100 Qualified With the Following Results bullets............................................................................................. 1
•
Deleted Ordering Information table ....................................................................................................................................... 3
•
Changed HBM value from ±2000 kV to ±2000 V in ESD Ratings table................................................................................. 3
2
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SLVSAJ4C – SEPTEMBER 2010 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
GND
1
IN
2
EN
3
5
OUT
4
NR
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
GND
—
2
IN
I
Ground
Input supply
3
EN
I
Bipolar enable pin. Driving this pin above the positive enable threshold or below the negative
enable threshold turns on the regulator. Driving this pin below the positive disable threshold
and above the negative disable threshold puts the regulator into shutdown mode.
4
NR
—
Fixed-voltage versions only. Connecting an external capacitor between this pin and ground
bypasses noise generated by the internal band gap. This configuration allows output noise to
be reduced to very low levels.
5
OUT
O
Regulated output voltage. The device requires the connection of a small 2.2-μF ceramic
capacitor from this pin to GND to ensure stability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
Input voltage range, VIN
–11
0.3
V
Noise reduction pin voltage range, VNR
–11
5.5
V
Enable voltage range, VEN
–VIN
5.5
V
Output current, IOUT
Internally limited
Output short-circuit duration
Indefinite
See the Power Dissipation Ratings
table
Continuous total power dissipation, PD
Latch-up performance meets 100 mA per AEC-Q100 | Class I
100
Junction temperature range, TJ
–55
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±500
Machine model
±200
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Power Dissipation Ratings
TA ≤ 25°C
POWER
RATING
TA = 70°C
POWER
RATING
TA = 85°C
POWER
RATING
BOARD
PACKAGE
RθJC
RθJA
DERATING FACTOR
ABOVE TA = 25°C
Low-K (1)
DBV
64°C/W
255°C/W
3.9 mW/°C
390 mW
215 mW
155 mW
(2)
DBV
64°C/W
180°C/W
5.6 mW/°C
560 mW
310 mW
225 mW
High-K
(1)
(2)
The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3- inch (7,62-cm × 7,62-cm), two-layer board with 2-ounce
(0.071-mm thick) copper traces on top of the board.
The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch (7,62-cm × 7,62-cm), multilayer board with 1ounce (0.035-mm thick) internal power and ground planes and 2-ounce (0.071-mm thick) copper traces on the top and bottom of the
board.
6.4 Electrical Characteristics
Over operating junction temperature range, VIN = VOUTnom – 0.5V, IOUT = 1mA, VEN = 1.5V, COUT = 2.2μF, and CNR = 0.01μF,
unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range
TEST CONDITIONS
MIN
(1)
V
–10
–2.7
–1%
1%
TPS723xx-Q1
versus
VIN / IOUT / T
–10V ≤ VIN ≤ VOUT – 0.5V,
10 μA ≤ IOUT ≤ 200 mA
–2%
VOUT% /
VIN
Line regulation
–10 V ≤ VIN ≤ VOUT(nom) – 0.5 V
VOUT% /
IOUT
Load regulation
0 mA ≤ IOUT ≤ 200 mA
VDO
Dropout voltage at VOUT = 0.96 × VOUTnom
IOUT = 200 mA
ICL
Current limit
VOUT = 0.85 × VOUT(nom)
Ground pin current
Shutdown ground pin current
PSRR
UNIT
TJ = 25°C
Accuracy
ISHDN
MAX
Nominal
VOUT
IGND
TYP
Power-supply rejection ratio
±1%
2%
0.04
%/V
0.002
%/mA
280
500
mV
550
800
mA
IOUT = 0 mA (IQ),
–10 V ≤ VIN ≤ VOUT – 0.5 V
130
200
IOUT = 200 mA,
–10 V ≤ VIN ≤ VOUT – 0.5 V
350
500
–0.4 V ≤ VEN ≤ 0.4 V,
–10V ≤ VIN ≤ VOUT – 0.5 V
0.1
2
IOUT = 200 mA, 1 kHz,
CIN = COUT = 10 μF
65
IOUT = 200 mA, 10 kHz,
CIN = COUT = 10 μF
48
60
μVRMS
1
ms
300
μA
μA
dB
Vn
Output noise voltage
COUT = 10 μF, 10 Hz to 100 kHz,
IOUT = 200 mA
tSTR
Startup time
VOUT = –2.5 V, COUT = 1 μF,
RL = 25 Ω
VEN(HI)
Enable threshold positive
VEN(LO)
Enable threshold negative
–1.5
V
VDIS(HI)
Disable threshold positive
0.4
V
VDIS(LO)
Disable threshold negative
IEN
Enable pin current
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
4
1.5
V
–0.4
V
–10 V ≤ VIN ≤ VOUT – 0.5 V,
–10 V ≤ VEN ≤ ±3.5 V
0.1
Shutdown, temperature increasing
165
Reset, temperature decreasing
145
–40
2
μA
°C
125
°C
Maximum VIN = (VOUT – VDO) or – 2.7 V, whichever is more negative.
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SLVSAJ4C – SEPTEMBER 2010 – REVISED OCTOBER 2017
6.5 Typical Characteristics
TPS723xx-Q1 at VIN = VOUTnom – 0.5 V, IOUT = 1 mA, VEN = 1.5 V, COUT = 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
-2.475
Output Voltage, VOUT (V)
Output Voltage (V)
-2.475
-2.488
TJ = +25°C
TJ = -40°C
-2.500
TJ = +85°C
-2.513
TJ = +125°C
-2.525
-10
VIN = 3V, IOUT = 200mA
-2.488
VIN = 10V, IOUT = 200mA
-2.500
VIN = 10V, IOUT = 0mA
-2.513
VIN = 3V, IOUT = 0mA
-2.525
-9
-8
-7
-6
-5
-4
-3
-2
-40
0
-20
Input Voltage (V)
Figure 1. Output Voltage vs Input Voltage
60
80
100
120
140
350
300
300
TJ = +125°C
Dropout Voltage (mV)
Dropout Voltage (mV)
40
Figure 2. Output Voltage vs Ambient Temperature
350
250
TJ = +25°C
200
150
TJ = -40°C
100
50
250
200
150
100
50
0
0
0
25
50
75
100
125
150
175
200
-40
-20
0
20
40
60
80
100
120
140
Output Current (mA)
Junction Temperature (°C)
Figure 3. Dropout Voltage vs Output Current
Figure 4. TPS723xx-Q1 Dropout Voltage vs Junction
Temperature
500
400
450
350
400
TJ = +25°C
RL = 12.5W
350
Ground Current (mA)
Ground Current (mA)
20
Ambient Temperature (°C)
300
250
200
150
No Load
100
300
250
TJ = +125°C
200
TJ = -40°C
150
100
50
50
0
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0
50
Input Voltage (V)
Figure 5. Ground Current vs Input Voltage
100
150
200
Output Current (mA)
Figure 6. Ground Current vs Output Current
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Typical Characteristics (continued)
TPS723xx-Q1 at VIN = VOUTnom – 0.5 V, IOUT = 1 mA, VEN = 1.5 V, COUT = 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
500
800
450
750
700
VIN = 10V, IOUT = 200mA
350
Current Limit (mA)
Ground Current (mA)
400
300
250
200
VIN = 3V, IOUT = 0mA
150
100
650
600
550
500
450
400
VIN = 10V, IOUT = 0mA
50
350
0
300
-40
-20
0
20
40
60
80
100
120
140
-40
0
-20
20
40
60
80
100
120
140
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7. Ground Current vs Junction Temperature
Figure 8. Current Limit vs Junction Temperature
250
1000
800
Enable Pin Current (nA)
Standby Current (nA)
200
VIN = -10V
150
VIN = -3V
100
50
600
400
200
VIN = -10V, VEN = -0.5V
0
-200
VIN = -10V, VEN = 3.5V
-400
-600
VIN = -10V, VEN = -10V
-800
0
-40
-20
0
20
40
60
80
100
120
-1000
140
-40
0
-20
Junction Temperature (°C)
Figure 9. Standby Current vs Junction Temperature
40
60
80
100
120
140
Figure 10. Enable Pin Current vs Junction Temperature
Input Voltage (V) Output Voltage (mV)
Line Regulation (%/V)
Load Regulation (%/mA)
0.25
0.13
Load
0
Line
-0.13
-0.25
100
50
0
-50
0
-3.0
-3.5
CIN = 2.2mF
COUT = 2.2mF
CNR = 0mF
-4.0
-4.5
-40
-20
0
20
40
60
80
100
120
140
0
20
40
Junction Temperature (°C)
Figure 11. Line and Load Regulation vs Junction
Temperature
6
20
Ambient Temperature (°C)
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60
80
100 120
140 160
180 200
Time (ms)
Figure 12. Line Transient Response
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Typical Characteristics (continued)
TPS723xx-Q1 at VIN = VOUTnom – 0.5 V, IOUT = 1 mA, VEN = 1.5 V, COUT = 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
Current Load (mA)
0
0
-100
CIN = 2.2mF
COUT = 2.2mF
CNR = 0mF
-200
0
20
40
60
80
100 120
140 160
DVOUT, Change In
Output Voltage (mV)
Current Load (mA)
DVOUT, Change In
Output Voltage (mV)
100
100
0
0
-100
CIN = 2.2mF
COUT = 2.2mF
CNR = 0mF
-200
180 200
0
20
40
60
80
Time (ms)
Output Voltage (mV)
Input Voltage (V)
Input Voltage (V)
CIN = 2.2mF
COUT = 2.2mF
IOUT = 50mA
CNR = 0mF
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2
0
1
CIN = 2.2mF
COUT = 2.2mF
IOUT = 50mA
CNR = 0.01mF
2
3
1.0
0
0.1
0.2
Figure 15. Start-Up Response
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Figure 16. Start-Up Response
250
Total Noise (mVRMS)
VIN
-1.0
-1.5
-2.0
CIN = 2.2mF
COUT = 2.2mF
IOUT = 50mA
CNR = 0mF
-2.5
-3.0
CIN = 2.2mF
COUT = 2.2mF, IOUT = 100mA
VOUT
200
Voltage (V)
0.3
Time (ms)
0.5
-0.5
180 200
0
Time (ms)
0
140 160
Figure 14. Load Transient Response
Output Voltage (mV)
Figure 13. Load Transient Response
0
100 120
Time (ms)
COUT = 10mF, IOUT = 100mA
150
COUT = 2.2mF, IOUT = 25mA
100
50
COUT = 10mF, IOUT = 25mA
0
-3.5
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1k
10k
100k
CNR (pF)
Time (ms)
Figure 17. Power Up and Power Down
Figure 18. Total Noise vs CNR
(10 Hz to 100 kHz)
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Typical Characteristics (continued)
TPS723xx-Q1 at VIN = VOUTnom – 0.5 V, IOUT = 1 mA, VEN = 1.5 V, COUT = 2.2 μF, and CNR = 0.01 μF, unless otherwise noted.
Output Noise (100mV/div)
Noise Spectral Density (VRMS/ÖHz)
10m
CIN = -2.2mF, COUT = 2.2mF
IOUT = 100mA, CNR = 0.01mF
IOUT = 25mA
1m
IOUT = 100mA
100n
CIN = 0.01mF
COUT = 2.2mF
CNR = 0.01mF
10n
100
Time (1ms/div)
1k
10k
100k
Frequency (Hz)
Figure 19. Output Noise vs Time
Figure 20. Noise Spectral Density vs Frequency
90
Power-Supply Rejection Ratio (dB)
Noise Spectral Density (VRMS/ÖHz)
10m
IOUT = 100mA
1m
IOUT = 25mA
100n
CIN = 0mF
COUT = 2.2mF
CNR = 0.01mF
10n
80
70
IOUT = 100mA
60
IOUT = 1mA
50
40
30
20
VIN = -5V
CIN = 10mF
COUT = 10mF
CNR = 0mF
10
0
IOUT = 200mA
-10
100
1k
10k
10
100k
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 21. Noise Spectral Density vs Frequency
Figure 22. PSRR vs Frequency
Power-Supply Rejection Ratio (dB)
90
80
70
IOUT = 100mA
60
IOUT = 1mA
50
40
30
20
10
0
VIN = -5V
CIN = 10mF
COUT = 10mF
CNR = 0.01mF
IOUT = 200mA
-10
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 23. PSRR vs Frequency
8
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7 Detailed Description
7.1 Overview
The TPS723xx-Q1 is a low-dropout negative linear voltage regulator with a rated current of 200 mA. It features
very low noise and high power-supply rejection ratio (PSRR), making it ideal for high-sensitivity analog and RF
applications. A shutdown mode is available, reducing ground current to 2 μA maximum over temperature and
process. The TPS723xx-Q1 comes in a small SOT23 package, specified over a –40°C to 125°C junctiontemperature range.
7.2 Functional Block Diagram
TPS72325
IN
OUT
EN
100 kW
5 pF
VREF
1.186 V
Current Limit
/Thermal
Protection
R1
GND
R2
R1 + R2 = 97 kW
NR
7.3 Feature Description
7.3.1 Enable
The enable pin is active above 1.5 V and below –1.5 V, allowing control by a standard TTL signal or by
connection to VI if not used. Driving the pin to GND turns off most internal circuitry, putting the TPS723xx-Q1 into
shutdown mode, drawing 2-μA maximum ground current.
7.3.2 Capacitor Selection for Stability
Use appropriate input and output capacitors for the intended application. The TPS723xx-Q1 only requires the
use of a 2.2-μF ceramic output capacitor for stable operation. Both the capacitor value and ESR affect stability,
output noise, PSRR, and transient response. For typical applications, a 2.2-μF ceramic output capacitor located
close to the regulator is sufficient.
7.3.3 Output Noise
Without external bypassing, output noise of the TPS723xx-Q1 from 10 Hz to 100 kHz is 200 μVRMS typical. The
dominant contributor to output noise is the internal band-gap reference. Adding an external 0.01-μF capacitor to
ground reduces the noise to 60 μVRMS. To achieve best noise performance, use appropriate low-ESR capacitors
for bypassing noise at the NR and OUT pins. See Figure 18 in the Typical Characteristics section.
7.3.4 Power-Supply Rejection
The TPS723xx-Q1 offers a very high PSRR for applications with noisy input sources or highly sensitive output
supply lines. For best PSRR, use high-quality input and output capacitors.
7.3.5 Current Limit
The TPS723xx-Q1 has internal circuitry that monitors and limits output current to protect the regulator from
damage under all load conditions. When output current reaches the output-current limit (550 mA typical),
protection circuitry turns on, reducing output voltage to ensure that current does not increase. See Figure 8 in the
Typical Characteristics section.
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Feature Description (continued)
Do not drive the output more than 0.3 V above the input. Doing so biases the body diode in the pass FET,
allowing current to flow from the output to the input. The device does not limit this current. If this condition is
likely, take care to limit the reverse current externally.
7.3.6 Thermal Protection
As protection from damage due to excessive junction temperatures, the TPS723xx-Q1 has internal protection
circuitry. When junction temperature reaches approximately 165°C, the output device turns off. After the device
has cooled by about 20°C, the output device turns on, allowing normal operation. For reliable operation, design is
for worst-case junction temperature of ≤ 125°C, taking into account worst-case ambient temperature and load
conditions.
7.3.7 Adjustable Voltage Applications
The TPS72301-Q1 allows designers to specify any output voltage from –10 V to –1.2 V. As shown in the
application circuit in Figure 24, use of an external resistor divider scales the output voltage (VOUT) to the
reference voltage. For best accuracy, use precision resistors for R1 and R2. Use the equations in Figure 24 to
determine the values for the resistor divider.
VOUT = –1.186 1 +
R1
R2
R1+R2 ≈ 100kΩ
2
5
IN
OUT
R1
4
3
FB
EN
GND
R2
1
Figure 24. TPS72301-Q1 Adjustable LDO Regulator Programming
10
Submit Documentation Feedback
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS72325-Q1 TPS72301-Q1
TPS72325-Q1, TPS72301-Q1
www.ti.com
SLVSAJ4C – SEPTEMBER 2010 – REVISED OCTOBER 2017
8 Device and Documentation Support
8.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS72325-Q1
Click here
Click here
Click here
Click here
Click here
TPS72301-Q1
Click here
Click here
Click here
Click here
Click here
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2010–2017, Texas Instruments Incorporated
Product Folder Links: TPS72325-Q1 TPS72301-Q1
Submit Documentation Feedback
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS72301QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PPHQ
TPS72325QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PSBQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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