TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
D
D
D
D
D
D
D
D, P, OR PW PACKAGE
(TOP VIEW)
Available in 5-V, 4.85-V, 3.3-V, 3.0-V, and
2.5-V Fixed-Output and Adjustable Versions
Dropout Voltage 100 mA simultaneously, pass element rDS(on) increases (see Figure 10) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3. To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7225Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
TJ
Output voltage
VI = 3.5 V,
3.5 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
Dropout voltage
IO = 250 mA,
mA
VI = 2
2.97
97 V
Pass element series resistance
Pass-element
(
(2.97
V – VO)/I
) O,
IO = 250 mA
VI = 2.97 V,,
Input regulation
3 5 V to 10 V,
V
VI = 3.5
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
3 5 V ≤ VI ≤ 10 V
3.5
IO = 50 µA to 250 mA,
mA
3 5 V ≤ VI ≤ 10 V
3.5
IO = 50 µA
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
H ≤ f ≤ 100 kHz,
kH
10 Hz
CSR† = 1 Ω
PG trip-threshold voltage
IPG = 1.2
1 2 mA,
mA
25°C
2.55
560
– 40°C to 125°C
25°C
2.24
25°C
9
– 40°C to 125°C
25°C
28
24
– 40°C to 125°C
47
– 40°C to 125°C
45
25°C
40
– 40°C to 125°C
38
27
Ω
mV
36
41
mV
58
dB
46
25°C
248
CO = 10 µF
25°C
200
CO = 100 µF
25°C
130
– 40°C to 125°C
0.95 ×
VO(nom)
25°C
50
25°C
0.3
– 40°C to 125°C
V
3.4
73
25°C
CO = 4.7 µF
VI = 2
2.13
13 V
mV
60
25°C
V
1.1
33
– 40°C to 125°C
UNIT
850
3.84
2
VO voltage decreasing from above VPG
MAX
2.5
2.45
25°C
PG hysteresis voltage
PG output low voltage
25°C
– 40°C to 125°C
TYP
– 40°C to 125°C
Output regulation
Ripple rejection
TPS7225Q
MIN
µV/√Hz
µVrms
V
mV
0.44
0.5
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7230Q electrical characteristics, IO = 10 mA, VI = 4 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TJ
VI = 4 V,
4 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 100 mA,
mA
VI = 2
2.97
97 V
Dropout voltage
IO = 250 mA,
mA
VI = 2
2.97
97 V
Pass element series resistance
Pass-element
((2.97 V – VO)/I
) O,
IO = 250 mA
VI = 2.97 V,,
Input regulation
VI = 4 V to 10 V,
V
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
4 V ≤ VI ≤ 10 V
4 V ≤ VI ≤ 10 V
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
Output noise voltage
PG trip-threshold voltage
f = 120 Hz
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR† = 1 Ω
IPG = 1.2
1 2 mA,
mA
25°C
3.06
145
– 40°C to 125°C
390
502
1.56
2.01
– 40°C to 125°C
3.6
25°C
9
– 40°C to 125°C
25°C
34
– 40°C to 125°C
mV
42
– 40°C to 125°C
Ω
mV
45
74
25°C
60
mV
98
25°C
45
– 40°C to 125°C
44
25°C
40
– 40°C to 125°C
38
56
dB
45
2
256
CO = 10 µF
25°C
206
CO = 100 µF
25°C
132
µV/√Hz
µVrms
0.95 ×
VO(nom)
25°C
50
25°C
0.25
– 40°C to 125°C
27
33
25°C
VI = 2
2.55
55 V
V
900
25°C
– 40°C to 125°C
UNIT
185
270
25°C
25°C
VO voltage decreasing from above VPG
MAX
3
2.94
CO = 4.7 µF
PG hysteresis voltage
PG output low voltage
25°C
– 40°C to 125°C
TYP
– 40°C to 125°C
Output regulation
IO = 50 µA to 250 mA,
mA
TPS7230Q
MIN
V
mV
0.44
0.44
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7233Q electrical characteristics, IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TJ
VI = 4.3 V,
4.3 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 10 mA,
mA
VI = 3
3.23
23 V
IO = 100 mA,
mA
VI = 3
3.23
23 V
mA
IO = 250 mA,
23 V
VI = 3
3.23
Pass element series resistance
Pass-element
(
(3.23
V – VO)/I
) O,
IO = 250 mA
VI = 3.23 V,,
Input regulation
VI = 4.3
4 3 V to 10 V,
V
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
4 3 V ≤ VI ≤ 10 V
4.3
Dropout voltage
4 3 V ≤ VI ≤ 10 V
4.3
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR† = 1 Ω
PG trip-threshold voltage
1 2 mA,
mA
IPG = 1.2
25°C
3.37
14
20
140
180
– 40°C to 125°C
– 40°C to 125°C
232
25°C
360
460
1.5
1.84
– 40°C to 125°C
2.5
25°C
8
– 40°C to 125°C
25
33
25°C
32
– 40°C to 125°C
mV
41
– 40°C to 125°C
Ω
mV
42
71
25°C
55
mV
98
25°C
40
– 40°C to 125°C
38
25°C
35
– 40°C to 125°C
33
52
dB
44
25°C
265
CO = 10 µF
25°C
212
CO = 100 µF
25°C
135
– 40°C to 125°C
0.95 ×
VO(nom)
25°C
32
25°C
0.22
– 40°C to 125°C
V
610
25°C
CO = 4.7 µF
8V
VI = 2
2.8
UNIT
30
25°C
2
VO voltage decreasing from above VPG
MAX
3.3
3.23
25°C
PG hysteresis voltage
PG output low voltage
25°C
– 40°C to 125°C
TYP
– 40°C to 125°C
Output regulation
IO = 50 µA to 250 mA,
mA
TPS7233Q
MIN
µV/√Hz
µVrms
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7248Q electrical characteristics, IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TJ
VI = 5.85 V,
5.85 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 10 mA
mA,
VI = 4
4.75
75 V
IO = 100 mA,
mA
VI = 4
4.75
75 V
mA
IO = 250 mA,
75 V
VI = 4
4.75
Pass element series resistance
Pass-element
(
(4.75
V – VO)/I
) O,
IO = 250 mA
VI = 4.75 V,,
Input regulation
VI = 5
5.85
85 V to 10 V
V,
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
5 85 V ≤ VI ≤ 10 V
5.85
Dropout voltage
Output regulation
IO = 50 µA to 250 mA,
mA
5 85 V ≤ VI ≤ 10 V
5.85
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
H ≤ f ≤ 100 kHz,
kH
10 Hz
CSR† = 1 Ω
PG trip-threshold voltage
25°C
4.95
10
19
90
100
– 40°C to 125°C
– 40°C to 125°C
150
25°C
216
– 40°C to 125°C
mV
250
0.8
1
– 40°C to 125°C
1.4
25°C
34
– 40°C to 125°C
50
25°C
43
– 40°C to 125°C
55
– 40°C to 125°C
Ω
mV
55
95
25°C
75
mV
135
25°C
42
– 40°C to 125°C
36
25°C
36
– 40°C to 125°C
34
53
dB
46
25°C
370
CO = 10 µF
25°C
290
CO = 100 µF
25°C
µV/√Hz
µVrms
168
0.95 ×
VO(nom)
25°C
50
25°C
0.2
– 40°C to 125°C
V
285
25°C
– 40°C to 125°C
UNIT
30
25°C
CO = 4.7 µF
VI = 4
4.12
12 V
MAX
4.85
4.75
2
VO voltage decreasing from above VPG
IPG = 1.2
1 2 mA,
mA
25°C
– 40°C to 125°C
TYP
25°C
PG hysteresis voltage
PG output low voltage
TPS7248Q
MIN
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7250Q electrical characteristics, IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
VI = 6 V,
6 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 10 mA
mA,
VI = 4
4.88
88 V
IO = 100 mA,
mA
VI = 4
4.88
88 V
mA
IO = 250 mA,
88 V
VI = 4
4.88
Pass element series resistance
Pass-element
(
(4.88
V – VO))/IO,
IO = 250 mA
VI = 4.88 V,,
Input regulation
VI = 6 V to 10 V,
V
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
6 V ≤ VI ≤ 10 V
Dropout voltage
6 V ≤ VI ≤ 10 V
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR† = 1 Ω
PG trip-threshold voltage
25°C
– 40°C to 125°C
25°C
5.1
8
76
– 40°C to 125°C
V
12
85
136
25°C
190
206
0.76
0.825
– 40°C to 125°C
mV
312
25°C
1.25
25°C
28
– 40°C to 125°C
35
25°C
46
– 40°C to 125°C
59
– 40°C to 125°C
Ω
mV
61
100
25°C
79
mV
150
25°C
41
– 40°C to 125°C
37
25°C
36
– 40°C to 125°C
32
52
dB
46
CO = 4.7 µF
25°C
390
CO = 10 µF
25°C
300
CO = 100 µF
25°C
175
– 40°C to 125°C
0.95 ×
VO(nom)
25°C
50
25°C
0.19
– 40°C to 125°C
UNIT
30
25°C
2
25 V
VI = 4
4.25
MAX
5
4.9
25°C
VO voltage decreasing from above VPG
1 2 mA,
mA
IPG = 1.2
TYP
– 40°C to 125°C
PG hysteresis voltage
PG output low voltage
TPS7250Q
MIN
– 40°C to 125°C
Output regulation
IO = 50 µA to 250 mA
mA,
TJ
µV/√Hz
µVrms
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Ground current (active mode)
EN ≤ 0.5 V,
0 mA ≤ IO ≤ 250 mA
VI = VO + 1 V,
Output current limit threshold
VO = 0 V,
VI = 10 V
MIN
TPS72xxY
TYP
MAX
UNIT
µA
180
0.6
A
165
°C
EN hysteresis voltage
50
mV
Minimum VI for active pass element
1.9
V
1.1
V
Thermal shutdown junction temperature
Minimum VI for valid PG
IPG = 300 µA
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, FB shorted to
OUT at device leads (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Reference voltage (measured at FB with OUT
connected to FB)
TPS7201Y
MIN
TYP
VI = 3.5 V,
IO = 10 mA
VI = 2.4 V,§
VI = 2.4 V,§
50 µA ≤ IO ≤ 100 mA
2.1
100 mA ≤ IO ≤ 200 mA
2.9
VI = 2.9 V,
VI = 3.9 V,
50 µA ≤ IO ≤ 250 mA
1.6
50 µA ≤ IO ≤ 250 mA
1
VI = 5.9 V,
3 V ≤ VI ≤ 10 V,
See Note 2
50 µA ≤ IO ≤ 250 mA
0.8
IO = 5 mA to 250 mA,
15
3 V ≤ VI ≤ 10 V,
See Note 2
IO = 50 µA to 250 mA,
17
Ripple rejection
VI = 3
3.5
5V
V,
f = 120 Hz
IO = 50 µA
IO = 250 mA,
See Note 2
Output noise spectral density
VI = 3.5 V,
f = 120 Hz
Pass-element series resistance (see Note 3)
Output regulation
Output noise voltage
VI = 3.5 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
1.188
MAX
UNIT
V
Ω
mV
60
50
2
CO = 4.7 µF
235
CO = 10 µF
190
CO = 100 µF
125
dB
µV/√Hz
µVrms
PG hysteresis voltage¶
VI = 3.5 V,
Measured at VFB
12
mV
PG output low voltage¶
VI = 2.13 V,
IPG = 400 µA
0.1
V
FB input current
0.1
nA
VI = 3.5 V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§ This voltage is not recommended.
¶ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 2 When VI < 2.9 V and IO > 100 mA simultaneously, pass element rDS(on) increases (see Figure 10) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3 To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, FB shorted to
OUT at device leads (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
TPS7225Y
MIN
TYP
MAX
UNIT
Output voltage
VI = 3.5 V,
IO = 10 mA
2.5
V
Dropout voltage
VI = 2.97 V,
IO = 250 mA
560
mV
Pass-element series resistance
(2.97 V – VO)/IO,
IO = 250 mA
VI = 2.97 V,
2.24
Ω
VI = 3.5 V to 10 V,
3.5 V ≤ VI ≤ 10 V
50 µA ≤ IO ≤ 250 mA
9
28
3.5 V ≤ VI ≤ 10 V
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Ripple rejection
VI = 3.5 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
58
Output noise spectral density
VI = 3.5 V,
f = 120 Hz
Output noise voltage
VI = 3.5 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
Input regulation
Output regulation
PG hysteresis voltage
24
46
2
CO = 4.7 µF
248
CO = 10 µF
200
CO = 100 µF
130
50
VI = 3.5 V
mV
mV
dB
µV/√Hz
µVrms
mV
VI = 2.13 V
IPG = 1.2 mA
0.3
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TPS7230Y
MIN
TYP
VI = 4 V,
VI = 2.97 V,
IO = 10 mA
IO = 100 mA
VI = 2.97 V,
(2.97 V – VO)/IO,
IO = 250 mA
IO = 250 mA
VI = 2.97 V,
VI = 4 V to 10 V,
4 V ≤ VI ≤ 10 V
50 µA ≤ IO ≤ 250 mA
9
34
4 V ≤ VI ≤ 10 V
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Ripple rejection
VI = 4 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
56
Output noise spectral density
VI = 4 V,
f = 120 Hz
Output noise voltage
VI = 4 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
Dropout voltage
Pass-element series resistance
Input regulation
Output regulation
PG hysteresis voltage
MAX
3
V
145
mV
390
Ω
1.56
mV
mV
41
dB
45
µV/√Hz
2
CO = 4.7 µF
256
CO = 10 µF
206
CO = 100 µF
132
µVrms
50
VI = 4 V
UNIT
mV
VI = 2.55 V
IPG = 1.2 mA
0.25
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TEST CONDITIONS‡
PARAMETER
TPS7233Y
MIN
TYP
Output voltage
VI = 4.3 V,
VI = 3.23 V,
IO = 10 mA
IO = 10 mA
3.3
Dropout voltage
VI = 3.23 V,
VI = 3.23 V,
IO = 100 mA
IO = 250 mA
140
(3.23 V – VO)/IO,
IO = 250 mA
VI = 3.23 V,
VI = 4.3 V to 10 V,
4.3 V ≤ VI ≤ 10 V,
50 µA ≤ IO ≤ 250 mA
8
32
4.3 V ≤ VI ≤ 10 V,
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Ripple rejection
VI = 4.3 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
52
Output noise spectral density
VI = 4.3 V,
f = 120 Hz
Pass-element series resistance
Input regulation
Output regulation
Output noise voltage
PG hysteresis voltage
VI = 4.3 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
UNIT
V
14
mV
360
1.5
41
44
2
CO = 4.7 µF
265
CO = 10 µF
212
CO = 100 µF
135
32
VI = 4.3 V
MAX
Ω
mV
mV
dB
µV/√Hz
µVrms
mV
VI = 2.8 V,
IPG = 1.2 mA
0.22
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted) (continued)
TEST CONDITIONS‡
PARAMETER
Output voltage
TPS7248Y
MIN
TYP
VI = 5.85 V,
VI = 4.75 V,
IO = 10 mA
IO = 10 mA
VI = 4.75 V,
VI = 4.75 V,
IO = 100 mA
IO = 250 mA
216
(4.75 V – VO)/IO,
IO = 250 mA
VI = 4.75 V,
0.8
5.85 V ≤ VI ≤ 10 V
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
43
5.85 V ≤ VI ≤ 10 V
Ripple rejection
VI = 5.85 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
53
Output noise spectral density
VI = 5.85 V,
f = 120 Hz
Output noise voltage
VI = 5.85 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
Dropout voltage
Pass-element series resistance
Output regulation
PG hysteresis voltage
MAX
4.85
UNIT
V
10
mV
90
Ω
mV
55
dB
46
µV/√Hz
2
CO = 4.7 µF
370
CO = 10 µF
290
CO = 100 µF
168
µVrms
50
VI = 5.85 V
mV
VI = 4.12 V
IPG = 1.2 mA
0.2
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TEST CONDITIONS‡
PARAMETER
TPS7250Y
MIN
TYP
Output voltage
VI = 6 V,
VI = 4.88 V
IO = 10 mA
IO = 10 mA
5
Dropout voltage
VI = 4.88 V
VI = 4.88 V,
IO = 100 mA
IO = 250 mA
76
190
(4.88 V – VO)/IO,
IO = 250 mA
VI = 4.88 V,
0.76
VI = 6 V to 10 V,
6 V ≤ VI ≤ 10 V,
50 µA ≤ IO ≤ 250 mA
Pass-element series resistance
Input regulation
6 V ≤ VI ≤ 10 V,
Ripple rejection
VI = 6 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
52
Output noise spectral density
VI = 6 V,
f = 120 Hz
PG hysteresis voltage
VI = 6 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
59
46
2
CO = 4.7 µF
390
CO = 10 µF
300
CO = 100 µF
175
50
VI = 6 V
V
mV
Ω
mV
46
Output noise voltage
UNIT
8
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Output regulation
MAX
mV
dB
µV/√Hz
µVrms
mV
VI = 4.25 V,
IPG = 1.2 mA
0.19
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
5
vs Input voltage
6
IQ
Quiescent current
∆IQ†
Change in quiescent current
vs Free-air temperature
7
VDO
∆VDO
Dropout voltage
vs Output current
8
Change in dropout voltage
vs Free-air temperature
9
VDO
rDS(on)
Dropout voltage (TPS7201 only)
vs Output current
10
Pass-element series resistance
vs Input voltage
11
∆VO
VO
Change in output voltage
vs Free-air temperature
12
Output voltage
vs Input voltage
13
Line regulation
(TPS7201, TPS7233, TPS7248, TPS7250)
14
Load regulation
(TPS7225, TPS7233, TPS7248, TPS7250)
15
VO(PG)
Power-good (PG) voltage
vs Output voltage
16
rDS(on)PG
Power-good (PG) on-resistance
vs Input voltage
17
VI
Minimum input voltage for valid PG
vs Free-air temperature
18
Output voltage response from enable (EN)
19
Load transient response (TPS7201/ TPS7233)
20
Load transient response (TPS7248/ TPS7250)
21
Line transient response (TPS7201)
22
Line transient response (TPS7233)
23
Line transient response (TPS7248/ TPS7250)
24
Ripple rejection
vs Frequency
25
Output Spectral Noise Density
vs Frequency
26
vs Output current (CO = 4.7 µF)
27
vs Added ceramic capacitance (CO = 4.7 µF)
28
vs Output current (CO = 10 µF)
29
vs Added ceramic capacitance (CO = 10 µF)
30
Compensation series resistance (CSR)
† This symbol is not currently listed within EIA or JEDEC standards for semiconductor symbology.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
OUTPUT CURRENT
QUIESCENT CURRENT
vs
INPUT VOLTAGE
230
250
TA = 25°C
TPS7233
200
210
200
TPS7233 VI = 10 V
190
TPS7250 VI = 10 V
180
TPS7248 VI = 5.85 V
I Q – Quiescent Current – µ A
I Q – Quiescent Current – µ A
220
170
TPS7250 VI = 6.0 V
160
150
150
TPS7201 With
VO Programmed to 2.5 V
100
TPS7250
50
TPS7233 VI = 4.3 V
0
50
100
150
200
IO – Output Current – mA
0
250
0
1
2
Figure 5
9
10
600
IO = 10 mA
VI = VO + 1 V
TA = 25°C
500
30
VDO – Dropout Voltage – mV
∆I Q – Change in Quiescent Current – µ A
8
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
50
40
3
4
5
6
7
VI – Input Voltage – V
Figure 6
CHANGE IN QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
20
10
0
– 10
– 20
TPS7225
400
TPS7230
300
TPS7233
TPS7248
200
100
TPS7250
– 30
– 40
– 40 – 20
0
20
40 60
80 100 120 140
TA – Free-Air Temperature – °C
0
0
50
100
150
200
IO – Output Current – mA
Figure 8
Figure 7
18
TPS7248
TA 25°C
IO = 250 mA
TPS7248 VI = 10 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
250
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TPS7201
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
1.6
0.04
VI = 2.4 V†
1.4
TPS7230
0.03
VDO – Dropout Voltage – V
TPS7233
0.02
0.01
TPS7248/TPS7250
0
– 0.01
– 0.02
1.2
VI = 2.9 V
1
VI = 2.6 V†
VI = 3.2 V
VI = 3.9 V
0.8
VI = 5.9 V
0.6
VI = 9.65 V
0.4
0.2
– 0.03
– 0.04
– 40 – 20
0
0
20
40
60 80 100 120 140
TA – Free-Air Temperature – °C
0
50
100
150
200
IO – Output Current – mA
250
† This voltage is not recommended.
Figure 10
Figure 9
CHANGE IN OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
PASS ELEMENT SERIES RESISTANCE
vs
INPUT VOLTAGE
15
6
TA = 25°C
VFB = 1.12 V
∆VO – Change in Output Voltage – mV
r DS(on) – Pass Element Series Resistance – Ω
∆VDO – Change in Dropout Voltage – V
0.05
5
4
IO = 250 mA
3
2
1
IO = 100 mA
0
2
3
4
5
6
7
8
9
10
IO = 10 mA
VI = VO + 1 V
10
5
0
–5
– 10
– 15
– 20
– 25
– 40 – 20
VI – Input Voltage – V
0
20 40
60
80 100 120 140
TA – Free-Air Temperature – °C
Figure 12
Figure 11
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
LINE REGULATION
5.5
25
5
TPS7250
TPS7248
4.5
∆VO – Output Voltage – V
∆VO – Change in Output Voltage – mV
TA = 25°C
IO = 250 mA
4
3.5
TPS7233
3
2.5
2
TPS7201 With
VO Programmed to 2.5 V
1.5
1
15
TPS7201 With
VO Programmed to 2.5 V
10
5
TPS7233
0
–5
TPS7248
– 10
– 15
TPS7250
– 20
0.5
0
TA = 25°C
IO = 250 mA
20
0
1
2
3
4
5
6
7
8
9
– 25
10
4
4.5
VI – Input Voltage – V
6 6.5 7 7.5 8 8.5 9
VI – Input Voltage – V
Figure 13
Figure 14
6
TA = 25°C
PG Pulled Up to VI With 5 kΩ Resistor
TA = 25°C
VO(PG) – Power-Good (PG) Voltage – V
40
∆VO – Change in Output Voltage – mV
9.5 10
POWER-GOOD (PG) VOLTAGE
vs
OUTPUT VOLTAGE†
LOAD REGULATION
50
30
20
10
TPS7233
0
– 10
TPS7225
– 20
TPS7250
– 50
0
50
100
150
200
IO – Output Current – mA
VI
ÁÁ
ÁÁ
TPS7248
– 30
– 40
250
GND
0
92
93
94
95
Figure 16
POST OFFICE BOX 655303
96
VO – Output Voltage – %
† VO as a percent of VOnom.
Figure 15
20
5 5.5
• DALLAS, TEXAS 75265
97
98
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
MINIMUM INPUT VOLTAGE FOR VALID PG
vs
FREE-AIR TEMPERATURE
POWER-GOOD (PG) ON-RESISTANCE
vs
INPUT VOLTAGE
1.3
VI – Minimum Input Voltage for Valid PG
TA = 25°C
10
1
1.125
1.12
1.115
1.11
1.105
ÁÁ
1.095
– 40 – 20
0
1.5
2
2.5
3
3.5
4
4.5
5
0
20
40
60
80
100 120 140
TA – Free-Air Temperature – °C
VI – Input Voltage – V
Figure 18
Figure 17
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
10
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
5
0
VO nom
V I(EN)– EN Voltage – V
1
1.1
VO – Output Voltage – V
(Values Vary With
Selection of Device)
rDS(on) – Power-Good (PG) On-Resistance – kΩ
100
0
50
100
150
t – Time – µs
Figure 19
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
200
100
0
TA = 25°C
VI = 6 V
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
– 200
105
55
5
0
100
200
300
400
500
I O – Output Current – mA
∆VO – Change in Output Voltage – mV
TPS7201 (WITH VO PROGRAMMED TO 2.5 V), TPS7233
t – Time – µs
Figure 20
200
100
0
TA = 25°C
VI = 6 V
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
– 200
105
55
5
0
100
200
300
400
t – Time – µs
Figure 21
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
500
I O – Output Current – mA
∆VO – Change in Output Voltage – mV
TPS7248/TPS7250
LOAD TRANSIENT RESPONSE
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7201 WITH VO PROGRAMMED TO 2.5 V
LINE TRANSIENT RESPONSE
100
50
0
– 50
– 100
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
6.5
6.25
6
0
100
200
300
VI – Input Voltage – V
∆VO – Change in Output Voltage – mV
TYPICAL CHARACTERISTICS
400
t – Time – µs
Figure 22
200
100
0
– 50
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
6.5
6.25
6
0
100
200
300
400
5.75
500
V I – Input Voltage – V
∆VO – Change in Output Voltage – mV
TPS7233
LINE TRANSIENT RESPONSE
t – Time – µs
Figure 23
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
100
50
0
– 50
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
6.5
6.25
6
0
100
200
300
400
500
V I – Input Voltage – V
∆VO – Change in Output Voltage – mV
TPS7248/TPS7250
LINE TRANSIENT RESPONSE
t – Time – µs
Figure 24
RIPPLE REJECTION
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
60
TPS7233
TPS7248/
TPS7250
Output Spectral Noise Density – µV/ Hz
Ripple Rejection – dB
50
40
10
TA = 25°C
No Input
Capacitance Added
VI = VO + 1 V
IO = 100 mA
CO = 4.7 µF (CSR = 1 Ω)
TPS7201 With
VO Programmed
to 2.5 V
30
20
10
0
10
100
1K
10 K
100 K
1M
10 M
TA = 25°C
No Input Capacitance Added
VI = VO + 1 V
CO = 4.7 µF (CSR = 1 Ω)
1
CO = 10 µF (CSR = 1 Ω)
0.1
CO = 100 µF (CSR = 1 Ω)
0.01
10
f – Frequency – Hz
Figure 25
24
100
1k
10 k
f – Frequency – Hz
Figure 26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100 k
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
100
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
Region of Instability
10
1
TA = 25°C
VI = VO + 1 V
CO = 4.7 µF
No Added Ceramic Capacitance
No Input Capacitance Added
0.1
Region of Instability
0.01
0
50
100
TA = 25°C
VI = VO + 1 V
IO = 250 mA
CO = 4.7 µF
No Input Capacitor Added
Region of
Instability
10
1
0.1
Region of Instability
0.01
150
200
0
250
0.1
0.2 0.3 0.4 0.5
Figure 27
0.9
1
Figure 28
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
100
100
Region of Instability
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
0.6 0.7 0.8
Added Ceramic Capacitance – µF
IO – Output Current – mA
10
TA = 25°C
VI = VO + 1 V
CO = 10 µF
No Added Ceramic Capacitance
No Input Capacitor Added
1
0.1
Region of Instability
0.01
Region of
Instability
10
TA = 25°C
VI = VO + 1 V
IO = 250 mA
CO = 10 µF
No Input Capacitor Added
1
0.1
Region of Instability
0.01
0
50
100
150
200
250
IO – Output Current – mA
0
0.1
0.2 0.3 0.4 0.5
0.6 0.7 0.8
0.9
1
Added Ceramic Capacitance – µF
Figure 29
Figure 30
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
The design of the TPS72xx family of low-dropout (LDO) regulators is based on the higher-current TPS71xx
family. These new families of regulators have been optimized for use in battery-operated equipment and feature
extremely low dropout voltages, low supply currents that remain constant over the full-output-current range of
the device, and an enable input to reduce supply currents to less than 0.5 µA when the regulator is turned off.
device operation
The TPS72xx uses a PMOS pass element to dramatically reduce both dropout voltage and supply current over
more conventional PNP-pass-element LDO designs. The PMOS transistor is a voltage-controlled device that,
unlike a PNP transistor, does not require increased drive current as output current increases. Supply current
in the TPS72xx is essentially constant from no-load to maximum.
Current limiting and thermal protection prevent damage by excessive output current and/or power dissipation.
The device switches into a constant-current mode at approximately 1 A; further load increases reduce the output
voltage instead of increasing the output current. The thermal protection shuts the regulator off if the junction
temperature rises above 165°C. Recovery is automatic when the junction temperature drops approximately 5°C
below the high temperature trip point. The PMOS pass element includes a back diode that safely conducts
reverse current when the input voltage level drops below the output voltage level.
A logic high on the enable input, EN, shuts off the output and reduces the supply current to less than 0.5 µA.
EN should be grounded in applications where the shutdown feature is not used.
Power good (PG) is an open-drain output signal used to indicate output-voltage status. A comparator circuit
continuously monitors the output voltage. When the output drops to approximately 95% of its nominal regulated
value, the comparator turns on and pulls PG low.
Transient loads or line pulses can also cause activation of PG if proper care is not taken in selecting the input
and output capacitors. Load transients that are faster than 5 µs can cause a signal on PG if high-ESR output
capacitors (greater than approximately 7 Ω) are used. A 1-µs transient causes a PG signal when using an output
capacitor with greater than 3.5 Ω of ESR. It is interesting to note that the output-voltage spike during the transient
can drop well below the reset threshold and still not trip if the transient duration is short. A 1-µs transient must
drop at least 500 mV below the threshold before tripping the PG circuit. A 2-µs transient trips PG at just 400 mV
below the threshold. Lower-ESR output capacitors help by reducing the drop in output voltage during a transient
and should be used when fast transients are expected.
A typical application circuit is shown in Figure 31.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
TPS72xx
(see Note A)
5
VI
IN
PG
6
PG
1
250 kΩ
SENSE
IN
OUT
C1
0.1 µF
2
4
OUT
EN
7
VO
8
+
GND
3
10 µF
CSR = 1 Ω
NOTE A: TPS7225, TPS7230, TPS7233, TPS7248, TPS7250
(fixed-voltage options).
Figure 31. Typical Application Circuit
external capacitor requirements
Although not required, a 0.047-µF to 0.1-µF ceramic bypass input capacitor, connected between IN and GND
and located close to the TPS72xx, is recommended to improve transient response and noise rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
An output capacitor is required to stabilize the internal feedback loop. For most applications, a 10-µF to 15-µF
solid-tantalum capacitor with a 0.5-Ω resistor (see capacitor selection table) in series is sufficient. The maximum
capacitor ESR should be limited to 1.3 Ω to allow for ESR doubling at cold temperatures. Figure 32 shows the
transient response of a 5-mA to 85-mA load using a 10-µF output capacitor with a total ESR of 1.7 Ω.
A 4.7-µF solid-tantalum capacitor in series with a 1-Ω resistor may also be used (see Figures 27 and 28)
provided the ESR of the capacitor does not exceed 1 Ω at room temperature and 2 Ω over the full operating
temperature range.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
VI = VO + 1 V
VO
1→
IO = 85 mA
IO = 5 mA
2→
Ch1
Ch 2
50 mV
50 mA
100 µs/div
Figure 32. Load Transient Response (CSR total = 1.7 Ω), TPS7248Q
A partial listing of surface-mount capacitors usable with the TPS72xx family is provided below. This information
(along with the stability graphs, Figures 27 through 30) is included to assist the designer in selecting suitable
capacitors.
CAPACITOR SELECTION
SIZE (H × L × W)†
MFR.
VALUE
MAX ESR†
592D156X0020R2T
Sprague
15 µF, 20 V
1.1
1.2 × 7.2 × 6
595D156X0025C2T
Sprague
15 µF, 25 V
1
2.5 × 7.1 × 3.2
595D106X0025C2T
Sprague
10 µF, 25 V
1.2
2.5 × 7.1 × 3.2
695D106X0035G2T
Sprague
10 µF, 35 V
1.3
2.5 × 7.6 × 2.5
PART NO.
† Size is in mm. ESR is maximum resistance in ohms at 100 kHz and TA = 25°C. Listings are sorted by height.
sense-pin connection
SENSE must be connected to OUT for proper operation of the regulator. Normally this connection should be
as short as possible; however, remote sense may be implemented in critical applications when proper care of
the circuit path is exercised. SENSE internally connects to a high-impedance wide-bandwidth amplifier through
a resistor-divider network, and any noise pickup on the PCB trace will feed through to the regulator output.
SENSE must be routed to minimize noise pickup. Filtering SENSE using an RC network is not recommended
because of the possibility of inducing regulator instability.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
output voltage programming
The output voltage of the TPS7201 adjustable regulator is programmed using an external resistor divider as
shown in Figure 33. The output voltage is calculated using:
V
O
ǒ Ǔ
+ Vref @ 1 ) R1
R2
(1)
Where:
Vref = 1.188 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 169 kΩ to set the divider current at 7 µA and then calculate R1 using:
R1
+
ǒ Ǔ
V
V
O
ref
* 1 @ R2
(2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
VOLTAGE
(V)
TPS7201
5
DIVIDER RESISTANCE
(kΩ)†
R1
R2
2.5
191
169
3.3
309
169
3.6
348
169
4
402
169
5
549
169
6.4
750
169
>2.7 V
VI
0.1 µF
6
IN
PG
IN
OUT
4
EN
OUT
2
8
Power-Good Indicator
250 kΩ
7
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