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TPS732
SBVS037P – AUGUST 2003 – REVISED DECEMBER 2015
TPS732xx Capacitor-Free, NMOS, 250-mA Low-Dropout Regulator With Reverse Current
Protection
1 Features
3 Description
•
The TPS732 family of low-dropout (LDO) voltage
regulators uses an NMOS pass element in a voltagefollower configuration. This topology is stable using
output capacitors with low equivalent series
resistance (ESR), and even allows operation without
a capacitor. The device also provides high reverse
blockage (low reverse current) and ground pin current
that is nearly constant over all values of output
current.
1
•
•
•
•
•
•
•
•
•
•
Stable with No Output Capacitor or Any Value or
Type of Capacitor
Input Voltage Range: 1.7 V to 5.5 V
Ultralow Dropout Voltage: 40 mV Typical at
250 mA
Excellent Load Transient Response—With or
Without Optional Output Capacitor
NMOS Topology Provides Low Reverse Leakage
Current
Low Noise: 30 μVRMS Typical (10 kHz to 100 kHz)
0.5% Initial Accuracy
1% Overall Accuracy (Line, Load, and
Temperature)
Less Than 1-μA Maximum IQ in Shutdown Mode
Thermal Shutdown and Specified Min and Max
Current Limit Protection
Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.2 V to 5 V
– Adjustable Outputs from 1.2 V to 5.5 V
– Custom Outputs Available
The TPS732 uses an advanced BiCMOS process to
yield high precision while delivering very low dropout
voltages and low ground pin current. Current
consumption, when not enabled, is less than 1 μA
and ideal for portable applications. The extremely low
output noise (30 μVRMS with 0.1-μF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
Device Information(1)
PART NUMBER
TPS732xx
BODY SIZE (NOM)
2.90 mm × 1.60 mm
SOT-223 (6)
6.50 mm × 3.50 mm
SON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
PACKAGE
SOT-23 (5)
Portable and Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point-of-Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
Typical Application Circuit for Fixed-Voltage Versions
Optional
VIN
Optional
IN
VOUT
OUT
TPS732xx
EN
GND
NR
ON
OFF
Optional
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS732
SBVS037P – AUGUST 2003 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 19
10.3 Thermal Considerations ........................................ 20
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (August 2010) to Revision P
Page
•
Changed Features bullet about NMOS topology; deleted "new"............................................................................................ 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed first paragraph of Description section; deleted description of NMOS topology as "new" ....................................... 1
•
Changed Pin Configuration and Functions section; updated table format ............................................................................ 3
•
Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement ................... 4
•
Changed Thermal Information table; updated thermal resistance values for all packages .................................................. 5
Changes from Revision N (August, 2009) to Revision O
•
Page
Replaced the Dissipation Ratings table with the Thermal Information table .......................................................................... 6
Changes from Revision M (May, 2008) to Revision N
Page
•
Changed Figure 10 ................................................................................................................................................................ 7
•
Added paragraph about recommended start-up sequence to Internal Current Limit section .............................................. 14
•
Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section .................................. 14
2
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SBVS037P – AUGUST 2003 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
DCQ Package
6-Pin SOT-223
Top View
5
OUT
4
NR/FB
TAB IS GND
6
1
IN
2
3
4
5
GND
EN
OUT
NR/FB
DRB Package
8-Pin SON With Exposed Thermal Pad
Top View
OUT
1
8
IN
N/C
2
7
N/C
NR/FB
3
6
N/C
GND
4
5
EN
Pin Functions
PIN
NAME
NO.
SOT-23
SOT-223
I/O
DESCRIPTION
SON
IN
1
1
8
I
GND
2
3, 6
4, Pad
—
Input supply
EN
3
5
5
I
NR
4
4
3
—
FB
4
4
3
I
Adjustable voltage version only—this pin is the input to the control loop error
amplifier, and is used to set the output voltage of the device.
OUT
5
2
1
O
Output of the regulator. There are no output capacitor requirements for stability.
Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts
the regulator into shutdown mode. Refer to the Shutdown section under Feature
Description for more details. EN can be connected to IN if not used.
Fixed voltage versions only—connecting an external capacitor to this pin bypasses
noise generated by the internal bandgap, reducing output noise to very low levels.
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SBVS037P – AUGUST 2003 – REVISED DECEMBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
Voltage
Peak output current
(1)
MIN
MAX
VIN
–0.3
6
VEN
–0.3
6
VOUT
–0.3
5.5
VNR, VFB
–0.3
6
IOUT
Indefinite
Continuous total power dissipation
(1)
V
Internally limited
Output short-circuit duration
Temperature
UNIT
See Power Dissipation
Junction range ,TJ
–55
150
Storage range, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
VIN
Input supply voltage range
IOUT
Output current
TJ
Operating junction temperature
4
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NOM
MAX
UNIT
1.7
5.5
V
0
250
mA
–40
125
°C
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6.4 Thermal Information
TPS732 (3)
THERMAL METRIC (1) (2)
DRB [SON]
DCQ
[SOT223]
DBV [SOT23]
8 PINS
6 PINS
5 PINS
205.9
RθJA
Junction-to-ambient thermal resistance
58.3
53.1
RθJC(top)
Junction-to-case (top) thermal resistance
93.8
35.2
119
RθJB
Junction-to-board thermal resistance
72.8
7.8
35.4
ψJT
Junction-to-top characterization parameter
2.7
2.9
12.7
ψJB
Junction-to-board characterization parameter
25
7.7
34.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5
N/A
N/A
(1)
(2)
(3)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3 × 2 thermal via array.
. iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch × 3-inch copper area.
To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
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6.5 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and COUT =
0.1 μF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1)
VFB
Internal reference (TPS73201)
MIN
TJ = 25°C
1.198
Accuracy (1) (3)
ΔVOUT(ΔVIN)
Line regulation
Nominal
TJ = 25°C
VIN, IOUT, and T
VOUT + 0.5 V ≤ VIN ≤ 5.5 V;
10 mA ≤ IOUT ≤ 250 mA
(1)
UNIT
5.5
V
1.21
V
5.5 – VDO
V
–0.5%
0.5%
–1%
1.2
MAX
VFB
Output voltage range (TPS73201) (2)
VOUT
TYP
1.7
±0.5%
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
1%
0.01
%/V
1 mA ≤ IOUT ≤ 250 mA
0.002
%/mA
10 mA ≤ IOUT ≤ 250 mA
0.0005
%/mA
ΔVOUT(ΔIOUT)
Load regulation
VDO
Dropout voltage (4)
(VIN = VOUT (nom) – 0.1 V)
IOUT = 250 mA
ZO(do)
Output impedance in dropout
1.7 V ≤ VIN ≤ VOUT + VDO
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
ISC
Short-circuit current
VOUT = 0 V
300
IREV
Reverse leakage current (5) (–IIN)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
10
IGND
GND pin current
IOUT = 10 mA (IQ)
400
550
IOUT = 250 mA
650
950
ISHDN
Shutdown current (IGND)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5,
–40°C ≤ TJ ≤ 100°C
0.02
1
µA
IFB
FB pin current (TPS73201)
0.1
0.3
μA
40
250
425
58
PSRR
Power-supply rejection ratio
(ripple rejection)
f = 10 kHz, IOUT = 250 mA
37
Vn
Output noise voltage
BW = 10Hz – 100kHz
COUT = 10 μF, No CNR
27 × VOUT
COUT = 10 μF, CNR = 0.01 μF
8.5 × VOUT
VEN(high)
EN pin high (enabled)
VEN(low)
EN pin low (shutdown)
IEN(high)
EN pin current (enabled)
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
1.7
600
0
0.02
Shutdown
Temp increasing
160
Reset
Temp decreasing
140
–40
mA
mA
μA
μA
dB
μVRMS
VIN
VEN = 5.5 V
mV
Ω
0.25
f = 100 Hz, IOUT = 250 mA
(1)
(2)
(3)
(4)
(5)
150
V
0.5
V
0.1
μA
°C
125
°C
Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
TPS73201 is tested at VOUT = 2.5 V.
Tolerance of external resistors not included in this specification.
VDO is not measured for fixed output versions with VOUT(nom) < 1.8 V because minimum VIN = 1.7 V.
Fixed-voltage versions only; refer to Application Information section for more information.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tSTR
6
Start-up time
TEST CONDITIONS
VOUT = 3 V, RL = 30 Ω
COUT = 1 μF, CNR = 0.01 μF
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MIN
TYP
600
MAX
UNIT
μs
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6.7 Typical Characteristics
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
0.20
0.5
Referred to IOUT = 10 mA
0.4
0.2
0.1
0
-0.1
-0.2
Change in VOUT (%)
-40 °C
+25°C
+125 °C
0.3
Change in VOUT (%)
Referred to VIN = VOUT + 0.5 V at IOUT = 10 mA
0.15
0.10
+25 °C
+125 °C
0.05
0
-0.05
-40 °C
-0.10
-0.3
-0.15
-0.4
-0.20
-0.5
0
50
100
150
200
0
250
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN - VOUT (V)
IOUT (mA)
Figure 1. Load Regulation
Figure 2. Line Regulation
100
100
TPS73225DBV
80
80
TPS73225DBV
IOUT = 250 mA
VDO (mV)
VDO (mV)
+125 °C
60
+25 °C
40
60
40
20
20
-40 °C
0
-50
0
0
50
100
150
200
250
0
25
50
75
100
Temperature (°C)
Figure 3. Dropout Voltage vs Output Current
Figure 4. Dropout Voltage vs Temperature
30
18
IOUT = 10 mA
16
25
125
I OUT = 10 mA
All Voltage Versions
14
Percent of Units (%)
Percent of Units (%)
-25
IOUT (mA)
20
15
10
12
10
8
6
4
5
2
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/ °C)
Figure 5. Output Voltage Accuracy Histogram
Figure 6. Output Voltage Drift Histogram
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
1000
800
900
700
800
600
700
600
I GND (mA)
I GND (mA)
IOUT = 250 mA
500
400
300
100
50
100
150
200
300
VIN = 5.5 V
VIN = 4 V
VIN = 2 V
100
0
0
400
200
VIN = 5.5 V
VIN = 4 V
VIN = 2 V
200
500
0
-50
250
-25
0
IOUT (mA)
Figure 7. Ground Pin Current vs Output Current
50
75
100
125
Figure 8. Ground Pin Current vs Temperature
500
1
VENABLE = 0.5 V
VIN = VOUT + 0.5 V
450
ICL
400
Output Current (mA)
IGND (mA)
25
Temperature (°C)
0.1
350
300
ISC
250
200
150
100
50
0.01
-50
-25
0
25
50
75
100
TPS73233
0
-0.5
125
0
0.5
600
600
550
550
500
500
Current Limit (mA)
Current Limit (mA)
1.5
2.0
2.5
3.0
3.5
Figure 10. Current Limit vs VOUT (Foldback)
Figure 9. Ground Pin Current in Shutdown vs Temperature
450
400
350
300
450
400
350
300
250
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
250
-50
VIN (V)
-25
0
25
50
75
100
125
Temperature (°C)
Figure 11. Current Limit vs VIN
8
1.0
Output Voltage (V)
Temperature (°C)
Figure 12. Current Limit vs Temperature
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
40
90
IOUT = 100 mA
COUT = Any
70
IOUT = 1 mA
COUT = 1 mF
35
30
IOUT = 1 mA
COUT = 10mF
60
50
IO = 100 mA
CO = 1mF
IOUT = 1 mA
C OUT = Any
40
PSRR (dB)
Ripple Rejection (dB)
80
30
20
VIN = VOUT + 1 V
0
10
100
1k
10k
20
15
Frequency = 10 kHz
COUT = 10 mF
VOUT = 2.5 V
IOUT = 100 mA
10
I OUT = 100 mA
COUT = 10mF
IOUT = Any
COUT = 0mF
10
25
5
0
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VIN - VOUT (V)
Frequency (Hz)
Figure 14. PSRR (Ripple Rejection) vs (VIN – VOUT)
Figure 13. PSRR (Ripple Rejection) vs Frequency
1
1
COUT = 0 mF
0.1
COUT = 10 mF
eN (mV/√Hz)
eN (mV/√Hz)
C OUT = 1 mF
COUT = 1mF
0.1
COUT = 0 mF
COUT = 10mF
IOUT = 150 mA
0.01
0.01
10
100
1k
10k
100k
IOUT = 150 mA
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 15. Noise Spectral Density CNR = 0 µF
Figure 16. Noise Spectral Density CNR = 0.01 µF
60
140
50
120
VOUT = 5.0 V
VOUT = 5.0 V
100
30
VN (RMS)
VN (RMS)
40
VOUT = 3.3 V
20
20
CNR = 0.01 mF
10 Hz < Frequency < 100 kHz
0.1
0
1
10
VOUT = 3.3 V
60
40
VOUT = 1.5 V
10
0
80
VOUT = 1.5 V
COUT = 0 mF
10Hz < Frequency < 100 kHz
1p
10p
100p
1n
COUT (mF)
CNR (F)
Figure 17. RMS Noise Voltage vs COUT
Figure 18. RMS Noise Voltage vs CNR
10n
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Typical Characteristics (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
VIN = 3.8 V
COUT = 0 mF
IOUT = 250 mA
50 mV/tick
VOUT
COUT = 0 mF
50 mV/div
VOUT
COUT = 1 mF
50 mV/tick
VOUT
C OUT = 100mF
COUT = 10 mF
50 mV/tick
VOUT
50 mV/div
VOUT
dVIN
5.5 V
250 mA
= 0.5 V/ms
dt
50 mA/tick
4.5 V
1 V/div
10 mA
VIN
I OUT
10 ms/div
10 ms/div
Figure 19. TPS73233 Load Transient Response
RL = 1 kW
COUT = 0 mF
Figure 20. TPS73233 Line Transient Response
RL = 20W
COUT = 10mF
VOUT
R L = 20W
1 V/div C
OUT = 1mF
R L = 20W
C OUT = 1mF
1 V/div
RL = 1 kW
COUT = 0 mF
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1 V/div
1 V/div
0V
0V
VEN
100 ms/div
100 ms/div
Figure 21. TPS73233 Turnon Response
Figure 22. TPS73233 Turnoff Response
10
6
5
VIN
4
VOUT
IENABLE (nA)
Volts
3
2
1
1
0.1
0
-1
0.01
-50
-2
50 ms/div
-25
0
25
50
75
100
125
Temperature (°C)
.
Figure 23. TPS73233 Power Up and Power Down
10
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Figure 24. IENABLE vs Temperature
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Typical Characteristics (continued)
60
160
55
140
50
120
45
100
I FB (nA)
VN (rms)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 μF, unless otherwise
noted.
40
60
35
30
25
80
VOUT = 2.5 V
COUT = 0 mF
R1 = 39.2 kW
10Hz < Frequency < 100 kHz
20
10p
100p
40
20
1n
10n
0
-50
-25
0
25
50
75
100
CFB (F)
Temperature (°C)
Figure 25. TPS73201 RMS Noise Voltage vs CFB
Figure 26. TPS73201 IFB vs Temperature
CFB = 10 nF
R1 = 39.2 kW
COUT = 0 mF
100 mV/div
COUT = 0 mF
VOUT
100 mV/div
VOUT
100 mV/div
VOUT = 2.5 V
CFB = 10 nF
VOUT
COUT = 10 mF
C OUT = 10 mF
100 mV/div
125
VOUT
4.5 V
3.5 V
250 mA
VIN
10 mA
IOUT
5 ms/div
10 ms/div
Figure 27. TPS73201 Load Transient, Adjustable Version
Figure 28. TPS73201 Line Transient, Adjustable Version
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7 Detailed Description
7.1 Overview
The TPS732 family of low-dropout linear regulators operates down to an input voltage of 1.7 V and supports
output voltages down to 1.2 V while sourcing up to 500 mA of load current. This linear regulator uses an NMOS
pass element with an integrated 4-MHz charge pump to provide a dropout voltage of less than 250 mV at full
load current. This unique architecture also permits stable regulation over a wide range of output capacitors. In
fact, the TPS732 family of devices does not require any output capacitor for stability. The increased insensitivity
to the output capacitor value and type makes this family of linear regulators an ideal choice when powering a
load where the effective capacitance is unknown.
The TPS732 family of devices also features a noise reduction (NR) pin that allows for additional reduction of the
output noise. With a noise reduction capacitor of 0.01 µF connected from the NR pin to GND, the TPS73215
output noise can be as low as 12.75 µVRMS. The low noise output featured by the TPS732 family makes the
device well-suited for powering VCOs or any other noise-sensitive load.
7.2 Functional Block Diagrams
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kW
Bandgap
Error
Amp
Current
Limit
OUT
8kW
GND
R1
R1 + R2 = 80kW
R2
NR
Figure 29. Fixed-Voltage Version
12
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Functional Block Diagrams (continued)
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27kW
Bandgap
Error
Amp
GND
80kW
8kW
R1
R2
1.2V
Short
Open
1.5V
23.2kW
95.3kW
1.8V
28.0kW
56.2kW
2.5V
39.2kW
36.5kW
2.8V
44.2kW
33.2kW
3.0V
46.4kW
30.9kW
3.3V
52.3kW
30.1kW
NOTE: VOUT = (R1 + R2)/R2 ´ 1.204;
R1úú R2 @ 19kW for best
accuracy.
OUT
Current
Limit
VO
R1
FB
R2
Figure 30. Adjustable-Voltage Version
7.3 Feature Description
7.3.1 Output Noise
A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is
dominant noise source within the TPS732 and it generates approximately 32 µVRMS (10 Hz to 100 kHz) at
reference output (NR). The regulator control loop gains up the reference noise with the same gain as
reference voltage, so that the noise voltage of the regulator is approximately given by:
æ R + R2 ö
VOUT
VN = 32mVRMS ´ ç 1
÷÷ = 32mVRMS ´
ç R
VREF
2
è
ø
Because the value of VREF is 1.2 V, this relationship reduces to:
æ mV
ö
VN (mVRMS ) = 27 ç RMS ÷ ´ VOUT (V)
è V ø
the
the
the
(1)
(2)
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the
approximate relationship:
æ mV
ö
VN (mVRMS ) = 8.5 ç RMS ÷ ´ VOUT (V)
è V ø
(3)
for CNR = 10 nF.
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Feature Description (continued)
This noise reduction effect is shown as RMS Noise Voltage vs CNR (Figure 18) in the Typical Characteristics
section.
The TPS73201 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin (FB) reduces output noise and improve load transient
performance.
The TPS732 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above VOUT. The charge pump generates approximately 250 μV of switching noise at
approximately 4 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for
most values of IOUT and COUT.
7.3.2 Internal Current Limit
The TPS732 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps
to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT
drops below 0.5 V. See Figure 10 in the Typical Characteristics section for a graph of IOUT vs VOUT.
Note from Figure 10 that approximately –0.2 V of VOUT results in a current limit of 0 mA. Therefore, if OUT is
forced below –0.2 V before EN goes high, the device may not start up. In applications that work with both a
positive and negative voltage supply, the TPS732 should be enabled first.
7.3.3 Enable Pin and Shutdown
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5 V
(maximum) turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to
shut down the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a
regulated VOUT (see Figure 21).
When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power up. In addition, for VIN ramp times slower than a few milliseconds, the output may
overshoot upon power up.
Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit
section.
7.3.4 Dropout Voltage
The TPS732 uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(on) of the NMOS pass element.
For large step changes in load current, the TPS732 requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the DC
dropout. Values of (VIN – VOUT) above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to DC dropout levels], the TPS732 can take a couple of
hundred microseconds to return to the specified regulation accuracy.
14
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Feature Description (continued)
7.3.5 Reverse Current
The NMOS pass element of the TPS732 provides inherent protection against current flow from the output of the
regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from
the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not
done, the pass element may be left on due to stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Reverse current
is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. Additional current will
flow into the OUT pin due to the 80-kΩ internal resistor divider to ground (see Figure 29 and Figure 30).
For the TPS73201, reverse current may flow when VFB is more than 1 V above VIN.
7.4 Device Functional Modes
7.4.1 Normal Operation With 1.7 V ≤ VIN ≤ 5.5 V and VEN ≥ 1.7 V
The TPS732 family requires an input voltage of at least 1.7 V to function properly and attempt to maintain
regulation.
When operating the device near 5.5 V, take care to suppress any transient spikes that may exceed the 6-V
absolute maximum voltage rating. The device should never operate at a DC voltage greater than 5.5 V.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS732 device belongs to a family of LDO regulators that use an NMOS pass transistor to achieve ultralow-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These
features, combined with low noise and an enable input, make the TPS732 ideal for portable applications. This
regulator family offers a wide selection of fixed-output voltage versions and an adjustable-output version. All
versions have thermal and overcurrent protection, including foldback current limit.
8.2 Typical Applications
Figure 31 shows the basic circuit connections for the fixed-voltage models. Figure 32 gives the connections for
the adjustable-voltage version (TPS73201).
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
IN
VOUT
OUT
TPS732xx
EN
GND
NR
ON
OFF
Optional bypass
capacitor to reduce
output noise.
Figure 31. Typical Application Circuit for Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
IN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
TPS73201
EN
OFF
VOUT
OUT
GND
R1
CFB
FB
ON
R2
VOUT =
(R1 + R2)
R2
x 1.204
Optional capacitor
reduces output noise
and improves
transient response.
Figure 32. Typical Application Circuit for Adjustable-Voltage Version
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Typical Applications (continued)
8.2.1 Design Requirements
For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19 kΩ. This 19 kΩ, in
addition to the internal 8-kΩ resistor, presents the same impedance to the error amp as the 27-kΩ bandgap
reference output. This impedance helps compensate for leakages into the error amp terminals.
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1-μF, low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input
sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the
power source.
The TPS732 does not require an output capacitor for stability and has maximum phase margin with no capacitor.
It is designed to be stable for all available types and values of capacitors. In applications where multiple low ESR
capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50 nΩF. Total
ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In
most applications, the sum of capacitor ESR and trace resistance meets this requirement.
8.2.2.2 Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without an output capacitor for many applications. As with any regulator, the addition of a
capacitor (nominal value 1 μF) from the OUT pin to ground reduces undershoot magnitude but increases its
duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin also improves
the transient response.
The TPS732 does not have active pulldown when the output is overvoltage. This feature allows applications that
connect higher voltage sources, such as alternate power supplies, to the output. This feature also results in an
output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the
output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate
determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by:
(Fixed voltage versions)
VOUT
dV / dt =
COUT ´ 80kW P RLOAD
(4)
(Adjustable voltage version)
VOUT
dV / dt =
COUT ´ 80kW P (R1 + R2 ) P RLOAD
(5)
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Typical Applications (continued)
8.2.3 Application Curves
RL = 1 kW
COUT = 0 mF
VOUT
VIN = 3.8 V
COUT = 0 mF
50 mV/tick
VOUT
R L = 20W
1 V/div C
OUT = 1mF
COUT = 1 mF
50 mV/tick
RL = 20W
COUT = 10mF
2V
VEN
VOUT
COUT = 10 mF
50 mV/tick
VOUT
1 V/div
250 mA
0V
50 mA/tick
10 mA
100 ms/div
I OUT
10 ms/div
Figure 33. TPS73233 Turnon Response
Figure 34. TPS73233 Load Transient Response
60
CFB = 10 nF
R1 = 39.2 kW
55
COUT = 0 mF
100 mV/div
VN (rms)
50
VOUT
45
C OUT = 10 mF
VOUT
100 mV/div
40
35
30
25
VOUT = 2.5 V
COUT = 0 mF
R1 = 39.2 kW
10Hz < Frequency < 100 kHz
20
10p
100p
250 mA
10 mA
1n
10n
IOUT
10 ms/div
CFB (F)
Figure 35. TPS73201 RMS Noise Voltage vs CFB
18
Figure 36. TPS73201 Load Transient, Adjustable Version
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.7 V and 5.5 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
10 Layout
10.1 Layout Guidelines
To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the
PCB with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the
device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the
device.
Solder pad footprint recommendations for the TPS732 are presented in Application Bulletin Solder Pad
Recommendations for Surface-Mount Devices (SBFA015), available from the TI website at www.ti.com.
10.2 Layout Examples
GND PLANE
COUT
VIN
TPS736xxDRB
VOUT
CNR
1
8
N/C
2
7
N/C
NR/FB
3
6
N/C
4
5
EN
CIN
GND PLANE
Figure 37. Fixed Output Voltage Option Layout (DRB Package)
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Layout Examples (continued)
GND PLANE
COUT
VOUT
VIN
TPS73601DRB
CFF
R1
N/C
NR/FB
R2
1
8
2
7
N/C
3
6
N/C
4
5
EN
CIN
GND PLANE
Figure 38. Adjustable Output Voltage Option Layout (DRB Package)
10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worstcase junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS732 has been designed to protect against overload conditions. It was
not intended to replace proper heatsinking. Continuously running the TPS732 into thermal shutdown will degrade
device reliability.
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Thermal Considerations (continued)
10.3.1 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heat-sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT):
PD = (VIN - VOUT ) ´ IOUT
(6)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS732.
The TPS73201DRBEVM-518 evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS732 is available through the product folders under
Simulation Models.
11.1.2 Device Nomenclature
Table 1. Device Nomenclature (1)
PRODUCT
VOUT
TPS732xx yyy z
(1)
XX is the nominal output voltage (for example, 25 = 2.5 V; 01 = Adjustable).
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
• Regulating VOUT Below 1.2 V Using an External Reference, SLVA216
• Solder Pad Recommendations for Surface-Mount Devices, SBFA019
• TPS73x01DRBEVM-518 User's Guide, SBVU014
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
22
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS73201
Click here
Click here
Click here
Click here
Click here
TPS73213
Click here
Click here
Click here
Click here
Click here
TPS73215
Click here
Click here
Click here
Click here
Click here
TPS73216
Click here
Click here
Click here
Click here
Click here
TPS73218
Click here
Click here
Click here
Click here
Click here
TPS73219
Click here
Click here
Click here
Click here
Click here
TPS73225
Click here
Click here
Click here
Click here
Click here
TPS73230
Click here
Click here
Click here
Click here
Click here
TPS73233
Click here
Click here
Click here
Click here
Click here
TPS73250
Click here
Click here
Click here
Click here
Click here
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11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS73201DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJEQ
Samples
TPS73201DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJEQ
Samples
TPS73201DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJEQ
Samples
TPS73201DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PJEQ
Samples
TPS73201DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73201
Samples
TPS73201DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73201
Samples
TPS73201DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PJEQ
Samples
TPS73201DRBRG4
ACTIVE
SON
DRB
8
3000
RoHS & Green
Level-2-260C-1 YEAR
-40 to 125
PJEQ
Samples
TPS73201DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
PJEQ
Samples
TPS73201DRBTG4
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PJEQ
Samples
TPS73213DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
BWD
Samples
TPS73213DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
BWD
TPS73215DBVR
LIFEBUY
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T38
TPS73215DBVT
LIFEBUY
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T38
TPS73215DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73215
Samples
TPS73215DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73215
Samples
TPS73216DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T50
Samples
TPS73216DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T50
Samples
TPS73218DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T37
Samples
TPS73218DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T37
Samples
TPS73218DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T37
Samples
Addendum-Page 1
NIPDAU
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS73218DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73218
Samples
TPS73218DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73218
Samples
TPS73219DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CGE
Samples
TPS73219DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CGE
Samples
TPS73225DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T36
Samples
TPS73225DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T36
Samples
TPS73225DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T36
Samples
TPS73225DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73225
Samples
TPS73225DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73225
Samples
TPS73230DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T39
Samples
TPS73230DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T39
Samples
TPS73230DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73230
Samples
TPS73233DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T40
Samples
TPS73233DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T40
Samples
TPS73233DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73233
Samples
TPS73233DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS73233
Samples
TPS73250DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T41
Samples
TPS73250DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T41
Samples
TPS73250DCQ
LIFEBUY
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73250
TPS73250DCQR
LIFEBUY
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS73250
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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