TPS75003MRHLREP

TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Triple-Supply Power Management IC for Powering FPGAs and DSPs Check for Samples: TPS75003-EP FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • Two 95% Efficient, 3-A Buck Controllers and One 300-mA LDO Tested and Endorsed by Xilinx for Powering the Spartan™-3, Spartan-3E, and Spartan-3L FPGAs Adjustable (1.2 V to 6.5 V for Bucks, 1 V to 6.5 V for LDO) Output Voltages on All Channels Input Voltage Range: 2.2 V to 6.5 V Independent Soft-Start for Each Supply Independent Enable for Each Supply for Flexible Sequencing LDO Stable with 2.2-μF Ceramic Output Capicitor Small, Low-Profile 4,5 mm x 3,5 mm x 0,9 mm QFN Package SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability FPGA/DSP/ASIC Supplies Set-Top Boxes DSL Modems Plasma TV Display Panels DESCRIPTION The TPS75003 is a complete power management solution for FPGA, DSP and other multi-supply applications. The device has been tested with and meets all of the Xilinx Spartan-3, Spartan-3E, and Spartan-3L start-up profile requirements, including monotonic voltage ramp and minimum voltage rail rise time. Independent Enables for each output allow sequencing to minimize demand on the power supply at start-up. Soft-start on each supply limits inrush current during start-up. Two integrated buck controllers allow efficient, cost-effective voltage conversion for both low and high current supplies such as core and I/O. A 300-mA LDO is integrated to provide an auxiliary rail such as VCCAUX on the Xilinx Spartan-3 FPGA. All three supply voltages are offered in user-programmable options for maximum flexibility. The TPS75003 is fully specified from –55°C to +125°C and is offered in a QFN package, yielding a highly compact total solution size with high power dissipation capability. Additional temperature ranges available - contact factory 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Spartan is a trademark of Xilinx, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2011, Texas Instruments Incorporated TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) PRODUCT VOUT TPS75003MRHLREP Buck1: Adjustable Buck2: Adjustable LDO: Adjustable For the most current specifications and package information, see the Package Option Addendum located at the end of this document or see the Texas Instruments website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VINX range (IN1, IN2, IN3) TPS75003 UNIT -0.3 to +7 V VENX range (EN1, EN2, EN3) -0.3 to VINX + 0.3 V VSWX range (SW1, SW2, SW3) -0.3 to VINX + 0.3 V VISX range (IS1, IS2, IS3) -0.3 to VINX + 0.3 V -0.3 to +7 V VSSX range (SS1, SS2, SS3) -0.3 to VINX + 0.3 V VFBX range (FB1, FB2, FB3) -0.3 to +3.3 V Internally limited — VOUT3 range Peak LDO output current (IOUT3) See the Thermal Information Table — Junction temperature range, TJ -55 to +150 °C Storage temperature range Continuous total power dissipation -65 to +150 °C ESD rating, HBM 1 kV ESD rating, CDM 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Figure 1. Wirebond Plot THERMAL INFORMATION THERMAL METRIC (1) TPS75003-EP RHL (20 PINS) θJA Junction-to-ambient thermal resistance 42.6 θJCtop Junction-to-case (top) thermal resistance 51.8 θJB Junction-to-board thermal resistance 39.5 ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 14.2 θJCbot Junction-to-case (bottom) thermal resistance 2.8 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 3 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF, TA = -55°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNIT Supply and Logic VINX Input voltage range (IN1, IN2, IN3) (1) IQ Quiescent current, IQ = IDGND + IAGND IOUT1 = IOUT2 = IOUT3= 0 mA ISHDN Shutdown supply current VEN1 = VEN2 = VEN3 = 0 V VIH1, 2 Enable high, enabled (EN1, EN2) TA = 25°C VIH3 Enable High, enabled (EN3) VILX Enable low, shutdown (EN1, EN2, EN3) IENX Enable pin current (EN1, EN2, EN3) 2.2 V 75 150 μA 0.05 3 μA 1.4 TA = Full Range 1.45 TA = 25°C 1.14 TA = Full Range 6.5 V V 1.2 0 0.01 0.3 V 0.5 μA VINX V Buck Controllers 1 and 2 VOUT1,2 Adjustable output voltage Range (2) VFB1,2 Feedback voltage (FB1, FB2) 1.22 Feedback voltage accuracy (1) (FB1, FB2) ±2% IFB1,2 VFBX Current into FB1, FB2 pins VIS1,2 Reference voltage for current sense IIS1,2 Current into IS1, IS2 pins (1) 0.01 TA = 25°C 80 TA = Full Range 75 100 0.01 V 0.5 120 125 0.5 μA mV μA Measured with the circuit in Figure 2, VOUT + 0.5 V ≤ VIN ≤ 6.5 V 0.1 %/V %/A ΔVOUT%/ΔVIN Line regulation ΔVOUT%/ΔIOUT Load regulation Measured with the circuit in Figure 2, 30 mA ≤ I OUT ≤ 2 A 0.6 n 1,2 Efficiency (3) Measured with the circuit in Figure 2, IOUT = 1 A 94% tSTR1,2 Startup time (3) Measured with the circuit in Figure 2, RL = 6 Ω, COUT = 100 μF, CSS = 2.2 nF 5 RDS,ON1,2 VIN1,2 > 2.5 V Gate driver P-Channel and N-Channel MOSFET on-resistance VIN1,2 = 2.2 V ISW1,2 Gate Driver P-Channel and N-Channel MOSFET drive current tON Minimum on time 1.36 1.55 1.84 μs tOFF Minimum off time 0.44 0.65 0.86 μs (1) (2) (3) ms 4 Ω 6 100 mA To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external components. Minimum VIN3 = VOUT3 + VDO or 2.2 V, whichever is greater. Maximum VOUT is dependent on external components and will be less than VIN. Parameter is not production tested. Depends on external components. 4 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF, TA = -55°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNIT LDO VOUT3 Output voltage range VFB3 Feedback pin voltage (4) Feedback pin voltage accuracy 1 6.5 - VDO 0.507 (5) 2.95 V ≤ VIN3 ≤ 6.5 V 1 mA ≤ IOUT3 ≤ 300 mA V V ±4% ΔVOUT%/ΔVIN Line regulation (5) VOUT3 + 0.5V ≤ VIN3 ≤ 6.5 V 0.075 %/V ΔVOUT%/ΔIOUT Load regulation 10 mA ≤ IOUT3 ≤ 300 mA 0.01 % / mA VDO Dropout voltage (VIN = VOUT(NOM) - 0.1) (6) IOUT3 = 300 mA 250 350 mV ICL3 Current limit VOUT = 0.9 x VOUT(NOM) 600 1000 mA IFB3 Current into FB3 pin 0.03 0.1 μA BW = 100 Hz - 100 kHz, IOUT3 = 300 mA Vn Output noise tSD Thermal shutdown temperature for Shutdown, temperature increasing LDO Reset, temperature decreasing UVLO (4) (5) (6) 375 400 175 160 μVRMS °C Undervoltage lockout threshold VIN rising 1.8 V Undervoltage lockout hysteresis VIN falling 100 mV Maximum VOUT is dependent on external components and will be less than VIN. Parameter is not production tested. To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external components. Minimum VIN3 = VOUT3 + VDO or 2.2 V, whichever is greater. VDO does not apply when VOUT + VDO < 2.2 V. 5 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com DEVICE INFORMATION Functional Block Diagram 6 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 IS1 SW1 IN1 DGND EN1 SS1 AGND SS3 www.ti.com IS2 IN2 SW2 DGND SS2 FB2 EN2 OUT3 EN3 FB1 FB3 IN3 PIN FUNCTIONS PIN DESCRIPTION NAME RHL DGND 6, 15, PAD AGND 18 Ground connection for LDO IN1 13 Input supply to BUCK1 IN2 8 Input supply to BUCK2 IN3 20 Input supply to LDO EN1 17 Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown mode, reducing operating current. The enable pin does not trigger on fast negative going transients. EN2 4 Same as EN1 but for BUCK2 controller EN3 3 Same as EN1 but for LDO SS1 16 Connecting a capacitor between this pin and ground increases start-up time of the BUCK1 regulator by slowing the ramp-up of current limit. This high-impedance pin is noise-sensitive; careful layout is important. See the Typical Characteristics, Applications, and PCB Layout sections for details. SS2 5 Same as SS1 but for BUCK2 regulator. SS3 19 Connecting a capacitor from this pin to ground slows the start-up time of the LDO reference, therby slowing output voltage ramp-up. See the Applications section for details. IS1 12 Current sense input for BUCK1 regulator. The voltage difference between this pin and IN1 is compared to an internal reference to set current limit. For a robust output start-up ramp, careful layout and bypassing are required. See the Applications section for details. IS2 9 Same as IS1, but compared to IN2 and used for BUCK2 controller SW1 14 Gate drive pin for external BUCK1 P-channel MOSFET SW2 7 Same as SW1, but for BUCK2 controller FB1 11 Feedback pin. Used to set the output voltage of BUCK1 regulator FB2 10 Same as FB1, but for BUCK2 controller FB3 2 Same as FB1, but for LDO OUT3 1 Regulated LDO output. A small ceramic capacitor (≥ 2.2 μF) is needed from this pin to ground to ensure stability. Ground connection for BUCK1 and BUCK2 converters. Pins 6 and 15 should be connected to the back side exposed pad by a short metal trace as shown in the PCB Layout section of this data sheet. 7 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA 15 mH 100 mF 0.01 mF DGND SW1 IN1 DGND SW2 IN2 IS1 EN1 SS1 SS3 15.4 kW IS2 SS2 EN2 61.9 kW EN3 10 mF 0.1 mF 1 mF FB3 100 mF AGND 33 mW 33 mW 36.5 kW 0.1 mF 61.9 kW 5 mH 100 mF Figure 2. TYPICAL CHARACTERISTICS Measured using circuit in Figure 2 Buck Converter BUCK LOAD REGULATION BUCK LOAD REGULATION Figure 3. Figure 4. 8 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 2 BUCK LINE REGULATION BUCK LINE REGULATION Figure 5. Figure 6. BUCK SWITCHING FREQUENCY vs IOUT, TA BUCK SWITCHING FREQUENCY vs IOUT Figure 7. Figure 8. BUCK OUTPUT VOLTAGE RIPPLE EFFICIENCY vs IOUT Figure 9. Figure 10. 9 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 2 BUCK START-UP vs VIN and IOUT BUCK START-UP vs VIN and COUT Figure 11. Figure 12. BUCK START-UP vs VIN and CSS BUCK START-UP vs IOUT and CSS Figure 13. Figure 14. LDO LOAD REGULATION LDO LINE REGULATION Figure 15. Figure 16. LDO Converter 10 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 2 LDO DROPOUT vs IOUT LDO DROPOUT vs TA Figure 17. Figure 18. RDS,ON PMOS vs VIN RDS,ON NMOS vs VIN Figure 19. Figure 20. LDO VOUT vs TA Figure 21. 11 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION The TPS75003 is an integrated power management IC designed specifically to power DSPs and FPGAs such as the Xilinx Spartan-3, Spartan-3E and Spartan-3L. Two non-synchronous buck controllers can be configured to supply up to 3 A for both CORE and I/O rails. A low dropout linear regulator powers auxiliary rails up to 300 mA. All channels have independent enable and soft-start, allowing control of inrush current and output voltage ramp time as required by the application. Figure 2 shows a typical application circuit for powering the Xilinx Spartan-3 FPGA. Table 1 through Table 4 show component values that have been tested for use with 2-A and 3-A load currents. Other similar external components can be substituted as desired; however, in all cases the circuits that are used should be tested for compliance to application requirements. Table 1. Inductors Tested with the TPS75003 PART NUMBER SLF7032T−100M1R4 MANUFACTURER INDUCTANCE DC RESISTANCE SATURATION CURRENT TDK 10 μH ±20% 53 mΩ ±20% 1.4 A TDK 15 μH ±20% 85 mΩ ±20% 0.88 A CDRH6D28−5R0 Sumida 5 μH 23 mΩ 2.4 A CDRH6D38-5R0 Sumida 5 μH 18 mΩ 2.9 A CDRH103R−100 Sumida 10 μH 45 mΩ 2.4 A CDRH4D28−100 Sumida 10 μH 96 mΩ 1A CDRH8D43-150 Sumida 15 μH 42 mΩ 2.9 A CDRH5D18−6R2 Sumida 6.2 μH 71 mΩ 1.4 A DO3316P−472 Coilcraft 4.7 μH 18 mΩ 5.4 A DT3316P−153 Coilcraft 15 μH 60 mΩ 1.8 A DT3316P−223 Coilcraft 22 μH 84 mΩ 1.5 A 744052006 Wurth 6.2 μH 80 mΩ 1.45 A 74451115 Wurth 15 μH 90 mΩ 0.8 A SLF6025−150MR88 Table 2. PMOS Transistors Tested with the TPS75003 MANUFACTURER RDS,ON (TYP) VDS ID PACKAGE Si5447DC PART NUMBER Vishay Siliconix 0.11 Ω at VGS = −2.5 V −20 V −3.5 A at +25°C 1206 Si5475DC Vishay Siliconix 0.041 Ω at VGS = −2.5 V −12 V −6.6 A at +25°C 1206 Si2323DS Vishay Siliconix 0.052 Ω at VGS = −2.5 V −20 V −4.1 A at +25°C SOT23 Si2301ADS Vishay Siliconix 0.19 Ω at VGS = −2.5 V −20 V −1.4 A at +25°C SOT23 Si2323DS Vishay Siliconix 0.41 Ω at VGS = −2.5 V −20 V −4.1 A at +25°C SOT23 FDG326P Fairchild 0.17 Ω at VGS = −2.5 V −20 V −1.5 A SC70 Table 3. Diodes Tested with the TPS75003 PART NUMBER MANUFACTURER VR IF PACKAGE MBRM120LT3 ON Semiconductor MBR0530T1 ON Semiconductor 20 V 1A DO216AA 30 V 1.5 A SOD123 Zetex 40 V 2A SOT23−6 B320 Diodes Inc. 20 V 3A SMA SS32 Fairchild 20 V 3A DO214AB ZHCS2000TA 12 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Table 4. Capacitors Tested with the TPS75003 MANUFACTURER CAPACITANCE ESR VOLTAGE RATING 6TPB47M (PosCap) PART NUMBER Sanyo 47 μF 0.1 Ω 6.3 V T491D476M010AS 10 V Kemet 47 μF 0.8 Ω B45197A Epco 47 μF 0.175 Ω 16 V B45294−R1107−M40 Epco 100 μF 0.045 Ω 6.3 V 594D476X0016C2 Vishay 47 μF 0.11 Ω 16 V 594D127X96R3C2 Vishay 120 μF 0.085 Ω 6.3 V AVX 100 μF 0.15 Ω 6.3 V Sanyo 100 μF 0.45 Ω 6.3 V TPSC107K006R0150 6TPS100MC OPERATION (BUCK CONTROLLERS) Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum off-time hysteretic control. (See Figure 2.) For clarity, BUCK1 is used throughout the discussion of device operation. When VOUT1 is below its target, an external PMOS (Q1) is turned on for at least the minimum on-time, increasing current through the inductor (L1) until VOUT1 reaches its target value or the current limit (set by R1) is reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on again when necessary. When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node capacitance. This is normal operation; it does not affect circuit performance, and can be minimized if desired by using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22. 0.1 mF R = 2pfL Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at the switch node and VOUT is equal to VIN times the duty cycle of the switching waveform. When VIN approaches or falls below VOUT, the buck controllers operate in 100% duty cycle mode, fully turning on the external PMOS to allow regulation at lower dropout than would otherwise be possible. Enable (Buck Controllers) The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2, respectively. If the soft-start feature is being used, enable should be driven high at least 10μs after VIN is applied to ensure this discharge cycle occurs. UVLO (Buck Controllers) An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from mis-operation at low input voltages. 13 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Current Limit (Buck Controllers) An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an internal reference to determine if an over-current condition exists. When current limit is exceeded, the external PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10 ns any time the PMOS is turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled. Current limit is calculated using the VIS1 or VIS2 specification in the Electrical Characteristics section, shown in Equation 1. V ILIMIT = IS1,2 R 1,2 (1) The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current calculated by Equation 2. IRMS = IOUT D = IOUT VOUT VIN 2 PDISS = (IRMS ) ´ R (2) For low-cost applications the IS1,2 pin can be connected to the drain of the PMOS, using RDS,ON instead of R1 or R2 to set current limit. Variations in the PMOS RDS,ON must be taken into account to ensure that current limit will protect external components such as the inductor, the diode, and the switch itself from damage as a result of overcurrent. Short-Circuit Protection (Buck Controllers) In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the feedback pin is lower than the reference voltage. When the output is shorted (VFB is zero), minimum off-time is increased to approximately 4 μs. The increase in off-time is proportional to the difference between the voltage at the feedback pin and the internal reference. Soft-Start (Buck Controllers) The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. See the soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are high-impedance and cannot be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low, any charge on the SS pin is discharged by an on-chip pulldown transistor. When EN1 is driven high, an on-chip current source starts charging the external soft-start capacitor CSS1. The voltage on the capacitor is compared to the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the soft-start time over a wide range for most applications. For detailed information on choosing CSS1 and CSS2, see the section, Selecting the Soft-Start Cap. 14 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Figure 23. Soft-Start Circuitry Figure 24. Soft-Start Timing Diagram Input Capacitor CIN1, CIN2 Selection (Buck Controllers) It is good analog design practice to place input capacitors near the inputs of the device in order to ensure a low impedance input supply. A capacitance of 10 μF to 22 μF for each buck converter is adequate for most applications, and should be placed within 100 mils (0.001 in) of the IN1 and IN2 pins to minimize the effects of pulsed current switching noise on the soft-start circuitry during the first ~1 V of output voltage ramp. Low ESR capacitors also help to minimize noise on the supply line. The minimum value of capacitance can be estimated using Equation 3. CIN , MIN = (1/2)L ´ (DIL )2 (1/2)L VRIPPLE ´ VIN » 2 ´ (0.3 ´ IOUT ) V(RIPPLE) ´ VIN (3) Note that the capacitors must be able to handle the RMS current in continuous conduction mode, which can be calculated using Equation 4. IC,IN(RMS ) » æ VOUT ö ç ÷ è VIN ,MIN ø (4) 15 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Inductor Value Selection (Buck Controllers) The inductor is chosen based on inductance value and maximum current rating. Larger inductors reduce current ripple (and therefore, output voltage ripple) but are physically larger and more expensive. Inductors with lower DC resistance typically improve efficiency, but also have higher cost and larger physical size. The buck converters work well with inductor values between 4.7 μH and 47 μH in most applications. When selecting an inductor, the current rating should exceed the current limit set by RIS or RDS,ON (see Current Limit section). To determine the minimum inductor size, first determine if the device will operate in minimum on-time or minimum off-time mode. The device will operate in minimum on-time mode if Equation 5 is satisfied. t(OFF,min) ´ (VOUT + VSCHO TTKY + RL ´ IO UT ) VIN - VOUT - IOUT ´ rDS(on) - RL ´ IOUT ³ tON ,MIN (5) where RL = the inductor's DC resistance. Minimum inductor size needed when operating in minimum on-time mode is given by Equation 6. L MIN = (VIN - VOUT - IOUT ´ rDS(on) - RL ´ IOUT ) ´ tON,MIN DI (6) Minimum inductor size needed when operating in minimum off-time mode is given by Equation 7. (VO UT + VS CHOTTKY + RL ´ IOUT ) ´ tOFF ,MIN LMIN = DI (7) External PMOS Transistor Selection (Buck Controllers) The external PMOS transistor is selected based on threshold voltage (VT), on-resistance (RDS,ON), gate capacitance (CG) and voltage rating. The PMOS VT magnitude must be much lower than the lowest voltage at IN1 or IN2 that will be used. A VT magnitude that is 0.5 V less than the lowest input voltage is normally sufficient. The PMOS gate will see voltages from 0 V to the maximum input voltage, so gate-to-source breakdown should be a few volts higher than the maximum input supply. The drain-to-source of the device will also see this full voltage swing, and should therefore be a few volts higher than the maximum input supply. The RMS current in the PMOS can be estimated by using Equation 8. IPMOS(RMS) » IOUT D = IOUT VOUT VIN (8) The power dissipated in the PMOS is comprised of both conduction and switching losses. Switching losses are typically insignificant. The conduction losses are a function of the RMS current and the RDS,ON of the PMOS, and are calculated by Equation 9. ( P(cond) = IOUT D 2 )´r DS(on) ( ) ´ 1 + TC ´ [TJ - 25°C ] » (I OUT 16 D )´r DS(on) (9) Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Diode Selection (Buck Controllers) The diode is off when the PMOS is on, and on when the PMOS is off. Since it will be turned on and off at a relatively high frequency, a Schottky diode is recommended for good performance. The peak current rating of the diode should exceed the peak current limit set by the sense resistor RIS1,2. A diode with low reverse leakage current and low forward voltage at operating current will optimize efficiency. Equation 10 calculates the estimated average power dissipation. æ ö V I(diode)(RMS) » IOUT (1 - D) = IOUT ç 1 - OUT ÷ VIN ø è (10) Output Capacitor Selection (Buck Controllers) The output capacitor is selected based on output voltage ripple and transient response requirements. As a result of the nature of the hysteretic control loop, a minimum ESR of a few tens of mΩ should be maintained for good operation unless a feed-forward resistor is used. Low ESR bulk tantalum or PosCap capacitors work best in most applications. A 1-μF ceramic capacitor can be used in parallel with this capacitor to filter higher frequency spikes. The output voltage ripple can be estimated by Equation 11. é 1 æ öù D VPP = DI ´ êESR + ç ÷ ú » 1.1D I ´ ESR ´ ´ 8 COUT f è øû ë (11) To calculate the capacitance needed to achieve a given voltage ripple as a result of a load transient from zero output to full current, use Equation 12. COUT = L ´ ΔIO UT 2 (VIN - VOUT ) ´ ΔV (12) If only ceramic or other very low ESR output capacitor configurations are desired, additional voltage ripple must be passed to the feedback pin. See Application Note, Using Ceramic Output Capacitors with the TPS6420x Buck Controllers (SLVA210), for detailed application information. Output Voltage Ripple Effect on VOUT (Buck Controllers) Output voltage ripple causes VOUT to be higher or lower than the target value by half of the peak-to-peak voltage ripple. For minimum on-time, the ripple adds to the voltage; for minimum off-time, it subtracts from the voltage. Soft-Start Capacitor Selection (Buck Controllers) BUCK1 is discussed in this section; it is identical to BUCK2. Soft-start is implemented on the buck controllers by ramping current limit from 0 to its target value (set by R1) over a user-defined time. This time is set by the external soft-start cap connected to pin SS1. If SS1 is left open, a small on-chip capacitor will provide a current limit ramp time of approximately 250 μs. Figure 25 shows the effects of R1 and SS1 on the current limit start-up ramp. 17 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com CSS1 = 0.01 mF R1 = 33 mW CSS1 = 0.022 mF R1 = 143 mW CSS1 = 0.022 mF CSS1 = 0.01 mF Figure 25. Effects of CSS1 and R1 on Current Ramp Limit This soft-start current limit ramo can be used to provide inrush current control or output voltage ramp control. While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a complex function of many variables. The dominant variables in this process are VOUT1, CSS1, IOUT1, and R1. Less important variables are VIN1 and L1. The best way to set a target start-up time is through bench measurement under target conditions, adjusting CSS1 to get the desired startup profile. To stay above a minimum start-up time, set the nominal start-up time to approximately five times the minimum. To stay below a maximum time, set the nominal start-up time at one-fifth of the maximum. Fastest start-up times occur at maximum VIN1, with minimum VOUT1, L1, COUT1, CSS1, and IOUT1. Slowest start-up times occur under opposite conditions. See Figure 11 to Figure 14 for characterization curves showing how the start-up profile is affected by these critical parameters. Output Voltage Setting Selection (Buck Controllers) Output voltage is set using two resistors as shown for Buck2 in Figure 2. Output voltage is then calculated using Equation 13. æR ö VOUT = VFB ç 5 +1÷ è R6 ø (13) where VFB = 1.24V. LDO OPERATION The TPS75003 LDO uses a PMOS pass element and is offered in an adjustable version for ease of programming to any output voltage. When used to power VCC,AUX it is set to 2.5 V; it can optionally be set to other output voltages to power other circuitry. The LDO has integrated soft-start, independent enable, and short-circuit and thermal protection. The LDO can be used to power VCC,AUX on the Xilinx Spartan-3 FPGA when 3.3-V JTAG signals are used as described in Application Note SLVA159 (available for download from www.ti.com). Input Capacitor Selection (LDO) Although an input capacitor is not required, it is good analog design practice to connect a 0.1-μF to 10-μF low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, stability, and ripple rejection. A higher value capacitor may be needed if large, fast rise-time load transients are anticipated, or if the device is located far from its power source. 18 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Output Capacitor Selection (LDO) A 2.2 μF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or lower ESR output capacitors can be used. Soft-Start (LDO) The LDO uses an external soft-start capacitor, CSS3, to provide an RC-ramped reference voltage to the control loop. (See the Functional Block Diagram.) This is a voltage-controlled soft-start, as compared to the current-controlled soft-start used by the buck controllers. Setting Output Voltage (LDO) Output voltage is set using two resistors as shown in Figure 2. Output voltage is then calculated using Equation 14. æR ö VOUT = VFB ç 3 + 1÷ è R4 ø (14) where VFB = 0.507 V. Internal Current Limit (LDO) The internal current limit of the LDO helps protect the regulator during fault conditions. When an over-current condition is detected, the output voltage will be reduced until the current falls to a level that will not damage the device. For good device reliability, the LDO should not operate at current limit. Enable Pin (LDO) The active high enable pin (EN3) can be used to put the device into shutdown mode. If shutdown and soft-start capability are not required, EN3 can be tied to IN3. Dropout Voltage (LDO) The LDO uses a PMOS transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the pass device is in its linear region of operation, and the input-output resistance is the RDS,ON of the pass transistor. In this region, the regulator is said to be out of regulation; ripple rejection, line regulation, and load regulation degrade as (VIN – VOUT) falls much below 0.5 V. Transient Response (LDO) The LDO does not have an on-chip pulldown circuit for output is over-voltage conditions. This feature permits applications that connect higher voltage sources such as an alternate power supply to the output. This design also results in an output overshoot of several percent if the load current quickly drops to zero. The amplitude of overshoot can be reduced by increasing COUT; the duration of overshoot can be reduced by adding a load resistor. Thermal Protection (LDO) Thermal protection disables the output when the junction temperature, TJ, reaches unsafe levels. When the junction cools, the output is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage. For good long term reliability, the device should not be continuously operated at or near thermal shutdown. 19 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Power Dissipation (LDO) The TPS75003 comes in a QFN-style package with an exposed lead frame on the package underside. The exposed lead frame is the primary path for removing heat and should be soldered to a PC board that is configured to remove the amount of power dissipated by the LDO, as calculated by Equation 15. PD = (VIN3 - VOUT3 ) ´ IO UT3 (15) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. The two buck converters do not contribute a significant amount of dissipated power. Using heavier copper increases the overall effectiveness of removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. PCB Layout Considerations Note: DGND IN1 IS1 IN2 IS2 SS2 SW1 EN2 SW2 EN1 SS1 EN3 DGND SS3 AGND FB3 As with any switching regulators, careful attention must be paid to board layout. A typical application circuit and corresponding recommended printed circuit board (PCB) layout with emphasis on the most sensitive areas are shown in Figure 26 through Figure 28. Most sensitive areas are highlighted by bold lines. Figure 26. Typical Application Circuit 20 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com Note: Most sensitive areas are highlighted in green. Figure 27. Recommended PCB Layout, Component Side, Top View 21 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 Note: www.ti.com Most sensitive areas are highlighted in green. Figure 28. Recommended PCB Layout, Bottom Side, Top View 22 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP TPS75003-EP SGLS311A – DECEMBER 2006 – REVISED MARCH 2011 www.ti.com REVISION HISTORY Changes from Original (December 2006) to Revision A • Page Replaced the DISSIPATION RATINGS table with the Thermal Information Table .............................................................. 3 23 Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Link(s): TPS75003-EP PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device TPS75003MRHLREP Package Package Pins Type Drawing VQFN RHL 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.8 B0 (mm) K0 (mm) P1 (mm) 4.8 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS75003MRHLREP VQFN RHL 20 3000 356.0 356.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE VQFN - 1 mm max height RHL0020A PLASTIC QUAD FLATPACK- NO LEAD A 3.6 3.4 B PIN 1 INDEX AREA 4.6 4.4 C 1 MAX SEATING PLANE 0.08 C 2.05±0.1 2X 1.5 20X 0.5 0.3 SYMM 10 14X 0.5 2X 3.5 9 12 SYMM 21 3.05±0.1 19 2 PIN 1 ID (OPTIONAL) (0.2) TYP 11 1 20 4X (0.2) 2X (0.55) 20X 0.29 0.19 0.1 0.05 C A B C 4219071 / A 05/2017 NOTES: 1. 2. 3. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT VQFN - 1 mm max height RHL0020A PLASTIC QUAD FLATPACK- NO LEAD (3.3) (2.05) 2X (1.5) SYMM 1 20 2X (0.4) 20X (0.6) 19 2 20X (0.24) 14X (0.5) SYMM 21 (3.05) (4.3) 6X (0.525) 2X (0.75) SOLDER MASK OPENING METAL UNDER SOLDER MASK 9 12 (R0.05) TYP (Ø0.2) VIA TYP) 11 10 4X (0.2) 4X (0.775) 2X (0.55) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 18X 0.07 MAX ALL AROUND EXPOSED METAL SOLDER MASK OPENING 0.07 MIN ALL AROUND SOLDER MASK OPENING EXPOSED METAL METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4219071 / A 05/2017 NOTES: (continued) 4. 5. 6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . Solder mask tolerances between and around signal pads can vary based on board fabrication site. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to theri locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN VQFN - 1 mm max height RHL0020A PLASTIC QUAD FLATPACK- NO LEAD (3.3) 2X (1.5) (0.55) TYP 1 20 (0.56) TYP SOLDER MASK EDGE TYP 20X (0.6) 2 19 20X (0.24) 14X (0.5) (1.05) TYP SYMM (4.3) 21 6X (0.85) (R0.05) TYP METAL TYP 12 9 2X (0.775) 2X (0.25) 11 10 4X (0.2) 6X (0.92) SYMM SOLDER PASTE EXAMPLE BASED ON 0.1mm THICK STENCIL EXPOSED PAD 75% PRINTED COVERAGE BY AREA SCALE: 20X 4219071 / A 05/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. 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