TPS75005
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SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
Integrated MCU Power Solution for C2000™ Microcontrollers
Check for Samples: TPS75005
FEATURES
DESCRIPTION
•
The TPS75005 is a complete power management
solution for Texas Instruments' C2000 real-time
microcontrollers and other DSP, FPGA, and ASIC
MCUs. The device has been tested with and meets
TI's F2833x (DELFINO), F2823x, F281x, and
F280x/F2801x power requirements.
1
23
•
•
•
•
•
•
•
•
•
Optimized to Supply TI's C2000 MCU Series:
F2833x ( DELFINO™), F2823x, F281x, and
F280x/F2801x
Dual 500-mA Voltage Regulators with
Dedicated Supply Voltage Supervisors (SVSs)
One Auxiliary SVS
LDO1 and SVS1 for 1.8 V/1.9 V (Selectable):
±5% Specified with PG
LDO2 and SVS2 for 3.3 V:
±5% Specified with PG
Input Voltage Range: 3.75 V to 6.5 V
Independent Soft-Start for LDO1 and LDO2
Preset Power-Up and Power-Down Sequencing
for C2000 MCUs
Supports C2000 MCU Transient with Two
10-µF Ceramic Output Capacitors
5-mm × 5-mm QFN Package (1)
All of these C2000 controllers require ±5% power-rail
accuracy. With the combination of high-accuracy,
low-dropout regulators (LDOs) and dedicated SVSs,
the device allows for a ±5% power supply to the
C2000 with a power-good (PG) signal. (For more
details, see Application Report SBVA032, LDO+SVS
Combined Accuracy.)
Two power outputs are controlled by an integrated
sequencer circuit. A single EN logic input signal
makes sure that the power-up and power-down
requirements of the C2000 controllers are met. The
sequencer includes a soft-start for both LDOs to
avoid inrush current. A third rail monitor is provided
for general-purpose monitoring (for example, to
monitor input voltage).
APPLICATIONS
•
•
(1)
A quick-start guide (SBVA030) is available with stepby-step instructions for connection to a C2000
controller.
C2000 MCUs
DSPs/FPGAs/ASICs
The TPS75005 is available in a 5-mm × 5-mm QFN
package, yielding a compact total solution size with
high power dissipation capability.
16-Pin HTSSOP package can be supported but minimum
quantity may be required; contact sales representative.
0.1 mF
0.1 mF
0.1 mF
0.1 mF
OUT1
10 kW
OUT1-S
0.1 mF
TPS75005
OUT2
OUT2-S
TEST
VDDIO-3
10 mF
0.1 mF
EN
VDDIO-n
VDET
VMON
5-V
Power
Supply
VDD-n
0.1 mF
VDD-3
100 kW
IN
VDD-2
27 kW
VDD-1
10 mF
10 mF
0.1 mF
VDDIO-2
C2000
Controller
VDDIO-1
100 kW
SEQ
VSET
PG
XRS
GND
GND
SS1
CT1
SS2
CT2
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C2000, DELFINO are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS75005
SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
VOLTAGE INFORMATION (1)
PRODUCT
TPS75005 (2)
TPS75005ADJ
(1)
(2)
VOUT1
VSET = L
VSET = H
1.818 V
(101%)
1.919 V
(101%)
Adjustable,
greater than 1.24 V
VOUT2
3.333 V
(101%)
Adjustable,
greater than 1.24 V
VSVS1
VSVS2
VSET = H
VSET = L
1.764 V
(98%)
1.862 V
(98%)
Adjustable,
97% of VOUT1
VSVS3
3.234
(98%)
1.206 V
Adjustable,
97% of VOUT2
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
VOUT1 and VSVS1 are selectable by VSET pin logic with the TPS75005.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +125°C (unless otherwise noted).
VALUE
Voltage (2)
MAX
IN, OUT1, OUT2, VMON, VSET, SEQ, OUT1_S, OUT2_S
–0.3
+7.0
CT1 CT2, SS1, SS2
–0.3
+3.6
EN, VDET, PG, TEST
–0.3
Temperature
Storage, Tstg
Electrostatic
discharge ratings (5)
Human body model (HBM) QSS 009-105 (JESD22-A114A)
(2)
(3)
(4)
(5)
2
VIN + 0.3
V
V
(3)
V
Internally limited (4)
Output current
(1)
UNIT
MIN
–55
Charge device model (CDM) QSS 009-147 (JESD22-C101B.01)
+150
°C
2
kV
500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
Absolute maximum rating of these pins is VIN + 0.3 V or + 7.0 V, whichever is smaller.
See Electrical Characteristics.
ESD testing is performed according to the respective JESD22 JEDEC standard.
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TPS75005
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SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
THERMAL INFORMATION
TPS75005
THERMAL METRIC (1) (2)
RGW (QFN) (3)
UNITS
20 PINS
Junction-to-ambient thermal resistance (4)
θJA
(5)
35.1
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (6)
14.4
ψJT
Junction-to-top characterization parameter (7)
0.4
ψJB
Junction-to-board characterization parameter (8)
14.5
θJCbot
Junction-to-case (bottom) thermal resistance (9)
3.7
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
31.9
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the RGW package is derived by thermal simulations based on JEDEC-standard methodology as specified in the
JESD51 series. The following assumptions are used in the simulations:
(a) RGW: The exposed pad is connected to the PCB ground layer through a 4 x 4 thermal via array.
(b) Each of top and bottom copper layers has a dedicated pattern for 4% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction
Temperature sections.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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TPS75005
SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
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ELECTRICAL CHARACTERISTICS
Over operating temperature range of TJ = –40 °C to +125 °C, with 4.0 V ≤ VIN ≤ 6.5 V, VOUT1_S = VOUT1, VOUT2_S = VOUT2, VEN =
VIN, CT1 = OPEN, CT2 = OPEN, SS1 = OPEN, SS2 = OPEN, PG = pulled up to VOUT2 through 100-kΩ resistor, TEST =
pulled up to VOUT2 through 100-kΩ resistor, VDET = pulled up to VIN through 100-kΩ resistor, VMON = VIN, COUT1 = 10 µF, COUT2
= 10 µF, ROUT1 = 1 kΩ to GND (1), ROUT2 = 1 kΩ to GND (1), and VSET = SEQ = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMPLETE DEVICE
VIN
Input voltage range
IGND
GND current
IOUT1 = IOUT2 = 500 mA, VSET = VIN or GND
IQ
Quiescent GND current
IOUT1 = IOUT2 = 0 A, VSET = VIN or GND
ISHDN
Shutdown ground current
VIN = 6.5 V, no pull-up resistors at PG, VDET, TEST pins
VSVS3
VMON supervisor threshold
ΔVSVS3
VMON supervisor hysteresis
Relative to VSVS3
VIH
High-level input voltage
For EN, SEQ, and VSET pins
2.0
VIL
Low-level input voltage
For EN, SEQ, and VSET pins
0
0.8
For SEQ and VSET pins, VSEQ = VSET = 2.0 V
– 0.1
0.1
For EN pin
– 0.2
0.2
IIN
Logic input current
VOL
Low-level output voltage
UVLO
Undervoltage lock out
TTSD
Thermal shutdown temperature
tDVS
VSET transition time (2)
3.75
6.5
V
500
µA
175
1.181
µA
17
40
1.206
1.230
µA
V
+4
V
Load current 1 mA into PG, TEST, and VDET pins
force VOUT1 < VSVS1, VMON = 0.5 V
Releasing: VIN rising
mV
V
µA
0.3
3.4
Locking: hysteresis, VIN falling
V
3.75
V
60
mV
Temperature rising to shutdown
+165
°C
Hysteresis, temperature falling to release shutdown
+145
°C
40
µs
LDO1 (1.8 V or 1.9 V Selectable by VSET Pin)
VOUT1
VSET= H, 4.0 V ≤ VIN ≤ 6.5 V, 1 mA ≤ IOUT1 ≤ 500 mA
1.881
(99%)
1.919
(101%)
1.957
(103%)
V
VSET= L, 4.0 V ≤ VIN ≤ 6.5 V, 1 mA ≤ IOUT1 ≤ 500 mA
1.782
(99%)
1.818
(101%)
1.854
(103%)
V
LDO1 output voltage accuracy
ΔVOUT1/ΔVIN
LDO1 line regulation
4.0 V ≤ VIN ≤ 6.5 V, IOUT1 = 1 mA
ΔVOUT1/ΔIOUT1
LDO1 load regulation
1 mA ≤ IOUT1 ≤ 500 mA
ICL1
LDO1 current limit
VOUT1 = 0.9 × VOUT1(NOM), 4.5 V < VIN < 6.5 V
VSVS1
LDO1 supervisor threshold
122
µV/V
29
µV/mA
900
mA
VSET= H, 4.0 V ≤ VIN ≤ 6.5 V
Force VOUT1 (decreasing)
1.805
(95%)
1.881
(99%)
V
VSET= L, 4.0 V ≤ VIN ≤ 6.5 V
Force VOUT1 (decreasing)
1.710
(95%)
1.782
(99%)
V
ΔVSVS1
LDO1 supervisor hysteresis
Relative to VSVS1
0.3
%
tW(SVS1)
LDO1 supervisor minimum pulse
width to Sense
VOUT1 = 100% → 90% → 100%
3.3
µs
tD(SVS1)
LDO1 supervisor delay time
From (VOUT1 > VSVS1) event to PG ↑ with SEQ = H,
CCT1 = (open)
33
µs
ICT1
CT1 charging current
Any capacitor connected between CT1 and GND,
0.2 V ≤ VCT1 ≤ 1.0 V
0.3
VCT1
CT1 timeout threshold
Any capacitor connected between CT1 and GND
1.05
tSS1
LDO1 soft-start time
VOUT1 waveform from 0% to 95%, CSS1 = (open)
ISS1
SS1 charging current
Any capacitor connected between SS1 and GND,
0.2 V ≤ VSS1 ≤ 1.0 V
0.3
RPD1
LDO1 active pull-down ON
resistance
EN = GND, VOUT1 = 1.8 V
225
VDOWN1
LDO1 power-down detector
accuracy
(1)
(2)
4
1
1.206
1.35
260
360
µA
V
µs
0.8
µA
475
Ω
0.3
V
These 1-kΩ resistors are disconnected when the test conditions specify an output current of LDO1 or LDO2.
With recommended usage of TPS75005, VSET does not need to be controlled on-the-fly. VSET transition time varies significantly
depending on application conditions. Stated typical value is almost the fastest transition.
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TPS75005
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SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS (continued)
Over operating temperature range of TJ = –40 °C to +125 °C, with 4.0 V ≤ VIN ≤ 6.5 V, VOUT1_S = VOUT1, VOUT2_S = VOUT2, VEN =
VIN, CT1 = OPEN, CT2 = OPEN, SS1 = OPEN, SS2 = OPEN, PG = pulled up to VOUT2 through 100-kΩ resistor, TEST =
pulled up to VOUT2 through 100-kΩ resistor, VDET = pulled up to VIN through 100-kΩ resistor, VMON = VIN, COUT1 = 10 µF, COUT2
= 10 µF, ROUT1 = 1 kΩ to GND(1), ROUT2 = 1 kΩ to GND(1), and VSET = SEQ = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.267
(99%)
3.333
(101%)
3.399
(103%)
UNIT
LDO2 (3.3 V)
VOUT2
LDO2 output voltage accuracy
4.0 V ≤ VIN ≤ 6.5 V, 1mA ≤ IOUT2 ≤ 500 mA
ΔVOUT2/ΔVIN
LDO2 line regulation
4.0 V ≤ VIN ≤ 6.5 V, IOUT2 = 1 mA
ΔVOUT2/ΔIOUT1
LDO2 load regulation
1 mA ≤ IOUT2 ≤ 500 mA
ICL2
LDO2 current limit
VOUT2 = 0.9 × VOUT2(NOM), 4.5 V < VIN < 6.5 V
VSVS2
LDO2 supervisor threshold
4.0 V ≤ VIN ≤ 6.5 V
force VOUT2 (decreasing)
ΔVSVS2
LDO2 supervisor hysteresis
Relative to VSVS2
0.3
%
tW(SVS2)
LDO2 supervisor minimum pulse
width to sense
VOUT2 = 100% → 90% → 100%
3.3
µs
tD(SVS2)
LDO2 supervisor delay time
From (VOUT2 > VSVS2) event to PG↑ with SEQ = L,
CCT2 = (open)
33
µs
ICT2
CT2 charging current
Any capacitor connected between CT2 and GND,
0.2 V ≤ VCT2 ≤ 1.0 V
0.3
VCT2
CT2 timeout threshold
Any capacitor connected between CT2 and GND
1.05
tSS2
LDO2 soft-start time
VOUT2 waveform from 0% to 95%, CSS2 = (open)
ISS2
SS2 charging current
Any capacitor connected between SS2 and GND,
0.2 V ≤ VSS2 ≤ 1.0 V
0.3
RPD2
LDO2 active pull-down ON
resistance
EN = L, VOUT2 = 3.3 V
225
VDOWN2
LDO2 power-down detector
accuracy
461
µV/V
50
µV/mA
900
3.135
(95%)
mA
3.267
(99%)
1
1.206
1.35
260
360
µA
V
0.8
µA
475
Ω
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V
µs
0.3
Copyright © 2011–2012, Texas Instruments Incorporated
V
V
5
TPS75005
SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
www.ti.com
PIN CONFIGURATION
NC
IN
IN
EN
VMON
20
19
18
17
16
RGW PACKAGE
5-mm x 5-mm QFN-20
(TOP VIEW)
13
CT1
SS2
4
12
SS1
VDET
5
11
TEST
PG
3
10
CT2
9
OUT1_S
VSET
14
8
2
SEQ
OUT2_S
7
OUT1
GND
15
6
1
GND
OUT2
PIN DESCRIPTIONS
PIN
RGW
QFN-20
NAME
CT1
13
CT2
3
SVS2 internal-power-good delay setting. Leave this pin open for the default delay setting or connect a capacitor
between this pin and GND to program the delay. Do not connect a regular oscilloscope probe for monitoring.
EN
17
Enable inputs. Logic-H input to this pin triggers power-up sequence. Logic-L triggers power-down sequence.
NOTE: The sequencing logic will automatically prevent powering up until the TPS75005 pulls the output rails to GND.
This ensures a proper startup every time.
GND
6, 7
Ground. Tie these pins to the thermal pad and maximize the copper in this area for optimal performance.
IN
18, 19
Power supply to the device. Connect a 10-µF X5R or X7R dielectric capacitor between IN and GND close to the
device.
NC
20
Not internally connected. This pin can be either tied to IN or GND to simplify layout.
OUT1
15
LDO1 output voltage. Connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device.
OUT1_S
14
LDO1 output voltage sense input. Connect directly to output capacitor close to pin 15.
OUT2
1
LDO2 output voltage. Connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device.
OUT2_S
2
LDO2 output voltage sense input. Connect directly to output capacitor close to pin 1.
PG
10
Power-Good output. This is an open-drain output terminal and a pull-up resistor is required. The typical connection is
100 kΩ to OUT2. When VOUT1 > VSVS1 and VOUT2 > VSVS2, this pin outputs logic-H.
SEQ
8
Sequence select pin. Logic-L input to this pin powers-up two LDOs in this order: LDO1 first, and then LDO2. Logic-L
also powers-down LDO2 first, and then LDO1.
Logic-H to this pin powers-up two LDOs in this order: LDO2 first, and then LDO1. Logic-H also powers-down LDO1
first, and then LDO2.
SEQ should be hard-wired to either IN or GND depending on the sequencing mode required.
SS1
12
LDO1 soft-start setting. Leave this pin open for the default ramp up setting or connect a capacitor, 10 nF or less,
between this pin and GND to program VOUT1 ramp-up slew rate. Do not connect a regular oscilloscope probe for
monitoring.
SS2
4
LDO2 soft-start setting. Leave this pin open for the default ramp up setting or connect a capacitor between this pin
and GND to program VOUT2 ramp-up slew rate. Do not connect a regular oscilloscope probe for monitoring.
TEST
11
Test pin for test and debugging purposes only. Do not connect this pin.
VDET
5
Output of SVS3. This is an open-drain output terminal and a pull-up resistor is required. The typical connection is
100 kΩ to IN. When VMON > VSVS3, VDET outputs logic-H; when VMON < VSVS3, VDET is logic-L.
VMON
16
Monitor input voltage of third voltage detector. A resistor divider on this pin between the voltage rail to be monitored
and GND sets the threshold voltage. The detect threshold is 1.206 V.
VSET
9
LDO1 output voltage setting. Logic-H input sets VOUT1 to 1.9 V. Logic-L sets VOUT1 to 1.8 V. It is recommended to tie
this pin either to IN or GND depending on voltage required for the application.
Thermal pad
6
DESCRIPTION
SVS1 internal-power-good delay setting. Leave this pin open for the default delay setting or connect capacitor
between this node and GND to program the delay. Do not connect a regular oscilloscope probe for monitoring.
Pad for thermal dissipation. Tie this pin to GND with vias through the board to internal heat spreading layers as well
as the back side of the PCB.
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SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
FUNCTIONAL BLOCK DIAGRAM
IN
EN1
CL1
A
IOUT1 > ICL1?
BG
97%
UVLO
UVLO
OUT1
CL1
TSD
0.3 V
VCORE
1.8 V/500 mA
TSD
VS1
PD1
EN1
OUT1_S
360 W
0.3 V
SW1
97%
PG1
Delay
110 pF
VMON
EN2
VSET
CL2
A
IOUT2 > ICL2?
VS1
EN2
OUT2
VIO
3.3 V/500 mA
110 pF
CL1
OUT2_S
PD2
360 W
0.3 V
SW2
EN
97%
SEQ
PG2
Delay
PD1
EN1
PD2
EN2
2 pF
PG1
PG2
UVLO
Control
Logic
Sequencer
2 pF
SW1
VDET
SW2
TEST
TSD
CL1
PG
CL2
GND
SS2
SS1
CT2
CT1
(Optional)
Figure 1. Functional Block Diagram
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V,
VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted.
LDO1 (OUTPUT AND SVS THRESHOLD) VOLTAGE
vs TEMPERATURE
LDO2 (OUTPUT AND SVS THRESHOLD) VOLTAGE
vs TEMPERATURE
1.890
3.465
VSVS1 at VIN = 4.0 V
VSVS1 at VIN = 5.0 V
VSVS1 at VIN = 6.5 V
1.872
1.854
VOUT1 at VIN = 4.0 V
VOUT1 at VIN = 5.0 V
VOUT1 at VIN = 6.5 V
3.399
1.818
1.800
1.782
1.764
3.333
3.300
3.267
3.234
1.746
3.201
Y axis is 1%/div scale by referring 1.8 V.
LDO1 is loaded at 250 mA.
1.728
1.710
−50
−25
0
25
50
Temperature (°C)
75
Y axis is 1%/div scale by referring 3.3 V.
LDO2 is loaded at 250 mA.
3.168
100
3.135
−50
125
−25
0
G000
Figure 2.
1.872
3.432
1.854
3.399
1.836
3.366
1.818
1.800
1.782
1.764
Y axis is 1%/div scale by referring 1.8 V.
LDO1 is loaded at 25 mA.
0.1
0.1
0.2 0.2 0.2 0.3 0.4
OUT1 Output Current (A)
0.4
0.5
3.300
3.267
3.135
0.5
0
0.1
0.1
G002
0.2 0.2 0.2 0.3 0.4
OUT2 Output Current (A)
0.4
0.5
0.5
G003
Figure 5.
QUIESCENT GROUND CURRENT vs TEMPERATURE
350
Quiescent Ground Current (µA)
Shutdown Ground Current (µA)
−40°C
25°C
85°C
125°C
Y axis is 1%/div scale by referring 3.3 V.
LDO2 is loaded at 25 mA.
3.168
50
40
30
20
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.5 V
The device is disabled. The graph
shows consumption current by
internal reference circuits for SVS3.
−25
0
25
50
Temperature (°C)
75
100
125
300
250
200
150
100
50
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.5 V
PG, VDET, and TEST are open.
LDO1 and LDO2 are enabled
but not loaded.
0
−50
G004
Figure 6.
8
G001
3.201
SHUTDOWN GROUND CURRENT vs TEMPERATURE
0
−50
125
3.333
Figure 4.
10
100
3.234
−40°C
25°C
85°C
125°C
1.746
0
75
LDO2 LOAD REGULATION
3.465
Voltage (V)
Voltage (V)
LDO1 LOAD REGULATION
1.728
25
50
Temperature (°C)
Figure 3.
1.890
1.710
VOUT2 at VIN = 4.0 V
VOUT2 at VIN = 5.0 V
VOUT2 at VIN = 6.5 V
3.366
Voltage (V)
1.836
Voltage (V)
VSVS2 at VIN = 4.0 V
VSVS2 at VIN = 5.0 V
VSVS2 at VIN = 6.5 V
3.432
−25
0
25
50
Temperature (°C)
75
100
125
G005
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V,
VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted.
LOADED GROUND CURRENT vs IOUT2
350
300
300
Loaded Ground Current (µA)
Loaded Ground Current (µA)
LOADED GROUND CURRENT vs IOUT1
350
250
200
150
100
50
0
−40°C
25°C
85°C
125°C
PG, VDET, and TEST are open.
LDO2 is loaded with 250 mA.
0
0.1
0.2
0.3
OUT1 Output Current (A)
0.4
250
200
150
100
50
0
0.5
PG, VDET, and TEST are open.
LDO1 is loaded with 250 mA.
0
0.1
G007
0.2
0.3
OUT2 Output Current (A)
Figure 8.
300
3.65
250
200
150
100
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.5 V
PG, VDET, and TEST are open.
LDO1 and LDO2 are loaded
with 250 mA each.
−25
0
25
50
Temperature (°C)
75
100
3.60
3.55
3.50
3.45
3.40
−50
125
−25
0
G006
1
1
0.8
0.6
0.4
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.5 V
Under high temperature conditions,
some units start hitting thermal
shutdown during this test.
0
25
50
Temperature (°C)
75
100
125
G009
LDO2 CURRENT LIMIT vs TEMPERATURE
1.2
OUT2 Current Limit (A)
OUT1 Current Limit (A)
LDO1 CURRENT LIMIT vs TEMPERATURE
−25
25
50
Temperature (°C)
Figure 11.
1.2
0
−50
G008
UVLO (VIN goes up, device starts working)
UVLO (VIN goes down, device locks)
Figure 10.
0.2
0.5
UVLO VOLTAGE vs TEMPERATURE
3.70
Input Voltage (V)
Loaded Ground Current (µA)
LOADED GROUND CURRENT vs TEMPERATURE
0
−50
0.4
Figure 9.
350
50
−40°C
25°C
85°C
125°C
75
100
0.8
0.6
0.4
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.5 V
0.2
125
0
−50
G010
Figure 12.
−25
0
25
50
Temperature (°C)
75
100
125
G011
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V,
VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted.
EN PIN THRESHOLD vs TEMPERATURE
SVS3 (VMON) THRESHOLD vs TEMPERATURE
1.40
SVS3 (VMON) Threshold Voltage (V)
EN Pin Threshold Voltage (V)
2
VIN = 4.0 V
VIN = 6.5 V
1.8
1.6
1.4
1.2
1
Y axis bottom 0.8 V is the highest logic−L level
and top 2.0 V is the lowest logic−H level.
0.8
−50
−25
0
25
50
Temperature (°C)
75
100
VIN = 4.0 V
VIN = 6.5 V
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
−50
125
−25
0
25
50
Temperature (°C)
G012
Figure 14.
400
400
300
200
−40°C
25°C
85°C
125°C
100
0.2
0.4
125
G013
LDO2 PULL DOWN RESISTANCE vs VOUT2
500
Resistance (Ω)
Resistance (Ω)
LDO1 PULL DOWN RESISTANCE vs VOUT1
0
100
Figure 15.
500
0
75
0.6
0.8
1
1.2
OUT1 Voltage (V)
1.4
1.6
300
200
−40°C
25°C
85°C
125°C
100
0
0.0
1.8
0.5
1.0
G014
1.5
2.0
OUT2 Voltage (V)
Figure 16.
2.5
3.0
3.3
G015
Figure 17.
OPEN DRAIN OUTPUT (PG and VDET) DRIVE CAPABILITY vs TEMPERATURE
0.45
0.40
Voltage (V)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
−50
PG = 1 mA
PG = 2 mA
VDET = 1 mA
VDET = 2 mA
Forcing 1−mA and 2−mA current,
measure PG and VDET voltage.
The spec is 0.3 V(max) at 1 mA.
−25
0
25
50
Temperature (°C)
75
100
125
G016
Figure 18.
10
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = 5 V, V(EN) = VIN, CIN = 22 μF, COUT1 = COUT2 = 10 μF, C(SS1) = C(SS2) = C(CT1) = C(CT2) = (open), VSET = 0 V,
VSNS1 = VOUT1, VSNS2 = VOUT2, PG pin pulled up to VOUT2 with 100-kΩ pull-up resistor, and VDET pin pulled up to VIN with 100kΩ pull-up resistor, unless otherwise noted.
LINE TRANSIENT RESPONSE
6
LINE TRANSIENT RESPONSE
1.88
6
3.42
VIN
4
1.84
3
5
1.82
VOUT1
4
3.38
VOUT2
3
3.36
1.8
2
3.34
1.78
1
LDO1 is loaded at 250 mA.
LDO2 is loaded at 250 mA.
1
Time (10 µs/div)
3.32
Time (10 µs/div)
G017
Figure 19.
LDO1 LOAD TRANSIENT RESPONSE
LDO2 LOAD TRANSIENT RESPONSE
5
1.872
VIN
4
1.854
VOUT1
1.836
3
1.818
1.8
2
1.782
1.764
IOUT1 (20 mA to 500 mA)
1.746
1.728
0
VIN Voltage (V) / IOUT2 Current (A)
1.89
VOUT1 Voltage (V) (scale is 1%/div)
VIN Voltage (V) / IOUT1 Current (A)
5
1
1.71
3.432
VIN
4
VOUT2
3.399
3.366
3
3.333
3.3
2
3.267
3.234
IOUT2 (20 mA to 500 mA)
1
3.201
3.168
3.135
Time (10 µs/div)
G018
G019
Figure 21.
Figure 22.
VOUTX RAMP-UP TIME vs CSSX
DELAY TIME (TO NEXT SEQUENCER EVENT) vs CCTX
100
Delay Time to Next Event (ms)
100
VOUTX Ramp Up Time (ms)
3.465
0
Time (10 µs/div)
10
1
0.1
0.01
G023
Figure 20.
VOUT2 Voltage (V) (scale is 1%div)
2
3.4
VOUT2 Voltage (V)
1.86
VIN Voltage (V)
5
VOUT1 Voltage (V)
VIN Voltage (V)
VIN
0.1
1
CSSX (nF)
10
10
1
0.1
0.01
0.01
G020
Figure 23.
0.1
1
CCTX (nF)
10
G021
Figure 24.
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APPLICATION INFORMATION
Design Guidelines
Figure 25 and Figure 26 show a basic schematic and PCB layout for applications using the internal default
settings for power-good delay and rise time of the LDO1 and LDO2 outputs at turn on. This configuration is
typical for applications involving the targeted C2000 microcontrollers. The unused adjustment pins, CT1, CT2,
SS1, and SS2, are left open or floating. Connecting the SEQ and VSET pins to ground selects the turn-on
sequence and the output voltage of LDO1. The open-drain outputs at PG and VDET are pulled up to the input
voltage through 100-kΩ resistors. VDET is connected to enable the TPS75005 when the input voltage exceeds
the SVS voltage set by resistor divider R1 and R2 to VMON. For highly dynamic loads, like that of the C2000
microcontroller, the input capacitor, C2, and the output capacitors, C3 and C8, are specified to be 10-µF, X5R or
X7R, 10-V, ceramic capacitors in order to meet transient performance requirements.
VIN
VIN
Power Supply
C2
10 mF
R1
10 kW
EN
R2
3.7 kW
VDDIO
C3
10 mF
EN
R3
100 kW
21
20
19
18
17
16
PWPD
NC
IN
IN
EN
VMON
1
OUT2
OUT1 15
2
OUT2_S
3
CT2
CT1 13
4
SS2
SS1 12
5
VDET
VDD
OUT1_S 14
C8
10 mF
TEST 11
GND
GND
SEQ
VSET
PG
6
7
8
9
10
PG
VIN
R6
100 kW
Figure 25. Configuration for F280x, F281x, F223x and F2833x Controllers
(Set to automatically sequence C2000 when VIN > 4.5 V)
(C2, C3, C8 / 10-µF X5R ceramic capacitors)
12
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The PCB layout of Figure 26 shows that the input and output capacitors C2, C3, and C8 are located near the
respective pins and interconnected with a wide, low-inductance, ground plane that includes the device ground
and the thermal pad ground of the device.
NOTE
The input capacitor ground is routed under the device package through NC, pin-20.
Figure 26. TPS75005EVM-023 Recommended Layout
The PCB typically consists of four layers, minimum. The top (surface) layer and one internal layer are used for
trace/signal routing. One internal layer as well as the bottom layer are devoted to be ground planes that also
function as spreading planes for dissipating heat away from the TPS75005 device. It is very important for proper
function of the device and long-term reliability to conduct heat away from the device. The PowerPAD is soldered
to a ground pad on the PCB that conducts heat away from the device through nine plated vias to the spreading
planes beneath. The internal spreading layer in this case consists of four square inches of 1-ounce copper, and
the bottom layer consists of an equal area of 2-ounce copper. Additional spreading layers should be added, if
necessary, to a given application.
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LDO BLOCKS
The TPS75005 integrates two high-bandwidth LDOs for powering the VDD and VDDIO pins of the C2000
controllers.
Input Capacitor
Although an input capacitor is not required for LDO stability, it is recommended to connect a 10-μF capacitor
across the input supply near the device. In addition to input capacitor consideration, pay attention to the printed
circuit board (PCB) design in order to reduce source impedance.
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR
over temperature. Maximum ESR should be less than 1.0 Ω.
Output Capacitors
The TPS75005 is designed to be stable using standard ceramic capacitors with capacitance values 4.7 μF or
greater. In order to meet C2000 transient requirements, a 10-µF output capacitor at each of OUT1 and OUT2 is
recommended.
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR
over temperature. Maximum ESR should be less than 1.0 Ω.
See the Sense Pins (OUT1_S AND OUT2_S) section for more details.
Sense Pins (OUT1_S AND OUT2_S)
The TPS75005 has output voltage sensing pins OUT1_S and OUT2_S. OUT1_S should be connected to OUT1
at the output capacitor of LDO1, and OUT2_S to OUT2 at the output capacitor of LDO2. Both output capacitors
should be placed close to the device to minimize OUT1_S and OUT2_S trace. Figure 27 shows capacitor
placement.
0.1 mF
0.1 mF
0.1 mF
0.1 mF
OUT1
VDD-n
0.1 mF
VDD-3
10 mF
VDD-2
VDD-1
LDO1
VDDIO-n
OUT1-S
0.1 mF
0.1 mF
VDDIO-3
VDDIO-2
C2000
Controller
OUT2
LDO2
10 mF
0.1 mF
VDDIO-1
OUT2-S
Figure 27. Output Capacitors Placement and Sense Pins
When the C2000 controller is placed far from the TPS75005 on a PCB, it is recommended to connect the output
capacitors of OUT1 and OUT2 as close as possible to the TPS75005 device in order to route OUT1 and OUT2
node to a C2000 controller, and to place 0.1-µF ceramic capacitors for each of the VDD and VDDIO pins.
14
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Soft-Start (SS1 and SS2)
The TPS75005 has a soft-start (or slow-start) function for LDO1 and LDO2 that work independently of one
another. The ramp-up time for LDO1 and LDO2 is by default 260 µs due to the internal 110-pF capacitors. By
connecting an external capacitor(s) at the SS1 and/or SS2 pins, the ramp-up time for the LDOs increases
proportionately by following this equation:
C
(F) + 110 ´ 10-12 (F)
tRAMPUP (s) = SSx
´ 1.2 (V)
0.5 ´ 10-6 (A)
(1)
where:
tRAMPUP = ramp up time
CSSx = external capacitor value at SS1 or SS2 pin
See Figure 23 for an actual measurement curve.
To ensure that these circuits are discharged during power down, the capacitors used can have a maximum value
of 10 nF approximately 24 ms of ramping time. When an application circuit must control a much larger timing
period, use the supervisor delay setting in addition to the soft-start mechanism. See and find TSSx and Td(SVSx) in
Figure 32. See the Delay Setting (CT1 and CT2) section for details.
All supported C2000 controllers work well with the TPS75005 default setting (without external soft-start
capacitors). In case a large number of output capacitors are connected for a specific application reason, it is
recommended to connect capacitors at SS1 and/or SS2 so that inrush current (into the TPS75005) does not
cause a large input voltage droop. This can be mitigated by increasing the bulk capacitance at VIN.
NOTE
SS1 and SS2 are very high impedance nodes with very low values of constant current
source. These two terminals cannot be monitored by regular oscilloscope probes.
Connecting such regular probes to SS1 or SS2 changes the behavior of the soft-start
function and no valid waveform can be monitored.
To monitor these terminals, use high-impedance probes, such as active FET probes.
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Internal Enable Signals and Pull-Down Switches
As shown in Figure 1, LDO1 is controlled by the internal signal EN1, and LDO2 is controlled by EN2. SW1 and
SW2 are the inverse signals of EN1 and EN2, respectively. Whenever LDO1 and LDO2 are disabled, that means
EN1 and EN2 are logic-L, respectively. The corresponding output node(s) is discharged by an internal MOSFET
and 360-Ω resistor controlled by SW1 and SW2.
These pull-down switches ensure that every power-down sequence is completed in a reasonable, finite time.
See the Power-Down Monitoring section for a very important notice.
LDO1 Voltage Setting (VSET)
LDO1 can be configured as either a 1.8-V regulator or a 1.9-V regulator by the configuration of the VSET pin.
When VSET is connected to ground, LDO1 outputs 1.8 V; when VSET is connected to the level of logic-H, LDO1
outputs 1.9 V.
Current Limit
The TPS75005 internal current limit helps protect the regulator during unexpected fault conditions. During current
limit, the output sources a fixed 900mA. If kept in current limit for an extended period of time, the device will
thermally shutdown.
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MONITOR BLOCKS
Supply Voltage Supervisors (SVS1 and SVS2)
The TPS75005 integrates two supply voltage supervisors (SVSs) to monitor the VDD and VDDIO pins of the C2000
controllers.
Delay Setting (CT1 and CT2)
The TPS75005 has a programmable delay function for both SVS1 and SVS2 that work independently of each
other. By default, both CT1 and CT2 are open, and both SVS1 and SVS2 take approximately 33 µs of delay time
from the comparator trip event to its output. By connecting an external capacitor(s) at the CT1 and/or CT2 pins,
the SVS delay time increases proportionately, as shown in the following equation:
CSSx (F)
td (s) =
´ 1.2 (V)
0.5 ´ 10-6 (A)
(2)
where:
td = delay time
CCTx = external capacitor value at CT1 or CT2 pin
See Figure 24 for an actual measurement curve.
For a long delay setting, use a very low leakage current capacitor such as X5R- or X7R-type to minimize
calculation errors from the previous equation.
All supported C2000 controllers work well with the TPS75005 default settings (without external delay capacitors).
NOTE
As with the SS1 and SS2 terminals, CT1 and CT2 are very high-impedance nodes with
very low values of constant current source. These two terminals cannot be monitored by
regular oscilloscope probes. Connecting such regular probes to CT1 or CT2 changes the
behavior of the soft-start function and no valid waveform can be monitored.
To monitor these terminals, use high-impedance probes, such as active FET probes.
Spike Noise Sensitivity
Application Report SBVA033, TPS75005 Advanced Information: Voltage Monitor Noise Immunity, explains
TPS75005 noise immunity performance.
Power-Down Monitoring
The TPS75005 monitors both OUT1 and OUT2 to become 0.3 V in power-down sequence so that next power-up
sequence starts from below 0.3 V.
See the SEQUENCER BLOCK section for more details.
NOTE
In any application circuit, a diode or two diodes in series should not be placed from
OUT1 (anode, 1.8 V) to OUT2 (cathode, 3.3 V). Such diode(s) prevent the TPS75005
from pulling OUT2 below 0.3 V; the device stays in a power-down sequence and will
not power up again.
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Auxiliary Voltage Monitor (SVS3)
The TPS75005 has an independent supply voltage supervisor (SVS3) for an auxiliary purpose. The input voltage
to the VMON pin is compared with the 1.206 V internal reference and VDET is the output.
One of the most common uses of this feature is to monitor the input voltage. For example, many applications
may need to monitor the input voltage at a level higher than the UVLO. Figure 28 shows this type of example. At
the VMON pin, use a proper voltage divider to set a target voltage, calculated by the following equation:
R + R2
(SVS3 Detection Voltage Target) = 1.206 (V) ´ 1
R2
(3)
By pulling up VDET to VIN, the VDET output can be connected to the EN pin.
Connect upper
side of R1 to the
voltage monitored
10 mF
100 kW
IN
R1
TPS75005
VDET
5V
SVS3
VMON
R2
Sequencer
EN
Figure 28. SVS (VMON and VDET) Connection
Thermal Shutdown (TSD)
The thermal protection feature disables the device outputs when the junction temperature rises to approximately
+165°C, allowing the device to cool. When the junction temperature cools to approximately +145°C, the output
circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal
protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from
damage because of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat spreading layers. For reliable operation, junction temperature should be limited to +125°C maximum by
using the appropriate area of heat spreading layers.
The internal protection circuitry of the TPS75005 is designed to protect against overload conditions, and is not
intended to replace proper PCB design. Continuously running the TPS75005 into thermal shutdown degrades
device reliability.
This thermal shutdown function disables both LDO1 and LDO2, regardless of sequencer status. Releasing the
TSD restarts the power-up sequence.
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Undervoltage Lockout (UVLO)
The TPS75005 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry
is operating properly. The UVLO circuit has a hysteresis feature so that short undershoot transients are typically
ignored.
See Figure 11 for the actual measurement. See the section for how to set a custom threshold voltage for the
input voltage.
Within the TPS75005, UVLO is combined with EN to create an internal enable signal. A logic AND operation of
the EN input signal and internal UVLO signal is used to control the sequencer. By connecting EN to VIN, a logic
input buffer for the EN and UVLO circuit refer to the same electric node and the device can be controlled by
UVLO function because VUVLO is greater than VIH(EN). Figure 29 shows how to control the TPS75005 without a
signal source to the EN pin.
10 mF
IN
TPS75005
Sequencer
EN
Figure 29. TPS75005 without EN Signal Control
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SEQUENCER BLOCK
The TPS75005 integrates a sequencer logic circuit to control the power-up and power-down sequences of the
two output voltage rails (VDD and VDDIO) for C2000 controllers.
Application Report SBVA031, TPS75005 Advanced Information: Sequencer and State Machine, explains a state
machine of this sequencer logic in detail.
C2000 Power Sequencing
Depending on the C2000 controller series, the required power-up and power-down order of VDD and VDDIO can
be different, as shown in Table 1. Figure 30 and Figure 31 shows the typical waveforms of two different
sequencing cycles set by the SEQ pin.
Table 1. Required Power-Up and Power-Down Sequence of C2000 Controllers
POWER-UP ORDER
C2000
CONTROLLER
POWER-DOWN ORDER
1ST CHANNEL
TURNED ON
2ND CHANNEL
TURNED ON
1ST CHANNEL
TURNED OFF
F280x/F2801x
VDD
VDDIO
VDDIO
F281x
VDDIO
VDD
VDD
F2823x
VDD
VDDIO
VDDIO
F2833X
VDD
VDDIO
VDDIO
2ND CHANNEL
TURNED OFF
6
VDD
Logic-L
Figure 30
VDDIO
Logic-H
Figure 31
VDD
Logic-L
Figure 30
VDD
Logic-L
Figure 30
4
3
4
3
2
2
1
1
0
0
Time
Time
G000
Figure 30. Power Sequence with SEQ = L
EN
OUT1
OUT2
PG
5
Voltage (V)
Voltage (V)
TYPICAL
WAVEFORM
6
EN
OUT1
OUT2
PG
5
20
TPS75005
SEQ SETTING
G000
Figure 31. Power Sequence with SEQ = H
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SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
Normal Power-Up and Power-Down Sequence
Figure 32 shows oscilloscope waveforms of the TPS75005 in a normal power-up and power-down sequence with
SEQ = L. Refer to the time lines labeled Event A through Event H.
1.
Before Event A, the TPS75005 is idle, waiting for an enable event.
(Power-Up Sequence Begins)
2.
At Event A, EN goes to logic-H and the device immediately discharges a soft-start capacitor (CSS1) by
using a one-shot circuit. Then, the LDO1 soft-start circuit starts charging CSS1. The OUT1 voltage follows
the SS1 voltage. Time between Event A and Event B is defined as tSS1 and can be programmed by CSS1.
3.
At Event B, the OUT1 voltage exceeds the VSVS1 threshold and the SVS1 delay circuit starts charging
CCT1. Time between Event B and Event C is defined as td(SVS1) and can be programmed by CCT1.
4.
At Event C, the CT1 voltage exceeds the VCT1 threshold to discharge a soft-start capacitor (CSS2) using a
one-shot circuit. Then, the LDO2 soft-start circuit starts charging CSS2. The OUT2 voltage follows the
SS2 voltage. Time between Event C and Event D is defined as tSS2 and can be programmed by CSS2.
5.
At Event D, the OUT2 voltage exceeds the VSVS2 threshold and the SVS2 delay circuit starts charging
CCT2. Time between Event D and Event E is defined as td(SVS2) and can be programmed by CCT2.
(Power-Up Sequence Ends)
6.
At Event E, the CT2 voltage exceeds the VCT2 threshold and PG goes high to enable the C2000
controller. The TPS75005 is up and running as long as a disable or an error event occurs.
(Power-Down Sequence Begins)
7.
At Event F, EN goes to logic-L and the device immediately turns PG to logic-L so that the C2000
controller is disabled. Then, an internal signal EN2 goes to logic-L in order to disable LDO2. Because the
active pull-down switch is enabled by SW2 (= EN2) signal, the OUT2 voltage starts decreasing (note that
this ramp-down speed depends on the application circuits).
8.
At Event G, the OUT2 voltage underruns the VDOWN2 threshold and an internal signal EN1 goes into
logic-L in order to disable LDO1. Because the active pull-down switch is enabled by SW1 (= EN1) signal,
the OUT1 voltage starts decreasing (note that this ramp-down speed is depends on the application
circuits).
9.
At Event H, the OUT1 voltage underruns the VDOWN1 threshold to return back to the idle state.
(Power-Down Sequence Ends)
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21
TPS75005
H
nt
Ev
e
Ev
e
nt
F
nt
Ev
e
Ev
e
G
www.ti.com
nt
Ev A
en
tB
Ev
en
tC
Ev
en
tD
Ev
en
tE
SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
EN
SS1
2%
VSVS1
OUT1
VDOWN1
tSS1
VCT1
CT1
tD(SVS1)
SS2
2%
VSVS2
OUT2
VDOWN2
tSS2
VCT2
CT2
tD(SVS2)
PG
Figure 32. Normal Power-Up and Power-Down Timing
22
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TPS75005
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SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
THERMAL INFORMATION
Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 4:
PD = (VIN - VOUT) IOUT
(4)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the QFN (RGW) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an
appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-toambient thermal resistance depends on the maximum ambient temperature, maximum device junction
temperature, and power dissipation of the device and can be calculated using Equation 5:
RqJA =
+125°C - TA
PD
(5)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heat sinking can
be estimated using Figure 33.
120
100
qJA (°C/W)
80
60
qJA (RGW)
40
20
0
0
1
2
3
4
5
7
6
8
9
10
2
Board Copper Area (in )
2
NOTE: θJA value at a board size of 9-in (that is, 3-in × 3-in) is a JEDEC standard.
Figure 33. θJA vs Board Size
Figure 33 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.
NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as
explained in the Estimating Junction Temperature section.
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TPS75005
SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
www.ti.com
Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
Where:
PD is the power dissipation shown by Equation 5
TT is the temperature at the center-top of the device
TB is the PCB temperature measured 1 mm away from the device on the PCB surface (as Figure 35
shows).
(6)
NOTE: Both TT and TB can be measured on actual application boards using an infrared thermometer.
For more information about measuring TT and TB, see Application Report SBVA025, Using New Thermal Metrics,
available for download at www.ti.com.
By looking at Figure 34, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
12
YJT and YJB (°C/W)
10
YJB (RGW)
8
6
4
2
YJT (RGW)
0
0
2
4
6
8
10
2
Board Copper Area (in )
Figure 34. ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to Application Report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For
further information, refer to Application Report SPRA953, IC Package Thermal Metrics, also available on the TI
website.
TB on PCB
TT on top of IC
1mm
(a) Example RGW (QFN) Package Measurement
Figure 35. Measuring Points for TT and TB
24
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TPS75005
www.ti.com
SBVS144C – NOVEMBER 2011 – REVISED APRIL 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2012) to Revision C
Page
•
Changed Voltage Information table ...................................................................................................................................... 2
•
Added new note 2 to Thermal Information table .................................................................................................................. 3
•
Changed note 3(b) copper coverage value from 20% to 4% ............................................................................................... 3
•
Changed test condition for tD(SVS1) parameter ....................................................................................................................... 4
•
Changed test condition for tD(SVS2) parameter ....................................................................................................................... 5
•
Changed functional block diagram ....................................................................................................................................... 7
Changes from Revision A (February 2012) to Revision B
Page
•
Changed Thermal Information table values .......................................................................................................................... 3
•
Changed functional block diagram ....................................................................................................................................... 7
Changes from Original (November 2011) to Revision A
Page
•
Changed all "PowerPAD" to "thermal pad". .......................................................................................................................... 1
•
Added application report links to Description section ........................................................................................................... 1
•
Changed "VIN" to "IN" in front page diagram ....................................................................................................................... 1
•
Changed "VIN" to "IN" ............................................................................................................................................................ 6
•
Changed "VIN" to "input voltage" ........................................................................................................................................ 12
•
Changed caption for Figure 25 ........................................................................................................................................... 12
•
Changed Voltage Monitor Blocks section title and updated subsection order ................................................................... 17
•
Changed "VIN" to "IN" in Figure 28 .................................................................................................................................... 18
•
Changed "VIN" to "IN" in Figure 29 .................................................................................................................................... 19
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS75005RGWR
NRND
VQFN
RGW
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PPMQ
TPS75005RGWT
NRND
VQFN
RGW
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PPMQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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