TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
www.ti.com ............................................................................................................................................................ SGLS161A – APRIL 2003 – REVISED JUNE 2008
ULTRALOW NOISE, HIGH PSRR, FAST RF, 100-mA
LOW-DROPOUT LINEAR REGULATORS
FEATURES
1
• 100-mA Low-Dropout Regulator With EN
• Available in 1.8-V, 3.3-V, 4.7-V, and Adjustable
Versions
• High PSRR (70 dB at 10 kHz)
• Ultralow Noise (15 µVRMS)
• Fast Start-Up Time (63 µs)
• Stable With Any 1-µF Ceramic Capacitor
• Excellent Load/Line Transient
• Very Low Dropout Voltage
(38 mV at Full Load, TPS79147)
• 5-Pin SOT23 (DBV) Package
• TPS792xx Provides EN Options
2
APPLICATIONS
•
•
•
VCOs
RF
Bluetooth™, Wireless LAN
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
DESCRIPTION
The TPS791xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power supply rejection ratio (PSRR), ultralow noise,
fast start-up, and excellent line and load transient
responses in a small outline, SOT23, package. Each
device in the family is stable, with a small 1-µF
ceramic capacitor on the output. The family uses an
advanced, proprietary BiCMOS fabrication process to
yield extremely low dropout voltages (e.g., 38 mV at
100 mA, TPS79147). Each device achieves fast
start-up times (approximately 63 µs with a 0.001-µF
bypass capacitor) while consuming very low
quiescent current (170 µA typical). Moreover, when
the device is placed in standby mode, the supply
current is reduced to less than 1 µA. The TPS79118
exhibits approximately 15 µVRMS of output voltage
noise with a 0.1-µF bypass capacitor. Applications
with analog components that are noise sensitive,
such as portable RF electronics, benefit from the
high-PSRR and low-noise features as well as the fast
response time.
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
•
•
(1)
Custom temperature ranges available
TJ
–40°C to 125°C
OUTPUT
VOLTAGE
ORDERING INFORMATION (1)
PACKAGE (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
1.2 to 5.5 V
TPS79101DBVREP
PEUE
1.8 V
TPS79118DBVREP
PERE
TPS79133DBVREP
PESE
TPS79147DBVREP
PETE
TPS79133MDBVTEP
PIDM
3.3 V
SOT23 (DBV)
Reel of 3000
SOT23 (DBV)
Reel of 250
4.7 V
–55°C to 125°C
(1)
(2)
3.3 V
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
EN
3
OUT
100
4
DBV PACKAGE
(TOP VIEW)
IN
1
6
90
BYPASS
Fixed Option
OUT
GND
2
5
FB
EN
3
4
BYPASS
VI = 4.3 V
Co = 10 µF
C(byp) = 0.01 µF
80
IO = 100 mA
60
IO = 10 mA
40
30
Adjustable Option
20
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
0.4
0.35
VO = 4.3 V
Co = 1 µF
C(byp) = 0.1 µF
0.3
70
50
Hz
GND
5
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Output Spectral Noise Density −
1
Ripple Rejection − dB
IN
TPS79133
RIPPLE REJECTION
vs
FREQUENCY
µ V/
DBV PACKAGE
(TOP VIEW)
10 M
0.25
0.2
IO = 100 mA
0.15
0.1
IO = 1 mA
0.05
0
100
1k
10 k
f − Frequency − Hz
100 k
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
TPS79101, TPS79118,
TPS79133, TPS79147
Input voltage range (2)
–0.3 V to 6 V
Voltage range at EN
–0.3 V to VI + 0.3 V
Voltage on OUT
–0.3 V to 6 V
Peak output current
Internally limited
ESD rating, HBM
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
Operating virtual-junction temperature range, TJ
Operating ambient temperature range, TA
See Dissipation Rating Table
All others
–40°C to 150°C
TPS79133MDBVTEP
–55°C to 125°C
All others
–40°C to 120°C
TPS79133MBVTEP
–55°C to 125°C
Storage temperature range, Tstg
RθJC (3)
RθJA (4)
(1)
(2)
(3)
(4)
2
–65°C to 150°C
Low K
63.75°C/W
High K
63.75°C/W
Low K
256°C/W
High K
178.3°C/W
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top
of the board.
The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
Submit Documentation Feedback
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
www.ti.com ............................................................................................................................................................ SGLS161A – APRIL 2003 – REVISED JUNE 2008
RECOMMENDED OPERATING CONDITIONS
MI MA UNI
N
X T
Input voltage, VI (1)
2.7
Continuous output current, IO (2)
–40 125
Operating junction temperature, TJ
(1)
(2)
5.5
V
0 100 mA
TPS79133MBVTEP
–55 125
°C
To calculate the minimum input voltage for your maximum output current, use the following formula: VI(min) = VO(max) + VDO (max
load)
Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that
the device operate under conditions beyond those specified in this table for extended periods of time.
Notes:
1. See data sheet for absolute maximum and minimum recommended operating conditions.
2. Silicon operating-life design goal is 10 years at 105°C junction temperature (does not include
package interconnect life).
3. Enhanced plastic product disclaimer applies.
1000
Estimated Life (Years)
Electromigration Fail Mode
100
Wirebond Voiding
Fail Mode
10
1
100
110
120
130
140
150
160
Continuous T J (°C)
Figure 1. TPS79133 Operating Life Derating Chart
Copyright © 2003–2008, Texas Instruments Incorporated
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Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
3
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V,
Co = 10 µF, Co(byp) = 0.01 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TJ = 25°C, 1.22 V ≤ VO ≤ 5.2 V
TPS79101
0.98 VO
TJ = 25°C
TPS79118
1.836
3.234
TJ = 25°C
3.366
4.7
0 µA < IO < 100 mA, 5.2 V < VI < 5.5 V
4.606
0 µA < IO < 100 mA, TJ = 25°C
4.794
170
0 µA < IO < 100 mA
250
0 µA < IO < 100 mA, TJ = 25°C
Load regulation
5
VO + 1 V < VI ≤ 5.5 V, TJ = 25°C
Output voltage line regulation (ΔVO/VO) (2)
BW = 100 Hz to 100 kHz,
IO = 100 mA, TJ = 25°C
0.12
C(byp) = 0.001 µF
32
C(byp) = 0.0047 µF
17
C(byp) = 0.01 µF
16
C(byp) = 0.1 µF
15
C(byp) = 0.001 µF
53
C(byp) = 0.0047 µF
67
RL 33 Ω, CO = 1 µF,
TJ = 25°C
Output current limit
VO = 0 V (1)
285
600
UVLO threshold
VCC rising
2.25
2.65
UVLO hysteresis
TJ = 25°C, VCC rising
(1)
(2)
µs
98
100
mA
V
mV
The minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. The maximum IN voltage is 5.5 V. The maximum
output current is 100 mA.
If VO ≤ 1.8 V then VImin = 2.7 V, VImax = 5.5 V:
Line regulation (mV) + ǒ%ńVǓ
V
O
ǒV Imax * 2.7 VǓ
100
If VO ≥ 2.5 V then VImin = VO + 1 V, VImax = 5.5 V:
Line regulation (mV) + ǒ%ńVǓ
4
%/V
µVRMS
Time, start-up (TPS79133)
C(byp) = 0.01 µF
µA
mV
0.05
VO + 1 V < VI ≤ 5.5 V
Output noise voltage (TPS79118)
V
3.3
0 µA < IO < 100 mA, 4.3 V < VI < 5.5 V
Quiescent current (GND current)
1.02 VO
1.764
TJ = 25°C
TPS79147
UNIT
1.8
0 µA < IO < 100 mA, 2.8 V < VI < 5.5 V
TPS79133
MAX
VO
0 µA < IO < 100 mA (1), 1.22 V ≤ VO ≤ 5.2 V
Output voltage
TYP
ǒ
ǒ
1000
ǓǓ
VO V Imax * VO ) 1 V
100
Submit Documentation Feedback
1000
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
www.ti.com ............................................................................................................................................................ SGLS161A – APRIL 2003 – REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, (TJ = –40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V,
Co = 10 µF, Co(byp) = 0.01 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Standby current
EN = VI, 2.7 V < VI < 5.5 V
High-level enable input voltage
2.7 V < VI < 5.5 V
Low-level enable input voltage
2.7 V < VI < 5.5 V
Input current (EN)
EN = VI
TPS79118
Power supply ripple rejection
TPS79133
TPS79133
Dropout voltage (3)
TPS79147
(3)
MIN
TYP
MAX
0.07
1
2
µA
V
–1
f = 100 Hz, TJ = 25°C, IO = 10 mA
80
f = 100 Hz, TJ = 25°C, IO = 100 mA
75
f = 10 kHz, TJ = 25°C, IO = 100 mA
72
f = 100 kHz, TJ = 25°C, IO = 100 mA
45
f = 100 Hz, TJ = 25°C, IO = 10 mA
70
f = 100 Hz, TJ = 25°C, IO = 100 mA
75
f = 10 kHz, TJ = 25°C, IO = 100 mA
73
f = 100 kHz, TJ = 25°C, IO = 100 mA
37
IO = 100 mA, TJ = 25°C
50
IO = 100 mA
0.7
V
1
µA
dB
90
IO = 100 mA, TJ = 25°C
UNIT
38
IO = 100 mA
mV
70
IN voltage equals VO(typ) – 100 mV. The TPS79118 dropout voltage is limited by the input voltage range limitations.
Copyright © 2003–2008, Texas Instruments Incorporated
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5
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
VOUT
VIN
Current
Sense
UVLO
SHUTDOWN
ILIM
R1
_
GND
+
FB
EN
R2
UVLO
Thermal
Shutdown
External to
the Device
250 kΩ
Bandgap
Reference
VIN
Vref
Bypass
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
VOUT
VIN
UVLO
Current
Sense
GND
SHUTDOWN
ILIM
_
R1
+
EN
UVLO
R2
Thermal
Shutdown
VIN
Bandgap
Reference
250 kΩ
Vref
Bypass
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
ADJ
FIXED
BYPASS
4
4
EN
3
3
I
The EN terminal is an input which enables or shuts down the device. When EN is a logic
high, the device will be in shutdown mode. When EN is a logic low, the device will be
enabled.
FB
5
N/A
I
This terminal is the feedback input voltage for the adjustable device.
GND
2
2
IN
1
1
I
The IN terminal is the input to the device.
OUT
6
5
O
The OUT terminal is the regulated output of the device.
6
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An external bypass capacitor, connected to this terminal, in conjunction with an internal
resistor, creates a low-pass filter to further reduce regulator noise.
Regulator ground
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
www.ti.com ............................................................................................................................................................ SGLS161A – APRIL 2003 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS
TPS79118
TPS79133
TPS79118
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
3.303
VI = 2.8 V
Co = 10 µF
TJ = 25° C
3.302
V O − Output Voltage − V
1.801
1.8
1.799
1.798
1.797
1.815
3.301
3.3
3.299
3.298
20
40
60
80
IO − Output Current − mA
100
0
20
40
60
80
1.78
−40 −25 −10 5
100
20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 3.
Figure 4.
TPS79118
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
GROUND CURRENT
vs
JUNCTION TEMPERATURE
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Hz
260
VI = 4.3 V
Co = 10 µF
Ground Current − µ A
IO = 1 mA
3.3
3.29
IO = 100 mA
3.28
µ V/
220
200
IO = 1 mA
180
IO = 100 mA
160
140
120
3.27
−40 −25 −10 5
100
20 35 50 65 80 95 110 125
−40 −25 −10 5
TJ − Junction Temperature − °C
0.2
0.18
20 35 50 65 80 95 110 125
Output Spectral Noise Density −
240
3.31
0.14
0.12
IO = 100 mA
0.1
0.08
IO = 1 mA
0.06
0.04
0.02
0
100
TJ − Junction Temperature − °C
Figure 5.
VI = 2.8 V
Co = 1 µF
C(byp) = 0.1 µF
0.16
1k
10 k
f − Frequency − Hz
Figure 6.
100 k
Figure 7.
TPS79118
TPS79118
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
IO = 1 mA
µ V/
Output Spectral Noise Density −
0.2
VI = 2.8 V
Co = 10 µF
C(byp) = 0.1 µF
0.15
IO = 100 mA
0.1
0.05
0
100
1k
10 k
f − Frequency − Hz
100 k
Figure 8.
Copyright © 2003–2008, Texas Instruments Incorporated
1.2
IO = 0.001 µF
1
VI = 2.8 V
IO = 100 mA
Co = 10 µF
IO = 0.1 µF
0.6
IO = 0.01 µF
0.4
0.2
0
100
1k
10 k
f − Frequency − Hz
VI = 4.3 V
Co = 1 µF
C(byp) = 0.1 µF
0.3
IO = 0.0047 µF
0.8
0.4
0.35
Output Spectral Noise Density −
Hz
0.25
Hz
V O − Output Voltage − V
IO = 100 mA
1.79
TPS79133
VI = 4.3 V
Co = 10 µF
Hz
1.795
TPS79133
3.32
µ V/
IO = 1 mA
1.8
IO − Output Current − mA
Figure 2.
Output Spectral Noise Density −
1.81
1.785
3.297
0
VI = 2.8 V
Co = 10 µF
1.805
µ V/
V O − Output Voltage − V
1.802
1.82
VI = 4.3 V
Co = 10 µF
TJ = 25° C
V O − Output Voltage − V
1.803
100 k
0.25
0.2
IO = 100 mA
0.15
0.1
IO = 1 mA
0.05
0
100
Figure 9.
1k
10 k
f − Frequency − Hz
100 k
Figure 10.
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Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
7
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
0.25
IO = 100 mA
0.2
0.15
IO = 1 mA
0.1
0.05
0
100
1k
10 k
f − Frequency − Hz
IO = 0.001 µF
1.6
1.4
IO = 0.0047 µF
1.2
IO = 0.1 µF
1
0.8
IO = 0.01 µF
0.6
0.4
0.2
0
1k
100
100 k
10 k
30
VO = 1.8 V
20
10
0
0.001
µ V (RMS)
Figure 13.
TPS792133
OUTPUT IMPEDANCE
vs
FREQUENCY
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
100
VI = 3.2 V,
Co = 10 µF
2
IO = 1 mA
1.5
1
IO = 100 mA
0.5
60
50
IO = 100 mA
40
30
20
0
100
1k
10 k 100 k
1M
10 M
Figure 14.
IO = 10 mA
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
Minimum Required Input Voltage − V
IO = 100 mA
100
TJ = 125°C
80
TJ = 25°C
40
TJ = −40°C
20
4
4.5
60
TJ = 25°C
50
40
30
20
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
4.7
TJ = −40°C
0
5
0.02
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0.06
0.08
0.1
Figure 16.
TPS79118
RIPPLE REJECTION
vs
FREQUENCY
90
IO = 1 mA
80
TJ = 125°C
3.7
TJ = −40°C
3.2
TJ = 25°C
2.7
70
60
50
40
30
20
10
2
2.5
3
3.5
4
VO − Output Voltage − V
4.5
5
IO = 100 mA
0
100
VI = 2.8 V
Co = 10 µF
C(byp) = 0.01 µF
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
VI − Input Voltage − V
Figure 17.
0.04
IO − Output Current − A
VI = 3.2 V
Co = 10 µF
4.2
2.2
1.5
3.5
TJ = 125°C
70
10
5.2
120
3
80
Figure 15.
MINIMUM REQUIRED INPUT VOLTAGE
vs
OUTPUT VOLTAGE
TPS79101
60
VI = 3.2 V
CO = 10 µF
90
V DO − Dropout Voltage − mV
V DO − Dropout Voltage − mV
70
f − Frequency − Hz
8
0.1
0.01
C(bypass) − Bypass Capacitance − µF
Figure 12.
10
V DO − Dropout Voltage − mV
VO = 3.3 V
40
100 k
80
0
2.5
50
TPS79133
VI = 4.3 V
Co = 10 µF
TJ = 25°C
0
10
BW = 100 Hz to 100
kHz
60
TPS79133
3
2.5
70
f − Frequency − Hz
Figure 11.
Z o − Output Impedance − Ω
VI = 4.3 V
IO = 100 mA
Co = 10 µF
Ripple Rejection − dB
Output Spectral Noise Density −
1.8
VI = 4.3 V
Co = 10 µF
C(byp) = 0.1 µF
0.3
2
ROOT MEAN SQUARED OUTPUT NOISE
vs
BYPASS CAPACITANCE
RMS − Root Mean Squared Output Noise −
Hz
0.35
µ V/
0.4
Output Spectral Noise Density −
Hz
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
µ V/
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Figure 18.
Figure 19.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
www.ti.com ............................................................................................................................................................ SGLS161A – APRIL 2003 – REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
TPS79118
TPS79118
TPS79133
RIPPLE REJECTION
vs
FREQUENCY
RIPPLE REJECTION
vs
FREQUENCY
RIPPLE REJECTION
vs
FREQUENCY
80
IO = 10 mA
Ripple Rejection − dB
70
60
50
40
IO = 100 mA
30
20
0
100
1k
10 k
70
60
50
40
30
IO = 100 mA
20
VI = 2.8 V
Co = 1 µF
C(byp) = 0.01 µF
10
1M
0
100
10 M
1k
10 k
60
50
40
30
20
100 k
1M
10 M
10
1k
10 k 100 k
f − Frequency − Hz
1M
10 M
Figure 21.
TPS79133
TPS79133
Figure 22.
RIPPLE REJECTION
vs
FREQUENCY
RIPPLE REJECTION
vs
FREQUENCY
OUTPUT VOLTAGE, ENABLE VOLTAGE
vs
TIME (START-UP)
100
60
IO = 10 mA
30
20
20
Figure 23.
Copyright © 2003–2008, Texas Instruments Incorporated
1
0
C(byp) = 0.001 µF
IO = 10 mA
50
30
10 M
VI = 4.3 V
VO = 3.3 V
IO = 100 mA
Co = 1 µF
TJ = 25°C
2
60
40
1M
IO = 100 mA
70
40
1k
10 k 100 k
f − Frequency − Hz
Enable Voltage − V
70
80
3
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
10 M
V O − Output Voltage − V
IO = 100 mA
100
VI = 4.3 V
Co = 1 µF
C(byp) = 0.1 µF
90
Ripple Rejection − dB
80
10
100
Figure 20.
VI = 4.3 V
CO = 1 µF
C(byp) = 0.01 µF
50
IO = 10 mA
TPS79133
100
90
IO = 100 mA
70
f − Frequency − Hz
f − Frequency − Hz
Ripple Rejection − dB
80
VI = 2.8 V
Co = 1 µF
C(byp) = 0.1 µF
10
100 k
VI = 4.3 V
Co = 10 µF
C(byp) = 0.01 µF
90
IO = 10 mA
Ripple Rejection − dB
80
Ripple Rejection − dB
100
90
90
3
2
C(byp) = 0.0047 µF
1
C(byp) = 0.01 µF
0
0
20 40
60 80 100 120 140 160 180 200
t − Time − µs
Figure 24.
Figure 25.
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9
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com
TPS79118
TPS79118
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
∆ VO − Change In
Output Voltage − mV
− Output Voltage − mV
TYPICAL CHARACTERISTICS (continued)
IO = 100 mA
Co = 1 µF
C(byp) = 0.01 µF
− Input Voltage − V V
O
10
0
0
−20
−40
Current Load − mA
−10
100
2.8
V O − Output Voltage − mV
0
10 20
30 40 50
0
0
60 70 80 90 100
200 400 600 800 1 k 12 k 14 k 16 k 18 k 2 k
t − Time − µs
t − Time − µs
Figure 26.
Figure 27.
TPS79133
TPS79133
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
∆ V − Change In
O
I O − Output Current − mA Output Voltage − mV
V
I
3.8
V I − Input Voltage − V
VI = 2.8 V
Co = 10 µF
20
20
0
−20
5.3
4.3
IO = 100 mA
Co = 1 µF
C(byp) = 0.01 µF
0
5
10
15 20
dv
0.4 V
+
µs
dt
25
30
35 40
45 50
t − Time − µs
VI = 4.3 V
Co = 10 µF
20
0
−20
−40
100
0
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
TPS79118
TPS79118
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
10
Region of Instability
1
0.1
Region of
Instability
0.01
0.02
0.04
0.06
0.08
0.1
IO − Output Current − A
Figure 30.
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100
Ω
Co = 0.47 µF
VI = 5.5 V
TJ = −40 °C to 125°C
Co = 1 µF
VI = 5.5 V
TJ = −40 °C to 125°C
ESR − Equivalent Series Resistance −
100
Ω
TPS79118
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
0
10
Figure 29.
ESR − Equivalent Series Resistance −
ESR − Equivalent Series Resistance −
Ω
Figure 28.
10
Region of Instability
1
0.1
Region of Stability
0.01
0
0.02
0.04
0.06
0.08
IO − Output Current − A
0.1
100
Co = 10 µF
VI = 5.5 V
TJ = −40 °C to 125°C
10
Region of Instability
1
0.1
Region of Stability
0.01
0
0.02
0.04
0.06
0.08
0.1
IO − Output Current − A
Figure 31.
Figure 32.
Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
www.ti.com ............................................................................................................................................................ SGLS161A – APRIL 2003 – REVISED JUNE 2008
APPLICATION INFORMATION
The TPS791xx family of low-dropout (LDO) regulators have been optimized for use in noise-sensitive
battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output
noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA
when the regulator is turned off.
A typical application circuit is shown in Figure 33.
TPS791xx
1
VI
IN
BYPASS
OUT
0.1 µF
4
5
VO
3
0.01 µF
EN
+
GND
1 µF
2
Figure 33. Typical Application Circuit
External Capacitor Requirements
A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS791xx, is required for stability and to improve transient response, noise rejection, and ripple rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
Like all low dropout regulators, the TPS791xx requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitance is 1 µF. Any 1-µF or larger ceramic
capacitor is suitable. The device is also stable with a 0.47-µF ceramic capacitor with at least 75 mΩ of ESR.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS791xx has a BYPASS pin
which is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to reduce
the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the BYPASS pin must be at a minimum because any leakage current creates an
IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have
minimal leakage current.
For example, the TPS79118 exhibits approximately 15 µVRMS of output voltage noise using a 0.1-µF ceramic
bypass capacitor and a 1-µF ceramic output capacitor. Note that the output starts up slower as the bypass
capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250 kΩ
resistor and external capacitor.
Board Layout Recommendation To Improve PSRR And Noise Performance
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board
be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground
pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
ground pin of the device.
Copyright © 2003–2008, Texas Instruments Incorporated
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11
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com
Power Dissipation and Junction Temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max).
The maximum power-dissipation limit is determined using the following equation:
T max * T
A
P
+ J
D(max)
R
qJA
(1)
Where:
TJmax is the maximum allowable junction temperature.
RθJA is the junction-to-ambient thermal resistance for the package (see the dissipation rating table).
TA is the ambient temperature.
The regulator dissipation is calculated using:
P
D
ǒ
+ V *V
I
O
Ǔ
I
O
(2)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
Programming the TPS79101 Adjustable LDO Regulator
The output voltage of the TPS79101 adjustable regulator is programmed using an external resistor divider as
shown in Figure 34. The output voltage is calculated using:
V
O
+V
ref
ǒ1 ) R1
Ǔ
R2
(3)
Where:
Vref = 1.2246 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should be
avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases VO. The recommended
design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA, C1 = 15 pF for stability, and then
calculate R1 using:
R1 +
ǒ
V
V
Ǔ
O *1
ref
R2
(4)
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be
placed between OUT and FB. For voltages 1.8 V, the approximate value of this capacitor can be calculated as:
(3 10*7) (R1 ) R2)
C1 +
(R1 R2)
(5)
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is
not used (such as in a unity-gain configuration) or if an output voltage < 1.8 V is chosen, then the minimum
recommended output capacitor is 2.2 µF instead of 1 µF.
12
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Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP
TPS79101-EP, TPS79118-EP
TPS79133-EP, TPS79147-EP
www.ti.com ............................................................................................................................................................ SGLS161A – APRIL 2003 – REVISED JUNE 2008
TPS79101
VI
OUTPUT VOLTAGE
PROGRAMMING GUIDE
IN
1 µF
EN
≥2V
OUT
VO
C1
R1
≤ 0.7 V
BYPASS FB
GND
0.01 µF
1 µF
OUTPUT
VOLTAGE
R1
R2
C1
2.5 V
31.6 kΩ 30.1 kΩ
22 pF
3.3 V
51 kΩ 30.1 kΩ
15 pF
3.6 V
59 kΩ 30.1 kΩ
15 pF
R2
Figure 34. TPS79101 Adjustable LDO Regulator Programming
Regulator Protection
The TPS791xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be
appropriate.
The TPS791xx features internal current limiting and thermal protection. During normal operation, the TPS791xx
limits output current to approximately 400 mA. When current limiting engages, the output voltage scales back
linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum
voltage ratings of the device. If the temperature of the device exceeds approximately 165°C, thermal-protection
circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator operation
resumes.
Copyright © 2003–2008, Texas Instruments Incorporated
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13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS79101DBVREP
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PEUE
TPS79133DBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PESE
TPS79133MDBVTEP
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PIDM
TPS79147DBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PETE
V62/03644-01YE
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PEUE
V62/03644-03XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PESE
V62/03644-04XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PETE
V62/03644-05XE
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PIDM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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