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TPS79601, TPS79613, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633, TPS79650
SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
TPS796xx Ultralow-Noise, High PSRR, Fast, RF, 1-A Low-Dropout Linear Regulators
1 Features
3 Description
•
•
The TPS796 family of low-dropout (LDO) low-power
linear voltage regulators features high power-supply
rejection ratio (PSRR), ultralow-noise, fast start-up,
and excellent line and load transient responses in
small outline, 3 × 3 VSON, SOT223-6, and TO-263
packages. Each device in the family is stable with a
small, 1-μF ceramic capacitor on the output. The
family uses an advanced, proprietary BiCMOS
fabrication process to yield extremely low dropout
voltages (for example, 250 mV at 1 A). Each device
achieves fast start-up times (approximately 50 μs with
a 0.001-μF bypass capacitor) while consuming very
low quiescent current (265 μA typical). Moreover,
when the device is placed in standby mode, the
supply current is reduced to less than 1 μA. The
TPS79630 exhibits approximately 40 μVRMS of output
voltage noise at 3.0-V output, with a 0.1-μF bypass
capacitor. Applications with analog components that
are noise sensitive, such as portable RF electronics,
benefit from the high PSRR, low noise features, and
need fast response time.
1
•
•
•
•
•
•
•
1-A Low-Dropout Regulator With Enable
Available in Fixed and Adjustable (1.2 V to 5.5 V)
Versions
High PSRR (53 dB at 10 kHz)
Ultralow-Noise (40 μVRMS, TPS79630)
Fast Start-Up Time (50 μs)
Stable With a 1-μF Ceramic Capacitor
Excellent Load and Line Transient Response
Very Low Dropout Voltage (250 mV at Full Load,
TPS79630)
3 × 3 VSON PowerPAD™, SOT223-6, and
TO-263 Packages
2 Applications
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth®, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
Device Information(1)
PART NUMBER
TPS796
PACKAGE
BODY SIZE (NOM)
VSON (8)
3.00 mm × 3.00 mm
SOT-223 (6)
6.50 mm × 3.50 mm
TO-263 (5)
10.16 mm × 8.42 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Ripple Rejection vs Frequency
TPS79630
Ripple Rejection (dB)
70
VIN = 4 V
COUT = 10 mF
CNR = 0.01 mF
IOUT = 1 mA
60
50
IOUT = 1 A
40
30
20
10
0
1
10
100
1k
10 k
Frequency (Hz)
100 k
1M
10 M
Output Spectral Noise Density (mV/ÖHz)
Output Spectral Noise Density vs Frequency
TPS79630
80
0.7
0.6
VIN = 5.5 V
COUT = 2.2 mF
CNR = 0.1 mF
0.5
0.4
IOUT = 1 A
0.3
0.2
0.1
IOUT = 1.5 A
0
100
1k
10 k
100 k
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS79601, TPS79613, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633, TPS79650
SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
7
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
8.3 Do's and Don'ts ...................................................... 17
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1
10.2
10.3
10.4
Layout Guidelines .................................................
Layout Examples...................................................
Thermal Considerations ........................................
Estimating Junction Temperature ........................
17
18
19
20
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (November 2013) to Revision P
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed front-page figure; updated graph style, replaced device pinouts with application circuits ..................................... 1
•
Changed Pin Configuration and Functions section; updated table format and added pinout drawings................................. 3
•
Changed "free-air" to "junction" temperature in condition statement for Absolute Maximum Ratings .................................. 4
•
Changed VOUT accuracy for TPS79601, test conditions and specified values ...................................................................... 6
•
Deleted Start-up time symbol ................................................................................................................................................. 6
•
Added Thermal shutdown temperature specification to Electrical Characteristics ................................................................ 6
•
Added Operating junction temperature specification to Electrical Characteristics ................................................................ 6
•
Added condition statement to Typical Characteristics ........................................................................................................... 7
Changes from Revision N (January 2011) to Revision O
Page
•
Changed Power-Supply Ripple Rejection 3rd test condition from "f = 10 Hz" to "f = 10 kHz" (typo) .................................... 6
•
Changed Power-Supply Ripple Rejection 4th test condition from "f = 100 Hz" to "f = 100 kHz" (typo) ................................ 6
Changes from Revision M (October 2010) to Revision N
•
Page
Corrected typo in front-page figure......................................................................................................................................... 1
Changes from Revision L (August 2010) to Revision M
•
2
Page
Corrected typo in Figure 32 ................................................................................................................................................. 21
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650
TPS79601, TPS79613, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633, TPS79650
www.ti.com
SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
5 Pin Configuration and Functions
DCQ Package
6-Pin SOT-223
Top View
KTT Package
5-Pin TO-263
Top View
6
1
2
EN
3
1
IN
2
GND
3
OUT
4
NR/FB
5
NR/FB
GND
IN
5
4
EN
OUT
DRB Package
8-Pin VSON
Top View
1
8
EN
IN 2
7
N/C
IN
OUT 3
6
GND
OUT 4
5
NR/FB
Pin Functions
PIN
I/O
DESCRIPTION
8
I
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into shutdown mode. EN can be connected to IN if not used.
5
5
I
This terminal is the feedback input voltage for the adjustable device.
3, Tab
6,
PowerPAD
—
IN
2
1, 2
I
N/C
—
7
—
Not internally connected. This pin must either be left open, or tied to GND.
NR
5
5
—
Connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap. This improves power-supply rejection and reduces output noise.
OUT
4
3, 4
O
Output of the regulator.
SOT223
TO-263
VSON
EN
1
FB
NAME
GND
Copyright © 2002–2015, Texas Instruments Incorporated
Regulator ground
Unregulated input to the device.
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3
TPS79601, TPS79613, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633, TPS79650
SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
Voltage
(1)
MIN
MAX
IN
–0.3
6
EN
–0.3
VIN + 0.3
OUT
Peak output
Power dissipation
Continuous total
(1)
V
6
Current
Temperature
UNIT
Internally limited
See Thermal Information
Junction, TJ
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VIN
Input voltage
IOUT
Output current
TJ
Operating junction temperature
4
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NOM
MAX
UNIT
2.7
5.5
V
0
1
A
–40
125
°C
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650
TPS79601, TPS79613, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633, TPS79650
www.ti.com
SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
6.4 Thermal Information
TPS796xx (3)
THERMAL METRIC (1)
(2)
DRB (VSON)
DCQ
(SOT-223)
KTT (TO-263)
8 PINS
6 PINS
5 PINS
25
RθJA
Junction-to-ambient thermal resistance
47.8
70.4
RθJC(top)
Junction-to-case (top) thermal resistance
83
70
35
RθJB
Junction-to-board thermal resistance
N/A
N/A
N/A
ψJT
Junction-to-top characterization parameter
2.1
6.8
1.5
ψJB
Junction-to-board characterization parameter
17.8
30.1
8.52
RθJC(bot)
Junction-to-case (bottom) thermal resistance
12.1
6.3
0.4
(1)
(2)
(3)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
. ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3 × 2 thermal via array.
. iii. KTT: The exposed pad is connected to the PCB ground layer through a 5 × 4 thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
. ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see Power Dissipation and Estimating Junction Temperature.
Copyright © 2002–2015, Texas Instruments Incorporated
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TPS79601, TPS79613, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633, TPS79650
SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
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6.5 Electrical Characteristics
Over recommended operating temperature range (TJ = –40°C to 125°C), VEN = VIN,, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, COUT
= 10 μF, and CNR = 0.01 μF, unless otherwise noted. Typical values are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
VIN
Input voltage (1)
2.7
VFB
Internal reference (TPS79601)
1.2
IOUT
Continuous output current
Output voltage
range
TPS79601
Accuracy
ΔVO(ΔVI)
Line regulation
ΔVO(ΔIO)
Load regulation
Dropout voltage (3)
(VIN = VOUT(nom) –
0.1 V)
VDO
V
0
1
A
1.225
5.5 – VDO
V
1.02VOUT(nom)
V
0.98VOUT(nom)
–2%
Fixed VOUT = 5 V
0 μA ≤ IOUT ≤ 1 A, VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V (1)
–3%
VOUT + 1 V ≤ VIN ≤ 5.5 V
VOUT(nom)
2%
3%
0.12
5
IOUT = 1 A
TPS79628DRB
IOUT = 250 mA
52
90
TPS79630
IOUT = 1 A
250
345
TPS79633
IOUT = 1 A
220
325
TPS79650
IOUT = 1 A
200
300
VOUT = 0 V
IGND
Ground pin current
0 μA ≤ IOUT ≤ 1 A
ISHDN
Shutdown current (4)
VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V
IFB
Feedback pin current
VFB = 1.225 V
Power-supply rejection ratio
(TPS79630)
270
Output noise voltage (TPS79630)
Start-up time (TPS79630)
A
265
385
μA
0.07
1
μA
1
µA
59
f = 100 Hz, IOUT = 1 A
54
f = 10 kHz, IOUT = 1A
53
RL = 3 Ω,
COUT = 1 μF
mV
4.2
f = 100 Hz. IOUT = 10 mA
BW = 100 Hz to 100 kHz,
IOUT = 1 A
365
2.4
f = 100 kHz, IOUT = 1 A
%/V
mV
TPS79628
Output current limit
Vn
1.225
0.05
0 μA ≤ IOUT ≤ 1 A
ICL
PSRR
V
0 μA ≤ IOUT ≤ 1 A, VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V (1)
(1)
UNIT
1.25
Fixed VOUT < 5 V
0 μA ≤ IOUT ≤ 1 A, VOUT(nom) + 1 V ≤ VIN ≤ 5.5 V
MAX
5.5
(1)
TPS79601
VOUT
(2)
TYP
dB
42
CNR = 0.001 μF
54
CNR = 0.0047 μF
46
CNR = 0.01 μF
41
CNR = 0.1 μF
40
CNR = 0.001 μF
50
CNR = 0.0047 μF
μVRMS
μs
75
CNR = 0.01 μF
110
VEN(HI)
Enable high (enabled)
2.7 V ≤ VIN ≤ 5.5 V
1.7
VIN
VEN(LO)
Enable low (shutdown)
2.7 V ≤ VIN ≤ 5.5 V
0
0.7
V
IEN(HI)
Enable pin current, enabled
VEN = 0 V
–1
1
μA
Undervoltage lockout
VCC rising
2.25
UVLO
Hysteresis
Tsd
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
6
2.65
100
Shutdown, temperature increasing
165
Reset, temperature decreasing
140
–40
V
V
mV
°C
125
°C
Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater. TPS79650 is tested at VIN = 5.5 V.
Tolerance of external resistors not included in this specification.
VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7 V.
For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
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SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
6.6 Typical Characteristics
At VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C, unless otherwise
noted.
2.795
4
3.05
VIN = 4 V
COUT = 10 mF
TJ = 25°C
3.04
3.03
VIN = 3.8 V
COUT = 10 mF
IOUT = 1 mA
3
2.790
3.02
3.00
VOUT (V)
VOUT (V)
3.01
2.99
2.98
2
2.785
IOUT = 1 A
2.780
1
2.97
2.96
2.95
0.0
0.2
0.4
0.6
0.8
2.775
0
−40 −25 −10 5
1.0
20 35 50 65 80 95 110 125
IOUT (A)
TJ (°C)
Figure 1. TPS79630 Output Voltage vs Output Current
Figure 2. TPS79628 Output Voltage vs
Junction Temperature
350
Output Spectral Noise Density − mV/ÖHz
340
0.7
VIN = 3.8 V
COUT = 10 mF
IGND (mA)
330
320
IOUT = 1 A
310
IOUT = 1 mA
300
290
−40 −25 −10 5
20 35 50 65 80 95 110 125
VIN = 5.5 V
COUT = 2.2 mF
CNR = 0.1 mF
0.5
0.4
0.3
IOUT = 1 mA
0.2
0.1
IOUT = 1.5 A
0.0
100
1k
10k
100k
TJ (°C)
Frequency (Hz)
Figure 3. TPS79628 Ground Current vs
Junction Temperature
Figure 4. TPS79630 Output Spectral Noise Density vs
Frequency
2.5
Output Spectral Noise Density − mV/ÖHz
0.6
Output Spectral Noise Density − mV/ÖHz
0.6
VIN = 5.5 V
COUT = 10 mF
CNR = 0.1 mF
0.5
0.4
0.3
IOUT = 1 mA
0.2
IOUT = 1 A
0.1
0.0
100
1k
10k
100k
Frequency (Hz)
Figure 5. TPS79630 Output Spectral Noise Density vs
Frequency
Copyright © 2002–2015, Texas Instruments Incorporated
2.0
CNR = 0.01 mF
VIN = 5.5 V
COUT = 10 mF
IOUT = 1 A
CNR = 0.1 mF
1.5
CNR = 0.0047 mF
1.0
CNR = 0.001 mF
0.5
0.0
100
1k
10k
100k
Frequency (Hz)
Figure 6. TPS79630 Output Spectral Noise Density vs
Frequency
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Typical Characteristics (continued)
60
350
VIN = 2.7 V
COUT = 10 mF
300
50
IOUT = 1 A
250
40
VDO (mV)
RMS − Root Mean Squared Output Noise − mVRMS
At VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C, unless otherwise
noted.
30
200
150
20
100
IOUT = 250 mA
COUT = 10 mF
BW = 100 Hz to 100 kHz
10
0
0.001 mF
0.0047 mF
50
0.01 mF
IOUT = 250 mA
0
-40-25-10 5 20 35 50 65 80 95 110 125
0.1 mF
CNR (mF)
TJ (°C)
Figure 7. TPS79630 Root Mean Squared Output Noise vs
Bypass Capacitance
Figure 8. TPS79628 Dropout Voltage vs
Junction Temperature
80
80
IOUT = 1 mA
Ripple Rejection − dB
60
50
IOUT = 1 A
40
30
IOUT = 1 mA
60
50
IOUT = 1 A
40
30
20
20
10
10
0
0
1
10
1k
100
10k 100k
1M
10
1
10M
100
1k
10k 100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 9. TPS79630 Ripple Rejection vs Frequency
Figure 10. TPS79630 Ripple Rejection vs Frequency
3
80
70
IOUT = 1 mA
VIN = 4 V
COUT = 2.2 mF
CNR = 0.01 mF
VIN = 4 V,
COUT = 10 mF,
IOUT = 1.0 A
2.75
2.50
60
CNR =
0.0047 mF
2.25
IOUT = 1 A
40
30
Enable
CNR =
0.001 mF
2
50
VOUT (V)
Ripple Rejection − dB
VIN = 4 V
COUT = 10 mF
CNR = 0.1 mF
70
Ripple Rejection − dB
70
VIN = 4 V
COUT = 10 mF
CNR = 0.01 mF
1.75
1.50
CNR =
0.01 mF
1.25
1
20
0.75
10
0.50
0.25
0
0
1
8
10
100
1k
10k 100k
1M
10M
0
100
200
300
400
500
Frequency (Hz)
t (µs)
Figure 11. TPS79630 Ripple Rejection vs Frequency
Figure 12. Start-Up Time
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600
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SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
Typical Characteristics (continued)
5
6
4
5
VIN (V)
VIN (V)
At VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C, unless otherwise
noted.
3
2
IOUT = 1 A
COUT = 10 mF
CNR = 0.01 mF
40
1V
µs
4
IOUT = 1 A
COUT = 10 mF
CNR = 0.01 mF
3
40
20
DVOUT (mV)
DVOUT (mV)
dv
dt
0
−20
dv
dt
20
0
−20
−40
−40
0
0
20 40 60 80 100 120 140 160 180 200
20 40 60 80 100 120 140 160 180 200
t (ms)
t (ms)
4.0
1
3.5
VOUT = 2.5 V
RL = 10 W
CNR = 0.01 mF
3.0
0
150
DVOUT (mV)
Figure 14. TPS79630 Line Transient Response
2
VIN = 3.8 V
COUT = 10 mF
CNR = 0.01 mF
di
dt
1A
µs
75
500 mV/Div
IOUT (A)
Figure 13. TPS79618 Line Transient Response
−1
1V
µs
2.5
2.0
1.5
VIN
0
1.0
−75
0.5
−150
0
VOUT
0
0
100 200 300 400 500 600 700 800 900 1000
1
2
3
4
5
6
7
8
9
10
200 ms/Div
t (ms)
Figure 15. TPS79628 Load Transient Response
Figure 16. TPS79625 Power Up/Power Down
350
300
300
250
TJ = 125°C
TJ = 125°C
250
200
VDO (mV)
VDO (mV)
200
TJ = 25°C
150
100
TJ = −40°C
TJ = 25°C
150
TJ = −40°C
100
IOUT = 1 A
COUT = 10 µF
CNR = 0.01 µF
50
50
0
0
0 100 200 300 400 500 600 700 800 9001000
2.5
3.0
3.5
4.0
4.5
5.0
IOUT (mA)
VIN (V)
Figure 17. TPS79630 Dropout Voltage vs Output Current
Figure 18. TPS79601 Dropout Voltage vs Input Voltage
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Typical Characteristics (continued)
At VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF, CIN = 2.2 µF, and TJ = 25°C, unless otherwise
noted.
100
ESR − Equivalent Series Resistance − W
ESR − Equivalent Series Resistance − W
100
COUT = 1 µF
Region of
Instability
10
1
Region of Stability
0.1
COUT = 2.2 mF
Region of
Instability
10
1
Region of Stability
0.1
0.01
0.01
1
10
30
60
1
125 250 500 750 1000
10
30
60
125 250 500 750 1000
IOUT (mA)
Figure 19. TPS79630 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
Figure 20. TPS79630 Typical Regions of Stability Equivalent
Series Resistance (ESR) vs Output Current
ESR − Equivalent Series Resistance − W
IOUT (mA)
100
COUT = 10.0 mF
Region of
Instability
10
1
Region of Stability
0.1
0.01
1
10
30
60
125 250 500 750 1000
IOUT (mA)
Figure 21. TPS79630 Typical Regions of Stability Equivalent Series Resistance (ESR) vs Output Current
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7 Detailed Description
7.1 Overview
The TPS796 family of low-dropout (LDO) regulators combines the high performance required of many RF and
precision analog applications with low current consumption. High PSRR is provided by a high-gain, highbandwidth error loop with good supply rejection at very low headroom (VIN – VOUT). A noise-reduction pin is
provided to bypass noise generated by the band-gap reference and to improve PSRR, while a quick-start circuit
quickly charges this capacitor at start-up. All versions have thermal and overcurrent protection, and are fully
specified from –40°C to 125°C.
7.2 Functional Block Diagrams
IN
OUT
UVLO
Current
Sense
SHUTDOWN
ILIM
GND
R1
FB
EN
UVLO
Thermal
Shutdown
Quickstart
Bandgap
Reference
1.225 V
VIN
R2
External to
the device
VREF
250 kW
Figure 22. Functional Block Diagram—Adjustable Version
IN
OUT
UVLO
Current
Sense
SHUTDOWN
ILIM
GND
R1
EN
UVLO
Thermal
Shutdown
VIN
Bandgap
Reference
1.225 V
R2
R2 = 40 kW
Quickstart
VREF
NR
250 kW
Figure 23. Functional Block Diagram—Fixed Version
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7.3 Feature Description
7.3.1 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
7.3.2 Start-Up
The TPS796 uses a start-up circuit to quickly charge the noise reduction capacitor, CNR, if present (see the
Functional Block Diagrams). This circuit allows for the combination of very low output noise and fast start-up
times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are
appropriate for this configuration.
For the fastest start-up, apply VIN first, and then drive the enable pin (EN) high. If EN is tied to IN, start-up is
somewhat slower. To ensure that CNR is fully charged during start-up, use a 0.1-μF or smaller capacitor.
7.3.3 Undervoltage Lockout (UVLO)
The TPS796 uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating
properly. The UVLO circuit has approximately 100 mV of hysteresis to help reject input voltage drops when the
regulator first turns on.
7.3.4 Regulator Protection
The TPS796xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power-down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting
might be appropriate.
The TPS796xx features internal current limiting and thermal protection. During normal operation, the TPS796xx
limits output current to approximately 2.8 A. When current limiting engages, the output voltage scales back
linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device
exceeds approximately 165°C (Tsd), thermal-protection circuitry shuts it down. Once the device has cooled down
to below approximately 140°C, regulator operation resumes.
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7.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
TJ
Normal
VIN > VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < TSD
Dropout
VIN < VOUT(nom) + VDO
VEN > VEN(HI)
IOUT < ICL
TJ < TSD
Disabled
—
VEN < VEN(LO)
—
TJ > TSD
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
• The enable voltage has previously exceeded the enable rising threshold voltage and not yet decreased below
the enable falling threshold.
• The output current is less than the current limit (IOUT < ICL).
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD).
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line
or load transients in dropout can result in large output-voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature (TJ > TSD).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS796xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive equipment.
The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current
(265 μA typically), and enable input to reduce supply currents to less than 1 μA when the regulator is turned off.
8.2 Typical Application
A typical application circuit is shown in Figure 24.
VIN
IN
VOUT
OUT
TPS796xx
2.2µF
EN
GND
1 µF
NR
0.01µF
Figure 24. Typical Application Circuit
8.2.1 Design Requirements
Table 2 lists the design parameters.
Table 2. Design Parameters
PARAMETER
Input voltage
Output voltage
Maximum output current
DESIGN REQUIREMENT
3.3V
2.5 V
700 mA
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND terminal current, and power the load.
8.2.2.1 Input and Output Capacitor Requirements
A 2.2-μF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS796xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A
higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the
device is located several inches from the power source.
Like most low dropout regulators, the TPS796xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitor is 1 μF. Any 1-μF or larger ceramic
capacitor is suitable.
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8.2.2.2 Output Noise
The internal voltage reference is a key source of noise in an LDO regulator. The TPS796xx has an NR pin which
is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the NR pin, creates a low-pass filter to reduce the
voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR
drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor should be no more than 0.1 μF in order to ensure that it is fully
charged during the quickstart time provided by the internal switch shown in the functional block diagram.
For example, the TPS79630 exhibits 40 μVRMS of output voltage noise using a 0.1-μF ceramic bypass capacitor
and a 10-μF ceramic output capacitor. The output starts up slower as the bypass capacitance increases due to
the RC time constant at the bypass pin that is created by the internal 250-kΩ resistor and external capacitor.
8.2.2.3 Dropout Voltage
The TPS796 uses a PMOS pass transistor to achieve a low dropout voltage. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in its linear region of operation and rDS(on) of the PMOS pass
element is the input-to-output resistance. Because the PMOS device behaves like a resistor in dropout, VDO
approximately scales with the output current.
As with any linear regulator, PSRR degrades as (VIN – VOUT) approaches dropout. This effect is illustrated in
Figure 9 through Figure 11 in Typical Characteristics.
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8.2.2.4 Programming the TPS79601 Adjustable LDO Regulator
The output voltage of the TPS79601 adjustable regulator is programmed using an external resistor divider, as
Figure 25 shows.
VIN
IN
2.2 mF
R1
EN TPS79601
GND
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VOUT
OUT
C1
1 mF
FB
OUTPUT
VOLTAGE
R1
R2
C1
1.8 V
14.0 kW
30.1 kW
33 pF
3.6 V
57.9 kW
30.1 kW
15 pF
R2
Figure 25. Typical Application, Adjustable Output
The output voltage is calculated using Equation 1:
R1 ·
§
VOUT VREF u ¨ 1
¸
© R2 ¹
where
•
VREF = 1.2246 V typical (the internal reference voltage)
(1)
Resistors R1 and R2 should be chosen for approximately 40-μA divider current. Lower value resistors can be
used for improved noise performance, but the device wastes more power. Higher values should be avoided, as
leakage current at FB increases the output voltage error.
The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 μA, C1 = 15 pF for
stability, and then calculate R1 using Equation 2:
§V
·
R1 ¨ OUT 1¸ u R2
© VREF
¹
(2)
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be
placed between OUT and FB. The approximate value of this capacitor can be calculated as Equation 3:
3 u 10 u R1 R2
7
C1
R1u R2
(3)
The suggested value of this capacitor for several resistor ratios is shown in the table in Figure 25. If this
capacitor is not used (such as in a unity-gain configuration) then the minimum recommended output capacitor is
2.2 μF instead of 1 μF.
8.2.3 Application Curves
80
VIN = 5.5 V
COUT = 10 mF
CNR = 0.1 mF
0.5
70
Ripple Rejection − dB
Output Spectral Noise Density − mV/ÖHz
0.6
0.4
0.3
IOUT = 1 mA
0.2
60
50
IOUT = 1 A
40
30
20
IOUT = 1 A
0.1
10
0.0
100
0
1k
10k
100k
Frequency (Hz)
Figure 26. TPS79630 Output Spectral Noise Density vs
Frequency
16
IOUT = 1 mA
VIN = 4 V
COUT = 10 mF
CNR = 0.1 mF
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1
10
100
1k
10k 100k
1M
10M
Frequency (Hz)
Figure 27. TPS79630 Ripple Rejection vs Frequency
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8.3 Do's and Don'ts
Place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Connect a 2.2-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the
regulator.
Do not exceed the absolute maximum ratings.
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 2.7 V and 5.5 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
is well-regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help
improve the output noise performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendation to Improve PSRR and Noise Performance
To improve AC measurements like PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to
the ground pin of the device.
10.1.2 Regulator Mounting
The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of
the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area
improves heat dissipation.
Solder pad footprint recommendations for the devices are presented in an application bulletin Solder Pad
Recommendations for Surface-Mount Devices, SBFA015, available from the TI website (www.ti.com).
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10.2 Layout Examples
GND PLANE
CIN
TPS79601DRB
VIN
VOUT
IN
1
8
EN
IN
2
7
N/C
OUT
3
6
GND
OUT
4
5
NR/FB
R2
COUT
GND PLANE
R1
Figure 28. TPS79601 (Adjustable Voltage Version)—DRB Layout Example
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Layout Examples (continued)
GND PLANE
CIN
TPS796xxDRB
VIN
VOUT
IN
1
8
EN
IN
2
7
N/C
OUT
3
6
GND
OUT
4
5
NR/FB
CNR
COUT
GND PLANE
Figure 29. TPS796xx (Fixed Voltage Versions)—DRB Layout Example
10.3 Thermal Considerations
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 4:
PD VIN VOUT u IOUT
(4)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the VSON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an
appropriate amount of copper PCB area to ensure the device does not overheat. On both SOT-223 (DCQ) and
TO-263 (KTT) packages, the primary conduction path for heat is through the tab to the PCB. That tab should be
connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient
temperature, maximum device junction temperature, and power dissipation of the device and can be calculated
using Equation 5:
125qC TA
RTJA
PD
'
(5)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 30.
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Thermal Considerations (continued)
160
DCQ
DRB
KTT
140
qJA (°C/W)
120
100
80
60
40
20
0
0
1
2
4
5
7
3
6
Board Copper Area (in2)
8
9
10
θJA value at board size of 9in2 (that is, 3in × 3in) is a JEDEC standard.
Figure 30. ΘJA vs Board Size
Figure 30 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in Estimating Junction Temperature.
10.4 Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in Thermal Information, the junction temperature can be
estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older θJC,Top
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 5
TT is the temperature at the center-top of the IC package
TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 32
shows).
(6)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal
Metrics, available at www.ti.com.
By looking at Figure 31, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
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Estimating Junction Temperature (continued)
35
YJT and YJB (°C/W)
30
DCQ
DRB YJB
KTT
25
20
15
10
DCQ YJT
5
DRB YJT
KTT YJT
0
0
1
3
2
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 31. ΨJT And ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For
further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI
website.
(1)
TB
1mm
TT on top of IC
X
TT on top
of IC
TB on PCB
surface
TB on PCB
(2)
TT
surface
1mm
X
1mm
(a) Example DRB (VSON) Package Measurement
(b) Example DCQ (SOT-223) Package Measurement
(1)
TT is measured at the center of both the X- and Y-dimensional axes.
(2)
TB is measured below the package lead on the PCB surface.
(c) Example KTT (TO-263) Package Measurement
Figure 32. Measuring Points For TT and TB
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS796.
The TPS79601DRBEVM evaluation module can be requested at the TI website through the product folders or
purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS796 is available through the product folders under
simulation models.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature (1)
PRODUCT
VOUT
TPS796xx(x) yyy z
(1)
xx(x) is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
yyy is package designator.
z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Using New Thermal Metrics, SBVA025
• IC Package Thermal Metrics, SPRA953
• TPS79601DRBEVM User's Guide, SLVU130
• Solder Pad Recommendations for Surface-Mount Devices, SBFA015
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
22
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS79601
Click here
Click here
Click here
Click here
Click here
TPS79613
Click here
Click here
Click here
Click here
Click here
TPS79618
Click here
Click here
Click here
Click here
Click here
TPS79625
Click here
Click here
Click here
Click here
Click here
TPS79628
Click here
Click here
Click here
Click here
Click here
TPS79630
Click here
Click here
Click here
Click here
Click here
TPS79633
Click here
Click here
Click here
Click here
Click here
TPS79650
Click here
Click here
Click here
Click here
Click here
TPS79601
Click here
Click here
Click here
Click here
Click here
TPS79613
Click here
Click here
Click here
Click here
Click here
TPS79618
Click here
Click here
Click here
Click here
Click here
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Product Folder Links: TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650
TPS79601, TPS79613, TPS79618, TPS79625
TPS79628, TPS79630, TPS79633, TPS79650
www.ti.com
SLVS351P – SEPTEMBER 2002 – REVISED MARCH 2015
Related Links (continued)
Table 4. Related Links (continued)
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS79625
Click here
Click here
Click here
Click here
Click here
TPS79628
Click here
Click here
Click here
Click here
Click here
TPS79630
Click here
Click here
Click here
Click here
Click here
TPS79633
Click here
Click here
Click here
Click here
Click here
TPS79650
Click here
Click here
Click here
Click here
Click here
11.4 Trademarks
PowerPAD is a trademark of Texas Instruments Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2002–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS79601 TPS79613 TPS79618 TPS79625 TPS79628 TPS79630 TPS79633 TPS79650
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS79601DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79601
Samples
TPS79601DCQG4
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79601
Samples
TPS79601DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79601
Samples
TPS79601DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CES
Samples
TPS79601DRBRG4
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CES
Samples
TPS79601DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CES
Samples
TPS79601DRBTG4
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
CES
Samples
TPS79601KTTR
ACTIVE
DDPAK/
TO-263
KTT
5
500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TPS
79601
Samples
TPS79601KTTRG3
ACTIVE
DDPAK/
TO-263
KTT
5
500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TPS
79601
Samples
TPS79613DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CCT
Samples
TPS79618DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79618
Samples
TPS79618DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79618
Samples
TPS79618DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79618
Samples
TPS79618KTTR
ACTIVE
DDPAK/
TO-263
KTT
5
500
RoHS & Green
SN
Level-2-260C-1 YEAR
TPS
79618
Samples
TPS79625DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79625
Samples
TPS79625DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
PS79625
Samples
TPS79625DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79625
Samples
TPS79625KTTR
LIFEBUY
DDPAK/
TO-263
KTT
5
500
RoHS & Green
SN
Level-2-260C-1 YEAR
TPS79628DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Addendum-Page 1
TPS
79625
-40 to 125
PS79628
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS79628DCQR
ACTIVE
TPS79628DRBT
LIFEBUY
TPS79630DCQ
LIFEBUY
TPS79630DCQG4
LIFEBUY
TPS79630DCQR
LIFEBUY
TPS79630KTTR
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79628
SON
DRB
8
250
RoHS & Green
NIPDAU
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMI
Level-2-260C-1 YEAR
-40 to 125
PS79630
SOT-223
DCQ
6
78
RoHS & Green
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79630
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79630
ACTIVE
DDPAK/
TO-263
KTT
5
500
RoHS & Green
SN
Level-2-260C-1 YEAR
TPS79633DCQ
ACTIVE
SOT-223
DCQ
6
78
RoHS & Green
SN
Level-2-260C-1 YEAR
TPS79633DCQG4
LIFEBUY
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
TPS79633DCQR
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
TPS79633DCQRG4
ACTIVE
SOT-223
DCQ
6
2500
TPS79633KTTR
ACTIVE
DDPAK/
TO-263
KTT
5
TPS79633KTTRG3
ACTIVE
DDPAK/
TO-263
KTT
TPS79650DCQ
ACTIVE
SOT-223
TPS79650DCQG4
ACTIVE
TPS79650DCQR
Samples
TPS
79630
Samples
-40 to 125
PS79633
Samples
Level-2-260C-1 YEAR
-40 to 125
PS79633
SN
Level-2-260C-1 YEAR
-40 to 125
PS79633
Samples
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79633
Samples
500
RoHS & Green
SN
Level-2-260C-1 YEAR
TPS
79633
Samples
5
500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TPS
79633
Samples
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79650
Samples
SOT-223
DCQ
6
78
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79650
Samples
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79650
Samples
TPS79650DRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BYZ
Samples
TPS79650DRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BYZ
Samples
TPS79650DRBTG4
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BYZ
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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