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TPS7A52-Q1
SBVS296B – SEPTEMBER 2017 – REVISED JUNE 2018
TPS7A52-Q1 2-A, High-Accuracy, Automotive-Grade, Low-Noise, LDO Voltage Regulator
1 Features
3 Description
•
•
The TPS7A52-Q1 device is a low-noise (4.4 µVRMS),
low-dropout linear regulator (LDO) capable of
sourcing 2 A with only 115 mV of maximum dropout.
The device output voltage is adjustable from 0.8 V to
5.2 V using an external resistor divider.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified for Automotive Applications:
– Temperature Grade 1: –40°C ≤ TA ≤ +125°C
– HBM ESD Classification Level 2
– CDM ESD Classification Level C4A
Extended Junction Temperature (TJ) Range:
–40°C to +150°C
Input Voltage Range:
– Without BIAS: 1.4 V to 6.5 V
– With BIAS: 1.1 V to 6.5 V
Adjustable Output Voltage Range: 0.8 V to 5.2 V
Low Dropout: 115 mV (max) at 2 A With BIAS
Output Voltage Noise: 4.4 µVRMS
1% (max) Accuracy Over Line, Load, and
Temperature With BIAS
Power-Supply Ripple Rejection:
– 40 dB at 500 kHz
Adjustable Soft-Start Inrush Control
Open-Drain, Power-Good (PG) Output
Packages:
– 3.5-mm × 3.5-mm, 20-Pin VQFN
– 4-mm × 4-mm, 20-Pin VQFNP With Wettable
Flanks and High CTE (12 ppm/°C) Mold
Compound
For digital loads [such as application-specific
integrated circuits (ASICs), field-programmable gate
arrays (FPGAs), and digital signal processors
(DSPs)] requiring low-input voltage, low-output (LILO)
voltage operation, the exceptional accuracy (1% over
load and temperature), remote sensing, excellent
transient performance, and soft-start capabilities of
the
TPS7A52-Q1
provides
optimal
system
performance.
The versatility of the TPS7A52-Q1 makes the device
a component of choice for many demanding
applications.
Device Information(1)
2 Applications
•
•
•
The combination of low-noise (4.4 µVRMS), highPSRR, and high output current capability makes the
TPS7A52-Q1 ideal to power noise-sensitive
components such as those found in radar power and
infotainment applications. The high performance of
this device limits power-supply-generated phase
noise and clock jitter, making this device ideal for
powering RF amplifiers, radar sensors, and chipsets.
Specifically, RF amplifiers benefit from the highperformance and 5.0-V output capability of the
device.
PART
NUMBER
Telematic Control Units
Infotainment and Clusters
High-Speed Interfaces (PLL and VCO)
PACKAGE
TPS7A52-Q1
BODY SIZE (NOM)
VQFN (20)
3.50 mm × 3.50 mm
Wettable flank VQFNP (20)
4.00 mm x 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Powering RF Components
Output Voltage Noise vs
Frequency and Output Voltage
Bias Supply
2
VOUT = 5.0 V, 11.7 PVRMS
VOUT = 3.3 V, 8.3 PVRMS
VOUT = 1.5 V, 5.4 PVRMS
VOUT = 0.8 V, 4.5 PVRMS
1
0.5
Input Supply
BIAS
TPS7A52-Q1
EN Signal
EN
Noise (PV/—Hz)
IN
OUT
PG
VCC
Radar
EN
Sensor System
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106 5x106
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A52-Q1
SBVS296B – SEPTEMBER 2017 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 28
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2018) to Revision B
Page
•
Added new RTK (VQFNP) package and associated content................................................................................................. 1
•
Changed plots at IOUT > 2 A in Typical Characteristics section to match values shown in Specifications section ................ 7
•
Changed all IOUT test conditions from 3 A to 2 A to match values shown in Specifications section ...................................... 7
•
Changed all plots to use default COUT = 22 µF....................................................................................................................... 7
•
Changed Figure 48 to load transient plot ............................................................................................................................. 29
•
Changed Figure 49 to noise plot .......................................................................................................................................... 29
Changes from Original (September 2017) to Revision A
•
2
Page
Changed from product preview to production data (active).................................................................................................... 1
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Product Folder Links: TPS7A52-Q1
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SBVS296B – SEPTEMBER 2017 – REVISED JUNE 2018
5 Pin Configuration and Functions
GND
IN
IN
17
16
IN
16
18
IN
17
OUT
GND
18
19
OUT
1
15
IN
EN
NC
2
14
EN
13
NR/SS
FB
3
13
NR/SS
PG
4
12
BIAS
DNC
5
11
NC
OUT
1
15
IN
NC
2
14
FB
3
Thermal
OUT
OUT
19
RTK Package
4-mm × 4-mm, 20-Pin VQFNP With Wettable Flanks
Top View
20
OUT
20
RGR Package
3.5-mm × 3.5-mm, 20-Pin VQFN
Top View
Thermal pad
7
8
9
10
NC
GND
NC
NC
10
NC
Not to scale
6
9
NC
NC
11
8
5
GND
DNC
7
BIAS
NC
12
6
4
NC
PG
NC
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions
(that is, VIN = 1.2 V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage
improves dc and ac performance for VIN ≤ 2.2 V. A 10-µF capacitor or larger must be connected between
this pin and ground. If not used, this pin must be left floating or tied to ground.
BIAS
12
I
DNC
5
—
EN
14
I
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the
device. If enable functionality is not required, this pin must be connected to IN or BIAS.
FB
3
I
Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from
FB to OUT (as close to the device as possible) is recommended to maximize ac performance. The use of
a feed-forward capacitor can disrupt PG (power good) functionality.
GND
8, 18
—
IN
15-17
I
NC
2, 6, 7, 9,
10, 11
—
No internal connection
13
—
Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces
reference voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger
capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to
maximize ac performance.
1, 19, 20
O
Regulated output pin. A 22-µF or larger ceramic capacitor (10 µF or greater of capacitance) from OUT to
ground is required for stability and must be placed as close to the output as possible. Minimize the
impedance from the OUT pin to the load.
4
O
Active-high, power-good pin. An open-drain output indicates when the output voltage reaches VIT(PG) of
the target. The use of a feed-forward capacitor may disrupt PG (power good) functionality.
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
NR/SS
OUT
PG
Thermal
pad
Thermal
pad
Do not connect
Ground pin. These pins must be connected to ground, the thermal pad, and each other with a lowimpedance connection.
Input supply voltage pin. A 10-µF or larger ceramic capacitor (5 µF or greater of capacitance) from IN to
ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close
to the input as possible.
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SBVS296B – SEPTEMBER 2017 – REVISED JUNE 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted) (1)
Voltage
7.0
IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs)
–0.3
7.5
OUT (2)
–0.3
VIN + 0.3
NR/SS, FB
–0.3
3.6
UNIT
V
Internally limited
PG (sink current into device)
Temperature
(2)
MAX
–0.3
OUT
Current
(1)
MIN
IN, BIAS, PG, EN
5
A
mA
Operating junction, TJ
–55
150
Storage, Tstg
–55
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VIN + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over junction temperature range (unless otherwise noted)
MIN
VIN
Input supply voltage range
(1)
NOM
MAX
UNIT
1.1
6.5
V
3.0
6.5
V
0.8
5
V
VBIAS
Bias supply voltage range
VOUT
Output voltage range (2)
VEN
Enable voltage range
0
VIN
V
IOUT
Output current
0
2
A
CIN
Input capacitor
10
CBIAS
Bias capacitor
10
RPG
Power-good pullup resistance
10
CNR/SS
NR/SS capacitor
10
nF
CFF
Feed-forward capacitor
10
nF
R1
Top resistor value in feedback network for
adjustable operation (3)
12.1
kΩ
R2
Bottom resistor value in feedback network for
adjustable operation
160
kΩ
TJ
Operating junction temperature
(1)
(2)
(3)
4
–40
22
µF
µF
100
150
kΩ
°C
BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than
or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
This output voltage range does not include device accuracy or accuracy of the feedback resistors.
The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R1 value.
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SBVS296B – SEPTEMBER 2017 – REVISED JUNE 2018
6.4 Thermal Information
TPS7A52-Q1
THERMAL METRIC (1)
RGR (VQFN)
RTK (VQFNP)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
43.4
39.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.8
32.1
°C/W
RθJB
Junction-to-board thermal resistance
17.6
16.9
°C/W
ΨJT
Junction-to-top characterization parameter
0.8
0.4
°C/W
YJB
Junction-to-board characterization parameter
17.6
16.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.4
1.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to +150°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V (1), OUT connected to 50 Ω to GND (2), VEN = 1.1 V, CIN = 10 µF, COUT = 22 µF, CNR/SS
without CFF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
VFB
Feedback voltage
0.8
VNR/SS
NR/SS pin voltage
0.8
VUVLO1+(IN)
Rising input supply UVLO with BIAS
VIN rising with VBIAS = 3.0 V
1.02
VHYS1(IN)
VUVLO1(IN) hysteresis
VBIAS = 3.0 V
320
VUVLO1-(IN)
Falling input supply UVLO with BIAS
VIN falling with VBIAS = 3.0 V
VUVLO2+(IN)
Rising input supply UVLO without BIAS
VIN rising
VHYS2(IN)
VUVLO2(IN) hysteresis
VUVLO2-(IN)
Falling input supply UVLO without BIAS VIN falling
VUVLO+(BIAS)
Rising bias supply UVLO
VBIAS rising, VIN = 1.1 V
VUVLO-(BIAS)
Falling bias supply UVLO
VBIAS falling, VIN = 1.1 V
VHYS(BIAS)
VUVLO(BIAS) hysteresis
VIN = 1.1 V
ΔVOUT/ ΔVIN
ΔVOUT/ ΔIOUT
Output voltage
V
1.39
1.064
2.83
2.45
V
2.9
2.531
mV
Accuracy
–2.0%
1.0%
Accuracy with
BIAS
VIN = 1.1 V, 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤
6.5 V, –40℃ < TJ < 150℃
–1.75%
0.75%
Accuracy
0.8 V ≤ VOUT ≤ 5.15 V, 5 mA ≤ IOUT ≤ 2 A, over
VIN, –40℃ < TJ < 125℃
–1%
1%
Accuracy with
BIAS
VIN = 1.1 V, 5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤
6.5 V, –40℃ < TJ < 125℃
–0.75%
0.75%
Load regulation
IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V
0.03
5 mA ≤ IOUT ≤ 2 A, 3.0 V ≤ VBIAS ≤ 6.5 V,
VIN = 1.1 V
0.07
5 mA ≤ IOUT ≤ 2 A
0.08
5 mA ≤ IOUT ≤ 2 A, VOUT = 5.2 V
0.04
VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V – 3%
103
190
VIN = 5.3 V, IOUT = 2 A, VFB = 0.8 V – 3%
135
220
VIN = 5.5 V, IOUT = 2 A, VFB = 0.8 V – 3%
157
300
73
120
VIN = 1.1 V, 3.0 V ≤ VBIAS ≤ 6.5 V,
IOUT = 2 A, VFB = 0.8 V – 3%
Dropout voltage
V
V
290
5.2
Line regulation
V
mV
0.8
RTK package
(1)
(2)
0.65
V
mV
0.8 V ≤ VOUT ≤ 5.15 V, 5 mA ≤ IOUT ≤ 2 A, over
VIN , –40℃ < TJ < 150℃
RGR package
VDO
V
1.09
0.711
1.31
UNIT
V
253
Range
VOUT
0.55
MAX
V
mV/V
mV/A
VIN = 1.4 V, IOUT = 2 A, VFB = 0.8 V – 3%
215
VIN = 5.3 V, IOUT = 2 A, VFB = 0.8 V – 3%
265
VIN = 5.5 V, IOUT = 2 A, VFB = 0.8 V – 3%
340
VIN = 1.1 V, 3.0 V ≤ VBIAS ≤ 6.5 V,
IOUT = 2 A, VFB = 0.8 V – 3%
145
mV
mV
VOUT(nom) is the expected VOUT value set by the external feedback resistors.
This 50-Ω load is disconnected when the test conditions specify an IOUT value.
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Electrical Characteristics (continued)
over operating junction temperature range (TJ = –40°C to +150°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V(1), OUT connected to 50 Ω to GND(2), VEN = 1.1 V, CIN = 10 µF, COUT = 22 µF, CNR/SS
without CFF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
ILIM
Output current limit
VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V
ISC
Short-circuit current limit
RLOAD = 20 mΩ
MIN
TYP
MAX
2.7
3.3
4
1.0
VIN = 6.5 V, IOUT = 5 mA
IGND
GND pin current
VIN = 1.4 V, IOUT = 2 A
IEN
EN pin current
VIN = 6.5 V, VEN = 0 V and 6.5 V
IBIAS
BIAS pin current
VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 2 A
VIL(EN)
EN pin low-level input voltage
(disable device)
VIH(EN)
EN pin high-level input voltage
(enable device)
VIT-(PG)
PG pin threshold
VHYS(PG)
PG pin hysteresis
VIT+(PG)
PG pin threshold
For rising VOUT
VOL(PG)
PG pin low-level output voltage
VOUT < VIT(PG), IPG = –1 mA
(current into device)
Ilkg(PG)
PG pin leakage current
VOUT > VIT(PG), VPG = 6.5 V
INR/SS
NR/SS pin charging current
VNR/SS = GND, VIN = 6.5 V
IFB
FB pin leakage current
VIN = 6.5 V
4
3.7
5
PSRR
Vn
TSD
6
Power-supply ripple rejection
Output noise voltage
Thermal shutdown temperature
–0.5
2.3
0.82VOUT
25
µA
µA
3.5
mA
0.5
V
V
0.88VOUT
0.93VOUT
0.02VOUT
VIN – VO UT = 0.4 V,
IOUT = 2 A, CNR/SS = 100 nF,
CFF = 10 nF,
COUT = 22 µF
0.84VOUT
4.0
0.90VOUT
6.5
–100
f = 10 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V
42
f = 500 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V
39
f = 10 kHz,
VOUT = 5.0 V
40
f = 500 kHz,
VOUT = 5.0 V
25
BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 2 A,
CNR/SS = 100 nF, CFF = 10 nF, COUT = 22 µF
4.4
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 2 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 22 µF
7.7
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
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mA
0.5
1.1
For falling VOUT
A
A
3
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V
UNIT
V
V
0.95VOUT
V
0.4
V
1
µA
10
µA
100
nA
dB
µVRMS
°C
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Product Folder Links: TPS7A52-Q1
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SBVS296B – SEPTEMBER 2017 – REVISED JUNE 2018
6.6 Typical Characteristics
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 22 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
70
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
80
60
40
IOUT = 100mA
IOUT = 250mA
IOUT = 500mA
IOUT = 750mA
IOUT = 1A
IOUT = 1.5A
IOUT = 2A
20
0
10
100
1k
10k
100k
Frequency (Hz)
1M
60
50
40
30
20
10
VIN = 1.4V
VIN = 1.35V
VIN = 1.3V
VIN = 1.25V
VIN = 1.2V
VIN = 1.15V
VIN = 1.1V
0
10
10M
100
1k
Fig1
VIN = 1.1 V, VBIAS = 5 V, CNR/SS = 10 nF, CFF = 10 nF
10k
100k
Frequency (Hz)
1M
10M
Fig2
IOUT = 2 A, VBIAS = 5 V,
CNR/SS = 10 nF, CFF = 10 nF
Figure 1. PSRR vs Frequency and IOUT
Figure 2. PSRR vs Frequency and VIN With Bias
70
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
70
60
50
40
30
20
VBIAS = 0V
VBIAS = 3V
VBIAS = 5V
10
0
10
100
1k
10k
100k
Frequency (Hz)
1M
60
50
40
30
20
10
VIN = 1.1V, VBIAS = 5V
VIN = 1.2V, VBIAS = 5V
VIN = 1.4V, VBIAS = 0V
VIN = 2.3V, VBIAS = 0V
0
10
10M
100
VIN = 1.4 V, IOUT = 1 A,
CNR/SS = 10 nF, CFF = 10 nF
10k
100k
Frequency (Hz)
1M
10M
Fig4
IOUT = 1 A,
CNR/SS = 10 nF, CFF = 10 nF
Figure 3. PSRR vs Frequency and VBIAS
Figure 4. PSRR vs Frequency and VIN
80
Power-Supply Rejection Ratio (dB)
70
Power-Supply Rejection Ratio (dB)
1k
Fig2
60
50
40
30
20
10
VOUT = 0.8V
VOUT = 2.5V
0
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
70
60
50
40
30
20
10
0
-10
VIN = 4V
VIN = 3.85V
VIN = 3.8V
VIN = 3.75V
VIN = 3.7V
VIN = 3.65V
VIN = 3.6V
-20
10
Fig4
VIN = VOUT + 0.3 V, VBIAS = 5.0 V, IOUT = 2 A,
CNR/SS = 10 nF, CFF = 10 nF
Figure 5. PSRR vs Frequency and VOUT With Bias
100
1k
10k
100k
Frequency (Hz)
1M
10M
Fig6
VOUT = 3.3 V, IOUT = 2 A,
CNR/SS = 10 nF, CFF = 10 nF
Figure 6. PSRR vs Frequency and VIN for VOUT = 3.3 V
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 22 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
100
80
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
70
60
50
40
30
20
10
0
COUT = 22uF
COUT = 100uF
-10
-20
10
100
1k
10k
100k
Frequency (Hz)
1M
80
60
40
20
VBIAS = 3.0 V
VBIAS = 5.0 V
VBIAS = 6.5 V
0
1x101
10M
12
1x107
2
Output Voltage Noise Density (PVRMS)
IOUT = 2A
11
Output Voltage Noise (PVRMS)
1x106
Figure 8. VBIAS PSRR vs Frequency and VBIAS
Figure 7. PSRR vs Frequency and COUT
10
9
8
7
6
5
4
0.6
1.2
1.8
2.4
3
3.6
Output Voltage (V)
4.2
4.8
1
0.1
0.01
VOUT = 0.8 V
VOUT = 1.5 V
VOUT = 3.3 V
VOUT = 5 V
0.001
10
5.4
1k
10k
100k
Frequency (Hz)
1M
10M
Fig1
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤ 2.2 V, IOUT = 2 A,,
CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 10. Output Noise vs Frequency and VOUT
Figure 9. Output Voltage Noise vs Output Voltage
0.5
2
Output Voltage Noise Density (PVRMS)
VIN = 1.4 V, VBIAS = 5 V, 4.7 PVRMS
VIN = 1.4 V, 6.2 PVRMS
VIN = 1.5 V, 4.7 PVRMS
VIN = 2.5 V, 4.7 PVRMS
VIN = 5.3 V, 4.7 PVRMS
1
0.1
0.01
0.001
10
100
Fig9
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤ 2.2 V,
CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Output Voltage Noise Density (PVRMS)
1x103
1x104
1x105
Frequency (Hz)
VIN = VOUT + 0.3 V, VOUT = 1 V, IOUT = 2 A,
CNR/SS = 10 nF, CFF = 10 nF
VIN = VOUT + 0.3 V, VOUT = 1 V, IOUT = 2 A,
CNR/SS = 10 nF, CFF = 10 nF
100
1k
10k
100k
Frequency (Hz)
1M
10M
0.1
0.01
CNR/SS = 0 nF, 8.4 PVRMS
CNR/SS = 0.1 nF, 7.3 PVRMS
CNR/SS = 10 nF, 4.5 PVRMS
CNR/SS = 100 nF, 4.3 PVRMS
CNR/SS = 1 PF, 4.28 PVRMS
0.001
10
Fig1
IOUT = 2 A, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 11. Output Noise vs Frequency and VIN
8
1x102
Fig7
100
1k
10k
100k
Frequency (Hz)
1M
10M
Fig1
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT = 2 A,
CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz
Figure 12. Output Noise vs Frequency and CNR/SS
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 22 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
2
Output Voltage Noise Density (PVRMS)
1
0.1
0.01
CFF = 0 nF, 22 PVRMS
CFF = 1 nF, 15.7 PVRMS
CFF = 10 nF, 11.8 PVRMS
CFF = 100 nF, 10.2 PVRMS
0.001
10
100
1k
10k
100k
Frequency (Hz)
1M
1
0.1
0.01
CNR/SS = 10 nF, CFF = 10 nF, 11.8 PVRMS
CNR/SS = 10 nF, CFF = 100 nF, 10.2 PVRMS
CNR/SS = 100 nF, CFF = 100 nF, 6.3 PVRMS
0.001
10
10M
100
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT = 2 A, sequencing with a dcdc converter and PG,
CNR/SS = 10 nF, RMS noise BW = 10 Hz to 100 kHz
Output Current (A)
0.8
Voltage (V)
Fig1
50
Output Current
VOUT = 0.9 V
VOUT = 1.1 V
VOUT = 1.2 V
VOUT = 1.8 V
9
8
0.6
0.4
VEN
VOUT, CNR/SS = 0 nF
VOUT, CNR/SS = 10 nF
VOUT, CNR/SS = 47 nF
VOUT, CNR/SS = 100 nF
0.2
0
-0.2
0
5
10
15
20
25
30
Time (ms)
35
40
45
7
0
4
-10
3
-20
2
-30
1
-40
0
-50
1.75
0
6
10
5
0
4
-10
3
-20
2
-30
1
-40
-50
0.6
0.8
1
1.2
Time (ms)
1.4
1.6
1.8
0.75
1
Time (ms)
1.25
1.5
50
2
IOUT, DC = 100 mA,
CNR/SS = CFF = 10 nF, slew rate = 1 A/µs
Figure 17. Load Transient vs Time and VOUT Without Bias
AC-Coupled Output Voltage (mV)
20
0.4
0.5
Figure 16. Load Transient vs Time and VOUT With Bias
AC-Coupled Output Voltage (mV)
30
7
0.2
0.25
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT, DC = 100 mA, slew rate =
1 A/µs, CNR/SS = CFF = 10 nF
40
0
20
10
50
Output Current
VOUT = 0.9 V
VOUT = 1.1 V
30
5
Figure 15. Start-Up Waveform vs Time and CNR/SS
10
40
6
50
VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5.0 V, IOUT = 2 A,
CFF = 10 nF
Output Current (A)
10M
10
1
0
1M
Figure 14. Output Noise at VOUT = 5 V
1.2
8
10k
100k
Frequency (Hz)
VOUT = 5 V, IOUT = 2 A, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 13. Output Noise vs Frequency and CFF
9
1k
Fig1
AC-Coupled Output Voltage (mV)
Output Voltage Noise Density (PVRMS)
2
VOUT, 0.5 A/Ps
VOUT, 1 A/Ps
VOUT, 2 A/Ps
25
0
-25
-50
0
0.4
0.8
1.2
Time (ms)
1.6
2
VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 2 A,
CNR/SS = CFF = 10 nF
Figure 18. Load Transient vs Time and Slew Rate
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 22 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
400
VOUT, 100mA to 2A
VOUT, 500mA to 2A
40
-40qC
0qC
350
30
Dropout Voltage (mV)
AC-Coupled Output Voltage (mV)
50
20
10
0
-10
-20
300
250
200
150
100
50
-40
0
0
50
100
150
Time (ms)
200
250
1
300
1.5
2
Fig1
3
3.5
4
Input Voltage (V)
4.5
5
5.5
6
Figure 20. Dropout Voltage vs Input Voltage Without Bias
Figure 19. Load Transient vs Time and DC Load
400
200
-40qC
0qC
350
25qC
85qC
125qC
150qC
-40qC
0qC
175
300
Dropout Voltage (mV)
Dropout Voltage (mV)
2.5
IOUT = 2 A, VBIAS = 0 V
RGR package, VOUT = 0.9 V, VIN = 1.2 V, VBIAS = 5.0 V,
CNR/SS = CFF = 10 nF, slew rate = 1 A/µs
250
200
150
100
50
25qC
85qC
125qC
150qC
150
125
100
75
50
25
0
0
1
1.5
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
6
0
RGR package, IOUT = 2 A, VBIAS = 6.5 V
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
RGR package, VIN = 1.4 V, VBIAS = 0 V
Figure 21. Dropout Voltage vs Input Voltage With Bias
Figure 22. Dropout Voltage vs Output Current Without Bias
200
200
-40qC
0qC
175
25qC
85qC
125qC
150qC
-40qC
0qC
175
150
Dropout Voltage (mV)
Dropout Voltage (mV)
125qC
150qC
-30
-50
125
100
75
50
25
25qC
85qC
125qC
150qC
150
125
100
75
50
25
0
0
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
0
0.25
RGR package, VIN = 1.1 V, VBIAS = 3 V
Figure 23. Dropout Voltage vs Output Current With Bias
10
25qC
85qC
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
RGR package, VIN = 5.5 V
Figure 24. Dropout Voltage vs Output Current (High VIN)
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 22 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
1.5
1
-40qC
0qC
125qC
150qC
-40qC
0qC
0.8
0.9
0.6
0.6
0.4
Accuracy (%)
Accuracy (%)
1.2
25qC
85qC
0.3
0
-0.3
0
-0.2
-0.4
-0.9
-0.6
-1.2
-0.8
-1
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
1
VIN = 1.4 V, VBIAS = 0 V
Figure 25. Load Regulation With Bias
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
6.5
6.5
7
Figure 26. Line Regulation Without Bias
4
-40qC
0qC
3.75
25qC
85qC
125qC
150qC
-40qC
0qC
3.75
3.5
Ground Current (mA)
Ground Current (mA)
1.5
VOUT = 0.8 V, VBIAS = 0 V, IOUT = 5 mA
4
3.25
3
2.75
2.5
2.25
25qC
85qC
125qC
150qC
3.5
3.25
3
2.75
2.5
2.25
2
2
1
2
3
4
5
Input Voltage (V)
6
7
3
3.5
VBIAS = 0 V, IOUT = 5 mA
4
4.5
5
5.5
Bias Voltage (V)
6
VIN = 1.1 V, IOUT = 5 mA
Figure 27. Ground Current vs Input Voltage
Figure 28. Ground Current vs Bias Voltage
8
8
-40qC
0qC
7
25qC
85qC
125qC
150qC
-40qC
0qC
7
6
Shutdown Current (PA)
Shutdown Current (PA)
125qC
150qC
0.2
-0.6
-1.5
25qC
85qC
5
4
3
2
1
25qC
85qC
125qC
150qC
6
5
4
3
2
1
0
0
0
1
2
3
4
Input Voltage (V)
5
6
7
3
3.5
VBIAS = 0 V
4
4.5
5
5.5
Bias Voltage (V)
6
6.5
7
VIN = 1.1 V
Figure 29. Shutdown Current vs Input Voltage
Figure 30. Shutdown Current vs Bias Voltage
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 22 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
1.5
9
1.25
Undervoltage Lockout (V)
NR/SS Current (PA)
8.5
8
7.5
7
6.5
6
1
0.75
0.5
VUVLO2(IN) Rising
VUVLO2(IN) Falling
VUVLO1(IN) Rising
VUVLO1(IN) Falling
0.25
5.5
5
-50
-25
0
25
50
75
Temperature (qC)
100
125
0
-50
150
-25
0
25
50
75
Temperature (qC)
100
125
150
VBIAS = 0 V
Figure 31. NR/SS Current vs Temperature
Figure 32. VIN UVLO vs Temperature
3
1.1
2.9
1
2.8
Enable Threshold (V)
Undervoltage Lockout (V)
VIL(EN)
2.7
2.6
2.5
2.4
2.2
-50
-25
0
0.9
0.8
0.7
0.6
0.5
VUVLO(BIAS) Rising
VUVLO(BIAS) Falling
2.3
25
50
75
Temperature (qC)
100
125
0.4
-50
150
-25
0
VIN = 1.1 V
25
50
75
Temperature (qC)
100
125
150
VIN = 1.4 V, 6.5 V
Figure 33. VBIAS UVLO vs Temperature
Figure 34. Enable Threshold vs Temperature
600
-40qC
0qC
500
Temperature
25qC
85qC
PG Low Level Output Voltage (mV)
600
PG Low Level Output Voltage (mV)
VIH(EN)
125qC
150qC
400
300
200
100
0
-40qC
0qC
500
Temperature
25qC
85qC
125qC
150qC
400
300
200
100
0
0
0.5
1
1.5
2
PG Current (mA)
2.5
3
0
0.5
1
1.5
2
PG Current (mA)
2.5
3
VIN = 6.5 V
Figure 35. PG Voltage vs PG Current Sink
12
Figure 36. PG Voltage vs PG Current Sink
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Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT
= 22 µF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
93
3.5
PG Falling
PG Rising
Current Limit (A)
Power Good Threshold (%)
Temperature
25qC
85qC
125qC
3
91
90
89
88
2.75
2.5
2.25
2
87
86
-50
-40qC
0qC
3.25
92
1.75
1.5
-25
0
25
50
75
Temperature (qC)
100
125
150
0
100
200
300
400
500
Output Voltage (mV)
600
700
Temperature limited because of power dissipation
Figure 37. PG Threshold vs Temperature
Figure 38. Foldback Current Limit vs Output Voltage
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7 Detailed Description
7.1 Overview
The TPS7A52-Q1 is a high-current (2 A), low-noise (4.4 µVRMS), high accuracy (1%) low-dropout linear voltage
regulator with an input range of 1.1 V to 6.5 V, an output voltage range of 0.8 V to 5.2 V. The TPS7A52-Q1 has
an integrated charge pump for ease of use, and an external bias rail to allow for the lowest dropout across the
entire output voltage range. Table 1 categorizes the functions shown in the Functional Block Diagram section.
These features make the TPS7A52-Q1 a robust solution to solve many challenging problems by generating a
clean, accurate power supply in a variety of applications.
Table 1. Device Features
VOLTAGE REGULATION
SYSTEM START-UP
INTERNAL PROTECTION
High accuracy
Programmable soft start
Foldback current limit
Low-noise, high-PSRR output
No sequencing requirement between BIAS, IN, and EN
Power-good output
Fast transient response
Thermal shutdown
Start-up with negative bias on OUT
7.2 Functional Block Diagram
PSRR
Boost
IN
Current
Limit
OUT
Charge
Pump
BIAS
0.8-V
VREF
Active
Discharge
RNR/SS = 250 k:
+
Error
Amp
±
INR/SS
NR/SS
200 pF
FB
UVLO
Circuits
Internal
Controller
Thermal
Shutdown
±
0.88 x VREF
EN
PG
+
GND
14
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7.3 Feature Description
7.3.1 Voltage Regulation Features
7.3.1.1 DC Regulation
As shown in Figure 39, an LDO functions as a class-B amplifier in which the input signal is the internal reference
voltage (VREF). VREF is designed to have a very low bandwidth at the input to the error amplifier through the use
of a low-pass filter (VNR/SS).
As such, the reference can be considered as a pure dc input signal. The low output impedance of an LDO comes
from the combination of the output capacitor and pass element. The pass element also presents a high input
impedance to the source voltage when operating as a current source. A positive LDO can only source current
because of the class-B architecture.
This device achieves a maximum of 1% output voltage accuracy primarily because of the high-precision bandgap voltage (VBG) that creates VREF. The low dropout voltage (VDO) reduces the thermal power dissipation
required by the device to regulate the output voltage at a given current level, thereby improving system
efficiency. These features combine to make this device a good approximation of an ideal voltage source.
VIN
To Load
±
+
R1
VREF
R2
GND
NOTE: VOUT = VREF × (1 + R1 / R2).
Figure 39. Simplified Regulation Circuit
7.3.1.2 AC and Transient Response
The LDO responds quickly to a transient (large-signal response) on the input supply (line transient) or the output
current (load transient) resulting from the LDO high-input impedance and low output-impedance across
frequency. This same capability also means that the LDO has a high power-supply rejection ratio (PSRR) and,
when coupled with a low internal noise-floor (Vn), the LDO approximates an ideal power supply in ac (smallsignal) and large-signal conditions.
The choice of external component values optimizes the small- and large-signal response. The NR/SS capacitor
(CNR/SS) and feed-forward capacitor (CFF) easily reduce the device noise floor and improve PSRR.
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Feature Description (continued)
7.3.2 System Start-Up Features
In many different applications, the power-supply output must turn on within a specific window of time to either
provide proper operation of the load or to minimize the loading on the input supply or other sequencing
requirements. The LDO start-up is well-controlled and user-adjustable, solving the demanding requirements
faced by many power-supply design engineers in a simple fashion.
7.3.2.1 Programmable Soft Start (NR/SS Pin)
Soft start directly controls the output start-up time and indirectly controls the output current during start-up (inrush
current).
The external capacitor at the NR/SS pin (CNR/SS), as shown in Figure 40, sets the output start-up time by setting
the rise time of the internal reference (VNR/SS).
SW
INR/SS
RNR
VREF
+
CNR/SS
VFB
±
GND
Figure 40. Simplified Soft-Start Circuit
7.3.2.2 Internal Sequencing
Controlling when a single power supply turns on can be difficult in a power distribution network (PDN) because of
the high power levels inherent in a PDN, and the variations between all of the supplies. Figure 41 and Table 2
show that the LDO turnon and turnoff time is set by the enable circuit (EN) and undervoltage lockout circuits
(UVLO1,2(IN) and UVLOBIAS).
EN
UVLOBIAS
UVLO1,2(IN)
Internal Enable
Control
Figure 41. Simplified Turnon Control
Table 2. Internal Sequencing Functionality Table
INPUT VOLTAGE
VIN ≥ VUVLO_1,2(IN)
BIAS VOLTAGE
VBIAS ≥ VUVLO(BIAS)
ENABLE
STATUS
LDO
STATUS
ACTIVE
DISCHARGE
POWER
GOOD
EN = 1
On
Off
PG = 1 when
VOUT ≥ VIT(PG)
EN = 0
Off
On
VBIAS < VUVLO(BIAS) +VHYS(BIAS)
(1)
16
VIN < VUVLO_1,2(IN) – VHYS1,2(IN)
BIAS = don't care
IN = don't care
VBIAS ≥ VUVLO(BIAS)
Off
EN = don't care
Off
On (1)
PG = 0
Off
The active discharge remains on as long as VIN or VBIAS provides enough headroom for the discharge circuit to function.
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7.3.2.2.1 Enable (EN)
The enable signal (VEN) is an active-high digital control that enables the LDO when the enable voltage is past the
rising threshold (VEN ≥ VIH(EN)) and disables the LDO when the enable voltage is below the falling threshold (VEN
≤ VIL(EN)). The exact enable threshold is between VIH(EN) and VIL(EN) because EN is a digital control. Connect EN
to VIN if enable functionality is not desired.
7.3.2.2.2 Undervoltage Lockout (UVLO) Control
The UVLO circuits respond quickly to glitches on IN or BIAS and attempts to disable the output of the device if
either of these rails collapse.
7.3.2.2.3 Active Discharge
When either EN or UVLO is low, the device connects a resistor of several hundred ohms from VOUT to GND,
discharging the output capacitance.
Do not rely on the active discharge circuit for discharging large output capacitors when the input voltage drops
below the targeted output voltage. Current flows from the output to the input (reverse current) when VOUT > VIN,
which can cause damage to the device (when VOUT > VIN + 0.3 V).
7.3.2.3 Power-Good Output (PG)
The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals
when the output nears its nominal value. PG can be used to signal other devices in a system when the output
voltage is near, at, or above the set output voltage (VOUT(nom)). Figure 42 shows a simplified schematic.
The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high.
The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFF) delays the output voltage and, because the PG circuit monitors the FB
pin, the PG signal can indicate a false positive.
VPG
VBG
VIN
VFB
±
+
GND
UVLOBIAS
UVLOIN
GND
EN
GND
Figure 42. Simplified PG Circuit
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7.3.3 Internal Protection Features
In many applications, fault events can occur that damage devices in the system. Short circuits and excessive
heat are the most common fault events for power supplies. The TPS7A52-Q1 implements circuitry to protect the
device and its load during these events. Continuously operating in these fault conditions or above a junction
temperature of 140°C is not recommended because the long-term reliability of the device is reduced.
7.3.3.1 Foldback Current Limit (ICL)
The internal current limit circuit is used to protect the LDO against high load-current faults or shorting events.
During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased
load impedance. Thermal shutdown can activate during a current limit event because of the high power
dissipation typically found in these conditions. For proper operation of the current limit, minimize the inductances
to the input and load. Continuous operation in current limit is not recommended.
7.3.3.2 Thermal Protection (Tsd)
The thermal shutdown circuit protects the LDO against excessive heat in the system, either resulting from current
limit or high ambient temperature.
The output of the LDO turns off when the LDO temperature (junction temperature, TJ) exceeds the rising thermal
shutdown temperature. The output turns on again after TJ decreases below the falling thermal shutdown
temperature.
A high power dissipation across the device, combined with a high ambient temperature (TA), can cause TJ to be
greater than or equal to Tsd, triggering the thermal shutdown and causing the output to fall to 0 V. The LDO can
cycle on and off when thermal shutdown is reached under these conditions.
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7.4 Device Functional Modes
Table 3 provides a quick comparison between the regulation and disabled operation.
Table 3. Device Functional Modes Comparison
(1)
(2)
(3)
PARAMETER
OPERATING
MODE
VIN
VBIAS
EN
IOUT
TJ
Regulation (1)
VIN > VOUT(nom) + VDO
VBIAS ≥ VUVLO(BIAS) (2)
VEN > VIH(EN)
IOUT < ICL
TJ ≤ TJ(maximum)
Disabled (3)
VIN < VUVLO_1,2(IN)
VBIAS < VUVLO(BIAS)
VEN < VIL(EN)
—
TJ > Tsd
All table conditions must be met.
VBIAS is only required for VIN < 1.4 V.
The device is disabled when any condition is met.
7.4.1 Regulation
The device regulates the output to the nominal output voltage when all the conditions in Table 3 are met.
7.4.2 Disabled
When disabled, the pass device is turned off, the internal circuits are shut down, and the output voltage is
actively discharged to ground by an internal resistor from the output to ground. See the Active Discharge section
for additional information.
7.4.3 Current Limit Operation
During a current-limit event, the LDO regulates the output current instead of the output voltage; therefore, the
output voltage falls with decreased load impedance.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and how to best implement them to achieve a reliable design.
8.1.1 Recommended Capacitor Types
The TPS7A52-Q1 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at
the input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry
standard for these types of applications and are recommended, but must be used with good judgment. Ceramic
capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability
across temperature. The use of Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. Make sure to derate ceramic capacitors by at least 50%. The input and output capacitors
recommended herein account for a capacitance derating of approximately 50%, but at high VIN and VOUT
conditions (VIN = 5.5 V to VOUT = 5.0 V), the derating can be greater than 50%, and must be taken into
consideration.
8.1.1.1 Input and Output Capacitor Requirements (CIN and COUT)
The TPS7A52-Q1 is designed and characterized for operation with ceramic capacitors of 22 µF or greater (10 µF
or greater of capacitance) at the output and 10 µF or greater (5 µF or greater of capacitance) at the input. Use at
least a 22-µF capacitor at the input to minimize input impedance. Place the input and output capacitors as near
as practical to the respective input and output pins in order to minimize trace parasitics. If the trace inductance
from the input supply to the TPS7A52-Q1 is high, a fast current transient can cause VIN to ring above the
absolute maximum voltage rating and damage the device. This situation can be mitigated by additional input
capacitors to dampen and keep the ringing below the device absolute maximum ratings.
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Application Information (continued)
8.1.1.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
The TPS7A52-Q1 features a programmable, monotonic, voltage-controlled soft start that is set with an external
capacitor (CNR/SS). Use an external CNR/SS to minimize inrush current into the output capacitors. This soft-start
feature eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs),
digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces
peak inrush current during start-up, minimizing start-up transients to the input power bus.
To achieve a monotonic start-up, the TPS7A52-Q1 error amplifier tracks the voltage ramp of the external softstart capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the softstart charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS). Equation 1
calculates soft-start ramp time:
tSS = (VNR/SS × CNR/SS) / INR/SS
(1)
INR/SS is provided in the Electrical Characteristics table and has a typical value of 6.2 µA.
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that
filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the
device noise floor. The LPF is a single-pole filter and Equation 2 calculates the cutoff frequency. The typical
value of RNR is 250 kΩ. Increasing the CNR/SS capacitor has a greater affect because the output voltage
increases when the noise from the reference is gained up even more at higher output voltages. For low-noise
applications, a 10-nF to 1-µF CNR/SS is recommended.
fcutoff = 1/ (2 × π × RNR × CNR/SS)
(2)
8.1.1.3 Feed-Forward Capacitor (CFF)
Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a
10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher
capacitance CFF can be used; however, the start-up time is longer and the power-good signal can incorrectly
indicate that the output voltage is settled. For a detailed description, see Pros and Cons of Using a FeedForward Capacitor with a Low Dropout Regulator.
8.1.2 Soft-Start and Inrush Current
Soft start refers to the ramp-up characteristic of the output voltage during LDO turnon after EN and UVLO
achieve threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turnon.
Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
measure because the input capacitor must be removed, which is not recommended. However, Equation 3 can be
used to estimate this soft-start current:
VOUT(t)
COUT ´ dVOUT(t)
IOUT(t) =
+
RLOAD
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turnon ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(3)
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Application Information (continued)
8.1.3 Optimizing Noise and PSRR
Improve the ultra-low noise floor and PSRR of the device by careful selection of:
•
•
•
•
•
CNR/SS for the low-frequency range
CFF in the midband frequency range
COUT for the high-frequency range
VIN – VOUT for all frequencies, and
VBIAS at lower input voltages
A larger noise-reduction capacitor improves low-frequency PSRR by filtering any noise coupling from the input
into the reference. To improve midband PSRR, use the feed-forward capacitor to place pole-zero pair near the
edge of the loop bandwidth and push out the loop bandwidth. Use larger output capacitors to improve highfrequency PSRR.
A higher input voltage improves the PSRR by giving the device more headroom to respond to noise on the input.
A bias rail also improves PSRR at lower input voltages because greater headroom is provided for the internal
circuits.
The noise-reduction capacitor filters out low-frequency noise from the reference, and the feed-forward capacitor
reduces output voltage noise by filtering out the midband frequency noise. However, a large feed-forward
capacitor can create new issues that are discussed in Pros and Cons of Using a Feed-Forward Capacitor with a
Low Dropout Regulator.
Use a large output capacitor to reduce high-frequency output voltage noise. Additionally, a bias rail or higher
input voltage improves the noise because greater headroom is provided for the internal circuits.
Table 4 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5.0-V output for a variety of conditions
with an input voltage of 5.5 V, an R1 of 12.1 kΩ, and a load current of 2 A. The 5.0-V output was used because
this output is the worst-case condition for output voltage noise.
Table 4. Output Noise Voltage at a 5.0-V Output
OUTPUT VOLTAGE NOISE
(µVRMS)
CNR/SS
(nF)
CFF
(nF)
COUT
(µF)
11.7
10
10
22
7.7
100
10
22
6
100
100
22
7.4
100
10
1000
5.8
100
100
1000
8.1.4 Charge Pump Noise
The device internal charge pump generates a minimal amount of noise. Use a bias rail to minimize the internal
charge pump noise when the internal voltage is clamped, thereby reducing the overall output noise floor.
The high-frequency components of the output voltage noise density curves are filtered out in most applications
by using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and
the load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.
8.1.5 Current Sharing
Current sharing is possible through the use of external operational amplifiers. For more details, see the TI Design
Current-Sharing Dual LDOs and the verified reference design 6 A Current-Sharing Dual LDO.
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8.1.6 Adjustable Operation
As shown in Figure 43, the output voltage of the TPS7A52-Q1 is set using external resistors.
Optional Bias
Supply
CBIAS
BIAS
EN
PG
RPG
Input
Supply
IN
To Load
OUT
CIN
CFF
R1
TI-'HYLFHŒ
COUT
FB
NR/SS
R2
CNR/SS
GND
Figure 43. Adjustable Operation
Use Equation 4 to calculate R1 and R2 for any output voltage range. This resistive network must provide a
current equal to or greater than 5 µA for dc accuracy. To optimize the noise and PSRR, use an R1 of 12.1 kΩ.
VOUT = VNR/SS × (1 + R1 / R2)
(4)
Table 5 shows the resistor combinations required to achieve several common rails using standard 1%-tolerance
resistors.
Table 5. Recommended Feedback-Resistor Values
(1)
FEEDBACK RESISTOR VALUES (1)
TARGETED OUTPUT
VOLTAGE
(V)
R1 (kΩ)
R2 (kΩ)
CALCULATED OUTPUT
VOLTAGE
(V)
0.9
12.4
100
0.899
0.95
12.4
66.5
0.949
1.00
12.4
49.9
0.999
1.10
12.4
33.2
1.099
1.20
12.4
24.9
1.198
1.50
12.4
14.3
1.494
1.80
12.4
10
1.798
1.90
12.1
8.87
1.89
2.50
12.4
5.9
2.48
2.85
12.1
4.75
2.838
3.00
12.1
4.42
2.990
3.30
11.8
3.74
3.324
3.60
12.1
3.48
3.582
4.5
11.8
2.55
4.502
5.00
12.4
2.37
4.985
R1 is connected from OUT to FB; R2 is connected from FB to GND.
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8.1.7 Power-Good Operation
For proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ. The
lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the upper limit
of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is outside of
this range, then the power-good signal may not read a valid digital logic level.
Using a large CFF with a small CNR/SS causes the power-good signal to incorrectly indicate that the output voltage
has settled during turnon. The CFF time constant must be greater than the soft-start time constant for proper
operation of the PG during start-up. For a detailed description, see Pros and Cons of Using a Feed-Forward
Capacitor with a Low Dropout Regulator.
The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO
events and at light loads, power-good does not assert because the output voltage is sustained by the output
capacitance.
8.1.8 Undervoltage Lockout (UVLO) Operation
The UVLO circuit makes sure that the device remains disabled before the input or bias supplies reach the
minimum operational voltage range, and that the device shuts down when the input supply or bias supply falls
too low.
The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a
downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the
UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device.
When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled.
The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall
time of the input supply when operating near the minimum VIN, or by using a bias rail.
Figure 44 shows the UVLO circuit response to various input voltage events. The diagram can be separated into
the following regions:
•
•
•
•
•
•
•
Region A: The device does not turn on until the input reaches the UVLO rising threshold.
Region B: Normal operation with a regulated output
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device is still enabled.
Region D: Normal operation with a regulated output
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up then follows.
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 44. Typical UVLO Operation
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8.1.9 Dropout Voltage (VDO)
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (VDO = VIN – VOUT) that is required for regulation. When VIN drops below the required VDO for the
given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is proportional to the output current because the device is operating as a resistive switch.
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect
to VIN on this device because of the internal charge pump. The charge pump causes a higher dropout voltage at
lower input voltages when a bias rail is not used.
For this device, dropout voltage increases exponentially when the input voltage nears its maximum operating
voltage because the charge pump is internally clamped to 8.0 V.
8.1.10 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load, and the transition from a heavy to a light load. The regions shown in
Figure 45 are broken down in this section. Regions A, E, and H are where the output voltage is in steady-state
regulation.
tAt
tCt
tDt
B
tEt
tGt
tHt
F
Figure 45. Load Transient Waveform
During transitions from a light load to a heavy load:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B).
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C).
During transitions from a heavy load to a light load:
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F).
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G).
Transitions between current levels changes the internal power dissipation because the TPS7A52-Q1 is a highcurrent device (region D). The change in power dissipation changes the die temperature during these transitions,
and leads to a slightly different voltage level. This different output voltage level shows up in the various load
transient responses.
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
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8.1.11 Reverse Current Protection Considerations
As with most LDOs, this device can be damaged by excessive reverse current.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the
absolute maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT, then the input supply collapses quickly and the load current becomes very
small
• The output is biased when the input supply is not established
• The output is biased above the input supply
If an excessive reverse current flow is expected in the application, then external protection must be used to
protect the device. Figure 46 shows one approach of protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 46. Example Circuit for Reverse Current Protection Using a Schottky Diode
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8.1.12 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 5 to calculate PD:
PD = (VOUT - VIN) ´ IOUT
(5)
NOTE
Power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output
voltage differential to be obtained. The low dropout of the TPS7A52-Q1 allows for
maximum efficiency across a wide range of output voltages.
The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad
to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any
inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 6. The equation is rearranged for output current in Equation 7.
TJ = TA + (RθJA × PD)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(6)
(7)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a welldesigned thermal layout, RθJA is actually the sum of the VQFN package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.13 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 8 and are given in the Electrical Characteristics table.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in Equation 5
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(8)
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8.2 Typical Application
This section discusses the implementation of the TPS7A52-Q1 using an adjustable feedback network to regulate
a 2-A load requiring good PSRR at high frequency with low-noise at an output voltage of 5.0 V. Figure 47
provides a schematic for this typical application circuit.
Optional Bias
Supply
CBIAS
BIAS
EN
PG
RPG
Input
Supply
IN
To Load
OUT
CIN
CFF
R1
TI-'HYLFHŒ
COUT
FB
NR/SS
R2
CNR/SS
GND
Figure 47. Typical Application for a 5.0-V Rail
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 6 as the input parameters.
Table 6. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
5.50 V, ±1%, provided by the dc/dc converter switching at 500 kHz
Bias voltage
Not used because VOUT ≥ 2.20 V
Output voltage
5.0 V, ±1%
Output current
2.0 A (maximum), 10 mA (minimum)
RMS noise, 10 Hz to 100 kHz
< 10 µVRMS
PSRR at 500 kHz
> 40 dB
Start-up time
< 25 ms
8.2.2 Detailed Design Procedure
At 2.0 A and 5.0 VOUT, the dropout of the TPS7A52-Q1 has a 200-mV maximum dropout over temperature; thus,
a 500-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high
temperature on some devices, the TPS7A52-Q1 can enter dropout if both the input and output supply are
beyond the edges of the respective accuracy specification.
For a 5.0-V output. use external adjustable resistors. See the resistor values in listed Table 5 for choosing
resistors for a 5.0-V output.
Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.
Ceramic capacitances of 10 µF for the input and 22 µF for the output are selected.
To satisfy the required start-up time and still maintain low noise performance, a 100-nF CNR/SS is selected. Use
Equation 9 to calculate this value.
tSS = (VNR/SS × CNR/SS) / INR/SS
28
(9)
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At the 2.0-A maximum load, the internal power dissipation is 1.0 W and corresponds to a 43.4°C junction
temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient
temperature, the junction temperature is at 98.4°C. To further minimize noise, a feed-forward capacitance (CFF)
of 10 nF is selected.
8.2.3 Application Curves
2
2A/us
1A/us
0.5A/us
40
30
Output Voltage Noise Density (PVRMS)
AC-Coupled Output Voltage (mV)
50
20
10
0
-10
-20
-30
-40
-50
0
50
100
150
Time (ms)
200
250
300
1
0.1
0.01
CFF = 0 nF, 22 PVRMS
CFF = 1 nF, 15.7 PVRMS
CFF = 10 nF, 11.8 PVRMS
CFF = 100 nF, 10.2 PVRMS
0.001
10
100
Fig1
VOUT = 5.0 V
1k
10k
100k
Frequency (Hz)
1M
10M
Fig1
VOUT = 5.0 V
Figure 48. Load Transient vs Slew Rate
Figure 49. Noise vs Frequency and CFF
9 Power Supply Recommendations
The TPS7A52-Q1 is designed to operate from an input voltage supply range between 1.1 V and 6.5 V. If the
input supply is less than 1.4 V, then a bias rail of at least 3.0 V must be used. The input voltage range provides
adequate headroom in order for the device to have a regulated output. This input supply must be well regulated.
If the input supply is noisy, use additional input capacitors with low ESR to help improve output noise
performance.
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10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. To avoid negative system performance, do not use of vias and long traces to the input and
output capacitors. The grounding and layout scheme provided in Figure 50 minimizes inductive parasitics, and
thereby reduces load-current transients, minimizes noise, and increases circuit stability.
To improve performance, use a ground reference plane, either embedded in the PCB itself or placed on the
bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output
voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when
connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.
10.1.2 RTK Package—High CTE Mold Compound
The RTK package uses a mold compound with a high coefficient of thermal expansion (CTE) of 12 ppm/°C. This
mold compound allows for the CTE of the packaged IC to more closely match the CTE of a conventional FR4
PCB (~14 ppm/°C to 17 ppm/°C). This CTE match is important when considering the effects that temperature
swings can induce on a board with large differences in CTE values. Package and board combinations with widely
dissimilar CTEs can experience mechanical cracking or fracturing of the solder joints caused by frequent
changes in temperature and the corresponding differences in expansion. Devices with normal mold compounds
in similar packages typically have CTE values that are 25% lower than values found with the RTK package.
30
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10.2 Layout Example
CBIAS
To Bias Supply
NC
NC
NC
GND
NC
NC
Ground Plane for Thermal Relief and Signal
Ground
10
9
8
7
6
11
5
RPG
BIAS
12
4
PG Output
PG
R2
Thermal Pad
To Signal Ground
To PG Pullup Supply
DNC
NR/SS
13
3
FB
EN
14
2
NC
To Signal Ground
CNR/SS
Enable Signal
To Load
CFF R1
1
17
18
19
20
IN
GND
OUT
OUT
Input Power Plane
16
IN
15
IN
CIN
OUT
Output Power Plane
COUT
Power Ground Plane
Vias used for application purposes.
Figure 50. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A52.
The summary information for this fixture is shown in Table 7. The EVM can be requested through the TPS7A52
product folder.
Table 7. Evaluation Module
DEVICE
LITERATURE NUMBER
TPS7A52EVM-002 evaluation module
SBVU042
11.1.1.2 Reference Designs
For related TI reference designs, see the following:
TI Design - Current-Sharing Dual LDOs (TIDA-00270)
11.1.1.3 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. Models for the TPS7A52 are available through the TPS7A52 product folder under
Tools and Software → Models.
11.1.2 Device Nomenclature
Table 8. Ordering Information (1)
PRODUCT
TPS7A5201QYYYZ Q1
(1)
DESCRIPTION
YYY is the package designator.
Z is the package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, TPS3702 High-Accuracy, Overvoltage and Undervoltage Monitor Data Sheet
• Texas Instruments, TPS7A52-Q1 Automotive 2A High-Accuracy Low-Noise LDO Voltage Regulator
Evaluation Module
• Texas Instruments, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator
Application Report
• Texas Instruments, 6 A Current-Sharing Dual LDO User's Guide
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11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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TPS7A52-Q1
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PACKAGE OUTLINE
RTK0020C
VQFNP - 0.9 mm max height
SCALE 3.500
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.05
0.00
DETAIL A
4.1
3.9
PIN 1 ID
(
(0.09)
TYPICAL
DETAIL A
SCALE 20.000
3.75)
(0.15)
(0.15)
DETAIL B
DETAIL B
C
0.9 MAX
SCALE 20.000
TYPICAL
SEATING PLANE
(0.2)
0.08 C
SEE DETAIL A
2.3 0.1
SEE DETAIL B
SYMM
4X (45 X0.6)
10
6
5
11
SYMM
21
4X
2
1
15
16X 0.5
PIN 1 ID
(OPTIONAL)
EXPOSED
THERMAL PAD
20X
16
20
20X
0.6
0.4
0.30
0.18
0.1
0.05
C B A
C
4223543/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTK0020C
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.3)
(0.9) TYP
20
16
20X (0.7)
20X (0.25)
1
15
(0.9)
TYP
21
SYMM
(3.7)
(R0.05)
TYP
16X (0.5)
11
5
( 0.2) VIA
TYP
6
SYMM
10
(3.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223543/A 03/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTK0020C
VQFNP - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.61) TYP
20
16
20X (0.7)
21
20X (0.25)
1
15
(0.61)
TYP
SYMM
(3.7)
16X (0.5)
11
5
(R0.05)
TYP
METAL
TYP
6
10
4X ( 1.02)
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21:
79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223543/A 03/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A5201QRGRRQ1
ACTIVE
VQFN
RGR
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
A5201
TPS7A5201WQRTKRQ1
ACTIVE
VQFN
RTK
20
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 150
5201WQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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