TPS7A8500RGRT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 TPS7A85 High-Current (4 A), High-Accuracy (1%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator 1 Features 3 Description • • The TPS7A85 is a low-noise (4.4 µVRMS), low-dropout linear regulator (LDO) capable of sourcing 4 A with only 240 mV of maximum dropout. The device output voltage is pin-programmable from 0.8 V to 3.95 V and adjustable from 0.8 V to 5.0 V using an external resistor divider. 1 • • • • • • • • • • • Low Dropout: 150 mV (typ) at 4 A 1% (max) Accuracy Over Line, Load, and Temperature Output Voltage Noise: – 4.4 µVRMS at 0.8-V Output – 8.4 µVRMS at 5.0-V Output Input Voltage Range: – Without BIAS: 1.4 V to 6.5 V – With BIAS: 1.1 V to 6.5 V ANY-OUT™ Operation: – Output Voltage Range: 0.8 V to 3.95 V Adjustable Operation: – Output Voltage Range: 0.8 V to 5.0 V Power-Supply Ripple Rejection: – 40 dB at 500 kHz Excellent Load Transient Response Adjustable Soft-Start In-Rush Control Open-Drain Power-Good (PG) Output Stable with a 47-µF or Larger Ceramic Output Capacitor Operating Temperature Range: –40ºC to +125°C 3.5-mm × 3.5-mm, 20-Pin VQFN 2 Applications • • • • • Digital Loads: SerDes, FPGAs, and DSPs Instrumentation, Medical, and Audio High-Speed Analog Circuits: – VCO, ADC, DAC, and LVDS Imaging: CMOS Sensors and Video ASICs Test and Measurement Powering RF Components The combination of low-noise (4.4 µVRMS), highPSRR, and high output current capability makes the TPS7A85 ideal to power noise-sensitive components such as those found in high-speed communications, video, medical, or test and measurement applications. The high performance of the TPS7A85 limits power-supply-generated phase noise and clock jitter, making this device ideal for powering highperformance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and RF components. Specifically, RF amplifiers benefit from the high-performance and 5.0-V output capability of the device. For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.75% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A85 ensure optimal system performance. The versatility of the TPS7A85 makes the device a component of choice for many demanding applications. Device Information(1) PART NUMBER TPS7A85 PACKAGE VQFN (20) BODY SIZE (nom) 3.50 mm × 3.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Powering Digital Loads Bias Supply Bias Supply BIAS BIAS Input Supply IN Input Supply TPS7A85 IN TPS7A85 OUT EN Signal OUT EN EN Signal PG EN PG VDD ADC ADS54J40 ADS54J66 ACD31JB68 DAC DAC38J82 DAC39J84 DAC5670 GPIO DSP, ASIC, FPGA C6000 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configurations and Functions ....................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 15 7.1 Overview ................................................................. 15 7.2 Functional Block Diagram ....................................... 16 7.3 Feature Description................................................. 17 7.4 Device Functional Modes........................................ 19 8 Application and Implementation ........................ 20 8.1 Application Information............................................ 20 8.2 Typical Applications ................................................ 35 9 Power-Supply Recommendations...................... 37 10 Layout................................................................... 38 10.1 Layout Guidelines ................................................. 38 10.2 Layout Example .................................................... 38 11 Device and Documentation Support ................. 39 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 39 39 39 40 40 40 12 Mechanical, Packaging, and Orderable Information ........................................................... 40 4 Revision History Changes from Original (January 2016) to Revision A • 2 Page Released to production .......................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 5 Pin Configurations and Functions OUT OUT GND IN IN 20 19 18 17 16 RGR Package 3.5-mm × 3.5-mm, 20-Pin VQFN Top View OUT 1 15 IN SNS 2 14 EN FB 3 13 NR/SS PG 4 12 BIAS 50mV 5 11 1.6V 6 7 8 9 10 100mV 200mV GND 400mV 800mV Thermal Pad Pin Functions PIN NAME NO. 50mV 5 100mV 6 200mV 7 400mV 9 800mV 10 1.6V 11 BIAS I/O DESCRIPTION I ANY-OUT voltage setting pins. Connect these pins to ground, SNS, or leave floating. Connecting these pins to ground increases the output voltage, whereas connecting these pins to SNS increases the resolution of the ANY-OUT network but decreases the range of the network; multiple pins can be simultaneously connected to GND or SNS to select the desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output Voltage section for additional details. 12 I BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.2 V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance for VIN ≤ 2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used, this pin must be left floating or tied to ground. EN 14 I Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN. If enable functionality is required, VEN must always be high after VIN is established when a BIAS supply is used. See the Sequencing Requirements section for more details. FB 3 I Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor can disrupt PG (power good) functionality. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details. GND 8, 18 — IN 15-17 I 13 — Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. See the NoiseReduction and Soft-Start Capacitor section for more details. 1, 19, 20 O Regulated output pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to the load. See the Input and Output Capacitor Requirements section for more details. PG 4 O Active-high, power-good pin. An open-drain output indicates when the output voltage reaches 89.3% of the target. The use of a feed-forward capacitor can disrupt PG (power good) functionality. See the Power-Good (PG) Function section for more details. SNS 2 I Output voltage sense input pin. This pin connects the internal R1 resistor to the output. Connect this pin to the load side of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin floating. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details. NR/SS OUT Thermal pad — Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection. Input supply voltage pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from IN to ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as possible. See the Input and Output Capacitor Requirements section for more details. Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 3 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over junction temperature range (unless otherwise noted) (1) Voltage MIN MAX IN, BIAS, PG, EN –0.3 7.0 IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs) –0.3 7.5 SNS, OUT –0.3 VIN + 0.3 (2) NR/SS, FB –0.3 3.6 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V –0.3 VOUT + 0.3 OUT Current UNIT V Internally limited PG (sink current into device) A 5 mA Operating junction temperature, TJ –55 150 °C Storage temperature, Tstg –55 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The absolute maximum rating is VIN + 0.3 V or 7.0 V, whichever is smaller. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage range 1.1 6.5 V VBIAS Bias supply voltage range (1) 3.0 6.5 V VOUT Output voltage range (2) 0.8 5 V VEN Enable voltage range 0 VIN V IOUT Output current 0 4 CIN Input capacitor 10 47 COUT Output capacitor 47 47 || 10 || 10 (3) RPG Power-good pullup resistance 10 CNR/SS NR/SS capacitor 10 nF CFF Feed-forward capacitor 10 nF R1 Top resistor value in feedback network for adjustable operation 12.1 (4) kΩ R2 Bottom resistor value in feedback network for adjustable operation TJ Operating junction temperature (1) (2) (3) (4) (5) 4 –40 A µF µF 100 kΩ 160 (5) kΩ 125 °C BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V. This output voltage range does not include device accuracy or accuracy of the feedback resistors. The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency range is a typical value for dc-dc supplies. The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R1 value. The upper limit for the R2 resistor is to ensure accuracy by making the current through the feedback network much larger than the leakage current into the feedback node. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 6.4 Thermal Information TPS7A85 THERMAL METRIC (1) RGR (VQFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 35.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 47.6 °C/W RθJB Junction-to-board thermal resistance 12.3 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 12.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.0 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics Over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.5 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V (1), OUT connected to 50 Ω to GND (2), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF, CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS MIN TYP VIN Input supply voltage range (3) VBIAS Bias supply voltage range (3) VFB Feedback voltage 0.8 VNR/SS NR/SS pin voltage 0.8 VUVLO1(IN) Input supply UVLO with BIAS VIN rising with VBIAS = 3.0 V 1.02 VHYS1(IN) VUVLO1(IN) hysteresis VBIAS = 3.0 V 320 VUVLO2(IN) Input supply UVLO without BIAS VIN rising 1.31 VHYS2(IN) VUVLO2(IN) hysteresis VUVLO(BIAS) Bias supply UVLO VBIAS rising, VIN = 1.1 V VHYS(BIAS) VUVLO(BIAS) hysteresis VIN = 1.1 V ΔVOUT/ ΔVIN ΔVOUT/ ΔIOUT VDO Output voltage V 3.0 6.5 V V V 1.085 1.39 Dropout voltage 290 0.8 – 1.0% 5.0 + 1.0% –1.0% 1.0% –0.75% 0.75% IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.0035 5 mA ≤ IOUT ≤ 4 A, 3.0 V ≤ VBIAS ≤ 6.5 V, VIN = 1.1 V 0.07 5 mA ≤ IOUT ≤ 4 A 0.08 mV/A 0.4 VIN = 1.4 V, IOUT = 4 A, VFB = 0.8 V – 3% 215 320 VIN = 5.5 V, IOUT = 4 A, VFB = 0.8 V – 3% 325 500 VIN = 1.1 V, VBIAS = 5.0 V, IOUT = 4 A, VFB = 0.8 V – 3% 150 240 5.2 5.7 ILIM Output current limit VOUT forced at 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V ISC Short-circuit current limit RLOAD = 20 mΩ 1.0 VIN = 6.5 V, IOUT = 5 mA 2.8 4.0 VIN = 1.4 V, IOUT = 4 A 4.8 6.0 IGND GND pin current Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V (1) (2) (3) (4) (5) V mV/V 5 mA ≤ IOUT ≤ 4 A, VOUT = 5.0 V 4.7 V mV Using external resistors (4) VIN = 1.1 V, 5 mA ≤ IOUT ≤ 4 A, 3.0 V ≤ VBIAS ≤ 6.5 V Load regulation 2.9 3.95 + 1.0% 0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 4 A, over VIN V mV 0.8 – 1.0% Accuracy with BIAS Line regulation 2.83 V mV Using the ANY-OUT pins Accuracy (4) (5) UNIT 6.5 253 Range VOUT VIN = 1.1 V MAX 1.1 mV A A 25 mA µA VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the expected VOUT value set by the external feedback resistors. This 50-Ω load is disconnected when the test conditions specify an IOUT value. BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V. When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included. The device is not tested under conditions where VIN > VOUT + 1.25 V and IOUT = 4 A, because the power dissipation is higher than the maximum rating of the package. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 5 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Electrical Characteristics (continued) Over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.5 V (whichever is greater), VBIAS = open, VOUT(nom) = 0.8 V(1), OUT connected to 50 Ω to GND(2), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF, CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER IEN TEST CONDITIONS EN pin current VIN = 6.5 V, VEN = 0 V and 6.5 V IBIAS BIAS pin current VIN = 1.1 V, VBIAS = 6.5 V, VOUT(nom) = 0.8 V, IOUT = 4 A VIL(EN) EN pin high-level input voltage (enable device) VIH(EN) EN pin low-level input voltage (disable device) VIT(PG) PG pin threshold For falling VOUT VHYS(PG) PG pin hysteresis For rising VOUT VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA (current sunk into pin) Ilkg(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5 V INR/SS NR/SS pin charging current VNR/SS = GND, VIN = 6.5 V IFB FB pin leakage current VIN = 6.5 V PSRR Vn Power-supply ripple rejection Output noise voltage Tsd Thermal shutdown temperature TJ Operating junction temperature 6 VIN – VOUT = 0.5 V, IOUT = 4 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF MIN TYP –0.1 MAX µA 3.5 mA 0 0.5 V 1.1 6.5 V 93% × VOUT V 2.3 82% × VOUT 88.3% × VOUT 1% × VOUT 4.0 6.2 –100 f = 10 kHz, VOUT = 0.8 V, VBIAS = 5.0 V 42 f = 500 kHz, VOUT = 0.8 V, VBIAS = 5.0 V 39 f = 10 kHz, VOUT = 3.3 V 40 f = 500 kHz, VOUT = 3.3 V 25 BW = 10 Hz to 100 kHz, VIN = 1.2 V, VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 4 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF 4.4 BW = 10 Hz to 100 kHz, VOUT = 5.0 V, IOUT = 4 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF 8.4 Shutdown, temperature increasing 160 Reset, temperature decreasing 140 V 0.4 V 1 µA 9.0 µA 100 nA dB μVRMS –40 Submit Documentation Feedback UNIT 0.1 °C 125 °C Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 6.6 Typical Characteristics at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) 100 IOUT = 0.1 A IOUT = 0.5 A IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A IOUT = 3.5 A IOUT = 4.0 A 80 60 40 20 0 10 100 1k 10k 100k Frequency (Hz) 1M Power Supply-Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 100 80 60 40 20 0 10 10M VIN = 1.2 V, VBIAS = 5 V, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF 1k 10k 100k Frequency (Hz) 1M 10M Figure 2. PSRR vs Frequency and VIN with Bias 100 VBIAS = 0 V VBIAS = 3.0 V VBIAS = 5.0 V VBIAS = 6.5 V 80 60 40 20 0 10 100 1k 10k 100k Frequency (Hz) 1M Power-Supply Rejection Ratio (dB) 100 80 60 40 20 0 10 10M VIN = 1.4 V, IOUT = 1 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF VIN = 1.1 V, VBIAS = 5 V VIN = 1.2 V, VBIAS = 5 V VIN = 1.4 V, VBIAS = 0 V VIN = 2.5 V, VBIAS = 0 V VIN = 5.0 V, VBIAS = 0 V 100 1k 10k 100k Frequency (Hz) 1M 10M IOUT = 1 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF Figure 3. PSRR vs Frequency and VBIAS Figure 4. PSRR vs Frequency and VIN 100 VOUT = 0.8 V VOUT = 0.9 V VOUT = 1.1 V VOUT = 1.2 V VOUT = 1.5 V VOUT = 1.8 V VOUT = 2.5 V 80 60 40 20 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M VIN = VOUT + 0.4 V, VBIAS = 5.0 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF Figure 5. PSRR vs Frequency and VOUT with Bias Power-Supply Rejection Ratio (dB) 100 Power-Supply Rejection Ratio (dB) 100 IOUT = 4 A, VBIAS = 5 V, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF Figure 1. PSRR vs Frequency and IOUT Power-Supply Rejection Ratio (dB) VIN = 1.10 V VIN = 1.15 V VIN = 1.20 V VIN = 1.25 V VIN = 1.30 V VIN = 1.35 V VIN = 1.40 V VIN = 3.60 V VIN = 3.65 V VIN = 3.70 V VIN = 3.75 V VIN = 3.80 V VIN = 3.85 V VIN = 3.90 V 80 60 40 20 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF Figure 6. PSRR vs Frequency and VIN for VOUT = 3.3 V Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 7 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) 100 COUT = 47 PF||10 PF||10 PF COUT = 47 PF COUT = 100 PF COUT = 200 PF COUT = 500 PF 80 60 40 20 0 10 100 1k 10k 100k Frequency (Hz) 1M Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 100 Figure 7. PSRR vs Frequency and COUT 40 20 60 40 20 100 1k 10k 100k Frequency (Hz) 1M 40 20 VBIAS = 3.0 V VBIAS = 5.0 V VBIAS = 6.5 V 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 10. VBIAS PSRR vs Frequency 2 IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A IOUT = 4.0 A VOUT = 0.8 V, 4.5 PVRMS VOUT = 1.5 V, 5.4 PVRMS VOUT = 3.3 V, 8.5 PVRMS VOUT = 5.0 V, 12.4 PVRMS 1 Output Voltage Noise (PV/—Hz) Output Voltage Noise (PVRMS) 10M VIN = VOUT + 0.4 V, VOUT = 1 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF 15 10.5 9 7.5 6 4.5 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 1.2 1.8 2.4 3 3.6 Output Voltage (V) 4.2 4.8 5.4 VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF Figure 11. Output Voltage Noise vs Output Voltage 8 1M 60 Figure 9. PSRR vs Frequency and VIN for VOUT = 5.0 V 3 0.6 10k 100k Frequency (Hz) 80 0 10 10M IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF 12 1k Figure 8. PSRR vs Frequency and IOUT for VOUT = 5.0 V VIN = 5.35 V VIN = 5.4 V VIN = 5.45 V VIN = 5.5 V VIN = 5.55 V VIN = 5.60 V VIN = 5.65 V 80 13.5 100 100 Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 60 VIN = VOUT + 0.4 V, VOUT = 1 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF 100 0 10 80 0 10 10M VIN = 5.6 V, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF IOUT = 0.1 A IOUT = 0.5 A IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A IOUT = 4.0 A 0.001 10 100 1k 10k Frequency (Hz) 100k 1M VIN = VOUT + 0.4 V and VBIAS = 5 V for VOUT ≤ 2.2 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF Figure 12. Output Noise vs Frequency and VOUT Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 Typical Characteristics (continued) at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) 2 2 VIN = 1.4 V, VBIAS = 5.0 V, 4.5 PVRMS VIN = 1.4 V, 6.0 PVRMS VIN = 1.5 V, 4.5 PVRMS VIN = 1.8 V, 4.5 PVRMS VIN = 2.5 V, 4.6 PVRMS VIN = 5.0 V, 5.15 PVRMS 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10 100 1k 10k Frequency (Hz) 100k 0.001 10 1M IOUT = 1 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF Figure 13. Output Noise vs Frequency and VIN 1k 10k Frequency (Hz) 100k 1M Figure 14. Output Noise vs Frequency and CNR/SS 2 CFF = 0 nF, 6.2 PVRMS CFF = 0.1 nF, 5.8 PVRMS CFF = 1 nF, 4.9 PVRMS CFF = 10 nF, 4.5PVRMS CFF = 100 nF, 4.4 PVRMS 0.5 0.2 CNR/SS = 10 nF, 12.3 PVRMS CNR/SS = 100 nF, 8.4 PVRMS CFF = CNR/SS = 100 nF, 6.6 PVRMS 1 Output Voltage Noise (PV/—Hz) 1 0.1 0.05 0.02 0.01 0.005 0.002 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10 100 1k 10k Frequency (Hz) 100k 0.001 10 1M 100 1k 10k Frequency (Hz) 100k 1M VIN = 5.6 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF Figure 15. Output Noise vs Frequency and CFF Figure 16. Output Noise at 5.0-V Output vs CNR/SS and CFF 1.2 10 50 Output Current VOUT = 0.9 V VOUT = 1.2 V VOUT = 1.8 V 1 0.6 0.4 VEN VOUT, CNR/SS = 0 nF VOUT, CNR/SS = 10 nF VOUT, CNR/SS = 47 nF VOUT, CNR/SS = 100 nF 0.2 0 -0.2 Output Current (A) 7.5 0.8 25 5 0 2.5 -25 0 0 5 10 15 20 25 30 Time (ms) 35 40 45 50 VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5.0 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF Figure 17. Start-Up Waveform vs Time and CNR/SS AC-Coupled Output Voltage (mV) Output Voltage Noise (PV/—Hz) 100 VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 4 A, COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF 2 Voltage (V) CNR/SS = 0 nF, 6.2 PVRMS CNR/SS = 1 nF, 4.9 PVRMS CNR/SS = 10 nF, 4.5 PVRMS CNR/SS = 100 nF, 4.4 PVRMS 1 Output Voltage Noise (PV/—Hz) Output Voltage Noise (PV/—Hz) 1 -50 0 0.5 1 Time (ms) 1.5 2 VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT, DC = 100 mA, slew rate = 1 A/μs, CNR/SS = CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF Figure 18. Load Transient Waveform vs Time and VOUT with Bias Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 9 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) 50 Output Current (A) 7.5 25 5 0 2.5 -25 0 0.4 0.8 1.2 Time (ms) 1.6 25 0 -25 0 2 IOUT, DC = 100 mA, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = CFF = 10 nF, slew rate = 1 A/μs 0.8 1.2 Time (ms) 1.6 2 Figure 20. Load Transient Waveform vs Time and Slew Rate 50 50 AC-Coupled Output Voltage (mV) Figure 19. Load Transient Waveform vs Time and VOUT without Bias 25 0 -25 COUT = 100 PF COUT = 200 PF COUT = 500 PF COUT = 500 PF || 1 mF Oscon IOUT = 100 mA to 4 A IOUT = 500 mA to 4 A IOUT = 1 A to 4 A 25 0 -25 -50 0 0.4 0.8 1.2 Time (ms) 1.6 2 0 0.4 0.8 1.2 Time (ms) 1.6 2 VIN = 1.2 V, VBIAS = 5.0 V, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = CFF = 10 nF, slew rate = 1 A/μs VIN = 1.2 V, VBIAS = 5.0 V, IOUT = 100 mA to 4 A, CNR/SS = CFF = 10 nF, slew rate = 1 A/μs Figure 21. Load Transient Waveform vs Time and COUT (VOUT = 0.9 V) Figure 22. Load Transient Waveform vs Time and DC Load (VOUT = 0.9 V) 450 450 -40°C 0°C 25°C 85°C 125°C 350 -40°C 0°C 25°C 85°C 125°C 400 Dropout Voltage (mV) 400 300 250 200 350 300 250 200 150 150 1 2 3 4 Input Voltage (V) 5 6 1 IOUT = 4 A, VBIAS = 0 V 2 3 4 Input Voltage (V) 5 6 IOUT = 4 A, VBIAS = 6.5 V Figure 23. Dropout Voltage vs Input Voltage without Bias 10 0.4 VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 4 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = CFF = 10 nF -50 Dropout Voltage (mV) Slew Rate = 2 A/Ps Slew Rate = 1 A/Ps Slew Rate = 0.5 A/Ps -50 -50 0 AC-Coupled Output Voltage (mV) AC-Coupled Output Voltage (mV) 50 Output Current VOUT = 3.3 V VOUT = 5.0 V AC-Coupled Output Voltage (mV) 10 Figure 24. Dropout Voltage vs Input Voltage with Bias Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 Typical Characteristics (continued) at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) 300 0.2 -40°C 0°C 25°C 85°C 125°C 200 -40°C 0°C 25°C 85°C 125°C 0.175 Dropout Voltage (mV) Dropout Voltage (mV) 250 150 100 50 0.15 0.125 0.1 0.075 0.05 0.025 0 0 0 0.5 1 1.5 2 2.5 Output Current (A) 3 3.5 4 0 0.5 VIN = 1.4 V, VBIAS = 0 V 3 3.5 4 Figure 26. Dropout Voltage vs Output Current with Bias 0.2 350 -40°C 0°C 25°C 85°C 125°C 250 -40°C 0°C 25°C 85°C 125°C 0.15 Change in VOUT (%) 300 200 150 100 0.1 0.05 0 -0.05 50 -0.1 0.5 0 0 0.5 1 1.5 2 2.5 Output Current (A) 3 3.5 4 1 1.5 VIN = 5.5 V 2 2.5 3 3.5 Output Voltage (V) 4 4.5 5 IOUT = 100 mA to 4 A Figure 27. Dropout Voltage vs Output Current (High VIN) Figure 28. Load Regulation vs Output Voltage 0.025 0.15 -40°C 0°C 25°C 85°C 125°C 0 Change in VOUT (%) 0.1 Change in VOUT (%) 1.5 2 2.5 Output Current (A) VIN = 1.1 V, VBIAS = 3 V Figure 25. Dropout Voltage vs Output Current without Bias Dropout Voltage (mV) 1 0.05 0 -0.025 -0.05 -40°C 0°C 25°C 85°C 125°C -0.075 -0.05 -0.1 -0.1 0 0.8 1.6 2.4 Output Current (A) 3.2 4 0 Figure 29. Load Regulation (0.8-V Output) 0.8 1.6 2.4 Output Current (A) 3.2 Figure 30. Load Regulation (3.3-V Output) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 4 11 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) 0.025 0 0 -0.025 Change in VOUT (%) Change in VOUT (%) at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) -0.025 -0.05 -40°C 0°C 25°C 85°C 125°C -0.075 -0.05 -0.075 -40°C 0°C 25°C 85°C 125°C -0.1 -0.1 -0.125 0 0.8 1.6 2.4 Output Current (A) 3.2 4 1 1.5 2 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 6.5 IOUT = 5 mA Figure 31. Load Regulation (5-V Output) Figure 32. Line Regulation without Bias 0 25 Change in VOUT (ppm) Change in VOUT (ppm) 0 -25 -50 -40°C 0°C 25°C 85°C 125°C -75 3.5 4 4.5 5 Bias Voltage (V) 5.5 6 -40 -40°C 0°C 25°C 85°C 125°C -60 5.25 -100 3 -20 6.5 5.5 5.75 6 Input Voltage (V) VIN = 1.1 V, IOUT = 5 mA 6.25 6.5 IOUT = 5 mA Figure 33. Line Regulation vs Bias Voltage Figure 34. Line Regulation (5-V Output) 3.3 2.4 Bias Pin Current (mA) Ground Pin Current (mA) 3 2.7 2.4 2.1 -40°C 0°C 25°C 85°C 125°C 1.8 1.5 2 1.6 -40°C 0°C 25°C 85°C 125°C 1.2 0.8 1 2 3 4 5 Input Voltage (V) 6 7 3 3.5 IOUT = 5 mA 4.5 5 Bias Voltage (V) 5.5 6 6.5 VIN = 1.1 V, IOUT = 5 mA Figure 35. Ground Pin Current vs Input Voltage 12 4 Figure 36. Bias Pin Current vs Bias Voltage Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 Typical Characteristics (continued) at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) 6 5 -40°C 0°C 25°C 85°C 125°C Shutdown Current (PA) Shutdown Current (PA) 4 -40°C 0°C 25°C 85°C 125°C 5 3 2 1 4 3 2 1 0 0 1 1.5 2 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 6.5 3 3.5 4 4.5 5 Bias Voltage (V) 5.5 6 6.5 VIN = 1.1 V Figure 38. Shutdown Current vs Bias Voltage 1.4 7 1.2 6.5 6 5.5 -40°C 0°C 25°C 85°C 125°C 5 Input Voltage (V) NR/SS Charging Current (PA) Figure 37. Shutdown Current vs Input Voltage 7.5 1.5 2 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 0.8 0.6 VUVLO2(IN), Rising VUVLO2(IN), Falling VUVLO1(IN), Rising VUVLO1(IN), Falling 0.4 0.2 -40 4.5 1 1 6.5 -20 Figure 39. NR/SS Charging Current vs Input Voltage 40 60 80 Temperature (°C) 100 120 140 0.85 VUVLO(BIAS), Rising VUVLO(BIAS), Falling 0.8 Enable Voltage (V) 2.9 Bias Voltage (V) 20 Figure 40. VIN UVLO vs Temperature 3 2.8 2.7 2.6 2.5 -60 0 0.75 0.7 0.65 VIH(EN), VIN = 1.4 V VIH(EN), VIN = 6.5 V VIL(EN), VIN = 1.4 V VIL(EN), VIN = 6.5 V 0.6 -30 0 30 60 Temperature (°C) 90 120 150 0.55 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 VIN = 1.1 V Figure 41. VBIAS UVLO vs Temperature Figure 42. Enable Threshold vs Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 13 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.5 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V, COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted) 0.75 0.4 -40°C 0°C 25°C 85°C 125°C 0.32 PG Voltage (V) PG Voltage (V) 0.6 -40°C 0°C 25°C 85°C 125°C 0.45 0.3 0.15 0.24 0.16 0.08 0 0 0 0.5 1 1.5 2 PG Current Sink (mA) 2.5 3 0 0.5 1 1.5 2 PG Current Sink (mA) 2.5 3 VIN = 6.5 V Figure 43. PG Voltage vs PG Current Sink Figure 44. PG Voltage vs PG Current Sink 90.25 PG Threshold (% VOUT(NOM)) 90 89.75 VIT(PG) Rising, VIN = 1.4 V VIT(PG) Rising, VIN = 6.5 V VIT(PG) Falling, VIN = 1.4V VIT(PG) Falling, VIN = 6.5 V 89.5 89.25 89 88.75 88.5 88.25 88 87.75 -50 -25 0 25 50 Temperature (°C) 75 100 125 Figure 45. PG Threshold vs Temperature 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 7 Detailed Description 7.1 Overview The TPS7A85 is a high-current (4 A), low-noise (4.4 µVRMS), high accuracy (1%) low-dropout linear voltage regulator (LDO). These features make the device a robust solution to solve many challenging problems in generating a clean, accurate power supply. The TPS7A85 has several features that make the device useful in a variety of applications. As detailed in the Functional Block Diagram section, these features include: • • • • • • • • • Low-noise, high-PSRR output ANY-OUT resistor network Optional bias rail Power-good (PG) output Programmable soft-start Foldback current limit Enable circuitry Active discharge Thermal protection Overall, these features make the TPS7A85 the component of choice because of its versatility and ability to generate a supply for most applications. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 15 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 7.2 Functional Block Diagram PSRR Boost IN Current Limit OUT Charge Pump BIAS 0.8-V VREF Active Discharge RNR/SS = 250 k: + Error Amp ± INR/SS SNS NR/SS 200 pF R1 = 2×R = 12.1 k: FB 1×R = 6.05 k: 1.6V UVLO Circuits 2×R = 12.1 k: Internal Controller 800mV 4×R = 24.2 k: 400mV 8×R = 48.4 k: 200mV 16×R = 96.8 k: 100mV 32×R = 193.6 k: 50mV ANY-OUT Network Thermal Shutdown PG ± 0.893 x VREF EN + GND NOTE: For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual resistance can vary significantly from the values listed. 16 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 7.3 Feature Description 7.3.1 Low-Noise, High-PSRR Output The TPS7A85 includes a low-noise reference and error amplifier ensuring minimal noise during operation. The NR/SS capacitor (CNR/SS) and feed-forward capacitor (CFF) are the most effective way to reduce device noise. CNR/SS filters the noise from the reference and CFF filters the noise from the error amplifier. The noise contribution from the charge pump is minimal. The overall noise of the system at low output voltages can be reduced by using a bias rail because this rail provides more headroom for internal circuitry. The high power-supply rejection ratio (PSRR) of the TPS7A85 ensures minimal coupling of input supply noise to the output. The PSRR performance primarily results from a high-bandwidth, high-gain error amplifier and an innovative circuit to boost the PSRR between 200 kHz and 1 MHz. The combination of a low noise floor and high PSRR ensure that the device provides a clean supply to the application; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR performance. 7.3.2 Integrated Resistance Network (ANY-OUT) An internal feedback resistance network is provided, allowing the TPS7A85 output voltage to be programmed easily between 0.8 V to 3.95 V with a 50-mV step by tying the ANY-OUT pins to ground. Tying the ANY-OUT pins to SNS increases the resolution but limits the range of the output voltage because the effective value of R1 is decreased. The ANY-OUT network provides excellent accuracy across output voltage and temperature; see the Application and Implementation section for more details. 7.3.3 Bias Rail The device features a bias rail to enable low-input voltage, low-output (LILO) voltage operation by providing power to the internal circuitry of the device. The bias rail is required for operation with VIN < 1.4 V. An internal power MUX supplies the greater of either the input voltage or the bias voltage to an internal charge pump to power the internal circuitry. Unlike other LDOs that have a bias supply, the TPS7A85 does not have a minimum bias voltage with respect to the input supply because an internal charge pump is used instead. The internal charge pump multiples the output voltage of the power MUX by a factor of 4 to a maximum of typically 8 V; therefore, using a bias supply with VIN ≤ 2.2 V is recommended for optimal dc and ac performance. Sequencing requirements exist for when the bias rail is used; see the Sequencing Requirements section for more details. 7.3.4 Power-Good (PG) Function The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage. When the feedback pin voltage falls below the PG threshold voltage (VIT(PG) + VHYS(PG), typically 89.3%), the PG pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the VIT(PG) threshold by an amount greater than VHYS(PG) (typically 91.3%), the PG pin becomes high impedance. By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using an external voltage detector device such as the TPS3702 is also recommended in applications where more accurate voltage monitoring or overvoltage monitoring is required. The use of a feed-forward capacitor (CFF) can cause glitches on start-up, and the power-good circuit may not function normally below the minimum input supply range. For more details on the use of the power-good circuitry, see the Power-Good (PG) Operation section. 7.3.5 Programmable Soft-Start Soft-start refers to the ramp-up time of the output voltage during LDO turn-on after EN and UVLO exceed the respective threshold voltages. The noise-reduction capacitor (CNR/SS) serves a dual purpose of both governing output noise reduction and programming the soft-start ramp time during turn-on. The start-up ramp is monotonic. The majority of the ramp is linear; however, there is an offset voltage in the error amplifier that can cause a small initial jump in output voltage; see the Application and Implementation section on implementing a soft-start. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 17 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Feature Description (continued) 7.3.6 Internal Current Limit (ILIM) The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased load impedance. Thermal shutdown can activate during a current limit event because of the high power dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and load. Continuous operation in current limit is not recommended. The foldback current limit crosses 0 A when VOUT < 0 V and prevents the device from turning on into a negatively-biased output. See the Negatively-Biased Output section for additional ways to ensure start-up when the TPS7A85 output is pulled below ground. If VOUT > VIN + 0.3 V, then reverse current can flow from the output to the input. The reverse current can cause damage to the device; therefore, limit this reverse current to 10% of the rated output current of the device. See the Reverse Current Protection section for more details. 7.3.7 Enable The enable pin for the TPS7A85 is active high. The output of the TPS7A85 is turned on when the enable pin voltage is greater than its rising voltage threshold (1.1 V, max), and the output of the TPS7A85 is turned off when the enable pin voltage is less than its falling voltage threshold (0.5 V, min). A voltage less than 0.5 V on the enable pin disables all internal circuits. At the next turn-on this voltage ensures a normal start-up waveform with in-rush control, provided there is enough time to discharge the output capacitance. When the enable functionality is not desired, EN must be tied to VIN. However, when the enable functionality is desired, the enable voltage must come after VIN is above VUVLO1(IN) when a BIAS rail is used; see the Application and Implementation section for further details. 7.3.8 Active Discharge Circuit The TPS7A85 has an internal pulldown MOSFET that connects a resistance of several hundred ohms to ground when the device is disabled to actively discharge the output voltage when the device is disabled. Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 10% of the device rated current for a short period of time; see the Reverse Current Protection section for more details. 7.3.9 Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) circuit monitors the input and bias voltage (VIN and VBIAS, respectively) to prevent the device from turning on before VIN and VBIAS rise above the lockout voltage. The UVLO circuit also disables the output of the device when VIN or VBIAS fall below the lockout voltage. The UVLO circuit responds quickly to glitches on VIN or VBIAS and attempts to disable the output of the device if either of these rails collapse. As a result of the fast response time of the input supply UVLO circuit, fast slew rate and short duration line transients well below the input supply UVLO falling threshold can cause momentary glitches during the edges of the transient; see the Application and Implementation section for more details. 7.3.10 Thermal Protection The TPS7A85 contains a thermal shutdown protection circuit to disable the device when thermal junction temperature (TJ) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the semiconductor die is fairly short, and thus the device may cycle on and off when thermal shutdown is reached until the power dissipation is reduced. For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the device to exceed its operational specifications. Although the internal protection circuitry of the TPS7A85 is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A85 into thermal shutdown or above a junction temperature of 125°C reduces long-term reliability. 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 7.4 Device Functional Modes 7.4.1 Operation with 1.1 V ≤ VIN < 1.4 V The TPS7A85 requires a bias voltage on the BIAS pin greater than or equal to 3.0 V if the high-current input supply voltage is between 1.1 V to 1.4 V. The bias voltage pin consumes 2.3 mA, typically. 7.4.2 Operation with 1.4 V ≤ VIN ≤ 6.5 V If the input voltage is equal to or exceeds 1.4 V, no BIAS voltage is required. The TPS7A85 is powered from either the input supply or the BIAS supply, whichever is greater. For higher performance, a BIAS rail is recommended for VIN ≤ 2.2 V. 7.4.3 Shutdown Shutting down the device reduces the ground current of the device to a maximum of 25 µA. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 19 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS7A85 is a linear voltage regulator with an input voltage range of 1.1 V to 6.5 V and an output voltage range of 0.8 V to 5.0 V with a 1% accuracy and a 4-A maximum output current. The TPS7A85 has an integrated charge pump for ease of use and an external bias rail to allow for the lowest dropout across the entire output voltage range. 8.1.1 Recommended Capacitor Types The TPS7A85 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for a effective capacitance derating of approximately 50%, but at high VIN and VOUT conditions (that is, VIN = 5.5 V to VOUT = 5.0 V) the derating can be greater than 50% and must be taken into consideration. 8.1.2 Input and Output Capacitor Requirements (CIN and COUT) The TPS7A85 is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or greater of effective capacitance) at the output and 10 µF or greater (5 μF or greater of effective capacitance) at the input. Using at least a 47-µF capacitor is highly recommended at the input to minimize input impedance. Place the input and output capacitors as near as practical to the respective input and output pins to minimize trace parasitics. If the trace inductance from the input supply to the TPS7A85 is high, a fast current transient can cause VIN to ring above the absolute maximum voltage rating and damage the device. This situation can be mitigated by additional input capacitors to dampen the ringing and to keep the ringing below the device absolute maximum ratings. A combination of multiple output capacitors boosts the high-frequency PSRR, as illustrated in several of the PSRR curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized, 10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes PSRR for the frequency range of 400 kHz to 700 kHz (which is a typical range for dc-dc supply switching frequency). This 47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a voltage derating of approximately 60% to 75% at 5.0 V, so the addition of the two 10-µF capacitors ensures that the capacitance is at or above 22 µF. 8.1.3 Noise-Reduction and Soft-Start Capacitor (CNR/SS) The TPS7A85 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CNR/SS).The use of an external CNR/SS is highly recommended, especially to minimize in-rush current into the output capacitors. This soft-start eliminates power-up initialization problems when powering fieldprogrammable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces peak in-rush current during start-up, minimizing start-up transients to the input power bus. 20 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 Application Information (continued) To achieve a monotonic start-up, the TPS7A85 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS). Soft-start ramp time can be calculated with Equation 1: tSS = (VNR/SS × CNR/SS) / INR/SS (1) Note that INR/SS is provided in the Electrical Characteristics table and has a typical value of 6.2 µA. The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the device noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with Equation 2. The typical value of RNR is 250 kΩ. Increasing the CNR/SS capacitor has a greater affect because the output voltage increases when the noise from the reference is gained up even more at higher output voltages. For low-noise applications, a 10-nF to 1-µF CNR/SS is recommended. fcutoff = 1/ (2 × π × RNR × CNR/SS) (2) 8.1.4 Feed-Forward Capacitor (CFF) Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a 10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher capacitance CFF can be used; however, the start-up time is longer and the power-good signal can incorrectly indicate that the output voltage is settled. To ensure proper PG functionality the time constant defined by CNR/SS must be greater than or equal to the time constant from the CFF. For a detailed description, see application report Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042. 8.1.5 Soft-Start and In-Rush Current Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and both UVLOs exceed their threshold voltages. The noise-reduction capacitor serves a dual purpose of both governing output noise reduction and programming the soft-start ramp during turn-on. The soft-start ramp is not fully linear as the error amplifier has a several millivolt offset voltage. The output voltage starts to ramp only after the voltage created by the soft-start circuit increases above this offset voltage, at which point the output rises quickly to the voltage on the NR/SS pin. After this initial jump, the voltage rises at the ramp rate determined by the soft-start function. This jump typically does not cause a problem in applications because the quick rise in the output voltage has a very small amplitude. In-rush current is defined as the current into the LDO at the IN pin during start-up. In-rush current then consists primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, this soft-start current can be estimated by Equation 3: VOUT(t) COUT ´ dVOUT(t) IOUT(t) = + RLOAD dt where: • • • VOUT(t) is the instantaneous output voltage of the turn-on ramp dVOUT(t) / dt is the slope of the VOUT ramp RLOAD is the resistive load impedance (3) 8.1.6 Optimizing Noise and PSRR The ultra-low noise floor and PSRR of the device can be improved by careful selection of: • CNR/SS for the low-frequency range • CFF for the mid-band frequency range • COUT for the high-frequency range • VIN – VOUT for all frequencies, and • VBIAS at lower input voltages Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 21 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Application Information (continued) The noise-reduction capacitor filters out low-frequency noise from the reference and the feed-forward capacitor reduces output voltage noise by filtering out the mid-band frequency noise. However, a large feed-forward capacitor can create some new issues that are discussed in application report Pros and Cons of Using a FeedForward Capacitor with a Low Dropout Regulator, SBVA042. Note that a large output capacitor reduces high-frequency output voltage noise. Additionally, a bias rail or higher input voltage improves the noise because greater headroom is provided for the internal circuits. A high power dissipation across the die increases the output noise because of the increase in junction temperature. A larger noise-reduction capacitor improves low-frequency PSRR by filtering any noise coupling from the input into the reference. The feed-forward capacitor can be optimized by placing a pole-zero pair near the edge of the loop bandwidth and pushing out the loop bandwidth, thus improving mid-band PSRR. Larger output capacitors and various output capacitors can be used to improve high-frequency PSRR; see Figure 7 for more details. A higher input voltage improves PSRR by providing the device more headroom to respond to noise on the input; see Figure 2. A bias rail also improves the PSRR at lower input voltages because greater headroom is provided for the internal circuits. Table 1 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5.0-V output for a variety of conditions with an input voltage of 5.6 V, an R1 of 12.1 kΩ, and a load current of 4 A. The 5.0-V output is chosen because this output is the worst-case condition for output voltage noise. Note that the input voltage is 5.6 V, not 5.5 V as provided in the Electrical Characteristics table. The higher input voltage limits the maximum ambient temperature to below 40°C on a standard-JEDEC high-K board; see the Power Dissipation (PD) section for more information. Table 1. Output Noise Voltage at a 5.0-V Output with a 5.6-V Input 22 CNR/SS (nF) CFF (nF) COUT (µF) OUTPUT VOLTAGE NOISE (µVRMS) 10 10 47 || 10 || 10 12.3 100 10 47 || 10 || 10 8.4 100 100 47 || 10 || 10 6.6 100 100 1000 6.4 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 8.1.6.1 Charge Pump Noise The device internal charge pump generates a minimal amount of noise, as shown in Figure 46. Using a bias rail minimizes the internal charge pump noise when the internal voltage is clamped, thereby reducing the overall output noise floor. The high-frequency components of the output voltage noise density curve are filtered out in most applications by using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution. 0.5 VIN = 1.5 V, 4.5 PV RMS VIN = 1.4 V, VBIAS = 5.0 V, 4.5 PV RMS 0.3 0.2 Noise (PV/—Hz) 0.1 0.07 0.05 0.03 0.02 0.01 0.007 0.005 0.003 0.002 0.001 1000000 2000000 3000000 4000000 5000000 6000000 Frequency (Hz) 7000000 8000000 9000000 1E+7 Figure 46. Charge Pump Noise 8.1.7 ANY-OUT Programmable Output Voltage The TPS7A85 can either use external resistors or the internally-matched ANY-OUT feedback resistor network to set the output voltage. The ANY-OUT resistors are accessible via pins 2 and 5 to 11 and are used to program the regulated output voltage. Each pin can be connected to ground (active) or left open (floating), or connected to SNS. ANY-OUT programming is set by Equation 4 as the sum of the internal reference voltage (VNR/SS = 0.8 V) plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV (pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 2 summarizes these voltage values associated with each active pin setting for reference. By leaving all program pins open or floating, the output is thereby programmed to the minimum possible output voltage equal to VFB. VOUT = VNR/SS + (Σ ANY-OUT Pins to Ground) (4) Table 2. ANY-OUT Programmable Output Voltage ANY-OUT PROGRAM PINS (Active Low) ADDITIVE OUTPUT VOLTAGE LEVEL Pin 5 (50mV) 50 mV Pin 6 (100mV) 100 mV Pin 7 (200mV) 200 mV Pin 9 (400mV) 400 mV Pin 10 (800mV) 800 mV Pin 11 (1.6V) 1.6 V Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 23 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Table 3 provides a full list of target output voltages and corresponding pin settings when the ANY-OUT pins are only tied to ground or left floating. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground. There are several alternative ways to set the output voltage. The program pins can be driven by using external generalpurpose input/output pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable operation, the output voltage is set according to Equation 5 except that R1 and R2 are internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by lowering the value of R1; see the Increasing ANY-OUT Resolution for LILO Conditions section for additional information. VOUT = VNR/SS × (1 + R1 / R2) (5) NOTE For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the Adjustable Operation section). Table 3. User-Configurable Output Voltage Settings 24 VOUT(NOM) (V) 50mV 100mV 200mV 400mV 800mV 1.6V VOUT(NOM) (V) 50mV 100mV 200mV 400mV 800mV 1.6V 0.80 Open Open Open Open Open Open 2.40 Open Open Open Open Open GND 0.85 GND Open Open Open Open Open 2.45 GND Open Open Open Open GND 0.90 Open GND Open Open Open Open 2.50 Open GND Open Open Open GND 0.95 GND GND Open Open Open Open 2.55 GND GND Open Open Open GND 1.00 Open Open GND Open Open Open 2.60 Open Open GND Open Open GND 1.05 GND Open GND Open Open Open 2.65 GND Open GND Open Open GND 1.10 Open GND GND Open Open Open 2.70 Open GND GND Open Open GND 1.15 GND GND GND Open Open Open 2.75 GND GND GND Open Open GND 1.20 Open Open Open GND Open Open 2.80 Open Open Open GND Open GND 1.25 GND Open Open GND Open Open 2.85 GND Open Open GND Open GND 1.30 Open GND Open GND Open Open 2.90 Open GND Open GND Open GND 1.35 GND GND Open GND Open Open 2.95 GND GND Open GND Open GND 1.40 Open Open GND GND Open Open 3.00 Open Open GND GND Open GND 1.45 GND Open GND GND Open Open 3.05 GND Open GND GND Open GND 1.50 Open GND GND GND Open Open 3.10 Open GND GND GND Open GND 1.55 GND GND GND GND Open Open 3.15 GND GND GND GND Open GND 1.60 Open Open Open Open GND Open 3.20 Open Open Open Open GND GND 1.65 GND Open Open Open GND Open 3.25 GND Open Open Open GND GND 1.70 Open GND Open Open GND Open 3.30 Open GND Open Open GND GND 1.75 GND GND Open Open GND Open 3.35 GND GND Open Open GND GND 1.80 Open Open GND Open GND Open 3.40 Open Open GND Open GND GND 1.85 GND Open GND Open GND Open 3.45 GND Open GND Open GND GND 1.90 Open GND GND Open GND Open 3.50 Open GND GND Open GND GND 1.95 GND GND GND Open GND Open 3.55 GND GND GND Open GND GND 2.00 Open Open Open GND GND Open 3.60 Open Open Open GND GND GND 2.05 GND Open Open GND GND Open 3.65 GND Open Open GND GND GND 2.10 Open GND Open GND GND Open 3.70 Open GND Open GND GND GND 2.15 GND GND Open GND GND Open 3.75 GND GND Open GND GND GND 2.20 Open Open GND GND GND Open 3.80 Open Open GND GND GND GND 2.25 GND Open GND GND GND Open 3.85 GND Open GND GND GND GND 2.30 Open GND GND GND GND Open 3.90 Open GND GND GND GND GND 2.35 GND GND GND GND GND Open 3.95 GND GND GND GND GND GND Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 8.1.8 ANY-OUT Operation Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ) the output voltage is set by grounding the appropriate control pins, as shown in Figure 47. When grounded, all control pins add a specific voltage on top of the internal reference voltage (VNR/SS = 0.8 V). The output voltage can be calculated by Equation 6 and Equation 7. Figure 47 and Figure 48 show a 3.3-V and a 0.9-V output voltage, respectively, that provides an example of the circuit usage with and without bias voltage. BIAS EN PG RPG Input Supply IN OUT To Load COUT CIN Device SNS CFF NR/SS FB CNR/SS GND 50mV 100mV 200mV 400mV 800mV 1.6V Figure 47. ANY-OUT Configuration Circuit (3.3-V Output, No External Bias) VOUT(nom) = VNR/SS + 1.6 V + 0.8 V + 0.1 V = 0.8 V + 1.6 V + 0.8 V + 0.1 V = 3.3 V (6) CBIAS Bias Supply BIAS EN PG RPG Input Supply IN OUT To Load COUT CIN Device SNS CFF NR/SS FB CNR/SS GND 50mV 100mV 200mV 400mV 800mV 1.6V Figure 48. ANY-OUT Configuration Circuit (0.9-V Output with Bias) VOUT(nom) = VNR/SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V (7) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 25 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 8.1.9 Increasing ANY-OUT Resolution for LILO Conditions As with the adjustable operation, the output voltage is set according to Equation 5, except that R1 and R2 are internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal feedback network by lowering the value of R1. One of the more useful pin combinations is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range. The new ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. The new additive output voltage levels are listed in Table 4. Table 4. ANY-OUT Programmable Output Voltage with 800mV Tied to SNS ANY-OUT PROGRAM PINS (Active Low) ADDITIVE OUTPUT VOLTAGE LEVEL Pin 5 (50mV) 25 mV Pin 6 (100mV) 50 mV Pin 7 (200mV) 100 mV Pin 9 (400mV) 200 mV Pin 11 (1.6V) 800 mV 8.1.10 Current Sharing Current sharing is possible through the use of external operational amplifiers. For more details, see the reference design 6A Current-Sharing Dual LDO, TIDU421. 8.1.11 Adjustable Operation The TPS7A85 can either be used with the internal ANY-OUT network or by using external resistors. Using the ANY-OUT network allows the TPS7A85 to be programmed from 0.8 V to 3.95 V. To extend this output voltage range to 5.0 V, external resistors must be used. This configuration is referred to as the adjustable configuration of the TPS7A85 throughout this document. Regardless whether the internal resistor network or external resistors are used, the output voltage is set by two resistors, as shown in Figure 49. Using the internal resistor ensures a 1% accurate output voltage and minimizes the number of external components. Optional Bias Supply CBIAS BIAS EN PG RPG Input Supply IN OUT To Load COUT CIN Device SNS CFF NR/SS R1 FB CNR/SS R2 GND 50mV 100mV 200mV 400mV 800mV 1.6V Figure 49. Adjustable Operation R1 and R2 can be calculated for any output voltage range using Equation 8. This resistive network must provide a current equal to or greater than 5 μA for dc accuracy. Using an R1 of 12.1 kΩ is recommended to optimize the noise and PSRR. VOUT = VNR/SS × (1 + R1 / R2) 26 (8) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 Table 5 shows the resistor combinations required to achieve several common rails using standard 1%-tolerance resistors. Table 5. Recommended Feedback-Resistor Values (1) (1) TARGETED OUTPUT VOLTAGE (V) FEEDBACK RESISTOR VALUES R1 (kΩ) R2 (kΩ) CALCULATED OUTPUT VOLTAGE (V) 0.9 12.4 100 0.899 0.95 12.4 66.5 0.949 1.00 12.4 49.9 0.999 1.10 12.4 33.2 1.099 1.20 12.4 24.9 1.198 1.50 12.4 14.3 1.494 1.80 12.4 10 1.798 1.90 12.1 8.87 1.89 2.50 12.4 5.9 2.48 2.85 12.1 4.75 2.838 3.00 12.1 4.42 2.990 3.30 11.8 3.74 3.324 3.60 12.1 3.48 3.582 4.5 11.8 2.55 4.502 5.00 12.4 2.37 4.985 R1 is connected from OUT to FB; R2 is connected from FB to GND. 8.1.12 Sequencing Requirements Supply and enable sequencing is only required when the bias rail is present. The start-up is always monotonic, independent of the sequencing requirements. Under these conditions the following requirements apply: • VBIAS and VIN can be sequenced in any order, as long as VEN is tied to VIN or established after VIN, as shown in Figure 50. tt0 • 0t VIN VEN VUVLO1(IN) VIH(EN) Figure 50. Sequencing Diagram Two typical application circuits for implementing the sequencing requirements are detailed in the Sequencing with a Power-Good DC-DC Converter Pin and Sequencing with a Microcontroller (MCU) sections. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 27 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 8.1.12.1 Sequencing with a Power-Good DC-DC Converter Pin When a dc-dc converter is used to power the device and the PG of the dc-dc converter is used to enable the device, pull PG up to VIN, as shown in Figure 51. From Input Supply OUT IN DC-DC IN RPU BIAS Device PG EN Figure 51. Sequencing with a DC-DC Converter and PG 8.1.12.2 Sequencing with a Microcontroller (MCU) If a push-pull output stage is used to provide the enable signal to the device and the enable signal can possibly come before VIN when a bias is present (such as with an MCU), convert the enable signal to an open-drain signal as shown in Figure 52. Using an open-drain signal ensures that if the signal arrives before VIN, then the enable voltage does not violate the sequencing requirement. Bias Supply Input Supply IN RPU BIAS Device EN Enable Signal MCU Figure 52. Push-Pull Enable to Open-Drain Enable 8.1.13 Power-Good (PG) Operation To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is outside of this range, then the power-good signal may not read a valid digital logic level. Using a large CFF with a small CNR/SS causes the power-good signal to incorrectly indicate that the output voltage has settled during turn-on. The CFF time constant must be greater than the soft-start time constant to ensure proper operation of the PG during start-up. For a detailed description, see application report Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042. The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO events and at light loads, power-good does not assert because the output voltage is sustained by the output capacitance. 28 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 8.1.14 Undervoltage Lockout (UVLO) Operation The UVLO circuit ensures that the device stays disabled before its input or bias supplies reach the minimum operational voltage range, and ensures that the device shuts down when the input supply or bias supply collapse. The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled. The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall time of the input supply when operating near the minimum VIN, or by using a bias rail. Figure 53 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the following parts: • • • • • • • Region A: The device does not turn on until the input reaches the UVLO rising threshold. Region B: Normal operation with a regulated output Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The output may fall out of regulation but the device is still enabled. Region D: Normal operation with a regulated output Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising threshold is reached by the input voltage and a normal start-up then follows. Region F: Normal operation followed by the input falling to the UVLO falling threshold. Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The output falls because of the load and active discharge circuit. UVLO Rising Threshold UVLO Hysteresis VIN C VOUT tAt tBt tDt tEt tFt tGt Figure 53. Typical UVLO Operation 8.1.15 Dropout Voltage (VDO) Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and output voltage (VDO = VIN – VOUT) that is required for regulation. When VIN drops below the required VDO for the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is proportional to the output current because the device is operating as a resistive switch; see Figure 25, Figure 26, and Figure 27. Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect to VIN on this device because of the internal charge pump. The charge pump causes a higher dropout voltage at lower input voltages when a bias rail is not used, as illustrated in Figure 23. For this device, dropout voltage increases exponentially when the input voltage nears its maximum operating voltage because the charge pump is internally clamped to 8.0 V; see Figure 23 and Figure 24. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 29 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 8.1.16 Behavior when Transitioning from Dropout into Regulation Some applications may have transients that place the device into dropout, especially because this device is a high-current linear regulator. A typical application with these conditions requires setting VIN ≤ VDO in order to keep the device junction temperature within its specified operating range. A load transient or line transient in these conditions can place the device into dropout, such as a load transient from 1 A to 4 A at 1A/µs when operating with a VIN of 5.4- V and a VOUT of 5.0 V. The load transient saturates the error amplifier output stage when the pass element is fully driven on, thus making the pass element function like a resistor from VIN to VOUT. The error amplifier response time to this load transient (IOUT = 4 A to 1 A at 1 A/µs) is limited because the error amplifier must first recover from saturation and then place the pass element back into active mode. During the recovery from the load transient, VOUT overshoots because the pass element is functioning as a resistor from VIN to VOUT. If operating under these conditions, apply a higher dc load or increase the output capacitance to reduce the overshoot because these solutions provide a path to dissipate the excess charge. 8.1.17 Load Transient Response The load-step transient response is the output voltage response by the LDO to a step in load current, whereby output voltage regulation is maintained; see Figure 18. There are two key transitions during a load transient response: the transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure 54 are broken down in this section. Regions A, E, and H are where the output voltage is in steady-state. During transitions from a light load to a heavy load, the: • • Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the output capacitor (region B). Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage regulation (region C). During transitions from a heavy load to a light load, the: • • Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to increase (region F). Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load discharging the output capacitor (region G). Transitions between current levels changes the internal power dissipation because the TPS7A85 is a highcurrent device (region D). The change in power dissipation changes the die temperature during these transitions, and leads to a slightly different voltage level. This different output voltage level shows up in the various load transient responses; see Figure 18. A larger output capacitance reduces the peaks during a load transient but slows down the response time of the device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher current discharge path is provided for the output capacitor; see Figure 20. tAt tCt B tDt tEt tGt tHt F Figure 54. Load Transient Waveform 30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 8.1.18 Negatively-Biased Output The device does not start or operate as expected if the output voltage is pulled below ground. This issue commonly occurs when powering a split-rail system where the negative rail is established before the device is enabled. Several application solutions are possible, such as: • • • Enable the device before the negative regulator and disable the device after the negative regulator. Delaying the EN voltage with respect to the IN voltage allows the internal pulldown resistor to discharge any voltage at OUT. If the discharge circuit is not strong enough to keep the output voltage at ground, then use an external pulldown resistor. Place a zener diode from IN to OUT to provide a small positive dc bias on the output when the input is supplied to the device, as shown in Figure 55. IN VIN OUT To Load COUT GND Figure 55. Zener Diode Placed from IN to OUT • Use a PMOSFET to isolate the output of the device from the load causing the negative bias when the device is off, as shown in Figure 56. To All Other Loads VIN IN OUT COUT To Loads with Negative Bias GND Figure 56. PMOSFET to Isolate the Output from the Load 8.1.19 Reverse Current Protection As with most LDOs, this device can be damaged by excessive reverse current. Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT > VIN + 0.3 V: • If the device has a large COUT, then the input supply collapses quickly and the load current becomes very small • The output is biased when the input supply is not established • The output is biased above the input supply Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 31 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com If an excessive reverse current flow is expected in the application, then external protection must be used to protect the device. Figure 57 shows one approach of protecting the device. Schottky Diode IN CIN Internal Body Diode OUT Device COUT GND Figure 57. Example Circuit for Reverse Current Protection Using a Schottky Diode 8.1.20 Power Dissipation (PD) Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. PD can be approximated using Equation 9: PD = (VOUT - VIN) ´ IOUT (9) An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the TPS7A85 allows for maximum efficiency across a wide range of output voltages. The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane. The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (θJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 10. The equation is rearranged for output current in Equation 11. TJ = TA + (qJA ´ PD) (10) IOUT = (TJ – TA) / [θJA × (VIN – VOUT)] (11) Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The θJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal layout, θJA is actually the sum of the VQFN package junction-to-case (bottom) thermal resistance (θJCbot) plus the thermal resistance contribution by the PCB copper. 32 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 8.1.20.1 Estimating Junction Temperature The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the Electrical Characteristics table and are used in accordance with Equation 12. YJT: TJ = TT + YJT ´ PD YJB: TJ = TB + YJB ´ PD where: • • • PD is the power dissipated as explained in Equation 9 TT is the temperature at the center-top of the device package, and TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge (12) 8.1.20.2 Recommended Area for Continuous Operation (RACO) The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input voltage. The recommended area for continuous operation for a linear regulator can be separated into the following parts, and is shown in Figure 58: • • • Output Current (A) • Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a given output current level; see the Dropout Voltage (VDO) section for more details. Limited by rated output current: The rated output current limits the maximum recommended output current level. Exceeding this rating causes the device to fall out of specification. Limited by thermals: The shape of the slope is given by Equation 11. The slope is nonlinear because the junction temperature of the LDO is controlled by the power dissipation across the LDO; therefore, when VIN – VOUT increases, the output current must decrease in order to ensure that the rated junction temperature of the device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and reduces long-term reliability. Limited by VIN range: The rated input voltage range governs both the minimum and maximum of VIN – VOUT. Output Current Limited by Dropout Rated Output Current Output Current Limited by Thermals Limited by Maximum VIN Limited by Minimum VIN VIN ± VOUT (V) Figure 58. Continuous Operation Slope Region Description Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 33 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com Figure 59 to Figure 64 show the recommended area of operation curves for this device on a JEDEC-standard high-K board with a θJA = 35.4°C/W, as given in the Electrical Characteristics table. 5 5 4.5 Output Current (A) 4 3.5 3 2.5 2 1.5 4 2 1.5 1 0.5 0 0.25 0.5 0.75 VIN - VOUT (V) 1 1.25 1.5 0 Figure 59. Recommended Area for Continuous Operation for VOUT = 0.9 V with Bias 0.25 0.5 0.75 VIN - VOUT (V) 1 1.25 1.5 Figure 60. Recommended Area for Continuous Operation for VOUT = 1.2 V with Bias 5 5 4 3.5 3 2.5 2 1.5 TA = 40qC TA = 55qC TA = 70qC TA = 85qC RACO at TA = 85qC 4.5 4 Output Current (A) TA = 40qC TA = 55qC TA = 70qC TA = 85qC RACO at TA = 85qC 4.5 Output Current (A) 3 2.5 0.5 0 3.5 3 2.5 2 1.5 1 1 0.5 0.5 0 0 0 0.25 0.5 0.75 VIN - VOUT (V) 1 1.25 1.5 0 Figure 61. Recommended Area for Continuous Operation for VOUT = 1.8 V 0.25 0.5 0.75 VIN - VOUT (V) 1 1.25 1.5 Figure 62. Recommended Area for Continuous Operation for VOUT = 2.5 V 5 5 4 3.5 3 2.5 2 1.5 4 3.5 3 2.5 2 1.5 1 1 0.5 0.5 0 TA = 40qC TA = 55qC TA = 70qC TA = 85qC RACO at TA = 85qC 4.5 Output Current (A) TA = 40qC TA = 55qC TA = 70qC TA = 85qC RACO at TA = 85qC 4.5 Output Current (A) 3.5 1 0 0 0 0.25 0.5 0.75 VIN - VOUT (V) 1 1.25 1.5 Figure 63. Recommended Area for Continuous Operation for VOUT = 3.3 V 34 TA = 40qC TA = 55qC TA = 70qC TA = 85qC RACO at TA = 85qC 4.5 Output Current (A) TA = 40qC TA = 55qC TA = 70qC TA = 85qC RACO at TA = 85qC 0 0.25 0.5 0.75 VIN - VOUT (V) 1 1.25 1.5 Figure 64. Recommended Area for Continuous Operation for VOUT = 5.0 V Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 8.2 Typical Applications 8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions This section discusses the implementation of the TPS7A85 using the ANY-OUT configuration to regulate a 4.0-A load requiring good PSRR at high frequency with low noise at 0.9 V using a 1.3-V input voltage and a 5.0-V bias supply. The schematic for this typical application circuit is provided in Figure 65. CBIAS Bias Supply BIAS EN PG RPG Input Supply IN OUT To Load COUT CIN Device SNS CFF NR/SS FB CNR/SS GND 50mV 100mV 200mV 400mV 800mV 1.6V Figure 65. Typical Application 8.2.1.1 Design Requirements For this design example, use the parameters listed in Table 6 as the input parameters. Table 6. Design Parameters PARAMETER Input voltage DESIGN REQUIREMENT 1.4 V, ±3%, provided by the dc-dc converter switching at 500 kHz Output voltage 0.9 V, ±1% Output current 4.0 A (maximum), 100 mA (minimum) RMS noise, 10 Hz to 100 kHz < 10 µVRMS PSRR at 500 kHz > 40 dB Start-up time < 25 ms 8.2.1.2 Detailed Design Procedure For these conditions, the maximum dropout of the TPS7A85 is approximately 240 mV, thus a 400-mV headroom is sufficient for operation over both input and output voltage accuracy. The bias rail is provided for better performance for the LILO conditions. PSRR is greater than 40 dB in these conditions, as per Figure 2. Noise is less than 10 µVRMS, as per Figure 11. The ANY-OUT internal resistor network is also used for maximum accuracy. To achieve 0.9 V on the output, the 100mV pin is grounded. The voltage value of 100 mV is added to the 0.8-V internal reference voltage for VOUT(nom) equal to 0.9 V, as described in Equation 13. VOUT(nom) = VNR/SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V (13) Input and output capacitors are selected in accordance with the Recommended Capacitor Types section. Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the output are selected. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 35 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com To satisfy the required start-up time and still maintain low-noise performance, a 100-nF CNR/SS is selected. This value is calculated with Equation 14. To further minimize noise, a feed-forward capacitance (CFF) of 10 nF is selected. tSS = (VNR/SS × CNR/SS) / INR/SS (14) The maximum ambient temperature for this application is 40°C based on Figure 59 and given the 3% accuracy of the input supply. 8.2.1.3 Application Curves 15 VIN = 1.10 V VIN = 1.15 V VIN = 1.20 V VIN = 1.25 V VIN = 1.30 V VIN = 1.35 V VIN = 1.40 V 80 60 13.5 Output Voltage Noise (PVRMS) Power Supply-Rejection Ratio (dB) 100 40 20 12 IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A IOUT = 4.0 A 10.5 9 7.5 6 4.5 0 10 100 1k 10k 100k Frequency (Hz) 1M 3 0.6 10M 1.2 Figure 66. Output PSRR 1.8 2.4 3 3.6 Output Voltage (V) 4.2 4.8 5.4 Figure 67. Output Noise Level 8.2.2 Typical Application for a 5.0-V Rail This section discusses the implementation of the TPS7A85 using an adjustable feedback network to regulate a 4-A load requiring good PSRR at high frequency with low noise at an output voltage of 5.0 V. The schematic for this typical application circuit is provided in Figure 68. Optional Bias Supply CBIAS BIAS EN PG RPG Input Supply IN OUT To Load COUT CIN Device SNS CFF NR/SS R1 FB CNR/SS R2 GND 50mV 100mV 200mV 400mV 800mV 1.6V Figure 68. Typical Application 36 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 8.2.2.1 Design Requirements For this design example, use the parameters listed in Table 6 as the input parameters. Table 7. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 5.60 V, ±1%, provided by the dc-dc converter switching at 500 kHz Output voltage 5.0 V, ±1% Output current 4.0 A (maximum), 10 mA (minimum) Start-up time < 25 ms 8.2.2.2 Detailed Design Procedure For these conditions, the maximum dropout of the TPS7A85 is approximately 500 mV, thus a 600-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high temperature on some devices, the TPS7A85 can enter dropout if both the input and output supply are beyond the edges of their accuracy specification. For a 5.0-V output, use external adjustable resistors. See the resistor values in listed Table 5 for choosing resistors for a 5.0-V output. Input and output capacitors are selected in accordance with the Recommended Capacitor Types section. Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the output are selected. To further minimize noise, a feed-forward capacitance (CFF) of 10 nF is selected. To satisfy the required start-up time and still maintain low-noise performance, a 100-nF CNR/SS is selected. This value is calculated with Equation 14. tSS = (VNR/SS × CNR/SS) / INR/SS (15) The maximum ambient temperature for this application is 40°C based on Figure 64 and given the 1% accuracy of the input supply. This temperature can still exceed the maximum junction temperature, but the 4.0-A load is a short pulse requirement and not a dc load so the thermal effects are minimal. 8.2.2.3 Application Curves 100 IOUT = 0.1 A IOUT = 0.5 A IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A IOUT = 4.0 A 80 60 40 20 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 69. PSRR vs Frequency and IOUT for VOUT = 5.0 V with VIN = 5.6 V Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 100 VIN = 5.35 V VIN = 5.4 V VIN = 5.45 V VIN = 5.5 V VIN = 5.55 V VIN = 5.60 V VIN = 5.65 V 80 60 40 20 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 70. PSRR vs Frequency and VIN for VOUT = 5.0 V at IOUT = 4.0 A 9 Power-Supply Recommendations The TPS7A85 is designed to operate from an input voltage supply range between 1.1 V and 6.5 V. If the input supply is less than 1.4 V, then a bias rail of at least 3.0 V must be used. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve output noise performance. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 37 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 10 Layout 10.1 Layout Guidelines 10.1.1 Board Layout For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and negatively affects system performance. The grounding and layout scheme shown in Figure 71 minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements. 10.2 Layout Example CBIAS To Bias Supply 1.6V 800mV 400mV GND 200mV 100mv Ground Plane for Thermal Relief and Signal Ground 10 9 8 7 6 11 5 RPG BIAS 12 4 PG Output PG R2 Thermal Pad To Signal Ground To PG Pullup Supply 50mV NR/SS 13 3 FB EN 14 2 SNS To Signal Ground CNR/SS Enable Signal To Load CFF R1 1 17 18 19 20 IN GND OUT OUT Input Power Plane 16 IN 15 IN CIN OUT Output Power Plane COUT Power Ground Plane Vias used for application purposes. Figure 71. Example Layout 38 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 TPS7A85 www.ti.com SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Modules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A85. The summary information for this fixture is shown in Table 8. Table 8. Design Kits and Evaluation Modules NAME LITERATURE NUMBER TPS7A8300EVM-209 Evaluation Module SLVU919 TPS7A8300EVM-579 Evaluation Module SBVU021 The EVM can be requested at the Texas Instruments web site through the TPS7A85 product folder. 11.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS7A85 is available through the TPS7A85 product folder under simulation models. 11.1.2 Device Nomenclature Table 9. Ordering Information (1) PRODUCT TPS7A85YYZ (1) DESCRIPTION YY is the package designator. Z is the package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: • TPS3702 Data Sheet, SBVS251 • TPS7A8300EVM-209 Evaluation Module, SLVU919 • TPS7A8300EVM-579 Evaluation Module, SBVU021 • A Topical Index of TI LDO Application Notes, SBVA026 • Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042 • 6A Current-Sharing Dual LDO, TIDU421 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 39 TPS7A85 SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016 www.ti.com 11.4 Trademarks ANY-OUT, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 40 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: TPS7A85 PACKAGE OPTION ADDENDUM www.ti.com 22-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TPS7A8500RGRR ACTIVE VQFN RGR 20 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 11DI Samples TPS7A8500RGRT ACTIVE VQFN RGR 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 11DI Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of