TPS82693EVM-207

TPS8269xEVM-207 User's Guide Literature Number: SLVU802 October 2012 Contents 0.1 1 2 3 4 5 A 2 Introduction .................................................................................................................. 0.1.1 Features ............................................................................................................. 0.1.2 Applications ......................................................................................................... 0.1.3 EVM Ordering Options ............................................................................................ 4 4 4 4 ..................................................................................................... 5 Connector and Test Point Descriptions ................................................................................. 6 2.1 Input / Output Connectors: TPS8269xEVM ............................................................................. 6 2.1.1 J1 VIN ................................................................................................................. 6 2.1.2 J2 S+ / S– ........................................................................................................... 6 2.1.3 J3 GND .............................................................................................................. 6 2.1.4 J4 VOUT ............................................................................................................... 6 2.1.5 J5 S+ / S– ........................................................................................................... 6 2.1.6 J6 GND .............................................................................................................. 6 2.2 Jumpers and Switches ..................................................................................................... 6 2.2.1 JP1 ENABLE ....................................................................................................... 6 2.2.2 JP2 MODE .......................................................................................................... 6 Test Configuration .............................................................................................................. 7 3.1 Hardware Setup ............................................................................................................. 7 3.2 Procedure .................................................................................................................... 7 TPS8269xEVM Test Data ...................................................................................................... 8 4.1 Thermal Performance ...................................................................................................... 8 4.1.1 Thermal Measurement TPS82693 , IOUT = 400 mA ............................................................ 8 4.1.2 Thermal Measurement TPS82693 , IOUT = 800 mA ............................................................ 8 TPS8269xEVM Assembly Drawings and Layout ...................................................................... 9 Appendix .......................................................................................................................... 11 A.1 Bill of Materials ............................................................................................................. 11 A.2 Marking Information ....................................................................................................... 11 TPS8269xEVM Schematic Contents SLVU802 – October 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated www.ti.com List of Figures 1-1. TPS8269xEVM Schematic ................................................................................................. 5 3-1. Hardware Board Connection .............................................................................................. 7 4-1. VIN = 3.6 V, VOUT = 2.85 V, IOUT = 400 mA 80-mW Power Dissipation at Room Temperature ..................... 8 4-2. VIN = 3.6 V, VOUT = 2.85 V, IOUT = 800 mA 330-mW Power Dissipation at Room Temperature .................... 8 5-1. TPS8269xEVM Component Placement .................................................................................. 9 5-2. TPS8269xEVM Top Layer ................................................................................................. 9 5-3. TPS8269xEVM Internal Layer 1 ......................................................................................... 10 5-4. TPS8269xEVM Internal Layer 2 ......................................................................................... 10 5-5. TPS8269xEVM Bottom Layer ............................................................................................ 10 List of Tables 0-1. Ordering Information ........................................................................................................ 4 A-1. TPS8269xEVM-207 Bill of Materials .................................................................................... 11 A-2. Marking Information ....................................................................................................... 11 SLVU802 – October 2012 Submit Documentation Feedback List of Figures Copyright © 2012, Texas Instruments Incorporated 3 www.ti.com This user’s guide describes the characteristics, operation, and use of the TPS8269xEVM-207 evaluation module (EVM). The TPS8269xEVM-207 is a fully assembled and tested platform for evaluating the performance of the TPS8269xSIP high-frequency, synchronous, step-down DC-DC converters optimized for battery-powered portable applications. This document includes schematic diagrams, a printed circuit board (PCB) layout, bill of materials, and test data. Throughout this document, the abbreviations EVM and TPS8269xEVM and the term evaluation module are synonymous with the TPS8269xEVM-207 unless otherwise noted. 0.1 Introduction The TPS8269xSIP device family is a high-frequency, synchronous, step-down DC-DC converters optimized for battery-powered portable applications. Intended for low-power applications, the TPS8269xSIP supports up to 500mA or 800mA and all TPS8269xSIP devices allow the use of low-cost chip inductors and capacitors. With a wide input voltage range of 2.3 V to 4.8 V, the devices support applications powered by lithium-ion (Li-Ion) batteries with extended voltage ranges. Different fixed voltage output versions of the TPS8269xSIP are available. These converters operate at a regulated 3-MHz switching frequency and enter a power-save mode operation under light load currents in order to maintain high efficiency over the entire load current range. A pulse frequency modulation (PFM) mode extends the battery life by reducing the quiescent current to 23 μA (typ) during light load operation. 0.1.1 Features • • • • • • • • Input Voltage Range: 2.3 V up to 4.8 V Fixed Output Voltages Up to 800-mA Output Current Sub 1-mm Profile Solution 3-MHz Regulated Frequency Operation Current Overload and Thermal Shutdown (Optional) Total Solution Size: < 6.7 mm2 Low Ripple Light-Load PFM Mode 0.1.2 Applications • • • LDO Replacement Cell Phones, Smart-Phones PoL Applications 0.1.3 EVM Ordering Options Table 0-1 provides the ordering information for the various EVM options. Table 0-1. Ordering Information Orderable EVM Number Device Part Number Output Voltage Maximum Output Current TPS82693EVM-207 TPS82693 2.85 V 800 mA All trademarks are the property of their respective owners. 4 List of Tables SLVU802 – October 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Chapter 1 SLVU802 – October 2012 TPS8269xEVM Schematic Figure 1-1 illustrates the TPS8269xEVM-207 schematic. 1 1 VOUT J7 J8 R1 U1 VIN FB1 J1 VIN 2.3V to 4.8V TPS8269xSIP VIN C1 + C2 A2 VIN 1 C3 J2 1 S+ J4 3 VOUT A1 A3 VIN GND C3 B1 MODE GND C2 B2 EN GND C1 1 R2 FB2 2 VOUT 1 C4 C5 C6 C7 C8 1 1 1 VOUT J5 S+ 1 S- 1 S- J6 J3 GND GND VIN PWM 1 Not Installed 1 JP1 MODE PSM 2 See BOM for IC usage 3 Refer to device datasheet for Output Voltage VIN ON 1 JP2 ENABLE OFF NOTE: For reference only; see Table A-1 for specific values. Figure 1-1. TPS8269xEVM Schematic SLVU802 – October 2012 Submit Documentation Feedback TPS8269xEVM Schematic Copyright © 2012, Texas Instruments Incorporated 5 Chapter 2 SLVU802 – October 2012 Connector and Test Point Descriptions 2.1 Input / Output Connectors: TPS8269xEVM 2.1.1 J1 VIN This header is the positive connection to the input power supply. The power supply must be connected between J1 and J3 (GND). The leads to the input supply should be twisted and kept as short as possible. The input voltage must be between 2.3 V and 4.8 V. 2.1.2 J2 S+ / S– J2 S+ / S– are the sense connection for the input of the converter. Connect a voltmeter, sense connection of a power supply, or oscilloscope to this header. 2.1.3 J3 GND This header is the return connection to the input power supply. Connect the power supply between J3 and J1 (VIN). The leads to the input supply should be twisted and kept as short as possible. The input voltage must be between 2.3 V and 4.8 V. Capacitor C1 compensates for parasitic inductance as a result of the wires from the DC power supply to the EVM. It is not required in an actual application circuit. 2.1.4 J4 VOUT This header is the positive output of the step-down converter. The TPS8269x has fixed output voltages; refer to the specific device data sheet for detailed information on the device output voltage. 2.1.5 J5 S+ / S– J5 S+ / S– are the sense connection for the output of the converter. Connect a voltmeter, sense connection of an electronic load, or oscilloscope to this header. 2.1.6 J6 GND J6 is the return connection of the converter. A load can be connected between J6 and J4 (VOUT). 2.2 Jumpers and Switches 2.2.1 JP1 ENABLE This jumper can enable or disable the converter on the EVM. Placing a shorting bar between ENABLE and ON turns on the converter. Placing a shorting bar between ENABLE and OFF disables the converter. 2.2.2 JP2 MODE This jumper can enable or disable the power-saving mode (PSM) under light loads. Placing a shorting bar between MODE and pulse width modulation (PWM) disables the PSM. If the PSM is disabled, the converter operates in forced PWM mode over the entire load current range. Placing a shorting bar between MODE and PSM enables the power-saving mode. The device operates in power-saving mode under light load conditions. See the specific device data sheet for detailed information. 6 Connector and Test Point Descriptions SLVU802 – October 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Chapter 3 SLVU802 – October 2012 Test Configuration 3.1 Hardware Setup Figure 3-1 illustrates a typical hardware test configuration. J2 S- S+ TPS82693EVM-207 S+ GND EN ON JP1 OFF MODE PWM PSM JP2 Load J6 VIN S- J5 J1 VOUT GND J4 -+ DC Power Supply +- J3 Oscilloscope J7 Figure 3-1. Hardware Board Connection 3.2 Procedure Follow these procedures when configuring the EVM for testing. CAUTION Many of the components on the TPS8269xEVM-207 are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap, bootstraps, or mats at an approved ESD workstation. An electrostatic smock and safety glasses should also be worn. • • • • • • Work at an ESD workstation. Make sure that any wrist straps, bootstraps, or mats are connected and reference the user to earth ground before power is applied to the EVM. Electrostatic smocks and safety glasses should also be worn. Connect a DC power supply between J1 and J3 on the TPS8269xEVM. Note that the input voltage should range from 2.3 V to 4.8 V. Keep the wires from the input power supply to EVM as short as possible and twisted. Connect a DC voltmeter or oscilloscope to the output sense connection of the EVM. A load can be connected between J4 and J6 on the TPS8269xEVM. To enable the converter, connect the shorting bar on JP1 between ENABLE and ON on the TPS8269xEVM. The TPS8269xEVM has a feature that allows users to switch between PSM under light loads and forced PWM mode, with jumper JP2. SLVU802 – October 2012 Submit Documentation Feedback Test Configuration Copyright © 2012, Texas Instruments Incorporated 7 Chapter 4 SLVU802 – October 2012 TPS8269xEVM Test Data This section presents typical performance data for the TPS8269xEVM. Actual performance data can be affected by measurement techniques and environmental variables; therefore, these results are presented for reference and may differ from actual results obtained by some users. 4.1 Thermal Performance Figure 4-1 and Figure 4-2 show the typical thermal performance for the TPS82693 for two load scenarios, respectively. 4.1.1 Thermal Measurement TPS82693 , IOUT = 400 mA TPWB = 27°C Tinductor = 33°C Tcapacitor = 30°C Tcapacitor = 30°C Figure 4-1. VIN = 3.6 V, VOUT = 2.85 V, IOUT = 400 mA 80-mW Power Dissipation at Room Temperature 4.1.2 Thermal Measurement TPS82693 , IOUT = 800 mA TPWB = 38°C Tinductor = 53°C Tcapacitor = 41°C Tcapacitor = 39°C Figure 4-2. VIN = 3.6 V, VOUT = 2.85 V, IOUT = 800 mA 330-mW Power Dissipation at Room Temperature 8 TPS8269xEVM Test Data SLVU802 – October 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Chapter 5 SLVU802 – October 2012 TPS8269xEVM Assembly Drawings and Layout Figure 5-1 through Figure 5-5 show the design of the show the design of the TPS8269xEVM-207 printed circuit boards. The EVM was designed using a four-layer, 1-ounce copper-clad PCB with all components in an active area on the top side of the board. Moving components to both sides of the PCB or using additional internal layers can offer additional size reduction for space-constrained systems. NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid out; they are not intended to be used for manufacturing TPS8269xEVM-207 PCBs. Figure 5-1. TPS8269xEVM Component Placement Figure 5-2. TPS8269xEVM Top Layer SLVU802 – October 2012 Submit Documentation Feedback TPS8269xEVM Assembly Drawings and Layout Copyright © 2012, Texas Instruments Incorporated 9 www.ti.com Figure 5-3. TPS8269xEVM Internal Layer 1 Figure 5-4. TPS8269xEVM Internal Layer 2 Figure 5-5. TPS8269xEVM Bottom Layer 10 TPS8269xEVM Assembly Drawings and Layout Copyright © 2012, Texas Instruments Incorporated SLVU802 – October 2012 Submit Documentation Feedback Appendix A SLVU802 – October 2012 Appendix A.1 Bill of Materials Table A-1 lists the bill of materials for the TPS8269xEVM. Table A-1. TPS8269xEVM-207 Bill of Materials EVM Device Option: Count A.2 RefDes Value Description 0 C1 150 μF Capacitor, Tantalum, 6.3 V, 25 mΩ, 20% 1 1 C2, C3, C4, C5, C6, C7, C8 Open 6 6 J1, J2, J3, J4, J5, J6 PEC02SAAN 0 0 J7, J8 Open 2 2 JP1, JP2 PEC03SAAN Header, Male 3-pin, 100 mil spacing 0 1 U1 TPS82693SIP IC, 800-mA, High-Freq μModule Step-Down Converter -001 -002 0 Capacitor, Ceramic Header, Male 2-pin, 100 mil spacing Connector, SMA , Straight, PC mount Size Part Number Mfr 3528(B) T520B157M006ATE025 Kemet 0603 Std Std PEC02SAAN Sullins 0.10 in x 2 0.210 in 901-144-8RFX AMP 0.10 in x 3 PEC03SAAN Sullins SIP-8 TPS82693 TI 2 Marking Information Table A-2 provides the marking information for this EVM. Table A-2. Marking Information Assembly Number Marking Text PWR207-002 TPS82693EVM-207 SLVU802 – October 2012 Submit Documentation Feedback Appendix Copyright © 2012, Texas Instruments Incorporated 11 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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