TPS92001, TPS92002
www.ti.com
SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
GENERAL PURPOSE LED LIGHTING PWM CONTROLLER
Check for Samples: TPS92001, TPS92002
FEATURES
DESCRIPTION
•
•
The TPS92001/2 family of general LED lighting PWM
controllers contains control and drive circuitry
required for off-line isolated or non-isolated LED
lighting applications.
1
•
•
•
•
•
•
•
•
Ideal for Single Stage Designs
Supports Isolated and Non-Isolated
Topologies
Phase-Cut TRIAC Dimmable
Few External Components Mode Operation
Wide Duty Cycle Range for Wide-Input Voltage
or Dimming Range
Convenient 5-V Reference Output
Undervoltage Lockout for Safe Operation
Operation to 1-MHz
0.4-A Source/0.8-A Sink FET Driver
Low 100-µA Startup Current
The controllers can support Phase Cut TRIAC
dimming with minimal external components. The
controllers can also be implemented for stage
conversion where the power factor (PF) exceeds
regulatory requirements for lighting. These controllers
also have an accessible 5-V reference that could be
used to power a microcontroller or other low power
peripheral components. The controllers operate in
fixed frequency current mode switching with minimal
external parts count. Internally implemented circuits
include undervoltage lockout featuring startup current
less than 100 µA, logic to ensure latched operation, a
PWM comparator, and a totem pole output stage to
sink or source peak current. The output stage,
suitable for driving N-Channel MOSFETs, is low in
the off state. Oscillator frequency and maximum duty
cycle are programmed with two resistors and a
capacitor.
APPLICATIONS
•
•
•
Residential LED Lighting Drivers for A19
E12/E26/27, GU10, MR16, PAR30/38 Integral
Lamps
Drivers for Wall Sconces, Pathway Lighting
and Overhead Lighting
Drivers for Wall Washing, Architectural and
Display Lighting
DEVICE
NUMBER
TURN-ON
THRESHOLD (V)
TPS92001
10
TPS92002
15
The TPS92001/2 family also features full cycle soft
start. The family offers UVLO thresholds and
hysteresis levels for off-line and DC-to-DC systems.
The TPS92001/2 is offered in the 8-pin MSOP (DGK)
and 8-pin SOIC (D) packages. The small MSOP
package makes the device ideally suited for
applications where board space and height are at a
premium.
TURN-OFF
THRESHOLD (V)
8
SIMPLIFIED APPLICATION
Linear
Regulator
EMI
Filter
TPS92001/2
TRIAC
Dimming
Control
1
CS
REF
8
2
SS
VDD
7
3
RTC
GD
6
4
RTD
GND
5
UDG-10003
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS92001, TPS92002
SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
RANGE
VDD
Input voltage range
Continuous input current
19
SS
-0.3 to REF + 0.3
RTC, RTD
-0.3 to REF + 0.3
IREF
-15
IVDD
25
Output current
IGD (tpw < 1 µs and Duty Cycle < 10%)
Operating junction temperature
Storage temperature
Lead temperature
Soldering, 10 s
(1)
UNIT
V
mA
-0.4 to 0.8
A
TJ
−55 to +150
°C
Tstg
−65 to +150
+300
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Input voltage
IGD
Output sink current
TJ
Operating junction temperature
MAX
UNIT
21
V
105
°C
0
–40
A
DISSIPATION RATINGS
PACKAGE
qJA, THERMAL
IMPEDANCE
JUNCTION-TO-AMBIENT,
NO AIRFLOW (°C/W)
qJB, THERMAL
IMPEDANCE
JUNCTION-TO-BOARD,
NO AIRFLOW (°C/W)
TA = 25°C
POWER
RATING (mW)
TA = 85°C
POWER
RATING (mW)
TB = 85°C
POWER
RATING (mW)
SOIC-8 (D)
165 (1)
55
606 (2)
242 (2)
730 (2) (3)
62
(2)
(2)
664 (3) (2)
MSOP-8 (DGK)
(1)
(2)
(3)
181
(1)
552
221
Tested per JEDEC EIA/JESD51-1. Thermal resistance is a function of board construction and layout. Air flow will reduce thermal
resistance. This number is included only as a general guideline; see TI document SPRA953 IC Package Thermal Metrics.
Maximum junction temperature TJ, equal to 125°C.
Thermal resistance to the circuit board is lower. Measured with standard single-sided PCB construction. Board temperature, TB,
measured approximately 1 cm from the lead to board interface. This number is provided only as a general guideline.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
Human body model
2000
CDM
1500
2
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UNIT
V
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS92001 TPS92002
TPS92001, TPS92002
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SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
ELECTRICAL CHARACTERISTICS
VVDD = 12 V, CREF = 0.47-mF, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
17.5
19
V
600
900
µA
SUPPLY SECTION
VDD
Supply clamp
IVDD = 10 mA
IVDD
Supply current
No Load
IVDD
Supply current startup (1)
Supply current standby
110
TPS92001
TPS92002
VVDD = Start threshold – 300 mv
µA
110
125
130
170
µA
UNDERVOLTAGE LOCKOUT SECTION
Start threshold
UVLO hysteresis
TPS92001
9.4
10.4
TPS92002
14.0
15.6
TPS92001
1.65
TPS92002
6.2
V
VOLTAGE REFERENCE SECTION
Output voltage
IREF = 0 mA
Line regulation
10 V ≤ VVDD ≤ 15 V
4.75
5
2
5.25
mV
V
Load regulation
0 mA ≤ IREF ≤ 5 mA
2
mV
COMPARATOR SECTION
ICS
Current sense
Output OFF
-100
Comparator threshold
GDDLY
0.9
0.8 V ≤ VCS ≤ 1.2 V at TR = 10 ns
GD propagation delay (No Load)
nA
0.95
1
V
50
100
ns
SOFT START SECTION
ISS
Soft-start current
VSS
Low-level output voltage
VVDD = 16 V, VSS = 0 V, -40°C ≤ TA ≤ 85°C
-4.9
-7.0
-9.1
µA
VVDD = 16 V, VSS = 0 V, -40°C ≤ TA ≤ 85°
-4.9
-7.0
-10.0
µA
0.2
V
VVDD = 7.5 V, ISS = 200 µA
Shutdown threshold
0.44
0.48
0.52
V
90
100
110
kHz
OSCILLATOR SECTION
VCT(peak)
Switching frequency
RRTC = 10 kΩ, RRTD = 4.32 kΩ, CCT =
820pF
Frequency change with voltage
10 V ≤ VVDD ≤ 15 V
Timing capacitor peak voltage
VCT(valley) Timing capacitor valley voltage
VCT(p-p)
0.1
%/V
3.33
V
1.67
Timing capacitor peak-to-peak voltage
1.54
V
1.67
1.80
V
GATE DRIVE SECTION
Power driver VSAT low
IGD = 80 mA (dc)
0.8
1.5
V
Power driver VSAT high
IGD = -40 mA (dc), (VVDD – VGD)
0.8
1.5
V
Power driver low-voltage during UVLO
IGD = 20 mA (dc)
1.5
V
DMIN
Minimum duty cycle
VCS = 2 V
DMAX
Maximum duty cycle
tRISE
Rise Time
CGD = 1nF
35
ns
tFALL
Fall Time
CGD = 1nF
18
ns
(1)
0%
70%
Specified by design. Not production tested.
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SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
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FUNCTIONAL BLOCK DIAGRAM
TPS92001/2
1V
CS
+
1
1V
+5V
+
6 mA
SS
5V
REF
8
REF
7
VDD
6
GD
5
GND
2
0.5 V
+
+
15/8 V
10/8 V
17.5 V
R
RTC
3
Q
CLK
OSC
RTD
S
4
PWM Latch
UDG-10004
4
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SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
ORDERING INFORMATION
THRESHOLD
OPERATING
TEMPERATURE
RANGE TA
PACKAGE
TURNON
TURNOFF
Plastic Small Outline (MSOP)
10
Plastic Small Outline (SOIC)
–40°C to 85°C
8
Plastic Small Outline (MSOP)
15
Plastic Small Outline (SOIC)
ORDERABLE
DEVICE
NUMBER
PINS
TRANSPORT
MEDIA
QUANTITY
TPS92001DGK
Tube
80
TPS92001DGKR
Tape and Reel
2500
TPS92001D
Tube
75
TPS92001DR
Tape and Reel
2500
Tube
80
TPS92002DGKR
Tape and Reel
2500
TPS92002D
Tube
75
TPS92002DR
Tape and Reel
2500
8
TPS92002DGK
DEVICE INFORMATION
TPS92001/2
D Package
(Top View)
DGK Package
(Top View)
CS
1
8
REF
CS
1
8
REF
SS
2
7
VDD
RTC
3
6
GD
RTD
4
5
GND
SS
2
7
VDD
RTC
3
6
GD
RTD
4
5
GND
PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
CS
1
I
This pin is the summing node for current sense feedback, voltage sense feedback (by optocoupler) and slope
compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered
with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to
GND is discharged by an internal 250ohm on resistance NMOS FET during PWM off time. It offers effective
leading edge blanking, with the delay set by the RC time constant of the feedback resistance from current sense
resistor to CS input and the high frequency filter capacitor at this node to GND.
GND
5
–
Reference ground and power ground for all functions.
GD
6
O
This pin is the high current power driver output. A minimum series gate resistor of 3.9 Ω is recommended to limit
the gate drive current when operating with high-bias voltages.
REF
8
O
The internal 5-V reference output. This reference is buffered and is available on the REF pin. The REF pin should
be bypassed with a 0.47-µF ceramic capacitor to GND.
RTC
3
I
This pin connects to timing resistor RRTC , and controls the positive ramp (rise) time of the internal oscillator (see
Equation 1). The positive threshold of the internal oscillator is sensed through inactive timing resistor RRTD which
connects to pin RTD and timing capacitor, CCT.
tRISE = 0.74 ´ (CCT + 27pF )´ RRTC
RTD
4
I
(1)
This pin connects to timing resistor RTD and controls the negative ramp (fall) time of the internal oscillator (see
Equation 2). The negative threshold of the internal oscillator is sensed through inactive timing resistor RRTC which
connects to pin RTC and timing capacitor, CCT.
tFALL = 0.74 ´ (CCT + 27pF )´ RRTD
(2)
SS
2
I
This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 6-µA
current source. Under normal soft-start, the SS pin is discharged to at least 0.4 V and then ramps positive to 1 V
during which time the output driver is held low. As the SS pin charges from 1 V to 2 V, the soft-start is
implemented by an increasing output duty cycle. If the SS pin is taken below 0.5 V, the output driver is inhibited
and held low. The user accessible 5-V voltage reference also goes low and IVDD = 100 µA
VDD
7
I
The power input connection for this device. This pin is shunt regulated at 17.5 V which is sufficiently below the
voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1-µF ceramic capacitor.
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SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
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APPLICATION INFORMATION
Introduction
The typical application diagrams in Figure 3 and Figure 4 show isolated and non-isolated flyback converters
utilizing the TPS92001. Note that the capacitors CREF and CVDD are local decoupling capacitors for the reference
and device input voltage, respectively. Both capacitors should be low ESR and ESL ceramic, placed as close as
possible to the device pins, and returned directly to the ground pin of the device for best stability. The REF pin
provides the internal bias to many of the device functions and CREF should be at least 0.47-µF to prevent the
REF voltage from drooping.
Current Sense (CS) Pin
In the TPS92001/2, the current regulation is obtained through the summation of the primary current sense and
any slope compensation at the CS pin compared to a 1-V threshold, as shown in the FUNCTIONAL BLOCK
DIAGRAM. Crossing this 1-V threshold resets the PWM latch and modulates the output driver on-time. In the
absence of a CS signal, the output obeys the programmed maximum on-time of the oscillator. When adding
slope compensation, it is important to use a small capacitor to AC couple the oscillator waveform before
summing this signal into the CS pin. By forcing the CS node to exceed the 1-V threshold the TPS92001/2 is
forced to zero percent duty cycle.
Oscillator
Equation 3 calculates the oscillator frequency setting.
(
-1
)
fOSC = 0.74 ´ (CCT + 27pF )´ (RRTC + RRTD )
(3)
DMAX = 0.74 ´ RTC ´ (CT + 27pF )´ fOSC
(4)
Referring to Figure 1 and the waveforms in Figure 2, when Q1 is on, CCT charges via the on-resistance of the Q1
MOSFET and the RTC pin. During this charging process, the voltage of CCT is sensed through the RTD pin. The
S input of the oscillator latch, SOSC, is level sensitive, so crossing the upper threshold (set at 2/3 VREF or 3.33 V
for a typical 5.0 V reference) sets the Q output (CLK signal) of the oscillator latch high. A high CLK signal results
in turning off Q1 and turning on Q2. The timing capacitor then discharges through RTD and the RDS(on) of Q2.
CCT discharges from 3.33 V to the lower threshold (set at 1/3 REF or 1.67 V for a typical 5.0-V reference) sensed
through RTC. The R input to the oscillator latch, ROSC, is also level sensitive and resets the CLK signal low when
CCT crosses the 1.67-V threshold, turning off Q2 and turning on Q1, initiating another charging cycle.
VREF
Q1
RTC
Oscillator
Latch
3
RRTC
3.33 V
+
–
S
+
–
R
1.67 V
CLK
Q
RTD
4
RRTD
Q2
Oscillator
CCT
UDG-10005
Figure 1. Oscillator Function
6
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SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
CCT Charging CCT Discharging
3.33 V
1.67 V
CCT
SOSC
ROSC
QOSC=CLK=SPWM
1V
CS
RPWM
QPWM
70%
ON
30%
OFF
VGD
CS Signal Dominant
Maximum Duty Cycle Dominant
UDG-10006
Figure 2. Oscillator Latch and PWM Latch Waveforms
Figure 2 shows the waveforms associated with the oscillator latch and the PWM latch (shown in the Typical
Application Diagram). A high CLK signal not only initiates a discharge cycle for CCT, it also turns on the internal
N-channel MOSFET on the CS pin causing any external capacitance used for leading edge blanking connected
to this pin to be discharged to ground. By discharging any external capacitor completely to ground during the
external switch off-time, the noise immunity of the converter is enhanced allowing the user to design in smaller
R-C components for leading edge blanking. A high CLK signal also sets the level sensitive S input of the PWM
latch, SPWM, high, resulting in a high output, QPWM, as shown in Figure 2. This QPWM signal remains high until a
reset signal, RPWM is received. A high RPWM signal results from the CS signal crossing the 1-V threshold, or
during soft-start or if the SS pin is disabled.
Assuming the UVLO threshold is satisfied, the GD signal of the device remains high as long as QPWM is high and
SPWM, also referred to as CLK, is low. The GD signal is dominated by the CS signal as long as the CS signal
trips the 1-V threshold while CLK is low. If the CS signal does not cross the 1-V threshold while CLK is low, the
GD signal will be dominated by the maximum duty cycle programmed by the user. Figure 2 illustrates the various
waveforms for a design set up for a maximum duty cycle of 70%.
The recommended value for CCT is 1 nF for frequencies in the 100 kHz or less range and smaller CCT for higher
frequencies. The minimum recommended values of RRTC is 10 kΩ. The minimum recommended value of RRTD is
4.32 kΩ. Using these values maintains a ratio of at least 20:1 between the RDS(on) of the internal FETs and the
external timing resistors, resulting in minimal change in frequency over temperature. Because of the oscillator
susceptibility to capacitive coupling, examine the oscillator frequency by looking at the common RTC-RTD-CT
node on the circuit board as opposed to looking at pins 3 and 4 directly. For good noise immunity, the RTC and
RTD resistors should be placed as close to pins 3 and 4 of the device as possible. The timing capacitor should
be returned directly to the ground pin of the device with minimal stray inductance and capacitance.
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Figure 3. Isolated Flyback with TRIAC Dimming Interface
CAUTION
Do not operate the Isolated Flyback described in Figure 3 without load.
8
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SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
Figure 4. Low-Side (Inverted) Buck with TRIAC Dimming Interface
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TYPICAL CHARACTERISTICS
VDD STANDBY CURRENT
vs
JUNCTION TEMPERATURE
UNDERVOLTAGE LOCKOUT THRESHOLD
vs
JUNCTION TEMPERATURE
16
VUVLO – Undervoltage Lockout Threshold – V
180
160
IVDD – Standby Current – mA
TPS92001
140
120
100
80
TPS92002
60
40
20
0
–50
–25
0
25
50
75
100
14
12
10
8
6
UVLO Off
4
2
0
–50
125
–25
0
25
50
75
100
125
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 5.
Figure 6.
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
OVERVOLTAGE PROTECTION THRESHOLD
vs
TEMPERATURE
110
1000
fOSC – Oscillator Frequency – kHz
fOSC – Oscillator Frequency – kHz
TPS92002
UVLO On
TPS92001
UVLO On
105
100
95
100
RRTC = 10 kW
RRTD = 4.32 kW
90
–50
–25
0
25
50
75
TJ – Junction Temperature – °C
100
125
1
100
1000
Figure 7.
10
10000
CCT – Timing Capacitance – pF
Figure 8.
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SLUSA24A – FEBRUARY 2010 – REVISED NOVEMBER 2010
REVISION HISTORY
Changes from Original (FEBRUARY 2010) to Revision A
Page
•
Changed diode direction ....................................................................................................................................................... 1
•
Changed Figure 4 title .......................................................................................................................................................... 9
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS92001D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
92001D
TPS92001DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
92001
TPS92001DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
92001D
TPS92002D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
92002D
TPS92002DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
92002D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of