TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
Off-Line Primary Side Sensing Controller with PFC
Check for Samples: TPS92314, TPS92314A
FEATURES
DESCRIPTION
•
The TPS92314/14A is an off-line controller
specifically designed to drive high power LEDs for
lighting applications. Features include adaptive
constant on-time control and quasi-resonant
switching. Resonant switching allows for a reduced
EMI signature and increased system efficiency. Thus,
the device introduces a low external parts count and
high level of integration. The control algorithm of
TPS92314/14A adjusts the on time with reference to
the primary side inductor peak current and secondary
side inductor discharge time dynamically, the
response time of which is set by an external
capacitor.
1
2
•
•
•
•
•
•
•
•
Regulates LED Current Without Secondary
Side Sensing
Adaptive ON-time Control with Inherent PFC
Critical-Conduction-Mode (CRM) with ZeroCurrent Detection (ZCD) for Valley Switching
Programmable Switch Turn ON Delay
Programmable Constant ON-Time (COT)
Over Current Limit Options:
– TPS92314: 1.15V
– TPS92314A: 2.0V
Advanced Over Current and Over Voltage
Protection
Internal Over-temperature Protection
8-Pin SOIC Package
The over current protection is implemented by a cycle
by cycle current limit of the primary inductor current.
TPS92314A has a higher OCP threshold which is
more suitable for universal line application and
TPS92314 can optimize the system cost. Other
supervisory features of the TPS92314/14A include
VCC over voltage protection and under-voltage
lockout, output LEDs over-voltage protection and
controller thermal shutdown. The TPS92314/14A is
available in 8-pin SOIC package.
APPLICATIONS
•
•
Residential LED Lamps: A19 (E26/27, E14),
PAR30/38, GU10
Solid State Lighting
spacer
TYPICAL APPLICATION
DOUT
LED+
ZSN
T1
R1a
CIN
D1
AC
IN
DSN
LP
LS
6±7
LED
R1b
DVCC
COUTa
RVCC
RAUX1
CVCC
DZCD
COUTb
LAUX
LED-
RAUX2
CY1
Q1
TPS92314
VCC
GATE
AGND ISNS
ZCD PGND
COMP DLY
CCOMP
RFILTER
RISNS
RDLY
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
VCC
1
8
GATE
AGND
2
7
ISNS
ZCD
3
6
PGND
COMP
4
5
DLY
Figure 1. 8-Pin SOIC (Top View)
See D Package
PIN DESCRIPTIONS
2
Pin
Name
Description
1
VCC
Power supply Input
This pin provides power to the internal control , connect a 10μF~20μF capacitor
to ground for filtering.
2
AGND
Small signal Ground
Control signal ground return.
3
ZCD
Zero crossing detection input
4
COMP
Compensation network
5
DLY
Delay control input
6
PGND
Power Ground
7
ISNS
8
GATE
Application Information
The pin senses the voltage of the auxiliary winding for zero current detection.
Output of the error amplifier. Connect a capacitor from this pin to ground to
determine the frequency response of average current control loop.
Connect a resistor from this pin to ground to set the delay between switching
ON and OFF periods.
Gate driver ground return.
Current sense voltage feedback Switching MOSFET current sense pin.
Gate driver output
Submit Documentation Feedback
The output provides the gate driver of the power switching MOSFET.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1)
VALUE / UNITS
VCC to GND
–0.3V to 40V
DLY,COMP,ZCD to GND
–0.3V to 7V
ISNS to GND
–0.3V to 7V
GATE to GND
(5ns,-6V) -0.3V to 12V
ESD Susceptibility: HBM
(2)
±2 kV
Storage Temperature Range
–65°C to +150°C
Junction Temperature (TJ-MAX)
+150°C
Maximum Lead Temperature (Solder and Reflow)
260°C
(1)
(2)
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For specifications and test conditions, see
the Electrical Characteristics. All voltages are with respect to the potential at the GND pin, unless otherwise specified.
Human Body Model, applicable std. JESD22-A114-C.
RECOMMENDED OPERATING CONDITIONS
VALUE / UNITS
Supply Voltage range VCC
13V to 35V
Junction Temperature (TJ)
-40°C to +125°C
Thermal Resistance (θJA)
(1)
(1)
162°C/W
This RθJA typical value determined using JEDEC specifications JESD51-1 to JESD51-11. However junction-to-ambient thermal
resistance is highly board layout dependent. In applications where high maximum power dissipation exists, special care must be paid to
thermal dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
ELECTRICAL CHARACTERISTICS
VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing
in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits
are specified by design, test or statistical analysis.
Symbol
Parameter
Conditions
Min
Typ
(1)
Max
Units
SUPPLY VOLTAGE INPUT (VCC)
VCC-UVLO
VCC Turn on threshold
22.5 / 21.7
25.4
28.3 / 29.5
V
VCCTurn off threshold
10.4 / 10.1
12.9
15.3 / 16.0
V
µA
Hysteresis
ISTARTUP
Startup Current
VCC-OVP
Over voltage protection threshold
IVCC
Operating supply current
12.5
VCC=VCC-UVLO–3.0V
Not switching
22.2
25.8
32.7
35.5
38.0
V
0.8
1.2
1.8
mA
2.3
3.0
mA
0.01
1
uA
4.3
4.7
65kHz switching
ZERO CROSS DETECT (ZCD)
IZCD
ZCD bais current
VZCD-OVP
ZCD over-voltage threshold
VZCD= 5V
TOVP
Over voltage de-bounce time
VZCD-ARM
ZCD Arming threshold
VZCD = Increasing
1.04
1.23
1.42
V
VZCD-TRIG
ZCD Trigger threshold
VZCD = Decreasing
0.48
0.6
0.77
V
VZCD-HYS
ZCD Hysteresis
VZCD-ARM-VZCD-TRIG
3.9
3
V
cycle
0.61
V
27
µA
COMPENSATION (COMP)
ICOMP-SOURCE
(1)
Internal reference current for primary
side current regulation
VCOMP = 2.0V, VISNS = 0V, Measure at COMP pin
Typical numbers are at 25°C and represent the most likely norm.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
3
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing
in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits
are specified by design, test or statistical analysis.
Symbol
Parameter
Conditions
gmISNS
ISNS error amp trans-conductance
Δ VISNS to Δ ICOMP at VCOMP = 2.5V
Min
Typ
(1)
Max
96
Units
µmho
DELAY CONTROL (DLY)
VDLY
DLY pin internal reference voltage
IDLY-MAX
DLY source current
1.21
1.24
VDLY= 0V
250
450
1.3
V
µA
CURRENT SENSE (ISNS)
VISNS-OCP
Over Current Limit Detection Threshold
TPS92314
1.07
1.15
1.22
VISNS-OCP
Over Current Limit Detection Threshold
TPS92314A
1.90
2.0
2.10
V
IISNS
Current Sense Bias Current
VISNS= 5V
1
µA
TOCP
Over current Limit Detection Propagation
Delay
Measure ISNS pin pulse width with VISNS = 5V
-1
256
V
ns
GATE DRIVER (GATE)
VGATE-H
GATE low voltage
IGATE = 50mA source
VGATE-L
GATE high drive voltage
IGATE = 50mA sink
7.6
9.4
85
tGATE-RISE
Rise Time
CLOAD = 1nF
94
tGATE-FALL
Fall Time
CLOAD = 1nF
16
TON-MIN
Minimum ON time
With ZCD signal.
TON-MAX
V
125
mV
ns
ns
311
500
900
ns
Maximum ON time
27
43.9
61
µs
TOFF-MIN
Minimum OFF time
1.00
1.50
1.93
µs
TOFF-MAX
Maximum OFF time
ZCD = GND
67
117
151
µs
TOFF-START
Maximum OFF time when start up.
Maximum OFF time at first 511 switching after
UVLO
44
78
102
µs
TOFF-OCP
Maximum OFF time when OCP
OFF time when VISNS =4V.
233
µs
165
°C
20
°C
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
See
(2)
Thermal Shutdown hysteresis
(2)
4
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typ.) and
disengages at TJ = 145°C (typ).
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS
All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in
this datasheet. TA=25°C, unless otherwise specified.
15.0
VCC-UVLO vs Temperature
28
VCCSTARTUP VOLTAGE (V)
14.5
14.0
VCC-UVLO(V)
VCC Startup Voltage vs Temperature
29
13.5
13.0
12.5
12.0
11.5
27
26
25
24
23
22
11.0
-50
150
21
-25
0
25 50 75
TEMPERATURE (°C)
Figure 2.
100 125
-50
TOFF-MAX vs Temperature
580
TON-MIN(ns)
TOFF-MAX( s)
120
110
100
520
500
480
440
80
420
-25
0
25 50 75
TEMPERATURE (°C)
Figure 4.
100 125
-50 -25
IVCC-SD vs Temperature
4.7
0
25 50 75 100 125
TEMPERATURE (°C)
Figure 5.
VZCD-OVP vs Temperature
4.6
2.8
4.5
VZCD-OVP(V)
2.6
IVCC-SD(mA)
TON-MIN vs Temperature
460
90
2.4
2.2
4.4
4.3
4.2
2.0
4.1
1.8
4.0
1.6
-50
100 125
540
130
3.0
0
25
50
75
TEMPERATURE (°C)
Figure 3.
560
140
-50
-25
3.9
-25
0
25 50 75
TEMPERATURE (°C)
Figure .
100 125
-50
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
-25
0
25 50 75
TEMPERATURE (°C)
Figure 6.
100 125
Submit Documentation Feedback
5
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in
this datasheet. TA=25°C, unless otherwise specified.
1.50
VZCD-ARM vs Temperature
1.45
0.75
0.70
1.35
VZCD-TRIG(V)
VZCD-ARM(V)
1.40
1.30
1.25
1.20
1.15
0
25 50 75
TEMPERATURE (°C)
Figure 7.
VISNS_OCP vs Temperature
1.18
2.15
1.17
2.10
1.16
1.15
1.14
100 125
2.05
2.00
1.95
TPS92314A
1.85
1.80
-25
0
25 50 75
TEMPERATURE (°C)
Figure 9.
100 125
-50
VDLY vs Temperature
1.28
1.26
36.5
VCCOVP(V)
37.0
1.25
1.24
1.23
0
25 50 75
TEMPERATURE °C
Figure 10.
100 125
36.0
35.5
35.0
1.22
34.5
1.21
34.0
1.20
-25
VCC-OVP vs Temperature
37.5
1.27
-50
0
25 50 75
TEMPERATURE (°C)
Figure 8.
1.90
1.12
1.11
-50
-25
VISNS_OCP vs Temperature
2.20
TPS92314
VDLY(V)
0.56
0.40
-50
100 125
VISNS-OCP(V)
VISNS-OCP(V)
-25
1.13
6
0.60
0.45
1.05
1.19
0.65
0.50
1.10
1.00
-50
VZCD-TRIG vs Temperature
0.80
33.5
-25
0
25 50 75
TEMPERATURE (°C)
Figure 11.
Submit Documentation Feedback
100 125
-50
-25
0
25 50 75
TEMPERATURE (°C)
Figure 12.
100 125
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
SIMPLIFIED INTERNAL BLOCK DIAGRAM
VCC
BIAS & VREF
UVLO
VOCP_TH
VREF VC1
DRV
GATE
VCC_UVLO_TH
AGND
VCC_OV
PGND
VCC_OV_TH
TSD
VTRIG/VARM
ZC
ZCD
TON Peak
Hold
VONpk
CONTROL
LOGIC
LEB
LEB
OCP
ISNS
ZCD_OVP
TON
ON
VOCP_TH
ROCP
VC1
Internal
Ramp
IREF
D
UVLO
DRV
COMP
OFT
ZC
DELAY
ON
IDLY
VONpk
V/I
DLY
Figure 13. Simplified Block Diagram
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
7
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
APPLICATION INFORMATION
The TPS92314/14A is an off-line controller specifically designed to drive LEDs. This device operates in Critical
Conduction Mode (CRM) with adaptive Constant ON-Time control, so that high power factor can be achieved
naturally. The TPS92314/14A can be configured as an isolated or non-isolated off-line converter. Refer to
TPS92314/14A typical schematic, on the front page, in the following discussion. The TPS92314/14A flyback
converter consists of a transformer which includes three windings LP, LS and LAUX. An external MOSFET Q1 and
inductor current sensing resistor RISNS. Secondary side components are secondary side transformer winding LS,
output diode DOUT, and output capacitor COUT. An auxiliary winding is required, and serves two functions.
Auxiliary power is developed from the winding to power the TPS92314/14A after start-up, and detect the zero
crossing point due to the end of a complete switching cycle. During the on-period, Q1 is turned on, and current
flows through LP, Q1 and RISNS to ground, input energy is stored in the primary inductor LP. Simultaneously, the
ISNS pin of the device monitors the voltage of the current sensing resistor RISNS to perform the cycle-by-cycle
inductor current limit function. During the time MOSFET Q1 is off, current flow in LP ceases and the energy stored
during the on cycle is released to output and auxiliary circuits. During Q1 off-time current in the secondary
winding LS charges the output capacitor COUT through DOUT and supplies the LED load. During Q1 on-time, COUT
is responsible to supply load current to LED load during subsequent on-period. Also during Q1 off-time current is
delivered to the auxiliary winding through DVCC and powers the TPS92314/14A. The voltage across LAUX, VLAUX
is fed back to the ZCD pin through a resistor divider network formed by RAUX1 and RAUX2 to perform zero crossing
detection of VLAUX, which determines the end of the off-period of a switching cycle. The next on period of a new
cycle will be initiated after an inserted delay of 2 x tDLY. The tDLY is programmable by a single resistor connecting
the DLY pin and ground. The setting of the delay time, tDLY will be described in a separate paragraph. The driver
signal tON time width is generated by comparing an internal generated saw-tooth waveform with the voltage on
the COMP pin (VCOMP). Since VCOMP is slow varying, tON is nearly constant within an AC line cycle. The duration
of the off-period (tOFF) is determined by the rate of discharging of the secondary current through the transformer.
Also,
where
•
n is the turn ratio of LP and LS.
(1)
Figure 14 shows the typical waveforms in normal operation.
8
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
VSW
t
2xtDLY
ILP
VCOMP
t
tON
ILS
ILED
t
tOFF
VZCD
VZCD-OVP
VZCD-PEAK
VZCD-ARM
VZCD-TRIG
t
tDLY
Figure 14. Primary and Secondary Side Current Waveforms
Startup Bias and UVLO
During startup, the TPS92314/14A is powered from the AC line through R1 and bridge diode D1 (Typical
Application on front page). In the startup state, most of the internal circuits of the TPS92314/14A are shut down
in order to minimize internal quiescent current. When VCC reaches the rising threshold of the VCC-UVLO (typically
26V), the TPS92314/14A is operating in a low switching frequency mode, where tON and tOFF are fixed to 1.5μs
and 72μs. When VZCD–PEAK is higher than VZCD-ARM, the TPS92314/14A enters normal operation.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
9
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
VSW
Low Freq state
Steady state
Startup
state
t
VCC
26V
t
VZCD
VZCD-OVP
VZCD-ARM
t
Figure 15. Start up Bias Waveforms
Zero Crossing Detection
To minimized the switching loss of the power MOSFET, a zero crossing detection circuit is embedded in the
TPS92314/14A. VLAUX is AC voltage coupled from VSW by means of the transformer, with the lower part of the
waveform clipped by DZCD. VLAUX is fed back to the ZCD pin to detect a zero crossing point through a resistor
divider network which consists of RAUX1 and RAUX2. The next turn on time of Q1 is selected VSW is the minimum,
an instant corresponding to a small delay after the zero crossing occurs. (Figure 15) The actual delay time
depends on the drain capacitance of the Q1 and the primary inductance of the transformer (LP). Such delay time
is set by a single external resistor as described in Delay Setting section.
During the off-period at steady state, VZCD reaches its maximum VZCD-PEAK (Figure 14), which is scalable by the
turn ratio of the transformer and the resistor divider network RAUX1 and RAUX2. It is recommended that VZCD-PEAK
is set to 3V during normal operation.
n u VLED +VIN
n u VLED
VSW
tDLY
Figure 16. Switching Node Waveforms
10
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
Delay Time Setting
In order to reduce EMI and switching loss, the TPS92314/14A inserts a delay between the off-period and the onperiod. The delay time is set by a single resistor which connects across the DLY pin and ground, and their
relationship is shown in Figure 17. The optimal delay time depends on the resonance frequency between LP and
the drain to source capacitance of Q1 (CDS). Circuit designers should optimize the delay time according to the
following equation.
(2)
(3)
After determining the delay time, tDLY can be implemented by setting RDLY according to the following equation:
where
•
KDLY = 32MΩ/ns is a constant
(4)
60
RDLY(k )
50
40
30
20
10
0
0
400
800
1200 1600
DELAY TIME (ns)
2000
Figure 17. Delay Time Setting
Protection Features
OUTPUT OPEN CIRCUIT PROTECTION
The open circuit protection can be trigger through ZCD pin or VCC pin. If the LED string is disconnected from the
output of the TPS92314/14A, The secondly output voltage (VLED) and AUX wiring voltage VZCD-PEAK will
increases. IF VZCD-PEAK is greater than VZCD-OVP for 3 continues switching cycles or VCC voltage higher than
VCCOVP threshold, Over Voltage Protection (OVP) protection will be trigger. At the meantime, switching of Q1 will
stop and VCC will decreases until it drops below the falling threshold of VCC-UVLO, the controller will restarts
automatically and enter into startup state (Figure 19).
VCC OVP PROTECTION
The TPS92314/14A has a built-in over voltage protection feature. It can be trigger through the VCC pin when
over VCC-OVP threshold. Once the VCC-OVP triggered, the output gate signal will pull low and VCC will decrease
until it drops below the VCC-UVLO, the controller will restarts automatically.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
11
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
OUTPUT SHORT CIRCUIT PROTECTION
If the LED string is shorted, the voltage of AUX wiring (VZCD-PEAK) will decrease, and as VZCD-PEAK voltage
decrease below VZCD-TRIG, the TPS92314/14A will enter low switching frequency operation. During low switching
frequency operation, power supplied from LAUX to VCC is not enough to maintain VCC. If the short remains VCC will
drop below the falling threshold of VCC-UVLO, the TPS92314/14A will attempt to restart at this time (Figure 18).
When the short is removed the TPS92314/14A will restore to steady state operation.
VSW
Steady
state
Low freq
state
Low freq
state
t
VCC
26V
13V
t
VZCD
VZCD-OVP
VZCD-ARM
t
VLED
t
Figure 18. Output Short Circuit waveforms
OVER CURRENT PROTECTION
Over Current Protection (OCP) limits the drain current of MOSFET and prevents inductor / transformer
saturation. When VISNS reaches a threshold, OCP function will be triggered, controller gate drive will pull low and
OFF time will extends to 233μs, also CCOMP capacitor will be discharged by internal switch and gate drive ON
time will force to minimum in next cycle.
THERMAL PROTECTION
Thermal protection is implemented by an internal thermal shutdown circuit, which activates at 165°C (typically).
In this case, the switching power MOSFET will turn off. Capacitor CVCC will discharge until UVLO. If the junction
temperature of the TPS92314/14A falls back below 145°C, the TPS92314/14A resumes normal operation.
12
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
Steady state
Startup
state
Low Freq state
VSW
OV state
Steady
state
Disconnect LED
Reconnect LED
Steady
state
Startup
state
Startup
state
Startup
state
Low
Freq
state
VCC
VCC_OVP
26V
13.2V
VZCD
VZCD-OVP
VZCD-ARM
VLED
ILED
Steady
state
Force output short circuit
Steady
state
Figure 19. Auto Restart Operation
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
13
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
Design Example
The following design example illustrates the procedures to calculate the external component values for the
TPS92314/14A isolated single stage fly-back LED driver with PFC.
• Design Specifications:
– Input voltage range, VAC_RMS = 85VAC – 132VAC
– Nominal input voltage, VAC_RMS(NOM) = 110VAC
– Number of LED in serial =7
– LED current, ILED = 350mA
– Forward voltage drop of single LED = 3.0V
– Forward voltage of LED stack, VLED = 21V
• Key operating Parameters:
– Converter minimum switching frequency, fSW = 75kHz
– Output rectifier maximum reverse voltage, VDOUT(MAX) = 100V
– Power MOSFET rating, VQ1(MAX) =800V
– Power MOSFET Output Capacitance, CDS = 37pF (estimated)
– Nominal output power, POUT = 8W
START UP BIAS RESISTOR
During start up, the VCC will be powered by the rectified line voltage through external resistor, R1. The VCC start
up current, IVCC(SU) must set in the range IVCC(MIN) > IVCC(SU) > ISTARTUP(MAX) to ensure proper restart operation
during OVP fault at maximum voltage input. In this example, a value of 0.88mA is suggested. The resistance of
R1 can be calculated by dividing the nominal input voltage in RMS by the start up current suggested.
So, RAC = 132V / 0.88mA = 150KΩ is recommended.
TRANSFORMER TURN RATIO
The transformer winding turn ratio, n is governed by the MOSFET Q1 maximum rated voltage, (VQ1(MAX)), highest
line input peak voltage (VAC-PEAK) and output diode maximum reverse voltage rating (VOUT(MAX)). The output diode
rating limits the lower bound of the turn ratio and the power MOSFET rating provide the upper bound of the turn
ratio. The transformer turn ratio must be selected in between the bounds. If the maximum reverse voltage of
DOUT (VDOUT(MAX)) is 100V. the minimum transformer turn ratio can be calculated with the equation in below.
(5)
In operation, the voltage at the switching node, VSW must be small than the MOSFET maximum rated voltage
VQ1(MAX) , For reason of safety, 10% safety margin is recommended. Hence, 90% of VQ1(MAX) is used in the
following equation.
(6)
where
•
VOS is the maximum switching node overshoot voltage allowed, in this example, 50V is assumed.
(7)
As a rule of thumb, lower turn ratio of transformer can provide a better line regulation and lower secondly side
peak current. In here, turn ratio n = 3.8 is recommended.
14
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
SWITCHING FREQUENCY SELECTION
TPS92314/14A can operate at high switching frequency in the range of 60kHz to 150kHz. In most off-line
applications, with considering of efficiency degradation and EMC requirements, the recommended switching
frequency range will be 60kHz to 80kHz. In this design example, switching frequency at 75kHz is selected.
SWITCHING ON TIME
The maximum power switch on-time, tON depends on the low line condition of 85VAC. At 85VAC the switching
frequency was chosen at 75kHz. This transformer design will follow the formulae as shown below.
(8)
TRANSFORMER PRIMARY INDUCTANCE
The primary inductance, LP of the transformer is related to the minimum operating switching frequency fSW,
converter output power POUT, system efficiency η and minimum input line voltage VAC_RMS(MIN). For CRM
operation, the output power, POUT can be described by the equation in below.
(9)
By re-arranging terms, the transformer primary inductance required in this design example can be calculated with
the equation follows:
(10)
The converter minimum switching frequency is 75kHz, tON is 5.3µs, VAC_RMS(MIN) = 85V and POUT = 8W, assume
the system efficiency, η = 85%. Then,
(11)
From the calculation in above, the inductance of the primary winding required is 0.81mH.
After the primary inductance and transformer turn ratio is determined, the current sensing resistor, RISNS can be
calculated.
The resistance for RISNS is governed by the output current and transformer turn ratio, the equation in below can
be used.
where
•
VREF is fixed to 0.14V internally.
(12)
Transformer turn ratio, NP : NS is 3.8 : 1 and ILED = 0.35A
(13)
In Figure 20, resistor RFILTER is used to reduce the high frequency noise into ISNS pin. the typical value is 300 x
RISNS .
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
15
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
Q1
TPS92314
GATE
RFILTER
ISNS
PGND
DLY
RISNS
RDLY
Figure 20. RISNS Resistor Interface
DVCC
VCC
RAUX1
LAUX
ZCD
DZCD
PGND
RAUX2
PGND
PGND
Figure 21. Auxiliary Winding Interface to ZCD
Auxiliary Winding Interface To ZCD
In Figure 21, RAUX1 and RAUX2 forms a resistor divider which sets the thresholds for over voltage protection of
VLED, VZCD-OVP, and VZCD-PEAK. Before the calculation, we need to set the voltage of the auxiliary winding, VLAUX at
open circuit.
• For example :
– Assume the nominal forward voltage of LED stack (VLED) is 21V.
– To avoid false triggering ZCDOVP voltage threshold at normal operation, select ZCDOVP voltage at 1.3
times of the VLED is typical in most applications. In case the transformer leakage is higher, the ZCDOVP
threshold can be set to 1.5 times of the VLED.
– In this design example, open circuit AUX winding OVP voltage threshold is set to 30V. Assume the current
through the AUX winding is 0.4mA typical.
– As a result, RAUX1 is 66kΩ and RAUX2 is 12kΩ.
Auxiliary Winding Vcc Diode Selection
The VCC diode DVCC provides the supply current to the converter, low temperature coefficient , low reverse
leakage and ultra fast diode is recommended.
Compensation Capacitor And Delay Timer Resistor Selection
To achieve PFC function with a constant on time flyback converter, a low frequency response loop is required. In
most applications, a 4.7µF CCOMP capacitor is suitable for compensation.
16
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
TPS92314
VCC GATE
AGND ISNS
ZCD PGND
COMP DLY
CCOMP
RDLY
AGND
Figure 22. Compensation and DLY Timer connection
The resistor RDLY connecting the DLY pin to ground is used to set the delay time between the ZCD trigger to
power MOSFET turn on. The delay time required can be calculated with the parasitic capacitance at the drain of
MOSFET to ground and primary inductance of the transformer. Equation 14 can be used to find the delay time
and Figure 17 can help to find the resistance once the delay time is calculated
(14)
For example, using a transformer with primary inductance LP = 1mH, and power MOSFET drain to ground
capacitor CDS=37pF, the tDLY can be calculated by the upper equation. As a result, tDLY=302ns and RDLY is
6.31kΩ. The delay time may need to change according to the primary inductance of the transformer. The typical
level of output current will shift if inappropriate delay time is chosen.
Output Flywheel Diode Selection
To increase the overall efficiency of the system, a low forward voltage schottky diode with appropriate rating
should be used.
Primary Side Snubber Design
The leakage inductance can induce a high voltage spike when power MOSFET is turned off. Figure 23 illustrates
the operation waveform. A voltage clamp circuit is required to protect the power MOSFET. The voltage of
snubber clamp (VSN) must be higher than the sum of over shoot voltage (VOS), LED open load voltage multiplied
by the transformer turn ratio (n). In this examples, the VOS is 50V and LED maximum voltage, VLED(MAX) is 30V,
transformer turn ratio is 3.8. The snubber voltage required can be calculated with following equations.
VOS
VSN
VMOS_BV
n u VLED
VAC_PEAK
Vsw
Figure 23. Snubber Waveform
(15)
where n is the turn ratio of the transformer.
(16)
At the same time, sum of the snubber clamp voltage and VAC peak voltage (VAC_PEAK) must be smaller than the
MOSFET breakdown voltage (VMOS_BV). By re-arranging terms, equation in below can be used.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
17
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
(17)
In here, snubber clamp voltage, VSN = 250V is recommended.
Output Capacitor
The capacitance of the output capacitor is determined by the equivalent series resistance (ESR) of the LED,
RLED and the ripple current allowed for the application. The equation in below can be used to calculate the
required capacitance.
(18)
Assume the ESR of the LED stack contains 7 LEDs and is 2.6Ω, AC line frequency fAC is 60Hz.
In this example, LED current ILED is 350mA and output ripple current is 30% of ILED:
(19)
Then, COUT = 480μF.
In here, a 470μF output capacitor with 10μF ceramic capacitor in parallel is suggested.
PCB Layout Considerations
The performance of any switching power supplies depend as much upon the layout of the PCB as the
component selection. Good layout practices are important when constructing the PCB. The layout must be as
neat and compact as possible, and all external components must be as close as possible to their associated
pins. High current return paths and signal return paths must be separated and connect together at single ground
point. All high current connections must be as short and direct as possible with thick traces. The drain voltage of
the MOSFET should be connected close to the transformer pin with short and thick trace to reduce potential
electromagnetic interference. For off-line applications, one more consideration is the safety requirements. The
clearance and creepage to high voltage traces must be complied to all applicable safety regulations.
18
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
TPS92314
TPS92314A
www.ti.com
SNVS856B – JUNE 2012 – REVISED MAY 2013
DOUT
1A 100V
L1 3.3 mH
LED+
250V
0.5A
90-132VAC
RAC
22Q/1W
R1a
75k
D1
VR1
CIN2
CIN1
0.1 F 0.1 F
CIN3
0.1 F
R1b
75k
CAC
47 nF
T1
1A
600V
LP
COUTa
10 F
RVCC
20Q
DVCC
RAUX1
66 kQ
VCC
10 F
DZCD
VCC GATE
AGND ISNS
ZCD PGND
COMP DLY
COUTb
470 F
6±7
LED
RL
49.9 kQ
LAUX
RAUX2
12 kQ
LEDCY1
2200 pF
2A
800V
TPS92314
CCOMP
4.7 F
LS
NP : NS : NAUX = 3.8 : 1 : 1
RF
450Q
RISNS 1.5Q
RDLY
6.34 kQ
Figure 24. Isolated Topology Schematic
L1 3.3 mH
LED+
0.5A
RAC
22Q/1W
R1a
75k
D1
90-132VAC
VR1
CIN2
0.1 F
CIN1
0.1 F
R1b
75k
CAC
47 nF
DVCC
CIN3
0.1 F
T1
LP
COUTa
10 F
RVCC
20Q
RAUX1
66 kQ
VCC
10 F
DZCD
VCC GATE
AGND ISNS
ZCD PGND
COMP DLY
RDLY
6.34 kQ
COUTb
470 F
RL
49.9 kQ
6±7
LED
LAUX
RAUX2
12 kQ
LED-
NP:NAUX = 1:1
2A
800V
TPS92314
CCOMP
4.7 F
DOUT
1A 600V
RF
120Q
RISNS 0.4Q
Figure 25. Non-isolated Topology Schematic
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
Submit Documentation Feedback
19
TPS92314
TPS92314A
SNVS856B – JUNE 2012 – REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
•
20
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS92314 TPS92314A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS92314AD/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
T92314
A
TPS92314ADR/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
T92314
A
TPS92314D/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
T92314
TPS92314DR/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
T92314
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
