TPS92660
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SLUSBC2 – APRIL 2013
Two-String LED Driver with I2C OTP ROM Current Trim
Check for Samples: TPS92660
FEATURES
APPLICATIONS
•
•
•
•
•
•
1
2
•
•
•
•
•
•
•
Input Voltage: Up to 80 V
Two-Output LED Current Controller
LED Currents Trimmed Through One-Time
Programmable (OTP) ROM with I2C Interface
Adjustable SADJ and LADJ Pins for PWM
Dimming of Each LED String
Input Undervoltage Lockout and Output
Overvoltage Protection
Enable On/Off
Accurate 3.0-V Reference Voltage
> 95% Efficiency
Thermal Shutdown Protection
20-pin TSSOP Exposed Pad Package
Professional Lighting
Industrial and Commercial Lighting
General Illumination
DESCRIPTION
The TPS92660 is a two-output LED driver with one
time programmable (OTP) ROM and I2C interface for
LED current trim. The current trim provides a way for
LED fixture manufacturers to produce LED lighting
fixtures at a consistent lumen output without binning
LEDs.
One output of the device is a non-synchronous buck
controller which is used to regulate current of higher
power white LEDs. The other output of the device is a
linear regulator controller which is used to regulate
current of lower power red LEDs. The TPS92660 is
used for applications of controlled CCT (correlated
color temperature) LED lights by mixing white LEDs
with red LEDs.
This device is available in a 20-pin, TSSOP exposed
pad package.
TYPICAL APPLICATION
VOUT1
VIN
EN/UVLO
AC/DC
Front End
VOUT2
LED2+
VCC
GATE
LED1+
RON
LED1+
VO
LED2+
SW
TPS92660
GND
BOOT
REF
CS
SVDD
2
I C
Interface
VCC
COMP
SCL
GND
SDA
Dimming
Signal
SADJ
LADJ
LNG
LNCS
UDG-12217
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS92660
SLUSBC2 – APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
(2)
TJ
PACKAGE
–40°C to 125°C
TSSOP exposed pad
ORDERABLE
DEVICE NUMBER
TPS92660PWP
TPS92660PWPR
(2)
PINS
20
OUTPUT
SUPPLY
MINIMUM ORDER
QUANTITY
Tube
73
Tape and Reel
2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
Supply voltage
Input voltage range (2)
Electrostatic discharge
MIN
MAX
VCC
–0.3
14
VIN, UVLO/EN
–0.3
80
BOOT to SW
–0.3
14
SADJ, LADJ, RON, VO, COMP, CS, LNCS
–0.3
6
SW
–2.0
80
BOOT
–0.3
90
SVDD, SCL, SDA
–0.3
5.5
Human body model (HBM) QSS 009-105 (JESD22-A114A)
Junction temperature range, TJ
165
–55
Lead temperature range, soldering, 10 s
(2)
(3)
2
V
V
750
(3)
Storage temperature range, Tstg
(1)
2000
Charged device model (CDM) QSS 009-147 (JESD22-C101B.01)
UNIT
°C
150
260
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Maximum junction temperature is internally limited
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THERMAL INFORMATION
TPS92660
THERMAL METRIC
(1)
TSSOP exposed
pad (PWP)
UNITS
20 PINS
(2)
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance (3)
22.7
θJB
Junction-to-board thermal resistance (4)
18.6
36.9
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
18.4
θJCbot
Junction-to-case (bottom) thermal resistance (7)
1.9
°C/W
0.6
.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VVIN
Input Voltage
8.6
80
UNIT
V
VSVDD
I2C VDD
2.7
5.5
V
VVO
Output voltage sense for control and protection
0
2.5
V
VUVLO/EN
Enable/Under Voltage lock-out
0
5.5
V
VSADJ
Switching regulator analog or PWM LED current adjust
0
5.5
V
VLADJ
Linear regulator analog or PWM LED current adjust
0
5.5
V
VRON
Resistor and capacitor sets switching frequency of device
0
5.5
V
TJ
Operating junction temperature
–40
125
°C
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ELECTRICAL CHARACTERISTICS
Unless otherwise specified VIN = 48 V, –40°C VVO
(3)
R VO2
R ´ CT
= T
´
´V
VIN
(R VO1 + R VO2 ) OUT
(4)
Use Equation 3 and Equation 4 to derive Equation 5.
(R VO1 + R VO2 )
fSW =
R VO2 ´ RT ´ CT
(5)
tON
LED Current Setting
The current sense resistor (RSNS), which is connected between the CS pin and GND, sets the LED current of the
switching regulator. The current sense resistor (RSNSLN), which is connected between the LNCS pin and GND,
sets the LED current of the linear regulator. The average LED current is calculated using Equation 6 and
Equation 7.
Equation 6 shows the calculation for the switching regulator current.
12
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ILED _ SW =
VSW _ REF
RSNS
where
•
VSW_REF is the switching regulator reference voltage which is default 202 mV without OTP trim
(6)
Equation 7 shows the linear regulator current calculation.
VLN _ REF
ILED _ LN =
RSNS _ LN
where
•
VLN_REF is the linear regulator reference voltage which is default 200mV without OTP trim
(7)
High Voltage Bias Regulator (VCC)
The TPS92660 contains an internal low dropout linear regulator (LDO), with an 8.2V output, connected between
the VIN and the VCC pins. Bypass the VCC pin to the GND pin with a 1µF ceramic capacitor connected close to
the pins of the device. VCC tracks VIN until VIN reaches 8.2 V and then regulates at 8.2V as VIN increases. The
TPS92660 comes out of UVLO and begins operating when VCC rises above 6.4V. The TPS92660 shuts down
when VCC falls below 6.1V. The VCC regulator current limit is 20mA.
Peak Switching Current Limit
The TPS92660 contains a current limit comparator to limit the peak current of the high-side switching MOSFET.
When the high-side switching MOSFET turns on, there is a 200ns leading edge blank time. After that if the
voltage difference between the VIN pin and the SW pin exceeds 275 mV, the switching MOSFET is turned off for
a cool down period of approximately 280µs. In the meanwhile, the COMP pin is pulled low. If the current limit
condition persists, this cycle of cool down period and restarting continues, creating a low-power hiccup mode,
and minimizes the thermal stress on the switching MOSFET. Equation 8 shows the peak current limit calculation.
275mV
IPEAK =
RDS(on )
where
•
RDS(on) is the on resistance of the switching MOSFET
(8)
Output Open Circuit Protection
The most common failure mode for power LEDs is a broken bond wire, and the result is an open circuit. When
this happens the feedback path is disconnected, and the output voltage of the switching regulator begins to rise.
The VO pin voltage (which senses the output voltage of the switching regulator through a resistor divider) rises
with it. When the VO pin voltage reaches 2.5 V, it triggers the output OV protection and the high-side gate driver
turns off. During this time, the COMP pin is also pulled low. There is 0.1 V hysteresis on the OVP. The converter
does not resume switching until the voltage on the OV pin falls below 2.4 V.
BOOT Under Voltage Lockout (UVLO)
The TPS92660 has a BOOT UVLO circuit. The switching regulator starts switching once the BOOT-SW voltage
rises to 5.6 V. There is 750 mV of hysteresis on the BOOT UVLO. It stops switching when the BOOT-SW voltage
falls to 4.85V. Once the BOOT UVLO is triggered, the SW pin is pulled down by an internal MOSFET, such that
the boot capacitor can be recharged. The maximum pull-down current is 60mA. When the BOOT-SW voltage is
charged above 5.6 V, the pull-down circuit is disabled.
Linear Regulator LED Current Control Overview
Figure 17 shows the TPS92660 linear regulator control circuit. The voltage drop across the current sense resistor
RSNSLN is applied on the LNCS pin. An internal operational amplifier compares this voltage with the linear
regulator reference voltage. The output of the operational amplifier drives the gate of an external N-channel
MOSFET. This MOSFET operates in the linear region when the LED current is in regulation.
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The gate-drive voltage controls the drain-to-source voltage of the MOSFET by changing the MOSFET onresistance. Applications must minimize the voltage difference between the linear regulator input voltage and the
LED string forward voltage in order to limit the power dissipation on the MOSFET.
VOUT
LNG
LNG
LNCS
Control
EA
+
VLN_REF
RSNSLN
UDG-12208
Figure 17. Linear Regulator Control
SADJ and LADJ Pins for Dimming
The SADJ pin controls the switching regulator dimming and the LADJ pin controls the linear regulator dimming.
There are two different types of dimming that can be performed on those two pins.
Analog to PWM Dimming
When a DC voltage is applied on the SADJ pin, the switching regulator LED current is PWM dimmed at a fixed
frequency of approximately 500 Hz. As shown in Figure 18, the PWM dimming duty cycle is linearly dependent
on the input voltage level, from 0% duty cycle at 0.1 V to 100% duty cycle at 2.5 V. Similarly when a DC voltage
is applied on the LADJ pin, the linear regulator LED current is PWM dimmed in the same way.
2.5 V
0.1 V
SADJ/LADJ
Input Voltage
500 Hz
Ramp
Ideal LED Current
UDG-12209
Figure 18. SADJ/LADJ Input to PWM Dimming
14
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PWM Dimming
During PWM dimming, the signal applied on the pin is a PWM signal instead of a DC voltage. The LED current is
PWM dimmed at the same frequency and duty cycle as the input PWM signal. To implement PWM dimming, the
rising edges of two consecutive pulses of the input PWM signal must be less than 10ms. Once the device
detects two consecutive rising edges, the regulator goes into PWM dimming mode. It turns on when the input
PWM signal rises above the 2.7-V threshold and turns off when the PWM signal falls below the 2.2V threshold.
For the switching regulator, when the input PWM signal is low, the regulator turns off the gate of the MOSFET
and the COMP pin capacitor is disconnected. When the input PWM signal is high, the regulator starts again and
the COMP pin capacitor is reconnected.
A low gate charge MOSFET is recommended for the linear regulator to prevent LED current overshoot during
PWM dimming.
Input Undervoltage Lockout (UVLO)
The TPS92660 enable pin (EN/UVLO) can also be used to implement input undervoltage lockout. The input
UVLO voltage is set by a resistor divider from VIN to ground and is compared against a 1.2 V threshold shown in
Figure 19. As soon as the input voltage is above the preset UVLO rising threshold, the internal circuitry becomes
active and a 1-µA current source at the UVLO pin is turned on. This extra current provides hysteresis to create a
lower input UVLO falling threshold.
VIN
10 mA
RUV 1
EN/UVLO
ON/OFF
+
1.2 V
RUV 2
UDG-12210
Figure 19. Input UVLO Circuit
The VIN turn-on threshold is defined by Equation 9.
1.2 V ´ (RUV1 + RUV2 )
VIN _ ON =
RUV2
(9)
VHYS = RUV1 ´ 10 mA
(10)
I2C OTP ROM LED Current Trim
I2C Compatible Interface
Interface Bus Overview
The I2C compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bi-directional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).
These lines should be connected to a positive supply, via a pull-up resistor, and remain HIGH even when the bus
is idle. Every device on the bus is assigned a unique address and acts as either a master or a slave depending
on whether it generates or receives the serial clock (SCL).
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Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the high period, the data should remain stable. Any changes on the SDA line
during the high state of SCL and in the middle of a transaction aborts the current transaction. New data should
be sent during the low SCL state. This protocol permits a single data line to transfer both command/control
information and data using the synchronous serial clock.
I2C Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line can only be changed when SCL is LOW.
SCL
SDA
Data
change
allowed
Data
valid
Data
change
allowed
Data
change
allowed
Data
valid
UDG-12224
2
Figure 20. I C Signals: Data Validity
I2C Start and Stop Conditions
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
transitioning from HIGH to LOW while SCL is HIGH. STOP condition is defined as SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. Consider the I2C bus as
busy after a START condition and free after a STOP condition. During data transmission, the I2C master can
generate repeated START conditions. First START and repeated START conditions are functionally equivalent.
SDA
SCL
S
P
STOP condition
START condition
UDG-12222
2
Figure 21. I C Start and Stop Conditions
16
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I2C Addresses and Transferring Data
Every data value put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred
first. Each byte of data has to be followed by an acknowledge bit. The master generates the clock pulse for the
acknowledge bit. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledgement. A receiver which has
been addressed must generate an acknowledge bit after each byte has been received. After the START
condition, the I2C master sends a slave address. This address is seven bits long followed by an eighth bit which
is a data direction bit (R/W). The I2C slave address (7 bits) for TPS92660 is 28H. For the eighth bit, a “0”
indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data is written.
The third byte contains data to write to the selected register.
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
R/W
bit0
2
I C Slave Address (Chip Address)
UDG-12215
2
Figure 22. I C Chip Address
Register changes take effect at the SCL rising edge during the last ACK from the slave as shown in Figure 23.
ack from slave
ack from slave
msb Chip Address lsb
start
w
ack
msb Register Add lsb
ack
w
ack
addr = 02h
ack
ack from slave
msb
DATA
lsb
ack
stop
ack
stop
SCL
SDA
start
id = 28h
address 02h data
UDG-12223
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 28H for TPS92660.
Figure 23. I2C Write Cycle
A WRITE function must precede the READ function, as shown in the read cycle waveform in Figure 24.
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ack from slave
msb Chip Address lsb
start
w
ack from slave
msb Register Add lsb
repeated start
ack from slave
rs
msb Chip Address lsb
r
rs
id = 28h
r
data from slave
msb
DATA
nack from master
lsb
stop
SCL
SDA
start
id = 28h
w ack
addr = 00h
ack
ack
Address 00h data
nack
stop
UDG-12214
Figure 24. I2C Read Cycle
I2C Timing Parameters (VSVDD = 5 V)
SDA
10
8
7
6
1
8
2
7
SCL
1
5
3
4
9
UDG-12221
Figure 25. I2C Timing Diagram
TIME
PERIOD
(1)
PARAMETER (1)
LIMIT
MIN
MAX
UNITS
1
Hold time (repeated) START condition
0.6
μs
2
Clock low time
1.3
µs
3
Clock high time
600
ns
4
Setup time for a repeated START condition
600
ns
5
Data hold time (output direction)
300
ns
5
Data hold time (input direction)
0
ns
6
Data setup time
7
Rise time of SDA and SCL
20+0.1Cb
300
ns
8
Fall time of SDA and SCL
15+0.1Cb
300
ns
9
Set-up time for STOP condition
600
ns
10
Bus free time between a STOP and a START condition
1.3
μs
Cb
Capacitive load for each bus line
10
100
ns
200
pF
Data specified by design. Not production tested.
I2C Register Details
The I2C bus interacts with the TPS92660 to realize the features of LED current trim. The operation of these
functions requires the writing and reading of the internal registers of the TPS92660. Table 1 is the master
register map of the device.
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Table 1. Master Register Map
ADDR
01h
02h
FFh
REGISTER
STRIM
LTRIM
OTP ROM
D7
RSV
RSV
RSV
D6
RSV
RSV
RSV
D5
D4
RSV
RSV
RSV
BURNED
D5
D4
D3
D2
D1
STRIM[5:0]
LTRIM[3:0]
RSV
WRITE
RSV
D0
READ
DEFAULT
0001 1111
0000 0111
0000 1000
Register Definitions
STRIM Register Definition
ADDR
01h
REG
STRIM
D7
RSV
D6
RSV
D3
D2
STRIM[5:0]
D1
D0
DEFAULT
0001_1111
Bits
Description
5:0
The STRIM register is meant to be programmed with possible trim values. When the best values
have been found, the contents of this register may then be made permanent by burning them to OTP
ROM using the OTP ROM write cycle (described below).
Upon power-up, the values in OTP ROM are loaded into this register.
Switching Regulator LED Current Trim Table
STRIM[5:0]
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
XX11
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CURRENT
CHANGE
–20.0%
–19.4%
–18.8%
–18.1%
–17.5%
–16.9%
–16.3%
–15.6%
–15.0%
–14.4%
–13.8%
–13.1%
–12.5%
–11.9%
–11.3%
–10.6%
STRIM[5:0]
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
XX10
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CURRENT
CHANGE
–10.0%
–9.38%
–8.75%
–8.13%
–7.50%
–6.88%
–6.25%
–5.63%
–5.00%
–4.38%
–3.75%
–3.13%
–2.50%
–1.88%
–1.25%
–0.625%
STRIM[5:0]
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
XX01
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CURRENT
CHANGE
0%
0.625%
1.25%
1.88%
2.50%
3.13%
3.75%
4.38%
5.00%
5.63%
6.25%
6.88%
7.50%
8.13%
8.75%
9.38%
STRIM[5:0]
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
XX00
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CURRENT
CHANGE
10.0%
10.6%
11.3%
11.9%
12.5%
13.1%
13.8%
14.4%
15.0%
15.6%
16.3%
16.9%
17.5%
18.1%
18.8%
19.4%
LTRIM Register Definition
ADDR
02h
REG
LTRIM
D7
RSV
D6
RSV
D5
RSV
D4
RSV
D3
D2
D1
LTRIM[3:0]
D0
DEFAULT
0000_0111
Bits
Description
3:0
The LTRIM register is meant to be programmed with possible trim values. When the best values have
been found, the contents of this register may then be made permanent by burning them to OTP ROM
using the OTP ROM write cycle (described below).
Upon power-up, the values in OTP ROM are loaded into this register.
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Linear Regulator LED Current Trim Table
LTRIM[3:0]
XXXX 1111
XXXX 1110
XXXX 1101
XXXX 1100
CURRENT
CHANGE
-25.0%
-21.9%
-18.8%
-15.6%
LTRIM[3:0]
XXXX 1011
XXXX 1010
XXXX 1001
XXXX 1000
CURRENT
CHANGE
–12.5%
–9.38%
–6.25%
–3.13%
LTRIM[3:0]
XXXX 0111
XXXX 0110
XXXX 0101
XXXX 0100
CURRENT
CHANGE
0%
3.13%
6.25%
9.38%
LTRIM[3:0]
XXXX 0011
XXXX 0010
XXXX 0001
XXXX 0000
CURRENT
CHANGE
12.5%
15.6%
18.8%
21.9%
OTP ROM Register Definition
ADDR
FFh
REG
OTP ROM
D7
RSV
D6
RSV
D5
RSV
D4
BURNED
D3
RSV
D2
WRITE
D1
RSV
D0
READ
DEFAULT
0000_1000
Bits
Description
7:5
Reserved. These bits are reserved for future use. When writing to the OTP ROM register, always
write ‘0’s to these bits.
4
BURNED – This bit indicates that OTP ROM has been burned (when “BURNED” = 1). After burning
OTP ROM, an OTP ROM read cycle must take place in order for the BURNED bit to be updated.
This happens automatically upon power-up, or it can be accomplished manually by issuing an OTP
ROM read command (see bit 0).
3
RSV
2
WRITE – Burning the LTRIM and STRIM register values to OTP ROM is accomplished by writing this
bit to a ‘1’, waiting at least 25ms, and then writing this bit back to ‘0’.
1
RSV
0
READ – To reload the STRIM and LTRIM registers from OTP ROM, write this bit to a ‘1’. This bit
always reads back as a ‘0’. Writing this bit to a ‘1’ temporarily enables the 500 kHz oscillator to
perform the OTP ROM read. When the OTP ROM read is finished, the oscillator is disabled.
OTP ROM Programming
The programming of both the STRIM and the LTRIM registers to OTP ROM is performed in a single sequence as
follows
1. Write the STRIM and LTRIM registers with the desired values.
2. Write a ‘1’ to the WRITE bit of the OTP ROM register (this switches the internal EVDD from 5V to 8V).
3. Wait at least 25 ms.
4. Write a ‘0’ to the WRITE bit (this returns EVDD to 5 V).
20
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Product Folder Links: TPS92660
TPS92660
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SLUSBC2 – APRIL 2013
1
STRIM[5:0]
must be valid
LTRIM[3:0]
must be valid
8V
EVDD
5V
2
OTP
ROM[7:0]
4
00h
04h
00h
>25 ms
3
UDG-12213
Figure 26. OTP ROM Programming Sequence
OTP ROM Reading
The EPROM is read under either of the following conditions:
• Power-on reset. Note that power-on reset starts when both EN pin and VCC voltages cross the UVLO
threshold. It takes apprimately 50µs to read the OTP ROM contents into the TRIM registers.
• Writing a ‘1’ to the READ bit of the OTP ROM register. It is not necessary to clear the READ bit after writing it
to a ‘1’.
The device temporarily enables the 500-kHz oscillator during the OTP ROM read cycle. This operation is
necessary because the digital counters generate the timing for the OTP ROM read cycle. After the OTP ROM
read cycle is finished, the oscillator is disabled.
Figure 27 shows a power-on OTP ROM read cycle. The device reads all OTP ROM registers simultaneously. All
timing values are approximate and based on a 500-kHz internal oscillator.
POR
50 ms
STRIM [5:0]
valid
LTRIM [3:0]
valid
UDG-12212
Figure 27. Power-ON OTP ROM Read Timing
Reference Voltage
The TPS92660 provides a 3.0V reference voltage which can be used in the AC/DC main power supply
secondary-side control circuit.
Thermal Shutdown
Internal thermal shutdown circuitry protects the device in the event that the maximum junction temperature is
exceeded. The threshold for thermal shutdown is 165°C with a 25°C hysteresis. Thermal shutdown protection
disables the MOSFET drivers.
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21
TPS92660
SLUSBC2 – APRIL 2013
www.ti.com
DESIGN EXAMPLE
Specifications
Switching Regulator
• Switching Regulator: (fSW): 200 kHz
• Input voltage (VIN): 60 V
• Output voltage (VOUT): 48 V
• Charge current (ILED): 500 mA
• Output overvoltage protection threshold (VOVP): 60 V
Linear Regulator
• Input voltage (VIN): 30 V
• Output voltage (VOUT): 24 V
• Charge current (ILED): 20 mA
Design Procedure
Step 1: Select Overvoltage and Timing Components ROV1, ROV2, RT and CT
R VO2
VOVP ´
= 2.5 V
R
( VO1 + R VO2 )
•
•
•
•
•
•
VOVP = 60 V
Choose RVO2 = 1.00 kΩ
The calculated RVO1 = 23 kΩ, the standard resistor with the closest value (± 1%) is 23.2 kΩ
(R VO1 + R VO2 )
fSW =
R VO2 ´ RT ´ CT
(11)
(12)
fSW = 200 KHz
RT × CT = 121 x 10-6, choose CT = 1000 pF
the calculated RT = 121 kΩ
Step 2: Select Current Sense Resistors RSNS and RSNS_LN
The current sense resistor of the switching regulator RSNS = 202 mV/500 mA = 0.404 Ω.
The current sense resistor of the linear regulator RSNS_LN = 200 mV/20 mA = 10 Ω.
Step 3: Select Inductor
Choose inductor current ripple ΔIL_PP = 0.15 A ( 30% of ILED)
VOUT
48 V
t ON =
=
= 4 ms
VIN ´ fSW 60 V ´ 200 kHz
(V - VOUT ) ´ tON (60 V - 48 V )´ 4 ms
=
= 320 mH
L = IN
DIL(P-P )
0.15 A
(13)
(14)
The closest standard inductor value is 330 µH.
22
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Product Folder Links: TPS92660
AC/DC
Front End
VOUT2
LED2+
VOUT1
1 µF
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS92660
Dimming
Signal
I C
Interface
23.2 kW
2
LED1+
1000 pF
121 kW
1 kW
10 kW
154 kW
LADJ
SADJ
SDA
SCL
LNCS
LNG
GND
COMP
CS
REF
SVDD
BOOT
TPS92660
SW
GATE
VCC
VIN
GND
VO
RON
EN/UVLO
1 µF
VCC
0.22 µF
330 µH
0.4 Ω
LED1+
www.ti.com
UDG-12216
10 Ω
LED2+
1 µF
TPS92660
SLUSBC2 – APRIL 2013
Figure 28. Design Example Application Schematic
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23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS92660PWP/NOPB
ACTIVE
HTSSOP
PWP
20
73
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
TP92660
PWP
TPS92660PWPR/NOPB
ACTIVE
HTSSOP
PWP
20
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
TP92660
PWP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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