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TPS92690
SLVSBK3A – DECEMBER 2012 – REVISED SEPTEMBER 2015
TPS92690 N-Channel Controller for Dimmable LED Drives With Low-Side Current Sense
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
The TPS92690 device is a high-voltage, low-side
NFET controller with an adjustable output current
sense resistor voltage. Ideal for LED drivers, it
contains all of the features needed to implement
current regulators based on boost, SEPIC, flyback,
and Cuk topologies.
1
Input Voltage Range from 4.5 to 75 V
Adjustable Current Sense (50 to 500 mV)
Low-Side Current Sensing
2-Ω MOSFET Gate Driver
Input Undervoltage Protection
Output Overvoltage Protection
Cycle-by-Cycle Current Limit
PWM Dimming Input
Programmable Oscillator Frequency
External Synchronization Capability
Slope Compensation
Programmable Soft-Start Function
HTSSOP (PWP), 16-Pin, Exposed Pad Package
Output current regulation is based on peak currentmode control supervised by a control loop. This
methodology eases the design of loop compensation
while providing inherent input voltage feed-forward
compensation. The TPS92690 device includes a
high-voltage start-up regulator that operates over a
wide input range between 4.5 and 75 V. The PWM
controller is designed for high-speed capability
including an oscillator frequency range up to 2 MHz.
The TPS92690 device includes an error amplifier,
precision reference, cycle-by-cycle current limit, and
thermal shutdown.
2 Applications
•
•
Device Information(1)
LED Drivers
Constant Current Regulator: Boost, Cuk, Flyback,
and SEPIC
PART NUMBER
TPS92690
PACKAGE
HTSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
VIN
VOUT
TPS92690
VOUT
1
nDIM
VIN
16
2
OVP
VCC
15
3
RT
IS
14
4
SYNC
GATE
13
5
SS/SD
PGND
12
6
COMP
CSP
11
7
AGND
IADJ
10
8
ILIM
VREF
9
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92690
SLVSBK3A – DECEMBER 2012 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ............................................... 20
9
Power Supply Recommendations...................... 31
9.1 Bench Supply Current Limit .................................... 31
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 34
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2012) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Separated data sheet from TPS92690-Q1. For the TPS92690-Q1 data sheet, see SLVSCU0 on www.ti.com. .................. 1
2
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SLVSBK3A – DECEMBER 2012 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP With PowerPAD
Top View
nDIM
1
16
VIN
OVP
2
15
VCC
RT
3
14
IS
SYNC
4
13
GATE
SS/SD
5
12
PGND
COMP
6
11
CSP
AGND
7
10
IADJ
ILIM
8
Thermal Pad
9
VREF
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
7
GND
COMP
6
I
Connect ceramic capacitor to GND to set loop compensation.
CSP
11
I
Connect to positive terminal of sense resistor in series with LED stack.
GATE
13
O
Connect to main N-channel MOSFET gate of switching converter.
IADJ
10
I
Connect resistor divider from VREF to set error amplifier reference voltage.
ILIM
8
I
Connect resistor divider from VREF to set current limit threshold voltage at IS pin.
IS
14
I
Connect to drain of main N-channel MOSFET or to source of MOSFET if sense resistor is used for
improved accuracy.
nDIM
1
I
Connect resistor divider from VIN to set UVLO threshold and hysteresis. Connect through diode or
MOSFET to PWM dim concurrently.
OVP
2
I
Connect resistor divider from output voltage to set OVP threshold and hysteresis.
PGND
12
GND
Connect to AGND through the exposed thermal pad for proper ground return path.
RT
3
O
Connect resistor to AGND to set base switching frequency.
SS/SD
5
I
Connect capacitor to AGND to set soft-start delay. Pull pin below 75 mV for low-power shutdown.
SYNC
4
I
Connect external PWM signal to set switching frequency. Must be higher than base frequency set at RT
pin. Can also connect series resistor and capacitor to drain of main MOSFET and capacitor to AGND to
implement zero-crossing detection for quasi-resonant topologies. In either case, a falling edge on SYNC
triggers a new on-time at GATE. If tied to ground, internal oscillator is used.
VCC
15
O
Bypass with 2.2-µF ceramic capacitor to provide bias supply for controller.
VIN
16
I
Connect to input supply of converter. Bypass with 100-nF ceramic capacitor to AGND as close to the
device as possible.
VREF
9
O
Connect to the IADJ pin directly or through resistor divider. Bypass with 100-nF ceramic capacitor to
AGND.
Thermal Pad
Connect to PGND through DAP exposed thermal pad for proper ground return path.
GND
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6 Specifications
6.1 Absolute Maximum Ratings
All voltages are with respect to GND, –40°C < TJ = TA< 125°C, all currents are positive into and negative out of the specified
terminal (unless otherwise noted) (1)
Supply voltage
Input voltage
Output voltage
MIN
MAX
UNIT
VIN
–0.3
76
V
nDIM, OVP
–0.3
76
IS (2)
–0.3
76
CSP, IADJ, SS/SD, ILIM
–0.3
6
VCC, GATE (3)
–0.3
14
COMP, RT, VREF
–0.3
6
IS
Continuous input current
Output current
–1
1
mA
SYNC
1
VREF
–1
mA
150
°C
150
°C
Storage Temperature
(2)
(3)
(4)
V
–1
GATE
Operating junction temperature, TJ (4)
(1)
V
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The IS pin can sustain –2 V for 100 ns without damage.
the GATE pin can sustain –2.5 V for 100 ns. The VCC pin can sustain –2.5 V for 100 ns.
Maximum junction temperature is internally limited.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VIN
Input voltage
4.5
12
75
V
TJ
Operating junction temperature
–40
25
125
°C
VIADJ(max)
Maximum operating IADJ voltage
5
V
0
UNIT
6.4 Thermal Information
TPS92690
THERMAL METRIC (1)
PWP (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
39.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.8
°C/W
RθJB
Junction-to-board thermal resistance
17.5
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
17.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
–40°C < TJ = TA < 125°C, VIN = 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7.45
UNIT
STARTUP REGULATOR (VCC)
VCCREG
VCC regulation voltage
ICC = 0 mA
6.35
6.9
ICCLIM
VCC current limit
VVCC = 0 V
–20
–30
IQ
Quiescent current
ISD
Shutdown current
VCCUV
VCC UVLO threshold
VCCHYS
VCC UVLO hysteresis
2
3
mA
μA
VSS/SD = 0 V
45
65
VVCC rising
4.1
4.50
VVCC falling
3.61
V
mA
4.01
83
V
mV
REFERENCE VOLTAGE OUTPUT
VREF
Reference voltage
No load
2.4
2.45
2.5
V
ERROR AMPLIFIER
gM
CSP input bias current
–0.6
0
0.6
μA
COMP sink current
17.1
28.5
39.9
μA
–12.6
–16.8
–21
μA
COMP source current
VIADJ = 5 V
Transconductance
VIADJ = 1 V, 0 V ≤ VCSP ≤ 0.8 V
Transconductance bandwidth
–6dB
IADJ pin input impedance
VCSP
Error amplifier reference voltage
Precise value implied in offset
Error amplifier input offset voltage
33
μA/V
1
MHz
1
MΩ
VIADJ/10
V
VVCC = 4.5 V, 1 V ≤ VCOMP ≤ 1.4 V,
TA = 25°C
–1.5
0
1.5
VVCC > 6 V, 1 V ≤ VCOMP ≤ 3 V, VIADJ
≤ 1.25 V, TA = 25°C
–1.8
0
1.8
VVCC > 6 V, 1 V ≤ VCOMP ≤3 V, VIADJ
> 1.25 V, TA = 25°C (% of )
–1.44
0
1.44
90%
94.4%
950
1100
mV
VCSP%
PWM COMPARATOR and SLOPE COMPENSATION
DMAX
Maximum duty cycle
Internal oscillator only
No slope added
IS to PWM offset voltage
IOFF
D = DMAX (maximum slope added)
IS source current
No slope added
IOFF + ISL
1250
125
D = DMAX (maximum slope added)
mV
–11.9
μA
–60
μA
CURRENT LIMIT
ILIM delay to output
tON(min)
Leading edge blanking time
Current limit off-timer
60
100
200
300
D = 50%
ns
μs
38
ILIM offset voltage
ns
–19
–5.6
5
mV
30
86
mV
24
mV
–10.8
μA
–1.1
μA
LOW POWER SHUTDOWN and SOFTSTART
VSD
Shutdown threshold voltage
VSDH
Shutdown hysteresis
ISS
SS/SD current source
VSS/SD falling
VSS/SD > (VSD + VSDH)
VSS/SD < VSD
OSCILLATOR and EXTERNAL SYNCHRONIZATION
ƒSW
Switching frequency
SYNC threshold voltage (falling edge triggers
on-time)
RRT = 121 kΩ
312
350
389
RRT = 100 kΩ
372
418
464
RRT = 84.5 kΩ
436
490
544
2.05
2.36
Rising
Falling
0.95
1.31
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V
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Electrical Characteristics (continued)
–40°C < TJ = TA < 125°C, VIN = 14 V (unless otherwise noted)
PARAMETER
SYNC Clamp Voltage
TEST CONDITIONS
MIN
TYP
Positive
6.2
Negative
–0.5
MAX
UNIT
V
OVERVOLTAGE PROTECTION
OVP OVLO threshold
OVP hysteresis source current
Rising
Falling
OVP active (high)
1.23
1.282
1.144
1.19
–14
–21.5
–28
1.23
1.285
V
μA
PWM DIMMING INPUT and UVLO
nDIM/UVLO threshold
Rising
Falling
nDIM hysteresis current
V
1.14
1.19
–14
–21.6
–28
μA
GATE DRIVER
GATE sourcing resistance
GATE = High
2.4
6
Ω
GATE sinking resistance
GATE = Low
1
5
Ω
Peak GATE current
Source
Sink
–0.47
A
1.1
A
175
°C
25
°C
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
TSD(hys)
Thermal shutdown hysteresis
6
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6.6 Typical Characteristics
95
95
93
93
Efficiency (%)
Efficiency (%)
Unless otherwise noted, –40°C ≤ TA = TJ≤ 125°C, VVIN = 14 V, CBYP = 2.2 µF, CCOMP = 0.1 µF
91
89
87
91
89
87
12 LEDs
500mA
85
8
12
16
20
24
Input Voltage (V)
28
32
6 LEDs
500mA
85
36
8
10
12
Input Voltage (V)
G000
Figure 1. Boost Efficiency vs Input Voltage
14
16
G000
Figure 2. Boost Efficiency vs Input Voltage
505
1000
Switching Frequency (kHz)
900
Output Current (mA)
503
501
499
497
12 LEDs
495
10
15
20
25
Input Voltage (V)
30
700
600
500
400
300
35
40
60
80
G000
Figure 3. Boost Line Regulation
100
120
RT Resistance (kΩ)
140
160
G000
Figure 4. Switching Frequency vs RT Resistance
800
800
Output Current (mA)
Output Current (mA)
800
600
400
600
400
200
200
1A Nominal
20
40
60
PWM Duty Cycle (%)
80
100
0.0
G000
Figure 5. 160-Hz Boost PWM Dimming
0.5
1.0
1.5
IADJ Voltage (V)
2.0
2.5
G000
Figure 6. IADJ Analog Dimming (RCS = 0.25 Ω)
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Typical Characteristics (continued)
Unless otherwise noted, –40°C ≤ TA = TJ≤ 125°C, VVIN = 14 V, CBYP = 2.2 µF, CCOMP = 0.1 µF
95
430
94
425
Efficiency (%)
Switching Frequency (kHz)
435
420
415
93
92
91
410
12V Input
36V Output @ 350mA
405
−40 −25 −10
5
20 35 50 65 80
Ambient Temperature (°C)
95
90
−40 −25 −10
110 125
Figure 7. Switching Frequency vs Ambient Temperature
(RT = 100 kΩ)
95
110 125
G000
Figure 8. Efficiency vs Ambient Temperature
2.5
370
2.48
360
VREF Voltage (V)
Output Current (mA)
5
20 35 50 65 80
Ambient Temperature (°C)
G000
350
340
2.46
2.44
2.42
12V Input
36V Output @ 350mA
330
−40 −25 −10
5
20 35 50 65 80
Ambient Temperature (°C)
95
110 125
G000
Figure 9. Output Current vs Ambient Temperature
8
2.4
0
50
Ambient Temperature (°C)
100
G000
Figure 10. VREF Voltage vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The TPS92690 device is an N-channel MOSFET (NFET) controller for boost, SEPIC, Cuk, and flyback current
regulators which are ideal for driving LED loads. The controller has wide input voltage range allowing for
regulation of a variety of LED loads. The low-side current sense, with low adjustable threshold voltage, provides
an excellent method for regulating output current while maintaining high system efficiency.
The TPS92690 device uses peak current mode control providing good noise immunity and an inherent cycle-bycycle current limit. The adjustable current sense threshold provides a way to analog dim the LED current, which
can also be used to implement thermal foldback. The dual function nDIM pin provides a PWM dimming input that
controls the main GATE output for PWM dimming the LED current also.
When designing, the maximum attainable LED current is not internally limited because the TPS92690 device is a
controller. Instead it is a function of the system operating point, component choices, and switching frequency
allowing the TPS92690 device to easily provide constant currents up to 5 A. This simple controller contains all
the features necessary to implement a high efficiency versatile LED driver.
7.2 Functional Block Diagram
6.9-V LDO
Regulator
VIN
75 mV
VCC
VCC UVLO
UVLO
(4.1 V)
+
SS/SD
Reference
1.24 V
Standby
20 µA
nDIM
TLIM Thermal
Limit
1.24 V
+
100 NŸ
+
1.24 V
nUVLO
100 NŸ
Reset
Dominant
Clock
S
SYNC
VREF
VCC
Q
GATE
Oscillator
Artificial Ramp
RT
PGND
R
COMP
ISS
nUVLO
SS/SD
SS/SD
IADJ
+
gM Error
Amplifier
IOFF
Fault
20 µA
ROFF
+
9R
AGND
PWM
Fault
CSP
LEB
DMAX = 0.9
Standby
RSL
R
ILIM
+
40-µs
Latch
IS
OVP
+
1.24 V
ILIM
LEB
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7.3 Feature Description
7.3.1 Current Regulators
Current regulators can be designed to accomplish different functions: boost, buck-boost, and flyback. The
TPS92690 device is designed to drive a ground referenced N-channel FET and sense a ground referenced LED
load. This control architecture is perfect for driving boost, SEPIC, flyback, or Cuk topologies. It does not work
with a floating buck or buck-boost topology since the LED current sense amplifier is ground referenced.
Looking at the boost design in the Typical Boost Application, the basic operation of a current regulator can be
analyzed. During the time that the N-channel FET (Q1) is turned on (tON), the input voltage source stores energy
in the inductor (L1) while the output capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF),
the re-circulating diode (D1) becomes forward biased and L1 provides energy to both CO and the LED load.
Figure 11 shows the inductor current (iL(t)) waveform for a regulator operating in CCM.
IL(max)
'iL(P-P)
iL
tON = D×tS .
IL(min)
tOFF = (1±D)×tS
0
tS .
Time
Figure 11. Basic CCM Inductor Current Waveform
The average output LED current (ILED) is proportional to the average inductor current (IL), therefore if IL is tightly
controlled, ILED is well regulated. As the system changes input voltage or output voltage, the ideal duty cycle (D)
is varied to regulate IL and ultimately ILED. For any current regulator, D is a function of the conversion ratio:
Use Equation 1 to calculate the duty cycle for an application using the boost topology.
V - VIN
D = O
VO
(1)
Use Equation 2 to calculate the duty cycle for an application using the buck-boost (SEPIC/Cuk) topology.
VO
D =
VO + VIN
(2)
Use Equation 3 to calculate the duty cycle for an application using the flyback topology.
nVO
D =
nVO + VIN
where
•
n is the primary to secondary turns ratio of the coupled inductor, n:1
(3)
7.3.2 Peak Current Mode Control
Peak current mode control is used by the TPS92690 device to regulate the average LED current through an
array of HBLEDs. This method of control uses a series resistor in the LED path to sense LED current and can
use either a series resistor in the MOSFET path or the MOSFET RDS(on) for both cycle-by-cycle current limit and
input voltage feed forward. The controller has a fixed switching frequency set by an internal programmable
oscillator therefore slope compensation is added to mitigate current mode instability. A detailed explanation of
this control method is presented in the following sections.
10
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Feature Description (continued)
7.3.3 Switching Frequency and Synchronization
The switching frequency of the TPS92690 device is programmed using an external resistor (RT) connected from
the RT pin to GND. This switching frequency is defined as shown in Equation 4.
1
¦ SW =
-11
2.29 ´ 10 ´ RT + 80 ´ 10-9
(4)
The Typical Characteristics shows a graph of switching frequency versus timing resistance on RT. For maximum
operational range and best efficiency, TI recommends a switching frequency of 1 MHz or lower. It is possible to
reduce the solution size in applications with switching frequencies as high as 2 MHz in some situations. Higher
frequencies require an increased gate-drive current and that can result in higher AC losses, both of which result
in decreased efficiency. It is also possible that the minimum on-time (leading edge blanking time) limits the
minimum operational duty cycle and reduces the input voltage range for a given output voltage.
Alternatively, an external PWM signal can be applied to the SYNC pin to synchronize the device to an external
clock. If the PWM signal frequency applied is higher than the base frequency set by the timing (RT) resistor, the
internal oscillator is bypassed and the switching frequency is equal to the synchronized frequency. The PWM
signal should have an amplitude between 2.5 and 5 V. The device triggers a switch-on time on the falling edge of
the PWM signal and operates correctly regardless of the duty cycle of the applied signal.
ILED
COMP
CCMP
CSP
*
RF
gM Error
Amplifier
+
VCS
RCS
CF
*
+
±
IADJ
0-5V
IT
GATE
PWM
+
IOFF
9R
R
ROFF
To GATE
Artificial Ramp
IS
RSL
+
VLIM
RLIM
+
*
ILIM
ILIM
±
0 - 400 mV
Figure 12. Current Sense and Control Circuitry (* optional)
7.3.4 Current Sense and Current Limit
The TPS92690 device implements peak current mode control using the circuit shown in Figure 12. The peak
detection is accomplished with a comparator that monitors the main MOSFET current, comparing it with the
COMP pin. When the IS pin voltage (plus the DC level shift and the ramp discussed later) exceeds the COMP
pin voltage, the MOSFET is turned off. The MOSFET is turned back on when the oscillator starts a new on-time
and the cycle repeats.
The IS pin incorporates a cycle-by-cycle overcurrent protection function. Current limit is accomplished by a
redundant internal current sense comparator. If the voltage at the current sense comparator input (IS) exceeds
the voltage at the ILIM pin, the MOSFET is turned off and the COMP pin is pulled to ground and discharged. The
MOSFET turns back on after either the 43-µs current limit timeout has passed or after the COMP pin is
recharged, whichever is longer. The IS input pin has an internal N-channel MOSFET which pulls it down at the
conclusion of every cycle. The discharge device remains on an additional 216 ns (typical) after the beginning of a
new cycle to blank the leading edge spike on the current sense signal. This blanking time also results in a
minimum switch-on time of 216 ns which determines a minimum duty cycle dependent upon switching frequency.
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Feature Description (continued)
IS sensing can be done in one of two ways. The most accurate current sensing is accomplished by using a
resistor, RLIM. This adds a component that dissipates additional power but the result is higher accuracy and no
limitation on the maximum MOSFET drain voltage. For applications that have a maximum MOSFET drain voltage
below 75 V MOSFET RDS(on) sensing can be used by connecting the IS pin directly to the drain of the MOSFET
and eliminating RLIM. This results in higher efficiency but the accuracy depends on the accuracy of the MOSFET
RDS(on). Care must be taken to use the maximum expected RDS(on) when setting the current limit threshold at the
ILIM pin.
7.3.5 Average LED Current
The COMP pin voltage is dynamically adjusted, via the internal error amplifier, to maintain the desired regulation.
A sense resistor in series with the LEDs sets the average LED current regulation. The voltage across the sense
resistor (VCS) is regulated to the IADJ voltage divided by 10.
The IADJ pin can be set to any value up to 2.45 V by connecting it to VREF through a resistor divider for static
output current settings. IADJ can also be used to change the regulation point if connected to a controlled voltage
source up to 5 V or potentiometer to provide analog dimming. It is also possible to configure the IADJ pin for
thermal foldback functions.
V
ILED = CS
RCS
(5)
VCS =
VIADJ
10
(6)
The TPS92690 device maintains high accuracy at any level of VCS. However, the accuracy remains better with
higher levels as offsets and other errors become a smaller percentage of the overall VCS voltage. Power losses
are also higher with higher VCS voltages. A good tradeoff for accuracy and efficiency is to set the maximum VCS
voltage to between 100 and 250 mV.
In some applications, such as standard boost or flyback topologies, the output capacitor can be connected from
the output directly to ground. In these cases the CS pin can be directly connected to RCS. In other applications an
additional filter may be desired on the CS pin (RF and CF). Use these filters with topologies where the current
through RCS is not continuous such as in the Cuk configuration. Another example would be a boost regulator
where PWM dimming is required and the output capacitor is connected directly across the LEDs. In these cases
it is recommended to add a 47-Ω resistor for RF and a 47-nF capacitor for CF to achieve the best accuracy and
line regulation.
7.3.6 Precision Reference (VREF)
The TPS92690 device includes a precision 2.45-V reference. This can be used in conjunction with a resistor
divider to set voltage levels for the ILIM pin and the IADJ pin to set the maximum current limit and LED current. It
can also be used with high impedance external circuitry requiring a reference. To set the current limit (ICL) using
VREF you can use the following equations:
V
ICL = LIM
RLIM
(7)
VLIM = VILIM = VREF ´
RLIM1
RLIM1 + RLIM2
(8)
When RDS(on) sensing is being used substitute RLIM in the above equation with RDS(on). A small amount of
capacitance (CLIM) can be placed from the ILIM pin to ground for filtering if desired. If so, a value between 47 pF
and 100 nF should be used but this value should not exceed the value of CCMP to avoid false triggering of the
current limit. To set the IADJ voltage level using VREF use the following equation:
R ADJ1
VIADJ = VREF ´
R ADJ1 + R ADJ2
(9)
If desired, place a small capacitor (CADJ) from the IADJ pin to ground for additional filtering. A value between 47
pF and 100 nF should be sufficient.
12
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Feature Description (continued)
7.3.7 Low-Level Analog Dimming
The IADJ pin can be driven as low as 0 V. The device encounters a minimum on-time at some level, depending
on the switching frequency. When the voltage on the IADJ pin falls beyond this point, the device begins to skip
pulses to maintain average output current regulation. Depending on external components and regulator
bandwidth this skipping may or may not result in visible flicker. If flicker is present below this level higher inductor
and/or output capacitor values may help and a lower COMP pin capacitor value may help. In many cases this
level occurs at very low LED current and it is more desirable to simply limit the low level on the IADJ pin as
shown in Figure 13.
TPS92690
VREF
RADJ2
IADJ
RADJ1
VIADJ
Figure 13. Limiting Minimum IADJ Voltage
The resulting IADJ voltage can be found using the following equation:
R ADJ1
VIADJ = (VREF - VADJ )´
R ADJ1 + R ADJ2
(10)
7.3.8 Soft-Start and Shutdown
The TPS92690 device can be placed into low power shutdown by grounding the SS/SD pin (any voltage below
86 mV). During low power shutdown, the device limits the quiescent current to approximately 40 µA, typical.
The SS/SD pin also has a 10-µA current source (or 1 µA when below the 86-mV shutdown threshold), which
charges a capacitor from SS/SD to GND to soft-start the converter. The SS/SD pin is attached through a PNP
transistor to COMP therefore it controls the speed at which COMP rises at startup. When VCCUV is below the
falling threshold, SS/SD is pulled down to reset the capacitor voltage to zero. Then when VCCUV rising threshold
is exceeded, the pin is released and charges via the 10-µA current source.
7.3.9 VCC Regulator and Start-Up
The TPS92690 device includes a high voltage, low dropout bias regulator. When power is applied, or SS/SD is
released, the regulator is enabled and sources current into an external capacitor (CBYP) connected to the VCC
pin. The recommended bypass capacitance for the VCC regulator is 2.2 to 3.3 µF. This capacitor should be rated
for 10 V or greater and an X7R dielectric ceramic is recommended. The output of the VCC regulator is monitored
by an internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage
and the supply is also internally current limited. VCC may also be driven externally to increase the GATE voltage
and reduce the RDS(on) of the external switching MOSFET. The maximum voltage on this pin is 14 V and should
not exceed the VIN voltage. The bypass capacitor voltage rating may need to be increased accordingly.
The start-up time of the device to full output current depends on the value of CBYP, CSS (soft-start capacitor),
CCMP, and CO (output capacitor) as shown in Figure 14:
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Feature Description (continued)
1.0
Voltage (V)
tVCC
0
tCMP-SS
tCO
1.0
0.7
0
tCMP-SS
tVCC
tSS
tCO
TIme
Figure 14. Start-up Waveforms
First, CBYP is charged to be above the VCC UVLO threshold of 4.1 V. The CBYP charging time (tVCC) can be
estimated as:
4.1V ´ CBYP
t VCC =
30 mA
(11)
Assuming there is no CSS (top trace), or if CSS is less than 40% of CCMP, CCMP is then charged to 1V over the
charging time (tCMP) which can be estimated as:
1V ´ CCMP
t CMP =
VCS ´ 35 mS
(12)
Once CCMP = 1 V, the device starts switching to charge CO until the LED current is in regulation. The CO charging
time (tCO) can be roughly estimated as:
C ´ VO
t CO = O
ILED
(13)
If CSS is greater than 40% of CCMP (bottom trace), the compensation capacitor only charges to 0.7 V over a
smaller CCMP charging time (tCMP-SS) which can be estimated as:
0.7V ´ CCMP
t CMP -SS =
VCS ´ 35 mS
(14)
Then COMP clamps to SS, forcing COMP to rise (the last 300 mV before switching begins) according to the CSS
charging time (tSS) which can be estimated as:
0.3V ´ CSS
t SS =
11 mA
(15)
The system start-up time tSU (for CSS < 0.4 CCMP) or tSU-SS (for CSS > 0.4 CCMP) is defined as:
t SU = t VCC + t CMP + t CO
14
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Feature Description (continued)
t SU-SS = t VCC + t CMP -SS + t SS + t CO
(17)
As a general rule of thumb, standard smooth startup operation can be achieved with CSS = CCMP. If SD/SS is
being driven by an external source the equations above may need to be modified depending on the current
sourcing capability of the external source.
7.3.10 Overvoltage Protection (OVP)
TPS92690
20 µA
VO
ROV2
OVP
OVLO
+
1.24 V
ROV1
Figure 15. Overvoltage Protection Circuitry
The TPS92690 device includes a dedicated OVP pin which can be used for either input or output over-voltage
protection. This pin features a precision 1.24-V threshold with 20 µA (typical) of hysteresis current as shown in
Figure 15. When the OVP threshold is exceeded, the GATE pin is immediately pulled low and a 20-µA current
source provides hysteresis to the lower threshold of the OVP hysteretic band.
The over-voltage turn-off threshold (VTURN-OFF) and the hysteresis (VHYSO) are defined by:
R
´ ROV2
VTURN-OFF = 1.24V ´ OV1
ROV1
VHYSO = 20 mA ´ ROV2
(18)
(19)
7.3.11 Input Undervoltage Lockout (UVLO)
The nDIM pin is a dual function input that features an accurate 1.24-V threshold with programmable hysteresis
as shown in Figure 16. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO.
When the pin voltage rises and exceeds the 1.24-V threshold, 20 µA (typical) of current is driven out of the nDIM
pin into the resistor divider providing programmable hysteresis.
TPS92690
20 µA
VIN
RUV2
RUVH
nDIM
+
RUV1
(optional)
UVLO
1.24 V
Figure 16. UVLO Circuit
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Feature Description (continued)
When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra resistor
to set the hysteresis. This allows the standard resistor divider to have smaller values minimizing PWM delays
due to a pull-down MOSFET at the nDIM pin (see PWM Dimming). In general, at least 3 V of hysteresis is
preferable when PWM dimming if operating near the UVLO threshold. The turn-on threshold (VTURN-ON) is defined
as follows:
R
´ RUV2
VTURN-ON = 1.24V ´ UV1
RUV1
(20)
The hysteresis (VHYS) is defined as follows:
UVLO Only
VHYS = 20 mA ´ RUV 2
(21)
PWM Dimming and UVLO
æ
RUVH ´ (RUV1 + RUV2 ) ö
VHYS = 20 mA ´ ç RUV2 +
÷
ç
÷
RUV1
è
ø
(22)
7.3.12 PWM Dimming
The active low nDIM pin can be driven with a PWM signal which controls the main N-channel FET. The
brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness is
approximately proportional to the PWM signal duty cycle (that is, 30% nDIM high duty cycle equals about 30%
LED brightness). This function can be ignored if PWM dimming is not required by using nDIM solely as a VIN
UVLO input as described in the Input Undervoltage Lockout (UVLO) section or by tying it directly to VCC or VIN
when UVLO is not required.
VIN
DDIM
RUV2
TPS92690
Inverted PWM
nDIM
RUVH
RUV1
QDIM
Standard PWM
Figure 17. PWM Dimming Circuit
When using a MOSFET (QDIM), connect the drain to the nDIM pin and the source to GND. Apply an external
logic-level PWM signal to the gate of QDIM. Brightness is proportional to the negative duty cycle of the PWM
signal. When using a Schottky diode (DDIM), connect the anode to the nDIM pin. Apply an external logic-level
PWM signal to the cathode of the diode and brightness is proportional to the positive duty cycle of the PWM
signal.
7.3.13 Control Loop Compensation
Compensating the TPS92690 device is relatively simple for most applications. To prevent subharmonic
oscillations due to current mode control, a minimum inductor value should be chosen. This minimum value can
be approximated with the following equation:
16
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Feature Description (continued)
Lmin =
VO ´ 425 ´ 103
(mH)
2 ´ ¦ SW
(23)
Compensating the control loop simply requires a capacitor from the COMP pin to ground. Most LED driver
applications do not require high bandwidth response since there are no significant output transients and
generally limited, low bandwidth input transients. The high output impedance (RO) of the error amplifier (typically
200MΩ) enables a low bandwidth system where standard poles and zeros, including the right half plane zero in
many cases, can be neglected. In this case the bandwidth of the system generally becomes the bandwidth of the
error amplifier. TI recommends a CCMP value of 1 to 100 nF, which results in the following dominant pole and
crossover frequency:
1
¦P1 =
2p ´ RO ´ CCMP
(24)
gm
¦C =
2p ´ CCMP
(25)
A 1-nF capacitor results in a bandwidth of approximately 5.2 kHz while a 100-nF capacitor results in a bandwidth
of approximately 52 Hz. Larger values are recommended for most applications unless higher bandwidth is
required. Larger values are also recommended for applications requiring PWM dimming as it allows the COMP
pin to hold its level more accurately during the LED current off time. In applications where the duty cycle (D)
exceeds 0.5 (VIN < VO / 2 for a boost regulator) the location of the right half plane zero should be calculated to
ensure stability using the following equation:
¦RHPZ =
rD ´ D'2
2p ´ D ´ L1
(26)
Where D and D’ are calculated using the minimum input voltage. The crossover frequency, ƒC, should be a
decade below ƒRHPZ for maximum stability. CCMP should be adjusted accordingly if required.
7.3.14 Thermal Shutdown
The TPS92690 device includes thermal shutdown protection. If the die temperature reaches approximately
175°C the device shuts down (GATE pin low). If the die temperature is allowed to cool until it reaches
approximately 150°C the device resumes normal operation.
7.4 Device Functional Modes
This device has no additional functional modes
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8 Application and Implementation
NOTE
Information in the following applications sections is not included in the TI component
specification, and TI does not warrant its accuracy or completeness. TI customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Inductor
The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy
is stored in the inductor and transferred to the load in different ways (as an example, boost operation is detailed
in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the switching
subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP). In the design process, L1 is chosen to
provide a desired ΔiL-PP. For a Cuk regulator the second inductor (L2) has a direct connection to the load, which
is good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to
the LED ripple current ΔiLED-PP since the inductor ripple in L2 is equal to that in L1. However, for boost and other
buck-boost regulators, there is always an output capacitor which reduces ΔiLED-PP, therefore the inductor ripple
can be larger than in the Cuk regulator case where output capacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED).
Therefore, for the Cuk regulator with no output capacitance, ΔiLED-PP should also be less than 40% of ILED unless
a large output capacitor is used. For the boost and other buck-boost topologies, ΔiL-PP can be much higher
depending on the output capacitance value. However, ΔiL-PP is suggested to be less than 100% of the average
inductor current (iL) to limit the RMS inductor current. ΔiL-PP is defined as:
V ´D
DiL -PP = IN
L ´ fSW
(27)
Be sure to observe the minimum inductor value from the Control Loop Compensation section. L1 is also
suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable RMS
inductor current (IL-RMS).
8.1.2 LED Dynamic Resistance
When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RCS.
LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the
forward voltage of a single LED (VLED) by the forward current (ILED) can lead to an incorrect calculation of the
dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value.
Figure 18. Dynamic Resistance
Obtaining rLED is accomplished by referring to the manufacturer LED I-V characteristic. It can be calculated as the
slope at the nominal operating point as shown in Figure 18. For any application with more than 2 series LEDs,
RCS can be neglected allowing rD to be approximated as the number of LEDs multiplied by rLED.
18
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Application Information (continued)
8.1.3 Output Capacitor
For boost, SEPIC, and flyback regulators, the output capacitor (CO) provides energy to the load when the
recirculating diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a Cuk
topology simply reduces the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases,
CO is sized to provide a desired ΔiLED-PP. As mentioned in Inductor, ΔiLED-PP is recommended by manufacturers to
be
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