TPSM63602
SLVSGK8 – APRIL 2022
TPSM63602 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 2-A Power Module
With Enhanced HotRod™ QFN Package
1 Features
3 Description
•
The TPSM63602 synchronous buck power module
is a highly integrated 36-V, 2-A DC/DC solution that
combines power MOSFETs, a shielded inductor, and
passives in an Enhanced HotRod™ QFN package.
The module has pins for VIN and VOUT located at the
corners of the package for optimized input and output
capacitor layout placement. Four larger thermal pads
beneath the module enable a simple layout and easy
handling in manufacturing.
•
•
•
•
With an output voltage from 1 V to 16 V, the
TPSM63602 is designed to quickly and easily
implement a low-EMI design in a small PCB footprint.
The total solution requires as few as four external
components and eliminates the magnetics and
compensation part selection from the design process.
Although designed for small size and simplicity
in space-constrained applications, the TPSM63602
module offers many features for robust performance:
precision enable with hysteresis for adjustable inputvoltage UVLO, resistor-programmable switch node
slew rate for improved EMI, integrated VCC, bootstrap
and input capacitors for increased reliability and
higher density, constant switching frequency over the
full load current range for enhanced load transient
performance, and a PGOOD indicator for sequencing,
fault protection, and output voltage monitoring.
Device Information
PART
2 Applications
•
•
•
NUMBER(1)
TPSM63602
Test and measurement, aerospace and defense
Factory automation and control
Buckand inverting buck-boost power supplies
(1)
PACKAGE
BODY SIZE (NOM)
B0QFN (30)
4.0 mm × 6.0 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
space
100
VIN = 3 V...36 V
95
VIN
CIN
CBOOT
90
RBOOT
85
PGND
TPSM63602
EN/SYNC
VOUT = 5 V
IOUT(max) = 2 A
VLDOIN
80
75
70
65
60
VOUT
VIN = 12 V
VIN = 24 V
VIN = 36 V
55
PG
RFBT
VCC
COUT
FB
RT
RFBB
CVCC
RRT
Efficiency (%)
•
Versatile synchronous buck DC/DC module
– Integrated MOSFETs, inductor, and controller
– Wide input voltage range of 3 V to 36 V
– Adjustable output voltage from 1 V to 16 V
– 4-mm × 6-mm × 1.8-mm overmolded package
– –40°C to 125°C junction temperature range
– Frequency adjustable from 200 kHz to 2.2 MHz
using the RT pin or an external SYNC signal
– Negative output voltage capability
Ultra-high efficiency across the full load range
– 93% peak efficiency at 12 VIN, 5 VOUT, 1 MHz
– External bias option for improved efficiency
– Shutdown quiescent current of 0.6 µA (typical)
– 0.3-V typical dropout voltage at 2-A load
Ultra-low conducted and radiated EMI signatures
– Low-noise package with dual input paths and
integrated capacitors reduces switch ringing
– Resistor-adjustable switch-node slew rate
– Constant-frequency FPWM mode of operation
– Meets CISPR 11 and 32 class B emissions
Suitable for scalable power supplies
– Pin compatible with the TPSM63603 (36 V, 3 A)
Inherent protection features for robust design
– Precision enable input and open-drain PGOOD
indicator for sequencing, control, and VIN UVLO
– Overcurrent and thermal shutdown protections
Create a custom design using the TPSM63602
with the WEBENCH® Power Designer
50
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
Typical Efficiency, VOUT = 5 V, fSW = 1 MHz
AGND
* VOUT enters dropout
if VIN < 5.4 V
Typical Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM63602
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SLVSGK8 – APRIL 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 System Characteristics............................................... 9
7.7 Typical Characteristics.............................................. 10
7.8 Typical Characteristics — 2-A Device (VIN = 12 V)... 11
7.9 Typical Characteristics — 2-A Device (VIN = 24 V)...12
7.10 Typical Characteristics — 2-A Device (VIN = 36
V).................................................................................13
8 Detailed Description......................................................14
8.1 Overview................................................................... 14
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................23
9 Applications and Implementation................................ 24
9.1 Application Information............................................. 24
9.2 Typical Applications.................................................. 24
10 Power Supply Recommendations..............................32
11 Layout........................................................................... 33
11.1 Layout Guidelines................................................... 33
11.2 Layout Example...................................................... 33
12 Device and Documentation Support..........................34
12.1 Device Support....................................................... 34
12.2 Documentation Support.......................................... 35
12.3 Receiving Notification of Documentation Updates..35
12.4 Support Resources................................................. 35
12.5 Trademarks............................................................. 35
12.6 Electrostatic Discharge Caution..............................35
12.7 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
April 2022
*
Initial Release
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5 Device Comparison Table
Device
Orderable Part
Number
Mode
Spread
Spectrum
Output Voltage
External
Sync
Junction
Temperature
TPSM63602
TPSM63602RDHR
FPWM
No
Adjustable
Yes
–40°C to 125°C
TPSM63602V3
TPSM63602V3RDHR
FPWM
No
Fixed 3.3 V
Yes
–40°C to 125°C
TPSM63602V5
TPSM63602V5RDHR
FPWM
No
Fixed 5 V
Yes
–40°C to 125°C
RT
1
EN/SYNC
2
VIN
3
PG
FB
AGND
VCC
VLDOIN
26
25
24
23
22
6 Pin Configuration and Functions
21
RBOOT
20
CBOOT
19
VIN
18
VIN
17
PGND
16
PGND
15
VOUT
14
VOUT
27
AGND
28
PGND
VIN
4
PGND
5
29
PGND
PGND
6
VOUT
7
30
VOUT
9
10
11
12
13
VOUT
SW
VOUT
VOUT
8
VOUT
VOUT
Figure 6-1. 30-Pin QFN, RDH Package (Top View)
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Table 6-1. Pin Functions
PIN
NAME
NO.
RT
1
DESCRIPTION
I
Frequency setting pin. This analog pin is used to set the switching frequency between 200 kHz and 2.2
MHz by placing an external resistor from this pin to AGND. Do not leave this pin open or connect this pin
to ground.
EN/SYNC
2
I
Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows
the pin to be used as an adjustable UVLO. It also functions as the synchronization input pin. Used to
synchronize the device switching frequency to a system clock. Triggers on the rising edge of an external
clock. A capacitor can be used to AC couple the synchronization signal to this pin. The module can be
turned off by using an open-drain or collector device to connect this pin to AGND. An external voltage
divider can be placed between this pin, AGND, and VIN to create an external UVLO.
VIN
3, 4, 18,
19
P
Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device. Refer to Section 11.2 for input capacitor placement
example.
PGND
5, 6, 16,
17, 28,
29
G
Power ground. This is the return current path for the power stage of the device. Connect this pad to the
input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See
Section 11.2 for a recommended layout.
VOUT
7–10,
12–15,
30
P
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external output capacitors between these pins and PGND.
SW
11
O
Switch node. Do not place any external component on this pin or connect to any signal. The amount of
copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.
I/O
Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally connected
from this pin to SW within the module to provide the bootstrap voltage. This pin is brought out to use in
conjunction with RBOOT to effectively lower the value of the internal RBOOT resistor to adjust the SW
node slew rate, if necessary.
External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected
between this pin and the CBOOT pin. This pin is brought out to use in conjunction with CBOOT
to effectively lower the value of the internal RBOOT resistor to adjust the switch node slew rate, if
necessary.
CBOOT
(1)
4
TYPE(1)
20
RBOOT
21
I/O
VLDOIN
22
P
Input bias voltage. Supplies the control circuitry of the power module. Input to internal LDO. Connect to
an output voltage point to improve efficiency. Connect an optional high-quality 0.1-μF to 1-μF capacitor
from this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin
to ground.
VCC
23
O
Internal LDO output. Used as supply to internal control circuits. Do not connect to any external loads.
Connect a high-quality 1-μF ceramic capacitor from this pin to PGND.
AGND
24, 27
G
Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are
measured with respect to this pin. This pin must be connected to PGND at a single point. See Section
11.2 for a recommended layout.
FB
25
I
Feedback input. For the adjustable output version, connect the mid-point of the feedback resistor divider
to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of
regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. When connecting with
feedback resistor divider, keep this FB trace short and as small as possible to avoid noise coupling. See
Section 11.2 for a feedback resistor placement. For a fixed output version, connect this pin directly to
output capacitor. Do not leave open or connect to ground.
PG
26
O
Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified
window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required to a suitable pullup voltage. If not used,
this pin can be left open or connected to PGND.
P = Power, G = Ground, I = Input, O = Output, NC = No connect
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7 Specifications
7.1 Absolute Maximum Ratings
Limits apply over TJ = –40°C to 125°C (unless otherwise noted). (1)
Input voltage
MIN
MAX
VIN to AGND, PGND
–0.3
40
RBOOT to SW
–0.3
5.5
CBOOT to SW
–0.3
5.5
VLDOIN to AGND, PGND
–0.3
16
EN/SYNC to AGND, PGND
–0.3
40
RT to AGND, PGND
–0.3
5.5
FB to AGND, PGND
–0.3
16
0
20
PG to AGND, PGND
PGND to AGND
Output voltage
–1
2
VCC to AGND, PGND
–0.3
5.5
SW to AGND, PGND(2)
–0.3
40
VOUT to AGND, PGND
–0.3
16
UNIT
V
V
Input current
PG
—
10
mA
TJ
Junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Tstg
Storage temperature
–55
150
°C
260
°C
Peak reflow case temperature
Maximum number of reflows allowed
3
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 ms, 1/2 sine, mounted
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
(1)
(2)
1500
G
20
G
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Limits apply over TJ = –40°C to 125°C (unless otherwise noted).
MIN
Input voltage
VIN (Input voltage range after start-up)
Input voltage
VLDOIN
Output voltage
VOUT(1)
Output voltage
VOUT(1)
TPSM63602V3
Output voltage
VOUT(1)
TPSM63602V5
Output current
IOUT(2)
Frequency
fSW set by RT or SYNC
Input current
PG
Output voltage
PG
TJ
TA
(1)
(2)
NOM
3
1
MAX
UNIT
36
V
12
V
16
V
3.3
V
5
V
0
2
200
2200
kHz
A
2
mA
0
16
V
Operating junction temperature
–40
125
°C
Operating ambient temperature
–40
105
°C
Under no conditions should the output voltage be allowed to fall below 0 V.
Maximum continuous DC current may be derated when operating with high switching frequency, high ambient temperature, or both.
Refer to the Typical Characteristics section for details.
7.4 Thermal Information
THERMAL METRIC(1)
30 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (TPSM63603 EVM)
29.1
°C/W
RθJA
Junction-to-ambient thermal resistance(2)
33.5
°C/W
ψJT
Junction-to-top characterization parameter(3)
4.1
°C/W
21.5
°C/W
ψJB
(1)
(2)
(3)
(4)
6
RDH (QFN)
Junction-to-board characterization
parameter(4)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 64-mm × 83-mm four-layer PCB with 2-oz.
copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA. For more information see the Layout
section.
The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1 mm from the device.
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7.5 Electrical Characteristics
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, fSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Needed to start up (over IOUT range)
VIN
Input operating voltage range
VIN_HYS
Hysteresis(1)
IQ_VIN
Input operating quiescent current (non-switching)
ISDN_VIN
VIN shutdown quiescent current
Once operating (over IOUT range)
3.95
3
36
V
36
V
1.0
V
TA = 25°C, VEN/SYNC = 3.3 V, VFB = 1.5 V
4
µA
VEN/SYNC = 0 V, TA = 25°C
3
µA
ENABLE
VEN_RISE
EN voltage rising threshold
VEN_FALL
EN voltage falling threshold
1.161
VEN_HYS
EN voltage hysteresis
0.275
VEN_WAKE
EN wake-up threshold
0.4
IEN
Input current into EN/SYNC (non-switching)
tEN
EN HIGH to start of switching delay(1)
1.263
1.365
0.91
VEN/SYNC = 3.3 V, VFB = 1.5 V
0.353
V
V
0.404
V
V
1.65
µA
0.7
ms
INTERNAL LDO VCC
VCC
VCC_UVLO
Internal LDO VCC output voltage
VCC UVLO rising threshold
hysteresis(2)
VCC_UVLO_HYS
VCC UVLO
IVLDOIN
Input current into VLDOIN pin (non-switching,
maximum at TA = 125°C)(3)
3.4 V ≤ VLDOIN ≤ 12.5 V
3.3
V
VLDOIN = 3.1 V, non-switching
3.1
V
VLDOIN < 3.1 V(1)
3.6
V
VIN < 3.6 V(2)
3.6
V
Hysteresis below VCC_UVLO
1.1
V
VEN/SYNC = 3.3 V, VFB = 1.5 V
25
31.2
µA
16
V
FEEDBACK
Adjustable output voltage range (TPSM63602)
VOUT
Fixed output voltage (TPSM63602V3)
1
Over the IOUT range
Fixed output voltage (TPSM63602V5)
VFB
3.3
V
5.0
V
1.0
V
Feedback voltage
TA = 25°C, IOUT = 0 A
VFB_ACC
Feedback voltage accuracy
Over the VIN range, VOUT = 1 V, IOUT = 0
A, fSW = 200 kHz
VFB
Load regulation
TA = 25°C, 0 A ≤ IOUT ≤ 3 A
0.1%
VFB
Line regulation
TA = 25°C, IOUT = 0 A, 4.0 V ≤ VIN ≤ 36 V
0.1%
IFB
Input current into the FB pin
VFB = 1.0 V
IOUT
Output current
TA = 25°C
IOCL
Output overcurrent (DC) limit threshold
IL_HS
High-side switch current limit
IL_LS
Low-side switch current limit
IL_NEG
Negative current limit
VHICCUP
Ratio of FB voltage to in-regulation FB voltage to
enter hiccup
–1%
+1%
10
nA
CURRENT
tW
0
2.0
3.8
Duty cycle approaches 0%
A
A
4.48
4.87
5.32
A
2.07
2.4
2.80
A
–3
Not during soft start
A
40%
Short circuit wait time ("hiccup" time before soft start)
80
(1)
ms
SOFT START
tSS
Time from first SW pulse to VREF at 90%
VIN ≥ 4.2 V
3.5
5
7
ms
tSS2
Time from first SW pulse to release of FPWM lockout
if the output not in regulation(1)
VIN ≥ 4.2 V
9.5
13
17
ms
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7.5 Electrical Characteristics (continued)
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, fSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
107%
110%
94%
96.5%
UNIT
POWER GOOD
PGOV
PG upper threshold — rising
% of VOUT setting
105%
PGUV
PG lower threshold — falling
% of VOUT setting
92%
PGHYS
PG upper threshold hysteresis (rising and falling)
% of VOUT setting
VIN_PG_VALID
Input voltage for valid PG output
46-μA pullup, VEN/SYNC = 0 V
VPG_LOW
Low level PG function output voltage
2-mA pullup to the PG pin, VEN/SYNC = 3.3
V
IPG
Input current into the PG pin when open-drain output
is high
VPG = 3.3 V
IOV
Pulldown current at the SW node under overvoltage
condition
tPG_FLT_RISE
Delay time to PG high signal
tPG_FLT_FALL
Glitch filter time constant for PG function
1.3%
1.0
V
0.4
1.5
V
10
nA
0.5
mA
2.0
2.5
120
ms
µs
SWITCHING FREQUENCY
fSW_RANGE
Switching frequency range by RT or SYNC
fSW_RT1
Default switching frequency by RT
RRT = 66.5 kΩ
200
fSW_RT2
Default switching frequency by RT
VIN = 12 V, RRT = 5.76 kΩ
2200
kHz
180
200
220
kHz
1980
2200
2420
kHz
SYNCHRONIZATION
VEN_SYNC
Edge amplitude necessary to sync using EN/SYNC
Rise and fall time < 30 ns
2.4
edges(1)
tB
Blanking of EN after rising or falling
tSYNC_EDGE
Enable sync signal hold time after edge for
edge recognition(1)
V
4
28
100
µs
ns
POWER STAGE
VBOOT_UVLO
Voltage on CBOOT pin compared to SW which will
turn off high-side switch
tON_MIN
Minimum ON pulse width(1)
tON_MAX
width(1)
tOFF_MIN
Maximum ON pulse
Minimum OFF pulse width
2.1
VOUT = 1 V, IOUT = 1 A, RBOOT shorted to
CBOOT
55
V
70
9
VIN = 4 V, IOUT = 1 A, RBOOT shorted to
CBOOT
ns
µs
65
85
ns
168
180
°C
THERMAL SHUTDOWN
TSDN
THYST
(1)
(2)
(3)
8
Thermal shutdown threshold (1)
Thermal shutdown
Temperature rising
hysteresis(1)
158
10
°C
Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
Production tested with VIN = 3 V.
This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total
input current to the system while regulating. For additional information, reference the Systems Characteristics and the Input Supply
Current sections.
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7.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. These specifications are not ensured by production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IIN
Input supply current when in
regulation
VIN = 24 V, VOUT = 3.3 V, VEN/SYNC = VIN, VVLDOIN = VOUT, fSW = 800
kHz, IOUT = 0 A
10
mA
OUTPUT VOLTAGE
VFB
Load regulation
VOUT = 3.3 V, VIN = 24 V, IOUT = 0.1 A to full load
1
mV
VFB
Line regulation
VOUT = 3.3 V, VIN = 4 V to 36 V, IOUT = 3 A
6
mV
VOUT
Load transient
VOUT = 3.3 V, VIN = 24 V, IOUT = 1 A to 2.5 A at 2 A/μs, COUT(derated) =
49 μF
50
mV
EFFICIENCY
η
Efficiency
VOUT = 3.3 V, VIN = 12 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 800 kHz
89.5%
VOUT = 3.3 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 800 kHz
87.5%
VOUT = 5 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 1 MHz
91%
VOUT = 5 V, VIN = 36 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 1 MHz
88.1%
VOUT = 12 V, VIN = 24 V, IOUT = 1.5 A, VLDOIN = VOUT, fSW = 2 MHz
94.1%
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7.7 Typical Characteristics
VIN = 24 V, unless otherwise specified
4
1.01
VIN = 3.3V
VIN = 36V
3
1.005
Feedback Voltage (V)
Shutdown Current (A)
TJ = -55C
TJ = 25C
TJ = 125C
2
1
0.995
1
0.99
-55
0
0
6
12
18
24
Input Voltage (V)
30
VEN/SYNC = 0 V
-15
70
MOSFET RDS(on) (m)
40
30
20
30
20
High-side MOSFET
Low-side MOSFET
10
-55
400
600
800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
115
1.2
110
1
105
PG Threshold (%)
1.4
0.8
0.6
0.4
VEN Rising
VEN Falling
VEN_WAKE Rising
VEN_WAKE Falling
0.2
-35
-15
5
25
45
65
Junction Temperature (C)
85
Figure 7-5. Enable Thresholds
105
125
-35
-15
5
25
45
65
Junction Temperature (C)
85
105
125
Figure 7-4. High-Side and Low-Side MOSFET
RDS(on)
Figure 7-3. Switching Frequency Set by the RT
Resistor
Enable Threshold Voltage (V)
125
40
10
10
105
50
50
0
-55
85
60
60
0
200
5
25
45
65
Junction Temperature (C)
Figure 7-2. Feedback Voltage
Figure 7-1. Shutdown Supply Current
RT Resistance (k)
-35
36
100
95
90
OV Tripping
OV Recovery
UV Recovery
UV Tripping
85
80
-55
-35
-15
5
25
45
65
Junction Temperature (C)
85
105
125
Figure 7-6. Power-Good (PG) Thresholds
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7.8 Typical Characteristics — 2-A Device (VIN = 12 V)
1.2
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
0.9
Power Dissipation (W)
Efficiency (%)
Refer to Section 9.2 for circuit designs.
0.6
0.3
0.0
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
0
0.25
0.5
VLDOIN = VOUT
1.5
1.75
2
VLDOIN = VOUT
Figure 7-7. Efficiency
Figure 7-8. Power Dissipation
115
20
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
16
105
95
Ambient Temperature (°C)
18
Output Voltage Ripple (mV)
0.75
1
1.25
Output Current (A)
14
12
10
85
75
65
55
45
8
35
6
Airflow
Nat Conv
25
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
Figure 7-9. Output Voltage Ripple
2
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
The device is soldered to a 64-mm × 83-mm, 4-layer PCB.
Figure 7-10. Safe Operating Area (All VOUT)
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7.9 Typical Characteristics — 2-A Device (VIN = 24 V)
Refer to Section 9.2 for circuit designs.
2.0
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.6
Power Dissipation (W)
Efficiency (%)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.2
0.8
0.4
0.0
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
0
0.25
0.5
VLDOIN = VOUT
2
Figure 7-12. Power Dissipation
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
23
20
105
95
Ambient Temperature (°C)
Output Voltage Ripple (mV)
1.75
115
26
17
14
85
75
65
55
45
Airflow
200LFM
100LFM
Nat conv
11
35
8
25
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
0
2
115
105
105
95
95
Ambient Temperature (°C)
115
85
75
65
55
0.75
1
1.25
Output Current (A)
1.5
1.75
2
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
0.5
Figure 7-14. Safe Operating Area (VOUT = 3.3 V)
Figure 7-13. Output Voltage Ripple
45
0.25
The device is soldered to a 64-mm × 83-mm, 4-layer PCB.
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
Ambient Temperature (°C)
1.5
VLDOIN = VOUT
Figure 7-11. Efficiency
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
25
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
The device is soldered to a 64-mm × 83-mm, 4-layer PCB.
Figure 7-15. Safe Operating Area (VOUT = 5.0 V)
12
0.75
1
1.25
Output Current (A)
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
The device is soldered to a 64-mm × 83-mm, 4-layer PCB.
Figure 7-16. Safe Operating Area (VOUT = 12 V)
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7.10 Typical Characteristics — 2-A Device (VIN = 36 V)
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
2.5
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.0
Power Dissipation (W)
Efficiency (%)
Refer to Section 9.2 for circuit designs.
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
1.5
1.0
0.5
0.0
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
0
0.25
0.5
VLDOIN = VOUT
1.75
2
Figure 7-18. Power Dissipation
115
32
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
28
105
95
Ambient Temperature (°C)
Output Voltage Ripple (mV)
1.5
VLDOIN = VOUT
Figure 7-17. Efficiency
24
20
16
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
12
35
8
25
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
0
2
115
105
105
95
95
Ambient Temperature (°C)
115
85
75
65
55
0.75
1
1.25
Output Current (A)
1.5
1.75
2
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
0.5
Figure 7-20. Safe Operating Area (VOUT = 3.3 V)
Figure 7-19. Output Voltage Ripple
45
0.25
The device is soldered to a 64-mm × 83-mm, 4-layer PCB.
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
Ambient Temperature (°C)
0.75
1
1.25
Output Current (A)
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
25
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
The device is soldered to a 64-mm × 83-mm, 4-layer PCB.
Figure 7-21. Safe Operating Area (VOUT = 5.0 V)
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
The device is soldered to a 64-mm × 83-mm, 4-layer PCB.
Figure 7-22. Safe Operating Area (VOUT = 12 V)
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8 Detailed Description
8.1 Overview
The TPSM63602 is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 36-V
supply voltage. The device is intended for step-down conversions from 5-V, 12-V, and 24-V supply rails. With an
integrated power controller, inductor, and MOSFETs, the TPSM63602 delivers up to 3-A DC load current with
high efficiency and ultra-low input quiescent current in a very small solution size. Although designed for simple
implementation, this device offers flexibility to optimize its usage according to the target application. Control-loop
compensation is not required, reducing design time and external component count.
With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal,
the TPSM63602 incorporates specific features to improve EMI performance in noise-sensitive applications:
• An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI.
• Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switchvoltage ringing, and radiated field coupling.
• Clock synchronization and FPWM mode enable constant switching frequency across the load current range.
• Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching.
• Adjustable switch-node slew rate allows optimization of EMI at higher frequency harmonics.
The TPSM63602 module also includes inherent protection features for robust system requirements:
•
•
An open-drain PGOOD indicator for power-rail sequencing and fault reporting
Precision enable input with hysteresis, providing:
– Programmable line undervoltage lockout (UVLO)
– Remote ON and OFF capability
Internally fixed output-voltage soft start with monotonic start-up into prebiased loads
Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
Thermal shutdown with automatic recovery
•
•
•
These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement
is designed for a simple layout, requiring few external components. See Section 11 for a layout example.
8.2 Functional Block Diagram
VLDOIN
RT
VIN
LDO bias
subregulator
Oscillator
RRT
VCC
CVCC
UVLO
SYNC
detect
RENT
Optional
external bias
(from VOUT)
OTP
VIN
VIN = 3 V to 36 V
Shutdown
logic
Precision
enable for
VIN UVLO
EN/SYNC
Enable
logic
RBOOT
100
RENB
PG
CBOOT
OCP
PGOOD
indicator
PGOOD
logic
SW
RFBT
To VOUT
sense point
Power
stage
and
control
logic
FB
UVLO
OTP
+
RFBB
VREF
OCP
Comp
2.2 µH
VOUT
CIN
VOUT = 1 V to 16 V
IOUT(max) = 2 A
Soft start
COUT
EN
PGND
Adjustable
output
variant only
14
AGND
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8.3 Feature Description
8.3.1 Input Voltage Range
With a steady-state input voltage range from 3 V to 36 V, the TPSM63602 module is intended for step-down
conversions from typical 12-V, 24-V, and 28-V input supply rails. The schematic circuit in Figure 8-1 shows all the
necessary components to implement a TPSM63602-based buck regulator using a single input supply.
VIN = 3 to 36 V
Precision
Enable UVLO
Optional
synchronization
SYNC
optional
VIN
VIN
CIN2
CIN1
PGND
RENT
TPSM63602
CSYNC
EN/SYNC
1 nF
PGND
VCC
RENB
CVCC
VLDOIN
Optional
VOUT = 1 to 16 V
external bias I
OUT(max) = 2 A
VOUT
VOUT
COUT
RPG
CBOOT
PGOOD
indicator
RRT
PG
RBOOT
RT
FB
AGND
PGND
RFBT
RFBB
Figure 8-1. TPSM63602 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V
Take extra care to make sure that the voltage at the VIN pins does not exceed the absolute maximum voltage
rating of 40 V during line or load transient events. Voltage ringing at the VIN pins that exceeds the absolute
maximum ratings can damage the IC.
8.3.2 Adjustable Output Voltage (FB)
The TPSM63602 has an adjustable output voltage range of 1 V to 16 V. Setting the output voltage requires two
resistors, RFBT and RFBB (see Figure 8-2). Connect RFBT between VOUT, at the regulation point, and the FB pin.
Connect RFBB between the FB pin and AGND (pin 10). The recommended value of RFBB is 10 kΩ. The value for
RFBT can be calculated using Equation 1. Table 8-1 lists the standard resistor values for several output voltages
and the recommended switching frequency. The minimum required output capacitance for each output voltage is
also included in Table 8-1. The capacitance values listed represent the effective capacitance, taking into account
the effects of DC bias and temperature variation.
(1)
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VOUT
RFBT
FB
RFBB
10 kΩ
AGND
Figure 8-2. FB Resistor Divider
Table 8-1. Standard RFBT Values, Recommended fSW and Minimum COUT
VOUT (V)
RFBT (kΩ)(1)
Recommended
fSW (kHz)
COUT(MIN) (µF)
(Effective)
VOUT (V)
RFBT (kΩ)(1)
Recommended
fSW (kHz)
COUT(MIN) (µF)
(Effective)
1.0
Short
400
300
3.3
23.2
800
40
1.2
2
500
200
5.0
40.2
1000
25
1.5
4.99
500
160
7.5
64.9
1300
20
1.8
8.06
600
120
10
90.9
1500
15
2.0
10
600
100
12
110
2000
5
2.5
15
750
65
15
140
2200
4
3.0
20
750
50
16
150
2200
3
(1)
RFBB = 10 kΩ
Note that higher feedback resistances consume less DC current, which is mandatory if light-load efficiency
is critical. However, RFBT larger than 1 MΩ is not recommended because the feedback path becomes more
susceptible to noise. High feedback resistance generally requires more careful layout of the feedback path. It is
important to keep the feedback trace as short as possible while keeping the feedback trace away from the noisy
area of the PCB. For more layout recommendations, see Section 11.
Fixed Output Voltage Variants
The TPSM63602V3 and TPSM63602V5 are the fixed output voltage variants of the module with 3.3-V and 5-V
fixed output voltages, respectively. In these variants, the resistor feedback dividers are located internal to the
module. Therefore, the FB pin can be connected directly to output voltage regulation point.
8.3.3 Input Capacitors
Input capacitors are required to limit the input ripple voltage to the module due to switching-frequency AC
currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over
a wide temperature range. Equation 2 gives the input capacitor RMS current. The highest input capacitor RMS
current occurs at D = 0.5, at which point, the RMS current rating of the capacitors must be greater than half the
output current.
ICIN,rms
§
2
D ˜ ¨ IOUT ˜ 1 D
¨
©
2
'IL ·
¸
12 ¸
¹
(2)
where
16
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D = VOUT / VIN is the module duty cycle.
Ideally, the DC and AC components of the input current to the buck stage are provided by the input voltage
source and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source
current of amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input
capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resulting
capacitive component of the AC ripple voltage is a triangular waveform. Together with the ESR-related ripple
component, Equation 3 gives the peak-to-peak ripple voltage amplitude.
IOUT ˜ D ˜ 1 D
'VIN
FSW ˜ CIN
IOUT ˜ RESR
(3)
Equation 4 gives the input capacitance required for a particular load current.
CIN t
D ˜ 1 D ˜ IOUT
FSW ˜ 'VIN RESR ˜ IOUT
(4)
where
•
ΔVIN is the input voltage ripple specification.
The TPSM63602 requires a minimum of 2 × 4.7-µF ceramic type input capacitance. Only use high-quality
ceramic type capacitors with sufficient voltage and temperature rating. The ceramic input capacitors provide a
low impedance source to the converter in addition to supplying the ripple current and isolating switching noise
from other circuits. Additional capacitance can be required for applications with transient load requirements. The
voltage rating of the input capacitors must be greater than the maximum input voltage. To compensate for the
derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing
multiple capacitors in parallel. Table 8-2 includes a preferred list of capacitors by vendor.
Table 8-2. Recommended Input Capacitors
Vendor(1)
Dielectric
Part Number
Case Size
TDK
X7R
C3216X7R1H475K160AC
Murata
X7R
GRM31CR71H475KA12L
TDK
X7R
Murata
X7S
(1)
(2)
Capacitor Characteristics
Voltage Rating (V)
Capacitance (µF)(2)
1206
50
4.7
1206
50
4.7
CGA6P3X7R1H475K250AB
1210
50
4.7
GCM31CC71H475KA03L
1206
50
4.7
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature.)
8.3.4 Output Capacitors
Table 8-1 lists the TPSM63602 minimum amount of required output capacitance. The effects of DC bias and
temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package
size, voltage rating, and dielectric material contribute to differences between the standard rated value and the
actual effective value of the capacitance.
When adding additional capacitance above COUT(MIN), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See Table 8-3 for a preferred list of output capacitors by vendor.
Table 8-3. Recommended Output Capacitors
Vendor(1)
Temperature
Coefficient
Part Number
Case Size
TDK
X7R
CGA5L1X7R1C106K160AC
Murata
X7R
TDK
X7R
Murata
X7S
GCJ31CC71E106KA15L
Capacitor Characteristics
Voltage (V)
Capacitance (µF)(2)
1206
16
10
GCM31CR71C106KA64L
1206
16
10
C3216X7R1E106K160AB
1206
25
10
1206
25
10
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Table 8-3. Recommended Output Capacitors (continued)
Temperature
Coefficient
Vendor(1)
(1)
(2)
Part Number
Case Size
Capacitor Characteristics
Voltage (V)
Capacitance (µF)(2)
Murata
X6S
GRM31CC81E226K
1206
25
22
Murata
X7R
GRM32ER71E226M
1210
25
22
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature.)
8.3.5 Switching Frequency (RT)
The switching frequency range of the TPSM63602 is 200 kHz to 2.2 MHz. The switching frequency can easily
be set by connecting a resistor (RRT) between the RT pin and AGND. Use Equation 5 to calculate the RRT value
for a desired frequency or simply select from Table 8-4. Note that a resistor value outside of the recommended
range can cause the device to shut down. This prevents unintended operation if the RT pin is shorted to ground
or left open. Do not apply a pulsed signal to this pin to force synchronization.
The switching frequency must be selected based on the output voltage setting of the device. See Table 8-4 for
RRT resistor values and the allowable output voltage range for a given switching frequency for common input
voltages.
(5)
Table 8-4. Switching Frequency Versus Output Voltage (IOUT = A)
VIN = 5 V
FSW (kHz) RRT (kΩ)
18
VIN = 12 V
VOUT Range (V)
VIN = 24 V
VOUT Range (V)
VIN = 36 V
VOUT Range (V)
VOUT Range (V)
Min
Max
Min
Max
Min
Max
Min
Max
200
66.5
1.0
2.0
1.0
2.0
1.0
1.5
1.0
1.5
400
33.2
1.0
3.0
1.0
4.0
1.0
3.3
1.2
3.0
600
22.1
1.0
3.5
1.0
6.0
1.5
6.0
1.8
5.0
800
16.5
1.0
3.5
1.0
7.0
1.5
9.0
2.5
7.0
1000
13.0
1.0
3.0
1.0
8.0
2.0
12.0
3.0
10.0
1200
10.7
1.0
3.0
1.5
9.0
2.5
13.0
3.5
14.0
1400
9.09
1.0
3.0
1.5
9.5
3.0
14.0
4.0
16.0
1600
8.06
1.0
3.0
1.5
9.0
3.0
15.0
4.5
16.0
1800
6.98
1.0
3.0
2.0
9.0
3.5
16.0
5.0
16.0
2000
6.34
1.2
2.5
2.0
9.0
4.0
16.0
5.5
16.0
2200
5.626
1.2
2.5
2.0
9.0
4.5
16.0
6.0
16.0
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8.3.6 Output ON and OFF Enable (EN/SYNC) and VIN UVLO
The EN/SYNC pin provides precision ON and OFF control for the TPSM63602. Once the EN/SYNC pin voltage
exceeds the threshold voltage and VIN is above the minimum turn-on threshold, the device starts operation. The
simplest way to enable the TPSM63602 is to connect EN/SYNC directly to VIN, allowing the TPSM63602 to start
up when VIN is within its valid operating range. However, many applications benefit from the employment of an
enable divider network as shown in Figure 8-3, which establishes a precision input undervoltage lockout (UVLO).
This can be used for sequencing, to prevent re-triggering the device when used with long input cables, or to
reduce the occurrence of deep discharge of a battery power source. An external logic signal can also be used to
drive the enable input to toggle the output on and off and for system sequencing or protection.
VIN
VIN
RENT
EN/SYNC
RENB
AGND
Figure 8-3. VIN UVLO Using the EN/SYNC Pin
RENB can be calculated using Equation 6.
(6)
where
•
•
•
RENT is 100 kΩ (typical).
VEN is 1.263 V (typical).
VIN(ON) is the desired start-up input voltage.
Note
The EN/SYNC pin can also be used as an external synchronization clock input. See Section 8.3.7 for
additional information. A blanking time of 4 µs to 28 µs is applied to the enable logic after a clock edge
is detected. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.
Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in
shutdown mode.
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8.3.7 Frequency Synchronization (EN/SYNC)
The TPSM63602 can be synchronized to an external clock using the EN/SYNC pin. The synchronization
frequency range is 200 kHz to 2.2 MHz. The internal oscillator can be synchronized by AC coupling a positive
clock edge into the EN/SYNC pin, as shown in Figure 8-4. It is recommended to keep the parallel combination
value of RENT and RENB in the 100-kΩ range. RENT is required for synchronization, but RENB can be left open.
The external clock must be off before start-up to allow proper start-up sequencing. After a valid synchronization
signal is applied for 2048 cycles, the clock frequency changes to that of the applied signal.
VIN
RENT
CSYNC
EN/SYNC
Clock
Source
RENB
AGND
AGND
Figure 8-4. Typical Synchronization Using the EN/SYNC Pin
Referring to Figure 8-5, the AC-coupled voltage edge at the EN/SYNC pin must exceed the SYNC amplitude
threshold, VEN_SYNC, of 2.4 V to trip the internal synchronization pulse detector. In addition, the minimum EN/
SYNC rising pulse and falling pulse durations must be longer than the SYNC signal hold time, tSYNC_EDGE, of
100 ns and shorter than the minimum blanking time, t B. A 3.3-V or higher amplitude pulse signal coupled through
a 1-nF capacitor, CSYNC, is suggested.
EN Voltage
VEN
tSYNC_EDGE
VEN_SYNC
0
VEN_SYNC
t
tSYNC_EDGE
Time
Figure 8-5. Typical SYNC Waveform
8.3.8 Power-Good Monitor (PG)
The TPSM63602 provides a PGOOD signal to indicate when the output voltage is within regulation. Use the
PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. The
PGOOD pin voltage goes low when the feedback voltage is outside of the PGOOD thresholds. This occurs
during the following:
•
•
•
•
While the device is disabled
In current limit
In thermal shutdown
During normal start-up, when the output voltage has not reach its regulation value
A glitch filter prevents false flag operation for short excursions (< 120 µs typical) of the output voltage, such as
during line and load transients.
20
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PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 20 V. The typical
range of pullup resistance is 10 kΩ to 100 kΩ. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is above 1 V (typical). Use the PG signal for start-up
sequencing of downstream regulators, as shown in Figure 8-6, or for fault protection and output monitoring.
VIN(on) = 13.9 V
VIN(off) = 10 V
VOUT2 = 3.3 V
VOUT1 = 5 V
RUV1
1 M
PG 13
14 EN/SYNC
RUV2
100 k
FB 10
RFB1
40.2 k
PG 13
RPG
100 k
14 EN/SYNC
FB 10
1V
RFB3
23.2 k
1V
RFB4
10 k
RFB2
10 k
Regulator #1
Start-up based on
input voltage UVLO
Regulator #2
Sequential start-up
based on PG
Figure 8-6. TPSM63602 Sequencing Implementation Using PG and EN/SYNC
8.3.9 Adjustable Switch-Node Slew Rate (RBOOT and CBOOT)
Adjust the switch-node slew rate of the TPSM63602 to slow the switch-node voltage rise time and improve EMI
performance at high frequencies. However, slowing the rise time decreases efficiency. Take care to balance the
improved EMI versus the decreased efficiency.
Internal to the device, a 100-Ω bootstrap resistor is connected between the RBOOT and CBOOT pins as shown
in Figure 8-7. Leaving these pins open incorporates the 100-Ω resistor into the BOOT circuit, slowing the SW
voltage slew rate and optimizing EMI. However, if improved EMI is not required, connecting RBOOT to CBOOT
shorts the internal resistor, resulting in higher efficiency. Placing a resistor across RBOOT and CBOOT allows
adjustment of the internal resistor to balance EMI and efficiency.
VCC
7
CVCC
1 µF
Power
MOSFET
gate drivers
4
RBOOT
3
CBOOT
2
SW
RBOOT
100 Ω
CBOOT
100 nF
Figure 8-7. Internal BOOT Resistor
8.3.10 Internal LDO, VCC Output, and VLDOIN Input
The TPSM63602 has an internal LDO to power internal circuitry. The VCC pin is the output of the internal LDO.
This pin must not be used to power external circuitry. Connect a high-quality, 1-μF capacitor from this pin to
AGND, close to the device pins. Do not load the VCC pin or short it to ground.
The VLDOIN pin is an optional input to the internal LDO. Connect an optional high quality 0.1-µF to 1-µF
capacitor from this pin to ground for improved noise immunity.
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The LDO generates the VCC voltage from one of the two inputs: VIN or the VLDOIN input. When VLDOIN is tied
to ground or below 3.1 V, the LDO is powered from VIN. When VLDOIN is tied to a voltage higher than 3.1 V, the
LDO input is powered from VLDOIN. VLDOIN voltage must be lower than both VIN and 12.5 V.
The VLDOIN input is designed to reduce the LDO power loss. The LDO power loss is:
PLDO-LOSS = ILDO × (VIN_LDO – VVCC)
(7)
The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the
same LDO output current. The VLDOIN input provides an option to supply the LDO with a lower voltage than
VIN, to reduce the difference of the input and output voltages of the LDO, and reduce power loss. For example, if
the LDO current were 10 mA at a certain frequency with VIN = 24 V and VOUT = 5 V. The LDO loss with VLDOIN
tied to ground is:
10 mA × (24 V – 3.3 V) = 207 mW
(8)
The loss with VLDOIN tied to VOUT (5 V) is:
10 mA × (5 V – 3.3 V) = 17 mW
(9)
The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher
percentage of the total loss. The improvement is more significant with higher switching frequency because
the LDO current is higher at higher switching frequency. The improvement is more significant when VIN » VOUT
because the voltage difference is higher.
Efficiency (%)
Figure 8-8 and Figure 8-9 show typical efficiency waveforms with VLDOIN powered by different input voltages.
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
VLDOIN
3.3V
5V
GND
0
0.5
1
1.5
2
Output Current (A)
VIN = 24 V
VOUT = 5 V
fSW = 1 MHz
ILDO = 10 mA
Figure 8-8. Efficiency Improvements with VLDOIN (VOUT = 5 V)
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Efficiency (%)
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100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
VLDOIN
3.3V
5V
12V
GND
0
0.5
1
1.5
2
2.5
3
Output Current (A)
VIN = 24 V
VOUT = 12 V
fSW = 2 MHz
ILDO = 20 mA
Figure 8-9. Efficiency Improvements with VLDOIN (VOUT = 12 V)
8.3.11 Overcurrent Protection (OCP)
The TPSM63602 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak
inductor current. The current is compared every switching cycle to the current limit threshold. During an
overcurrent condition, the output voltage decreases.
The TPSM63602 employs hiccup overcurrent protection if there is an extreme overload. In hiccup mode, the
regulator is shut down and kept off for 80 ms (typical) before the TPSM63602 tries to start again. If an
overcurrent or short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup
mode reduces power dissipation under severe overcurrent conditions and prevents overheating and potential
damage to the device. Once the fault is removed, the module automatically recovers and returns to normal
operation.
8.3.12 Thermal Shutdown
Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related
to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 168°C (typical) to
prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
TPSM63602 attempts to restart when the junction temperature falls to 158°C (typical).
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN/SYNC pin provides ON and OFF control for the TPSM63602. When VEN/SYNC is below approximately 0.4
V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The input quiescent
current in shutdown mode drops to 0.6 µA (typical). The TPSM63602 also employs internal undervoltage
protection. If the input voltage is below its UV threshold, the regulator remains off.
8.4.2 Standby Mode
The internal LDO has a lower enable threshold than the regulator itself. When VEN/SYNC is above 1.1 V
(maximum) and below the precision enable threshold of 1.263 V (typical), the internal LDO is on and regulating.
The precision enable circuitry is turned on once the internal VCC is above its UVLO threshold. The switching
action and voltage regulation are not enabled until VEN/SYNC rises above the precision enable threshold.
8.4.3 Active Mode
The TPSM63602 is in active mode when VIN and VEN/SYNC are above their relevant thresholds and no fault
conditions are present. The simplest way to enable the operation is to connect the EN/SYNC pin to VIN, which
allows self-start–up when the applied input voltage exceeds the minimum start-up voltage.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPSM63602 only requires a few external components to convert from a wide range of supply voltages
to a fixed output voltage. The following section describes the design procedure to configure the TPSM63602
power module. To expedite and streamline the design process, WEBENCH® online software is available to
generate complete designs, leveraging iterative design procedures and access to comprehensive component
databases. To expedite and streamline the design process for a TPSM63602-based regulator, a comprehensive
TPSM63602 quickstart calculator.
As mentioned previously, the TPSM63602 also integrates several optional features to meet system design
requirements, including the following:
•
•
•
•
Precision enable with hysteresis
External adjustable UVLO
Adjustable SW node slew rate
A power-good indicator
The following application circuits show the TPSM63602 configuration options suitable for several application use
cases. Refer to the TPSM63603EVM User's Guide for more detail.
9.2 Typical Applications
The following designs show sample typical applications and design procedures to implement the TPSM63602.
9.2.1 Design 1 — 2-A Synchronous Buck Regulator for Industrial Applications
Figure 9-1 shows the schematic diagram of a 5-V, 2-A buck regulator with a switching frequency of 1 MHz.
The nominal input voltage for the sample design is 24 V. A 13-kΩ RRT resistor sets the free-running switching
frequency at 1 MHz. An optional SYNC input signal allows adjustment of the switching frequency for this specific
application.
VIN = 24 V
VIN(on) = 6 V
VIN(off) = 4.3 V
Optional
synchronization
SYNC
optional
VIN
VIN
CIN2
CIN1
4.7 F
RENT
374 k
PGND
TPSM63602
CSYNC
EN/SYNC
1 nF
RENB
100 k
PGND
4.7 F
VCC
CVCC
100 k
PGOOD
indicator
RRT
13 k
Optional
external bias
CBOOT
PG
RBOOT
RT
FB
AGND
VOUT = 5 V
IOUT(max) = 2 A
VOUT
VOUT
1 F
RPG
VLDOIN
PGND
COUT
2
RFBT
40.2 k
47 F
RFBB
10 k
Figure 9-1. Circuit Schematic
24
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9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters and follow the design
procedures in Section 9.2.1.2.
Table 9-1. Design Example Parameters
Design Parameter
Value
Input voltage
24 V
Output voltage
5V
Output current
0 A to 2 A
Switching frequency
1 MHz
Table 9-2 gives the selected buck module power-stage components with availability from multiple vendors. This
design uses an all-ceramic output capacitor implementation.
Table 9-2. List of Materials for Application Circuit 1
Reference
Designator
CIN1, CIN2
Qty
2
Specification
4.7 µF, 50 V, X7R, 1210, ceramic
2
CVCC
1
U1
1
(1)
Part Number
Taiyo Yuden
UMK325B7475KN-TR
TDK
CGA6P3X7R1H475K250AB
Murata
GRM31CC72A475KE11L
Murata
GRM32ER71A476ME15L
AVX
1210ZC476MAT2A
1 µF, 16 V, X7R, 0603, ceramic
Murata
GCM188R71C105KA64J
1 µF, 16 V, X5R, 0402, ceramic
Taiyo Yuden
EMK105BJ105KVHF
TPSM63602 36-V, 2-A synchronous buck module
Texas Instruments
TPSM63602RDLR
4.7 µF, 100 V, X7S, 1206, ceramic
COUT1, COUT2
Manufacturer(1)
47 µF, 10 V, X7R, 1210, ceramic
See the Third-Party Products Disclaimer.
More generally, the TPSM63602 module is designed to operate with a wide range of external components
and system parameters. However, the integrated loop compensation is optimized for a certain range of output
capacitance.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM63602 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Output Voltage Setpoint
The output voltage of the TPSM63602 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10 kΩ. The value for RFBB can be selected from Table 8-1 or calculated using Equation 10:
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(10)
For the desired output voltage of 5 V, the formula yields a value of 40.2 kΩ. Choose the closest available
standard value of 40.2 kΩ for RFBT.
9.2.1.2.3 Switching Frequency Selection
The recommended switching frequency for standard output voltages can be found in Table 8-1. For a 5-V output,
the recommended switching frequency is 1 MHz. To set the switching frequency to 1 MHz, connect a 13.0-kΩ
resistor between the RT pin and AGND.
9.2.1.2.4 Input Capacitor Selection
The TPSM63602 requires a minimum input capacitance of 2 × 4.7-µF ceramic type. High-quality ceramic type
capacitors with sufficient voltage and temperature rating are required. The voltage rating of input capacitors must
be greater than the maximum input voltage.
For this design, select two 4.7-µF, 50-V, 1210 case size, ceramic capacitors.
9.2.1.2.5 Output Capacitor Selection
For a 5-V output, the TPSM63602 requires a minimum of 25 µF of effective output capacitance for proper
operation (see Table 8-1). High-quality ceramic type capacitors with sufficient voltage and temperature rating are
required. Additional output capacitance can be added to reduce ripple voltage or for applications with transient
load requirements.
For this design example, select two 47-µF, 10-V, 1210 case size, ceramic capacitors, which have a total effective
capacitance of approximately 48 µF at 5 V.
9.2.1.2.6 Other Connections
•
•
•
26
Short RBOOT to CBOOT for best efficiency.
Connect VLDOIN to VOUT to improve efficiency.
Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.
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9.2.1.3 Application Curves
Unless otherwise indicated, VIN = 24 V, VOUT = 5 V, IOUT = 2 A), and fSW = 1 MHz
VIN (20 V/DIV)
VIN (20 V/DIV)
EN (5 V/DIV)
EN (5 V/DIV)
VOUT (5 V/DIV)
VOUT (5 V/DIV)
PG (5 V/DIV)
PG (5 V/DIV)
500 µs/DIV
2 ms/DIV
VIN = 24 V
VIN = 24 V
VOUT = 5 V
VOUT = 5 V
Figure 9-3. Shutdown Waveforms
Figure 9-2. Start-Up Waveforms
VOUT (200 mV/DIV)
VOUT (200 mV/DIV)
5V
5V
IOUT (1 A/DIV)
IOUT (2 A/DIV)
50 µs/DIV
VIN = 24 V
VOUT = 5 V
50 µs/DIV
fSW = 1 MHz
COUT = 2 × 47 µF
Figure 9-4. Load Transient, 0 A to 2 A, 1 A/µs
VIN = 24 V
VOUT = 5 V
fSW = 1 MHz
COUT = 2 × 47 µF
Figure 9-5. Load Transient, 1 A to 2 A, 1 A/µs
VOUT (100 mV/DIV)
VOUT (100 mV/DIV)
3.3V
3.3V
IOUT (1 A/DIV)
IOUT (1 A/DIV)
50 µs/DIV
50 µs/DIV
VIN = 24 V
VOUT = 3.3 V
fSW = 1 MHz
COUT = 2 × 47 µF
Figure 9-6. Load Transient, 0 A to 2 A, 1 A/µs
VIN = 24 V
VOUT = 3.3 V
fSW = 1 MHz
COUT = 2 × 47 µF
Figure 9-7. Load Transient, 1 A to 2 A, 1 A/µs
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Figure 9-8. Thermal Image, VIN = 12 V, VOUT = 3.3 V,
fSW = 1 MHz, IOUT = 2 A
Figure 9-9. Thermal Image, VIN = 12 V, VOUT = 5 V,
fSW = 1 MHz, IOUT = 2 A
Figure 9-10. Thermal Image, VIN = 24 V, VOUT = 3.3
V, fSW = 1 MHz, IOUT = 2 A
Figure 9-11. Thermal Image, VIN = 24 V, VOUT = 5 V,
fSW = 1 MHz, IOUT = 2 A
28
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9.2.2 Design 2 — Inverting Buck-Boost Regulator with a –5-V Output
Figure 9-12 shows the schematic diagram of a –5-V inverting buck-boost regulator with a switching frequency of
1 MHz. The input voltage range for the sample design is 12 V to 24 V.
VIN+
VIN = 12 V to 24 V
CIN3
10 F
VIN
VIN(on) = 8.9 V
4.7 F
RENT
604 k
VIN–
VIN
CIN1
CIN2
PGND
–VOUT
PGND
–VOUT
TPSM63602
EN/SYNC
Optional
external bias
VLDOIN
VCC
RENB
100 k
4.7 F
VOUT
CVCC
VOUT
1 F
CBOOT
RBOOT
PG
RT
RRT
13 k
RFBT
40.2 k
FB
AGND
COUT
2 47 F
VOUT–
Optional
Schottky
Diode
–VOUT
RFBB
10 k
PGND
VOUT = –5 V
IOUT(max) = –1 A
–VOUT
Figure 9-12. Circuit Schematic
9.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-3 as the input parameters and follow the design
procedures in Section 9.2.2.2.
Table 9-3. Design Example Parameters
Design Parameter
Value
Input voltage
12 to 24 V
Output voltage
–5 V
Output current
0 A to 1 A
Switching frequency
1 MHz
Table 9-4 gives the selected module power-stage components with availability from multiple vendors. This
design uses an all-ceramic output capacitor implementation.
Table 9-4. List of Materials for Application Circuit 2
Reference
Designator
Qty
CIN1, CIN2, CIN3
3
Specification
4.7 µF, 50 V, X7R, 1210, ceramic
4.7 µF, 50 V, X7S, 1206, ceramic
Manufacturer(1)
Part Number
Taiyo Yuden
UMK325B7475KN-TR
TDK
CGA6P3X7R1H475K250AB
Murata
GCM31CC71H475KA03K
Murata
GRM32ER71A476ME15L
COUT1, COUT2
2
47 µF, 10 V, X7R, 1210, ceramic
AVX
1210ZC476MAT2A
CVCC
1
1 µF, 16 V, X7R, 0603, ceramic
Murata
GCM188R71C105KA64J
U1
1
TPSM63602 36-V, 2-A synchronous buck module
Texas Instruments
TPSM63602RDLR
More generally, the TPSM63602 module is designed to operate with a wide range of external components
and system parameters. However, the integrated loop compensation is optimized for a certain range of output
capacitance.
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9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Output Voltage Setpoint
The output voltage of the TPSM63602 device is externally adjustable using a resistor divider. The recommended
value of RFBB is 10 kΩ. Calculate the value for RFBT using Equation 11.
(11)
For the desired output voltage of –5 V, enter the absolute value of 5 V for VOUT in Equation 11. The formula
yields a value of 40.2 kΩ. Choose the closest available standard value of 40.2 kΩ for RFBT.
9.2.2.2.2 IBB Maximum Output Current
The achievable output current with an IBB topology using the TPSM63602 is:
IOUT(max) = ILDC(max) × (1 – D)
(12)
where
•
•
ILDC(max) = 2 A is the rated current of the module.
D = |VOUT| / (VIN + |VOUT|) is the module duty cycle.
Therefore, in the case of VIN = 12 V and VOUT = –5 V, the maximum output current is 1.4 A.
9.2.2.2.3 Switching Frequency Selection
To set the switching frequency to 1 MHz, connect a 13.0-kΩ resistor between the RT pin and AGND pins of the
module based on Equation 5.
9.2.2.2.4 Input Capacitor Selection
The TPSM63602 requires a minimum input capacitance of 2 × 4.7-µF ceramic type between the VIN pins and
PGND pins as close as possible to the module. High-quality ceramic type capacitors with sufficient voltage and
temperature rating are required. In an inverting buck-boost configuration, the maximum voltage between VIN and
PGND pin of the module is equal to VIN + |VOUT|.
For this design, two 4.7-µF, 50-V, 1210 case size, ceramic capacitors are selected.
9.2.2.2.5 Output Capacitor Selection
The TPSM63602 requires a minimum of 25 µF of effective output capacitance for proper operation. Highquality ceramic type capacitors with sufficient voltage and temperature rating are required. Additional output
capacitance can be added to reduce ripple voltage or for applications with transient load requirements.
For this design example, two 47-µF, 10-V, 1210 case size, ceramic capacitors are used, which have a total
effective capacitance of approximately 48 µF at 5 V.
9.2.2.2.6 Other Connections
Short RBOOT to CBOOT and connect VLDOIN to VOUT for the best efficiency.
Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.
The right-half-plane zero of an IBB topology is at its lowest frequency at minimum input voltage. However, it does
not appear at low frequency for a –5-V output and has minimal effect on the loop response for this application.
In an inverting buck-boost configuration, the input capacitor, CIN, and output capacitor, COUT, can form an AC
capacitive divider during a fast VIN transient or hot-plugged event at the input. This event will result in a positive
voltage spike at the output that can disturb the load. In this case, an optional Schottky diode can be installed
between –VOUT and GND as shown in Figure 9-12 to clamp the output spike.
30
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9.2.2.2.7 EMI
The TPSM63602 is compliant with EN55011 radiated emissions. Figure 9-13, Figure 9-14, and Figure 9-15 show
typical examples of radiated emission plots for the TPSM63603 , which is in the same family of parts. The
graphs include the plots of the antenna in the horizontal and vertical positions.
9.2.2.2.7.1 EMI Plots
EMI plots were measured using the standard TPSM63603EVM.
Figure 9-13. Radiated Emissions, 24-V Input, 5-V Output, 3-A Load
Figure 9-14. Radiated Emissions, 24-V Input, 5-V Output, 3-A Load, Spread Spectrum
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Figure 9-15. Radiated Emissions, 24-V Input, 3.3-V Output, 3-A Load
10 Power Supply Recommendations
The TPSM63602 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded regulator circuit. Estimate the average input current with Equation 13.
IIN
VOUT ˜ IOUT
VIN ˜ K
(13)
where
•
η is efficiency.
If the module is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the
low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage
transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input
voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can
cause false UVLO triggering and a system reset.
The best way to solve such issues is to reduce the distance from the input supply to the module and use an
electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps
damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range
of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady
during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit
configurations.
32
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11 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal
thermal performance, and minimal generation of unwanted EMI.
11.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 11-1 and
Figure 11-2 show a typical PCB layout. Some considerations for an optimized layout are:
•
•
•
•
•
•
Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
Place ceramic input and output capacitors close to the device pins to minimize high-frequency noise.
Locate additional output capacitors between the ceramic capacitors and the load.
Connect AGND to PGND at a single point.
Place RFBT and RFBB as close as possible to the FB pin.
Use multiple vias to connect the power planes to internal layers.
11.2 Layout Example
Figure 11-1. Typical Top-Layer Layout
Figure 11-2. Typical Top Layer
11.2.1 Package Specifications
Table 11-1. Package Specifications Table
TPSM63602
Weight
Flammability
Meets UL 94 V-0
MTBF calculated reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
Value
Unit
123
mg
84
MHrs
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
With an input operating voltage from 3 V to 36 V and rated output current from 2 A to 6 A, the TPSM63602,
TPSM63603, TPSM63604, and TPSM63606 family of synchronous buck power modules specified in Table 12-1
provides flexibility, scalability and optimized solution size for a range of applications. These modules enable
DC/DC solutions with high density, low EMI and increased flexibility. Available EMI mitigation features include
pseudo-random spread spectrum (PRSS), RBOOT-configured switch-node slew rate control, and integrated
input bypass capacitors. All modules are rated for an ambient temperature up to 105°C.
Table 12-1. Synchronous Buck DC/DC Power Module Family
DC/DC Module
Rated IOUT
TPSM63602
2A
TPSM63603
3A
TPSM63604
4A
TPSM63606
6A
Package
Dimensions
B0QFN (30)
4.0 × 6.0 × 1.8 mm
Features
RT adjustable fSW,
external synchronization
B3QFN (20)
5.0 × 5.5 × 4.0 mm
EMI Mitigation
PRSS, RBOOT, integrated
input and BOOT capacitors
PRSS, RBOOT, integrated
input, VCC and BOOT
capacitors
For development support, see the following:
•
•
•
•
•
•
•
•
•
•
•
TPSM63602 Quickstart Calculator
TPSM63602 Simulation Models
TPSM63603 and TPSM63603S EVM User's Guide
TPSM63603 Altium Layout Design Files
For TI's reference design library, visit the TI Reference Design library.
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
To design a low-EMI power supply, review TI's comprehensive EMI Training Series.
To design an inverting buck-boost (IBB) regulator, visit DC/DC inverting buck-boost modules.
TI Reference Designs:
– Multiple Output Power Solution For Kintex 7 Application
– Arria V Power Reference Design
– Altera Cyclone V SoC Power Supply Reference Design
– Space-optimized DC/DC Inverting Power Module Reference Design With Minimal BOM Count
– 3- To 11.5-VIN, –5-VOUT, 1.5-A Inverting Power Module Reference Design For Small, Low-noise Systems
Technical Articles:
– Powering Medical Imaging Applications With DC/DC Buck Converters
– How To Create A Programmable Output Inverting Buck-boost Regulator
To view a related device of this product, see the LM61460 36-V, 6-A synchronous buck converter.
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM63602 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
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In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
•
•
•
•
•
•
•
•
•
Texas Instruments, Innovative DC/DC Power Modules selection guide
Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package
Technology white paper
Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper
Texas Instruments, Simplify Low EMI Design with Power Modules white paper
Texas Instruments, Power Modules for Lab Instrumentation white paper
Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
Texas Instruments, Soldering Considerations for Power Modules application report
Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report
Texas Instruments, Using New Thermal Metrics application report
Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
Texas Instruments, Using the TPSM53602, TPSM53603, and TPSM53604 for Negative Output Inverting
Buck-Boost Applications application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPSM63602RDHR
ACTIVE
B0QFN
RDH
30
3000
RoHS Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
63602
Samples
TPSM63602V3RDHR
ACTIVE
B0QFN
RDH
30
3000
RoHS Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
63602V3
Samples
TPSM63602V5RDHR
ACTIVE
B0QFN
RDH
30
3000
RoHS Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
63602V5
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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