TRF1115IRGPR

TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 2.5-GHz, High Dynamic Range, Low-Noise Down-Converter FEATURES • • • • • • 20 19 18 17 16 RFAGC MXRPB TRF1115 (TOP VIEW) MXRI • DEVICE INFORMATION GND • • Performs First Down-Conversion in MMDS / WCS Radio 2300 MHz to 2700 MHz Integrated Low Noise, Variable Gain Amplifier Provisions For An External Image Reject / Band Pass Filter Differential Mixer Provides Extra Noise Immunity Integrated LO Buffer Amplifier 20 dB of Gain With 10 dB of Gain Control 3-dB Noise Figure, Typical Input Third Order Intercept of 0 dBm, Typical Input P-1 dB of –5 dBm, Typical LO Input Power: 3 dBm RXI • GND 1 15 GND GND 2 14 IFOP LNAO 3 13 IFON RES 4 12 GND LOB 5 11 IFB In order to provide exceptional image rejection and extra jammer rejection, the TRF1115 offers a signal path to an off-chip filter. Specifications are provided assuming an in-band 1.5-dB loss in this filter. The TRF1115 includes a differential LO buffer, mixer, and IF amplifier for improved performance. After the filter, an on-chip balun converts the signal from single-ended to differential in order to provide better noise immunity in the mixer. 6 7 8 9 10 LOP LON VDD VDD The TRF1115 is the first of two ASICs used in the receiver section of Texas Instruments MMDS/MDS/WCS/802.16x chipset. The TRF1115 down-converts the input frequency to an IF frequency in the range of 420 MHz to 480 MHz. The device provides a differential output that passes through a SAW filter before connecting to a second down converter chip. (Note: For the best performance, the Texas Instruments TRF1112 should be used to perform both the second down conversion and provide the local oscillator for the TRF1115.) GND DESCRIPTION P0031-03 Figure 1. TRF1115 Pin Out BPF LNAO LNA Mixer RXI VGM MXRI VGA IFOP IFON BALUN Power Supply LOP LON VDD RFAGC AGC LO Buffer B0084-03 Figure 2. Block Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 ABSOLUTE MAXIMUM RATINGS VALUE VDD Positive DC Supply Voltage, VDD IDD Current consumption Pin RF Input Power TJ Pd UNIT 0.0 to +5.5 V 200 mA 5 dBm Junction Temperature 200 °C Power Dissipation 1.1 W Digital Input Pins –0.3 to 5.5 θJC Thermal Resistance Junction to Case (1) 9.1 °C/W Tstg Storage Temperature –40 to 105 °C Top Operating Temperature –40 to 85 °C 260 °C Lead Temperature (40 sec max) (1) Thermal resistance is junction to ambient assuming thermal pad with 16 thermal vias under package metal base. See Recommended PCB layout. DC SPECIFICATIONS PARAMETER 2 TEST CONDITIONS MIN TYP MAX 5 5.25 V 130 180 mA VDD Supply Voltage IDD Supply Current (Total) ILNA Supply Current, LNA, pin 3 ILO Supply Current, LO, pin 9 IIF Supply Current, IF VC Gain Control Voltage 0 2 IC Gain Control Current 0 1.2 Pins 10 plus IF drain bias on pins 13 and 14. Submit Documentation Feedback UNIT 30 mA 45 mA 55 mA V mA TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS Unless otherwise stated VDD = 5.0 V, External Filter loss = 1.5 dB, TA = 25°C MAX UNIT fRF RF input frequency PARAMETER TEST CONDITIONS 2300 MIN TYP 2700 MHz fLO LO input frequency 1820 2220 MHz fIF IF output frequency 500 MHz G Gain VC = 0 V Gain control range VC > 1.5 V 400 480 16 18 dB 10 dB GNB Gaub fkatbess / 6 MHz 0.2 dB NFHG Noise figure, high gain VC = 0 V 3 4 dB NFLG Noise figure with AGC on VC > 1.5 V 6 7 dB IP-1dB Input power at 1 dB compression, high gain VC = 0 V, Without RF BPF -6 -2 dBm IP-1dB Input power at 1 dB compression with AGC on VC > 1.5 V, Without RF BPF -1 2 dBm IIP3 Input third order intercept point, high gain VC = 0 V, Without RF BPF -3 0 dBm IIP3 Input third order intercept point with AGC on VC > 1.5 V, Without RF BPF 5 8 dBm ZRF RF input impedance Differential 50 Ω RLRF RF input return loss Z = 50 Ω, PLO = 3 dBm, FRF = 2500 to 2700 MHz 10 dB ZLO LO input impedance Differential PLO LO input power Referenced to 100 Ω differential RLLO LO input return loss Differential, with external matching circuit. LO input = 3 dBm ZIF IF output impedance Differential RLIF IF1 output return loss Differential, with external matching circuit –7 –10 dB LO to RF leakage, differential LO input = 3 dBm, VC = 0 V –35 –45 dBm LO to IF1 leakage, differential LO input = 3 dBm, VC = 0 V –40 –50 dBm RF to IF1 isolation, differential LO input = 3 dBm, VC = 0 V 35 45 dBc RF to LO insolation, differential LO input = 3 dBm, VC = 0 V 25 dBc 8 Ω 100 0 3 6 dB –10 –12 dB 100 Ω TERMINAL FUNCTIONS TERMINAL NO. NAME I/O TYPE DESCRIPTION 1, 2, 6, 12, 15, 19 GND 3 LNAO 4 RES Reserved. Do not connect or ground this pin. 5 LOB Not connected for normal operation. Internal bias for LO buffer. Normal voltage at this pin is 3.0 to 3.2 V. Do not ground this pin or connect. 7 LOP I Analog LO input, Positive, ac coupled internally 8 LON I Analog LO input, Negative, ac coupled internally Ground O Analog/P Output of LNA, before mixer, Also provides DC bias to FET. Apply 5 V bias thru bias ower network. 9 VDD I Power DC bias for LO Buffer +5 V 10 VDD I Power DC bias for IF circuit +5 V 11 IFB 13 IFON O Analog/P IF output, negative, and dc bias for IF amplifier. Apply +5 V through bias network. ower 14 IFOP O Analog/P IF output, Positive, and dc bias for IF amplifier. Apply +5 V through bias network. ower Not connected for normal operation. Internal bias for IF circuitry Normal voltage at this pin is 2.8 to 3.0 V. Do not ground this pin or connect. Submit Documentation Feedback 3 TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 TERMINAL FUNCTIONS (continued) TERMINAL NO. NAME I/O TYPE I Analog DESCRIPTION Input voltage for gain control: VC = 0 to 1.5 V Maximum gain at VC = 0 V Minimum gain at VC = 1.5 V 16 RFAGC 17 MXRPB 18 MXRI I Analog Input to RF mixer, ac coupled, 50 Ω 20 RXI I Analog RF input, ac coupled, 50 Ω Back GND Not connected for normal operation. Internal bias for mixer circuitry. Normal voltage at this pin is 1.8 V to 2.5 V. Do not ground this pin or connect to any other pin. Back of package has metal base that must be grounded for thermal and RF performance. TYPICAL CHARACTERISTICS TYPICAL DATA GAIN vs FREQUENCY AND CONTROL VOLTAGE AT 25°C NOISE FIGURE vs FREQUENCY AND CONTROL VOLTAGE AT 25°C 25 7 NF with Vc = 1.5 V Gain at Vc = 0 V 6 20 5 Noise Figure − dB Gain − dB Gain at Vc = 0.5 V 15 Gain at Vc = 1 V 10 Gain at Vc = 1.5 V 4 3 NF with Vc = 0 V NF with Vc = 1 V 2 NF with Vc = 0.5 V 5 1 0 2300 2350 2400 2450 2500 2550 2600 2650 2700 0 2300 2350 2400 2450 2500 2550 2600 2650 2700 f − Frequency − MHz f − Frequency − MHz G001 Figure 3. 4 G002 Figure 4. Submit Documentation Feedback TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) INPUT IP3 vs FREQUENCY AND CONTROL VOLTAGE AT 25°C 10 10 5 5 Input IP3 − dBm Input P−1dB at Vc = 1.5 V 0 Input P−1dB at Vc = 1 V −5 Input IP3 at Vc = 1.5 V 0 Input IP3 at Vc = 0 V −5 Input IP3 at Vc = 1 V Input IP3 at Vc = 0.5 V −10 −10 Input P−1dB at Vc = 0.5 V Input P−1dB at Vc = 0 V −15 2300 2350 2400 2450 2500 2550 2600 2650 2700 −15 2300 2350 2400 2450 2500 2550 2600 2650 2700 f − Frequency − MHz f − Frequency − MHz G003 G004 Figure 5. Figure 6. RF AND LO RETURN LOSS AT 25°C 0 −5 RF Return Loss −10 Return Loss − dB Input P−12dB − dBm INPUT P-1dB vs FREQUENCY AND CONTROL VOLTAGE AT 25°C −15 LO Return Loss −20 −25 −30 −35 −40 2.31 2.36 2.41 2.46 2.51 2.56 2.61 2.66 2.71 f − Frequency − MHz G005 Figure 7. Submit Documentation Feedback 5 TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 RECOMMENDED PCB LAYOUT 2.00 0.50 TYP 0.20 TYP 0.60 TYP PIN 1 1.00 TYP 2.80 2.00 1.00 TYP DIA 0.38 TYP 0.25 TYP 2.80 Solder Mask. No Solder Mask Under Chip, On Lead Pads or On Ground Connections. Notes: 9 Via Holes, Each 0.38 mm. DIMENSIONS in mm M0022-04 A. 6 Four layer Board, Starting material: two: 10 mil core FR4 with 1 oz copper, both sides, pressed with 8 mil thick prepreg. Via plating ½ oz copper plate, final plate White immersion tin. Final thickness: 0.033” to 0.037” thick. Submit Documentation Feedback TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 APPLICATION SCHEMATIC 1 P2 P1 G G 2 4 Z = 50 W 3 Z = 50 W RF_IN Vc 10 pF (1) L = 23.9 nH 22 nH Quarter-wave @ Frf 5 10 pF IFN RES GND LOB IFB LOP 15 10 pF 14 13 7 8 9 0.01 mF 270 nH 22 nH (2) IF OUT_NEG 12 11 0.01 mF 6 LO_POS RFAGC LNAO GND VDD IFP GND VDD VDD 4 270 nH GND VDD 3 IF OUT_POS 16 GND LON 2 17 MXRPB GND Back 1 18 MXRI 19 RXI Z = 50 W 20 (2) VDD 10 10 pF 0.01 mF 10 pF 0.01 mF LO_NEG S0122-02 Submit Documentation Feedback 7 TRF1115 www.ti.com SLWS174B – APRIL 2005 – REVISED SEPTEMBER 2006 APPLICATION INFORMATION Figure 8. Package Outline: 4 mm x 4 mm LPCC 20-Pin Leadless Package 8 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TRF1115IRGPR ACTIVE QFN RGP 20 TBD Call TI Call TI TRF 1115 TRF1115IRGPRG3 ACTIVE QFN RGP 20 TBD Call TI Call TI TRF 1115 TRF1115IRGPT ACTIVE QFN RGP 20 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TRF 1115 TRF1115IRGPTG3 ACTIVE QFN RGP 20 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TRF 1115 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TRF1115IRGPR QFN RGP 20 2500 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TRF1115IRGPT QFN RGP 20 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRF1115IRGPR QFN RGP 20 2500 338.1 338.1 20.6 TRF1115IRGPT QFN RGP 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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