Not Recommended For New Designs
TR
F1
22
TRF1222
2
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
3.5-GHz Integrated Up-Converter
FEATURES
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
•
•
Performs Up-Conversion in 3.5-GHz Radios
(3300-3800 MHz)
Integrated IF amplifier, Mixer and LO Buffer
Amplifier
Provision for external Image Reject /
Band-Pass Filter
TTL Switched Attenuator For Gain Control
TTL Controlled Amplifier Power Down
RF Frequency Range: 3300-3800 MHz
18 dB of Gain with 16-dB Digital Attenuator
Output P-1dB: +14 dBm, Typical
Output IP3: +24 dBm, Typical
LO Drive Level = 0 dBm, Typical
DESCRIPTION
The TRF1222 up-converts a UHF IF signal to an RF signal in the 3300 to 3800 MHz range for 3.5-GHz radio
applications. The TRF1222 has 18 dB of gain and an output P-1dB of 14 dBm, typical. A TTL compatible, 1-bit
16-dB digital attenuator is provided for gain control and the IF and RF amplifiers can be shut off via a TTL control
signal for power critical or TDD applications. In order to provide system requirements for LO/spurious rejection,
the TRF1222 offers a signal path to an off-chip band-pass filter. Specifications are provided assuming an in-band
2-dB insertion loss filter.
The TRF1222 is designed to complete the second up-conversion in Texas Instruments complete 3.5-GHz chip
set. The linear nature of the up-converter makes it ideal for complex modulations schemes such as high order
QAM or OFDM.
BPF
RFI
MXRO
Mixer
RF AMPLIFIER
VGA
IFIP
BALUN
RFO
IFIN
LOP
Power
Supply
LON
LO Buffer
−VNEG
VDD
UCEN
UCATTN
Figure 1. Block Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
Not Recommended For New Designs
TRF1222
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
DEVICE INFORMATION
32 31
30
29
28 27
26
IFADJ
VDDIF
RFI
GND
GND
GND
VDD1
GND
LPCC−32 PACKAGE
(TOP VIEW)
25
MXRADJ
VDD2
2
23
UCEN
GND
3
22
MXRO
UCATTN
4
21
GND
GND
5
20
IFIN
RFO
6
19
IFIP
LOADJ1
7
18
VDDIFP
VNEG
8
17
VDDIFN
13 14
15
16
LON
12
LOP
11
GND
LOADJ2
10
GND
9
GND
24
GND
1
VDDLO
IADJ
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
1
IADJ
2
VDD2
3, 5, 9,
11, 15,
16, 21,
28,29,
30, 32
GND
I/O
TYPE
DESCRIPTION
Not connected for normal operation. Amplifier bias adjustment. Do not ground this pin
or connect to any other pin.
I
Power
RF amplifier bias 5 V
Ground
4
UCATTN
I
Digital
Logic high is high gain; logic low reduces gain by 16 dB. Normally set high.
6
RFO
O
Analog
RF output from RF amplifier
7
LOADJ1
8
VNEG
10
LOADJ2
12
LOP
I
Analog
13
LON
I
Analog
LO input, negative, internally ac-coupled
14
VDDLO
I
Power
Positive power for LO amplifier, 5 V
17
VDDIFN
I
Analog
VDD supply for IF amplifier, negative, 5 V
18
VDDIFP
I
Analog
VDD supply for IF amplifier, positive, 5 V
19
IFI P
I
Analog
IF input, positive, dc-coupled, typical dc voltage is 1.2 V
2
Not connected for normal operation. LO common gate bias adjustment. Do not
ground this pin or connect to any other pin.
I
Power
Negative bias used for enable circuitry -5 V. This pin can be grounded if the user
does not use the UCEN pin to turnoff the amplifier. If the VNEG is grounded the
UCEN pin should be tied high.
Not connected for normal operation. LO amplifier bias adjustment. Do not ground this
pin or connect to any other pin.
LO input, positive, internally ac-coupled
Not Recommended For New Designs
TRF1222
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
NAME
I/O
TYPE
DESCRIPTION
20
IFI N
I
Analog
IF input, negative, dc-coupled typical dc voltage is 1.2 V
22
MXRO
O
Analog
Output of mixer (after balun) 50-Ω impedance with high impedance dc ground.
23
UCEN
I
Digital
Set high to enable IF amplifier and RF amplifiers
24
MXRADJ
O
Analog
Normally grounded. Provide 0-Ω jumper to ground.
25
IFADJ
26
VDDIF
I
Power
27
RFI
I
Analog
Input to RF amplifier, 50-Ω impedance, internally ac-coupled
31
VDD1
I
Power
RF amplifier bias 5 V
Back
GND
Not connected for normal operation. IF amplifier bias adjustment. Do not ground this
pin or connect to any other pin.
Positive supply for IF bias circuitry 5 V
Back of package has metal base that must be grounded for thermal and RF
performance.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDD
Positive dc supply voltage
0 to 5.5
V
-VDD
Negative dc supply voltage
-5.5 to 0
V
PIN
RF input power
10
dBm
TJ
Junction temperature
200
°C
PD
Power dissipation
1
W
Digital input pins
-0.3 to 5.5
V
9.01
°C/W
θjc
Thermal resistance junction-to-case (1)
Tstg
Storage temperature
-40 to 105
°C
Top
Operating temperature
-40 to 85
°C
260
°C
Lead temperature (40 Sec Max)
(1)
Thermal resistance is junction to ambient assuming thermal pad with 16 thermal vias under package metal base. See the recommended
PCB layout.
ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
175
200
mA
-5
-4.75
3
6
DC CHARACTERISTICS
VDD
Positive supply voltage
IDD
Positive supply current (total)
VNEG
Negative supply voltage
INEG
Negative supply current
IVDD2
Supply current RF 2, pin 2
50
mA
ILO
Supply current, LO, pin 14
50
mA
IIF
Supply current, IF
47
mA
IVDD1
Supply current RF1, pin 31
28
mA
VIH
Input high voltage
VIL
Input low voltage
-5.25
Pin 17, 18, and 26 combined
2.5
5
V
mA
V
0.8
V
IIH
Input high current
300
µA
IIL
Input low current
–50
µA
3
Not Recommended For New Designs
TRF1222
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
Unless otherwise stated VDD = 5 V, FRF = 3500 MHz, IDD = 160 mA, VNEG = -5 V, FRF = 3.5 GHz, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3800
MHz
FIF
IF input frequency
IRF
RF output frequency
G
Gain
UCATTN = TTL high, input IF impedance is
100-Ω differential
22
dB
∆ATTN
Switched attenuator range
UCATTN from high-to-low
16
dB
GNB
Gain flatness / 6 MHz
OP-1dB
Output power at 1-dB compression, high
gain
UCATTN = TTL high
14
OIP3
Output 3rd order intercept point, high
gain
UCATTN = TTL high
24
Gain - IF to MXRO
UCATTN = TTL high
1
dB
Gain - RFI to RFO
UCATTN = TTL high
21
dB
LO input power
Referenced to 100-Ω differential
LO to RFO leakage (1)
LO input = 0 dBm
PLO
(1)
4
325
3300
MHz
0.2
Performance is sensitive to impedance termination and board layout.
-3
0
-5
dB
dBm
dBm
3
dB
dBm
Not Recommended For New Designs
TRF1222
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
APPLICATION INFORMATION
A typical application schematic is shown in Figure 3.
The PCB material recommendations are shown in Table 1 and Figure 2.
Table 1. PCB Recommendations
Board Material
Board Material Core Thickness
FR4
10 mil
Copper Thickness (starting)
1 oz
Prepreg Thickness
8 mil
Recommended Number of Layers
Via Plating Thickness
Final Plate
Final Board Thickness
4
½ oz
White immersion tin
33–37 mil
5
Not Recommended For New Designs
TRF1222
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
0.60 TYP
3.75
0.23 TYP
0.50 TYP
PIN 1
3.75
1.00
3.50
1.00
DIA 0.38
TYP
0.25 TYP
3.50
SOLDER MASK: NO SOLDERMASK UNDER CHIP, ON LEAD PADS
OR ON GROUND CONNECTIONS.
16 VIA HOLES, EACH 0.38 mm.
DIMENSIONS in mm
NOTE: Top and bottom surface finish: copper flash with 50–70 µin white tin immersion.
Figure 2. PCB Construction and Via Cross Section
6
Not Recommended For New Designs
TRF1222
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
VDD
0.01 F
100pF
100pF
26
RFI
25
IFADJ
27
VDDIF
28
GND
29
GND
30
GND
31
VDD1
BASE
GND
32
1
BPF
Z = 50
MXRADJ 24
IADJ
0(A)
23
2
VDD2
UCEN
3
GND
MXRO 22
4
UCATTN
GND 21
5
GND
IFIN
20
6
RFO
IFIP
19
7
LOADJ1
VDDIFP 18
8
VNEG
VDDIFN 17
UCEN
100pF
0.01 F
UCATTN
9
10
11
12
13
14
15
GND
GND
VDDLO
LON
LOP
GND
100pF
LOADJ2
0.01 F
GND
RF OUT
1000pF
IF IN N
1000pF IF IN P
33 nH(B) VDD
33 nH(B)
100pF
0.01 F
16
1 F
−VNEG
LO IN P
100pF
0.01 F
LO IN N
Place 100pF capacitors as close as possible to package pins.
A.
Connect pin 24 to ground through a 0-Ω resistor.
B.
Place 33-nH inductors close to package pins.
C.
Place 100-pF capacitors close as possible to package pins.
Figure 3. Recommended Application Schematic
7
TRF1222
Not Recommended For New Designs
www.ti.com
SLWS171A – APRIL 2005 – REVISED DECEMBER 2005
Figure 4. Package Outline 5 mm x 5 mm LPCC 32-Pin Leadless Package
8
Not Recommended For New Designs
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TRF1222IRTMT
OBSOLETE
VQFN
RTM
32
TBD
Call TI
Call TI
-40 to 85
TRF
1222
TRF1222IRTMTG3
OBSOLETE
VQFN
RTM
32
TBD
Call TI
Call TI
-40 to 85
TRF
1222
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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