TRF371125
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
INTEGRATED IQ DEMODULATOR
Check for Samples: TRF371125
FEATURES
DESCRIPTION
•
•
The TRF371125 is a highly linear and integrated
direct-conversion quadrature demodulator. The
TRF371125 integrates balanced I and Q mixers, LO
buffers, and phase splitters to convert an RF signal
directly to I and Q baseband. The on-chip
programmable-gain amplifiers allow adjustment of the
output signal level without the need for external
variable-gain (attenuator) devices. The TRF371125
integrates programmable baseband low-pass filters
that attenuate nearby interference, eliminating the
need for an external baseband filter.
1
2
•
•
•
•
•
•
•
Frequency Range: 700 MHz to 4000 MHz
Integrated Baseband Programmable-Gain
Amplifier
On-Chip Programmable Baseband Filter
High Out-of-Band IP3: 24 dBm at 2400 MHz
High Out-of-Band IP2: 60 dBm at 2400 MHz
Hardware and Software Power Down
Three-Wire Serial Interface
Single Supply: 4.5-V to 5.5-V Operation
Silicon Germanium Technology
Housed in a 7-mm × 7-mm QFN package, the
TRF371125 provides the smallest and most
integrated receiver solution available for highperformance equipment.
APPLICATIONS
•
•
•
•
Multicarrier Wireless Infrastructure
WiMAX
High-Linearity Direct-Downconversion
Receiver
LTE (Long Term Evolution)
To Microcontroller
READBACK
NC
Gain_B1
Gain_B2
NC
Gain_B0
MIXIoutn
NC
STROBE
MIXIoutp
CLOCK
RFin
DATA
To Microcontroller
48 47 46 45 44 43 42 41 40 39 38 37
36
GNDDIG
1
VCCDIG
2
35
GND
CHIP_EN
3
34
BBIoutn
VCCMIX1
4
33
BBIoutp
VCCBBI
To ADC I
GND
5
32
GND
MIXinp
6
31
LOip
MIXinn
7
30
LOin
GND
8
29
VCCLO
VCCMIX2
9
28
BBQoutp
NC
10
27
BBQoutn
NC
11
26
LOin
TRF371125
NC
GND
VCCBBQ
VCM
GNDBIAS
REXT
VCCBIAS
NC
NC
MIXQoutn
GND
MIXQoutp
GND
25
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
GND
To ADC Q
30 kW
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TRF371125
SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE DEVICE OPTIONS (1)
PRODUCT
PACKAGE
LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
TRF371125
QFN-48
RGZ
–40°C to 85°C
TRF371125
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
TRF371125IRGZR
Tape and Reel, 2500
TRF371125IRGZT
Tape and Reel, 500
MIXIoutn
44
45
MIXIoutp
FUNCTIONAL DIAGRAM
ADC Driver
VCCs
PGA
33
BBIoutp
34
BBIoutn
24
VCM
30
LOin
31
LOip
27
BBQoutn
28
BBQoutp
48
CLOCK
GND
DC Offset Control I
0°
MIXinp
6
MIXinn
7
90°
DC Offset Control Q
PGA
ADC Driver
CHIP_EN
3
Power
Down
DC Offset Control
47
LPFADJ Control
46
37
DATA
STROBE
READBACK
Gain_B2
39
40
Gain_B1
41
Gain_B0
17
MIXQoutn
MIXQoutp
16
PGA Control Q
SPI
B0385-01
(1)
2
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
DEVICE INFORMATION
PIN ASSIGNMENTS
space
GNDDIG
1
VCCDIG
2
NC
READBACK
Gain_B2
Gain_B0
Gain_B1
NC
NC
MIXIoutn
STROBE
MIXIoutp
DATA
CLOCK
RGZ PACKAGE
QFN-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
36
VCCBBI
35
GND
3
34
BBIoutn
VCCMIX1
4
33
BBIoutp
GND
5
32
GND
MIXinp
6
31
LOip
CHIP_EN
TRF371125
MIXinn
7
30
LOin
GND
8
29
VCCLO
VCCMIX2
9
28
BBQoutp
NC
10
27
BBQoutn
NC
11
26
GND
VCCBBQ
VCM
NC
GNDBIAS
VCCBIAS
REXT
NC
NC
MIXQoutn
GND
MIXQoutp
GND
25
12
13 14 15 16 17 18 19 20 21 22 23 24
GND
GND
PIN FUNCTIONS
PIN
NO.
NAME
I/O
DESCRIPTION
1
GNDDIG
Digital ground
2
VCCDIG
Digital power supply
3
CHIP_EN
4
VCCMIX1
Mixer power supply
5
GND
Ground
6
MIXinp
I
Mixer input: positive terminal
7
MIXinn
I
Mixer input: negative terminal
8
GND
Ground
I
Chip enable
9
VCCMIX2
Mixer power supply
10
NC
No connect
11
NC
No connect
12
GND
Ground
13
GND
Ground
14
GND
Ground
15
GND
Ground
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
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PIN FUNCTIONS (continued)
PIN
NO.
4
NAME
I/O
DESCRIPTION
16
MIXQoutp
O
Mixer Q output: positive terminal
17
MIXQoutn
O
Mixer Q output: negative terminal
18
NC
19
NC
20
REXT
21
VCCBIAS
Bias block power supply
22
GNDBIAS
Bias block ground
23
NC
24
VCM
25
VCCBBQ
26
GND
27
BBQoutn
O
Baseband Q (in quadrature) output: negative terminal
28
BBQoutp
O
Baseband Q (in quadrature) output: positive terminal
29
VCCLO
30
Loin
I
Local oscillator input: negative terminal
31
Loip
I
Local oscillator input: positive terminal
32
GND
33
BBIoutp
O
Baseband I (in-phase) output: positive terminal
34
BBIoutn
O
Baseband I (in-phase) output: negative terminal
35
GND
Ground
36
VCCBBI
Baseband I (in phase) power supply
37
NC
38
READBACK
O
SPI readback data
39
Gain_B2
I
PGA fast gain control bit 2
40
Gain_B1
I
PGA fast gain control bit 1
41
Gain_B0
I
PGA fast gain control bit 0
42
NC
43
NC
44
MIXIoutn
O
Mixer I output: negative terminal
45
MIXIoutp
O
Mixer I output: positive terminal
46
STROBE
I
SPI enable
47
DATA
I
SPI data input
48
CLOCK
I
SPI clock input
No connect
No connect
O
Reference bias external resistor
No connect
I
Baseband common-mode input voltage
Baseband Q chain power supply
Ground
Local oscillator power supply
Ground
No connect
No connect
No connect
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range (2)
VALUE
UNIT
–0.3 to 6
V
Digital I/O voltage range
–0.3 to 6
V
Operating free-air temperature range, TA
–40 to 85
°C
Operating virtual junction temperature range, TJ
–40 to 150
°C
Storage temperature range, Tstg
–65 to 150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VCC
Power supply voltage
MIN
NOM
MAX
4.5
5
5.5
V
940
µVpp
Power supply voltage ripple
UNIT
TA
Operating free-air temperature range
–40
85
°C
TJ
Operating virtual junction temperature range
–40
150
°C
MAX
UNIT
THERMAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
Soldered slug, no airflow
RqJA
Thermal resistance, junction-to-ambient
RqJA (2)
RqJB
(1)
(2)
Thermal resistance, junction-to-board
MIN
TYP
26
Soldered slug, 200-LFM airflow
20.1
Soldered slug, 400-LFM airflow
17.4
7-mm × 7-mm 48-pin PDFP
25
7-mm × 7-mm 48-pin PDFP
12
°C/W
°C/W
Determined using JEDEC standard JESD-51 with high-K board
16 layers, high-K board
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ELECTRICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PARAMETERS
ICC
Total supply current
360
mA
Power-down current
2
mA
IQ DEMODULATOR AND BASEBAND SECTION
fRF
Frequency range
700
Gain range
22
Gain step
See (1)
Pinmax
Max. RF power input
OIP3
4000
24
MHz
dB
1
dB
Before damage
25
dBm
Output third-order intercept point
Gain setting = 24 (2)
30
dBVrms
P1dBmin
Min. output compression point
1 tone (3)
3
dBVrms
fmin
Min. baseband low-pass filter cutoff
frequency
1–dB point (4)
fmax
Max. baseband low-pass filter cutoff
frequency
3–dB point (4)
fbypass
Baseband low-pass filter cutoff frequency in
bypass mode
3–dB point (5)
700
15
8
2 × fC
32
3 × fC
54
4 × fC
75
5 × fC
90
Image suppression
Vcm
Output, common-mode
Baseband harmonic level
dB
–40
Output BB attenuator
Output load impedance
MHz
1
1.5 × fC
Baseband relative attenuation at LPF cutoff
frequency (fC) (6)
MHz
30
1 × fC
Fsel
kHz
dB
3
dB
1
kΩ
Parallel capacitance
20
pF
Measured at I- and Q-channel
baseband outputs
1.5
V
Parallel resistance
Second harmonic (7)
Third harmonic
(7)
–100
dBc
–93
dBc
LOCAL OSCILLATOR PARAMETERS
Local oscillator frequency
700
(8)
LO input level
See
LO leakage
At MIXinn/p at 0-dBm LO drive level
–3
0
4000
MHz
6
dBm
–58
dBm
VCC
V
0.8
V
DIGITAL INTERFACE
VIH
High-level input voltage
0.6 × VCC
VIL
Low-level input voltage
0
VOH
High-level output voltage
VOL
Low-level output voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
6
5
0.8 × VCC
V
0.2 × VCC
V
Two consecutive gain settings
Two CW tones at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
Single CW tone at an offset from LO frequency smaller than the baseband-filter cutoff frequency. Performance is set by baseband
circuitry regardless of LO frequency.
Baseband low-pass filter cutoff frequency is programmable through SPI register LPFADJ. LPFADJ = 0 corresponds to max bandwidth;
LPFADJ = 255 corresponds to minimum BW.
Filter Ctrl setting equal to 0
Attenuation relative to passband gain
LO frequency set to 2.4 GHz. Power-in set to –40 dBm. Gain setting at 24. DC offset calibration engaged. Input signal set at 2.5-MHz
offset.
LO power outside of this range is possible but may introduce degraded performance.
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C (1) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fLO = 700 MHz
Gmax
Maximum gain (2)
Gain setting = 24
50
NF
Noise figure
Gain setting = 24
8.5
dB
IIP3
Third-order input intercept point
Gain setting = 24 (3) (4)
14
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (4) (5)
60
dBm
Gmax
Maximum gain (2)
Gain setting = 24
44
dB
NF
Noise figure
Gain setting = 24
11
dB
(3) (4)
dB
fLO = 1740 MHz
IIP3
Third-order input intercept point
Gain setting = 24
22
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (4) (5)
60
dBm
Gmax
Maximum gain (2)
Gain setting = 24
43
dB
NF
Noise figure
Gain setting = 24
12
dB
IIP3
Third-order input intercept point
Gain setting = 24 (3) (4)
23
dBm
IIP2
Second-order input intercept point
Gain Setting = 24 (4) (5)
60
dBm
Gmax
Maximum gain (2)
Gain setting = 24
42.5
dB
N3F
Noise figure
Gain setting = 24
12.5
dB
fLO = 1950 MHz
fLO = 2025 MHz
(3) (4)
22
dBm
60
dBm
IIP3
Third-order input intercept point
Gain setting = 24
IIP2
Second-order input intercept point
Gain setting = 24 (4) (5)
Maximum gain (2)
Gain setting = 24
40
dB
Gain setting = 24
13.5
dB
Gain setting = 16
15
dB
fLO = 2400 MHz
Gmax
NF
Noise figure
IIP3
Third-order input intercept point
Gain setting = 24 (3) (4)
24
dBm
IIP2
Second-order input intercept point
Gain setting = 24 (4) (5)
60
dBm
(1)
(2)
(3)
(4)
(5)
For broadband frequency sweeps, the Picosecond balun (model #5310A) is used at the RF and LO input. For frequency band between
2100 MHz and 2700 MHz the Murata balun LDB212G4005C-001 is used. Performance parameters adjusted for balun insertion loss.
Recommended baluns for respective frequency band is shown below:
700 MHz: Murata LDB21897M005C-001 (or equivalent)
1740 MHz: Murata LDB211G8005C-001 (or equivalent)
1950 MHz: Murata LDB211G9005C-001 (or equivalent)
2025 MHz: Murata LDB211G9005C-001 (or equivalent)
2500 MHz: Murata LDB212G4005C-001 (or equivalent)
3500 MHz: Johanson 3600BL14M050E (or equivalent)
Gain defined as voltage gain from Mixin (Vrms) to either baseband output: BBI/Qout (Vrms)
Two CW tones of –30 dBm at fRF1 = fLO ±(2 × fC) and fRF2 = fLO ±[(4 × fC) + 100 kHz] (fC = baseband filter 1-dB cutoff frequency).
Because the 2-tone interferers are outside of the baseband filter bandwidth, the results are inherently independent of the gain setting.
Intermodulation parameters are recorded at maximum gain setting, where measurement accuracy is best.
Two CW tones at –30 dBm at fRF1 = fLO ±2 × fC and fRF2 = fLO ±[(2 × fC) + 100 kHz]; IM2 product measured at 100-kHz output frequency
(fC = baseband filter 1-dB cutoff frequency)
TIMING REQUIREMENTS
VCC = 5 V, LO power = 0 dBm, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(CLK)
Clock period
50
ns
tsu1
Setup time, data
10
ns
th
Hold time, data
10
ns
tw
Pulse width, STROBE
20
ns
tsu2
Setup time, STROBE
10
ns
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TYPICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
Table of Graphs
Gain
vs LO frequency (1) (2)
Figure 1, Figure 2, Figure 3
(1) (2)
Figure 4, Figure 5, Figure 6
Noise figure
vs LO frequency
IIP3
vs LO frequency (3) (4) (5)
Figure 7, Figure 8, Figure 9
IIP2
vs LO frequency (3) (4) (5)
Figure 10, Figure 11, Figure 12
Gain
vs LO frequency
IIP3
vs LO frequency (4) (5)
Figure 16, Figure 17, Figure 18, Figure 19
IIP2
vs LO frequency (4) (5)
Figure 20, Figure 21, Figure 22, Figure 23
Figure 13, Figure 14, Figure 15
(4) (5) (6)
Optimized IIP2
vs LO frequency
Optimized IIP3
vs LO frequency (4) (5) (6)
Figure 24
Noise figure
vs LO frequency
OIP3
vs Frequency offset (7)
Noise figure
vs BB gain setting
Gain
vs BB gain setting
Gain
vs Frequency offset
Figure 35, Figure 36
Gain
vs Frequency offset (bypass mode)
Figure 37, Figure 38
1-dB LPF corner frequency
vs LPFADJ setting
Figure 39
Relative LPF group delay
vs Frequency offset (8)
Figure 40
Image rejection
vs BB frequency offset
Figure 41
DC offset limit
vs Temperature (9)
Figure 42
Out-of-band P1dB
vs Relative offset multiplier to corner frequency (10)
Figure 43
Figure 25
Figure 26, Figure 27, Figure 28
Figure 29, Figure 30, Figure 31, Figure 32
Figure 33
Figure 34
(1)
Measured with broadband Picosecond 5310A balun on the LO input and single ended connection on the RF input. Performance gain
adjusted for the 3 dB differential to single-ended insertion loss.
(2) Performance ripple due to impedance mismatch on the RF input.
(3) Measured with broadband Picosecond 5310A balun on the LO input and RF input. Balun insertion loss is compensated for in the
measurement.
(4) Out-of-band intercept point is defined with tones that are at least 2 times farther out than the programmed LPF corner frequency that
generate an intermodulation tone that falls inside the LPF passband.
(5) Out-of-band intercept point is dependent on the demodulator performance and not the baseband circuitry; the measurement is taken at
max gain but is valid across all PGA settings.
(6) Optimized intercept point within the band 2.5 to 2.7 GHz is achieved by setting trim values Mix GM trim, Mix LO Trim, LO Trim, Mix Buff
Trim, Filter trim, Out Buff Trim to: 2, 3, 0, 1, 2, 1 respectively.
(7) Measured with filter in bypass mode to characterize the passband circuitry across baseband frequencies.
(8) Relative to the low frequency offset group delay in bypass mode.
(9) Idet set to 50 µA; RF signal is off; LO at 2.4 GHz at 0 dBm; Det filter set to 1 kHz; Clk Div set to 1024.
(10) In-band tone set to 1 MHz; out-of-band jammer tone set to specified relative offset ratio from the programmed corner frequency. Jammer
tone is increased until in-band tone compresses 1 dB.
8
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TYPICAL CHARACTERISTICS
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
GAIN vs LO FREQUENCY
GAIN vs LO FREQUENCY
52
52
T A = −40°C
T A = −10°C
T A = 25°C
T A = 85°C
50
48
48
46
Gain (dB)
46
Gain (dB)
VCC = 4.5V
VCC = 5V
VCC = 5.5V
50
44
42
44
42
40
40
38
38
36
See Notes 1 and 2
34
500
1000
1500
36
See Notes 1 and 2
34
500
1000
1500
2000
2500
3000
LO Frequency (MHz)
3500
4000
G001
2000
2500
3000
LO Frequency (MHz)
Figure 1.
GAIN vs LO FREQUENCY
G002
NOISE FIGURE vs LO FREQUENCY
22
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
50
20
18
Noise Figure (dB)
48
46
Gain (dB)
4000
Figure 2.
52
44
42
40
T A = −40°C
T A = −10°C
T A = 25°C
T A = 85°C
16
14
12
10
38
8
36
See Notes 1 and 2
34
500
1000
1500
See Notes 1 and 2
2000
2500
3000
LO Frequency (MHz)
3500
6
500
4000
1000
1500
G003
2000
2500
3000
LO Frequency (MHz)
Figure 3.
NOISE FIGURE vs LO FREQUENCY
20
4000
G004
NOISE FIGURE vs LO FREQUENCY
22
VCC = 4.5V
VCC = 5 V
VCC = 5.5V
20
18
Noise Figure (dB)
18
16
14
12
10
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
16
14
12
10
8
8
See Notes 1 and 2
6
500
3500
Figure 4.
22
Noise Figure (dB)
3500
1000
1500
2000
2500
3000
LO Frequency (MHz)
3500
See Notes 1 and 2
4000
6
500
1000
G005
Figure 5.
1500
2000
2500
3000
LO Frequency (MHz)
3500
4000
G006
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
36
34
32
30
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
IIP3 (dBm)
28
26
24
22
20
18
16
14
12
10
500
500
1000
1000
1500
1500
2000
2000
2500
2500
3000
3000
3500
350
4000
400
Q
36
34
32
30
IIP3 (dBm)
28
26
24
22
20
18
16
14
12
10
500
See Notes 3, 4 and 5
1000
1500
2000
2500
LO Frequency (MHz)
3000
3500
4000
G007
Figure 7.
10
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
32
30
VCC = 4.5V
VCC = 5V
VCC = 5.5V
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
500
500
1000
1000
1500
1500
2000
2000
2500
2500
3000
3000
3500
350
4000
400
Q
34
32
30
28
IIP3 (dBm)
26
24
22
20
18
16
14
See Notes 3, 4 and 5
12
500
1000
1500
2000
2500
LO Frequency (MHz)
3000
3500
4000
G008
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
32
30
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
500
500
1000
1000
1500
1500
2000
2000
2500
2500
3000
3000
3500
350
4000
400
Q
34
32
30
28
IIP3 (dBm)
26
24
22
20
18
16
14
See Notes 3, 4 and 5
12
500
1000
1500
2000
2500
LO Frequency (MHz)
3000
3500
4000
G009
Figure 9.
12
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
90
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
IIP2 (dBm)
80
70
60
50
40
30
500
500
1000
1000
1500
1500
2000
2000
2500
2500
3000
3000
3500
350
4000
400
Q
100
90
IIP2 (dBm)
80
70
60
50
40
See Notes 3, 4 and 5
30
500
1000
1500
2000
2500
LO Frequency (MHz)
3000
3500
4000
G010
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
90
VCC = 4.5V
VCC = 5V
VCC = 5.5V
IIP2 (dBm)
80
70
60
50
40
30
500
500
1000
1000
1500
1500
2000
2000
2500
2500
3000
3000
3500
350
4000
400
Q
100
90
IIP2 (dBm)
80
70
60
50
40
See Notes 3, 4 and 5
30
500
1000
1500
2000
2500
LO Frequency (MHz)
3000
3500
4000
G011
Figure 11.
14
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
90
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
IIP2 (dBm)
80
70
60
50
40
30
500
500
1000
1000
1500
1500
2000
2000
2500
2500
3000
3000
3500
350
4000
400
Q
100
90
IIP2 (dBm)
80
70
60
50
40
See Notes 3, 4 and 5
30
500
1000
1500
2000
2500
LO Frequency (MHz)
3000
3500
4000
G012
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
GAIN vs LO FREQUENCY
GAIN vs LO FREQUENCY
44
44
T A = −40°C
T A = −10°C
T A = 25°C
T A = 85°C
43
42
41
Gain (dB)
Gain (dB)
42
40
39
41
40
39
38
38
37
37
36
2100
2200
2300
2400
2500
LO Frequency (MHz)
2600
VCC = 4.5V
VCC = 5V
VCC = 5.5V
43
2700
36
2100
2200
G013
2300
2400
2500
LO Frequency (MHz)
Figure 13.
2600
2700
G014
Figure 14.
GAIN vs LO FREQUENCY
44
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
43
Gain (dB)
42
41
40
39
38
37
36
2100
2200
2300
2400
2500
LO Frequency (MHz)
2600
2700
G015
Figure 15.
16
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
32
30
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
10
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
12
See Notes 4 and 5
10
2100
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
34
32
30
28
IIP3 (dBm)
26
24
22
20
18
16
14
G016
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
32
30
VCC = 4.5V
VCC = 5V
VCC = 5.5V
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
10
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
34
32
30
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
10
2100
See Notes 4 and 5
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
G017
Figure 17.
18
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
32
30
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
10
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
34
32
30
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
10
2100
See Notes 4 and 5
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
G018
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP3 vs LO FREQUENCY
W
I
34
32
30
LPFADJ = 0
LPFADJ = 24
LPFADJ = 82
LPFADJ = 142
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
10
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
34
32
30
28
IIP3 (dBm)
26
24
22
20
18
16
14
12
10
2100
See Notes 4 and 5
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
G019
Figure 19.
20
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
90
80
IIP2 (dBm)
70
60
50
40
30
20
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
See Notes 4 and 5
20
2100
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
100
90
80
IIP2 (dBm)
70
60
50
40
30
G020
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
90
VCC = 4.5V
VCC = 5V
VCC = 5.5V
80
IIP2 (dBm)
70
60
50
40
30
20
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
100
90
80
IIP2 (dBm)
70
60
50
40
30
See Notes 4 and 5
20
2100
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
G021
Figure 21.
22
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
90
LO Pwr = −3dB
LO Pwr = 0dB
LO Pwr = 3dB
LO Pwr = 6dB
80
IIP2 (dBm)
70
60
50
40
30
20
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
See Notes 4 and 5
20
2100
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
100
90
80
IIP2 (dBm)
70
60
50
40
30
G022
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
IIP2 vs LO FREQUENCY
W
I
100
90
LPFADJ = 0
LPFADJ = 24
LPFADJ = 82
LPFADJ = 142
80
IIP2 (dBm)
70
60
50
40
30
20
2100
210
2200
220
2300
230
2400
240
Q
2500
250
2600
260
2700
270
100
90
80
IIP2 (dBm)
70
60
50
40
30
See Notes 4 and 5
20
2100
2200
2300
2400
LO Frequency (MHz)
2500
2600
2700
G023
Figure 23.
24
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
OPTIMIZED IIP2 vs LO FREQUENCY
W
I
90
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
85
80
Optimized IIP2 (dBm)
75
70
65
60
55
50
45
40
35
30
2500
250
2525
2520
2550
2550
2575
2575
2550
2575
2600
2600
Q
2625
2625
2650
2650
2675
2675
2700
270
2600
2625
LO Frequency (MHz)
2650
2675
2700
90
85
80
Optimized IIP2 (dBm)
75
70
65
60
55
50
45
40
35
See Notes 4, 5 and 6
30
2500
2525
G024
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
OPTIMIZED IIP3 vs LO FREQUENCY
W
I
34
TA = −40°C
TA = −10°C
TA = 25°C
TA = 85°C
32
30
Optimized IIP3 (dBm)
28
26
24
22
20
18
16
14
12
2500
250
2525
2520
2550
2550
2575
2575
2550
2575
2600
2600
Q
2625
2625
2650
2650
2675
2675
2700
270
2600
2625
LO Frequency (MHz)
2650
2675
2700
34
32
30
Optimized IIP3 (dBm)
28
26
24
22
20
18
16
14
See Notes 4, 5 and 6
12
2500
2525
G025
Figure 25.
26
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SLWS219B – JANUARY 2010 – REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
NOISE FIGURE vs LO FREQUENCY
NOISE FIGURE vs LO FREQUENCY
20
20
T A = −40°C
T A = −10°C
T A = 25°C
T A = 85°C
19
18
17
Noise Figure (dB)
Noise Figure (dB)
18
VCC = 4.5V
VCC = 5 V
VCC = 5.5V
19
16
15
14
13
12
17
16
15
14
13
12
11
11
10
2100
10
2100
2200
2300
2400
2500
LO Frequency (MHz)
2600
2700
2200
G026
Figure 26.
2700
G027
OIP3 vs FREQUENCY OFFSET
NOISE FIGURE vs LO FREQUENCY
52
LO Pwr = −3dBm
LO Pwr = 0dBm
LO Pwr = 3dBm
LO Pwr = 6dBm
19
18
T A = −40°C
T A = 25°C
T A = 85°C
50
48
46
17
OIP3 (dBm)
Noise Figure (dB)
2600
Figure 27.
20
16
15
14
44
42
40
13
38
12
36
11
34
10
2100
32
2200
2300
2400
2500
LO Frequency (MHz)
2600
See Note 7
0
2700
5
G028
Figure 28.
10
15
Frequency Offset (MHz)
20
25
G029
Figure 29.
OIP3 vs FREQUENCY OFFSET
OIP3 vs FREQUENCY OFFSET
52
50
VCC = 4.5V
VCC = 5V
VCC = 5.5V
50
48
BB Gain = 12dB
BB Gain = 16dB
BB Gain = 20dB
BB Gain = 24dB
48
46
46
44
OIP3 (dBm)
OIP3 (dBm)
2300
2400
2500
LO Frequency (MHz)
44
42
40
42
40
38
38
36
36
34
34
See Note 7
See Note 7
32
32
0
5
10
15
Frequency Offset (MHz)
20
25
0
G030
Figure 30.
5
10
15
Frequency Offset (MHz)
20
25
G031
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
OIP3 vs FREQUENCY OFFSET
NOISE FIGURE vs BB GAIN SETTING
50
28
3dB Attn On
3dB Attn Off
48
3dB Attn On
3dB Attn Off
25
Noise Figure (dB)
46
OIP3 (dBm)
44
42
40
38
36
22
19
16
34
See Note 7
32
13
0
5
10
15
Frequency Offset (MHz)
20
25
0
2
4
6
8
G032
Figure 32.
22
24
G033
20
3dB Attn On
3dB Attn Off
40
0
37
34
-20
31
Gain (dB)
Gain (dB)
20
GAIN vs FREQUENCY OFFSET
GAIN vs BB GAIN SETTING
28
25
-40
-60
22
19
-80
16
0
2
4
6
8
10 12 14 16
BB Gain Setting
18
20
22
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
-100
0.1
13
24
1
10
Frequency Offset (MHz)
G034
Figure 34.
3
20
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
0
2
-20
Gain (dB)
1
0
-1
-40
-60
-2
-3
-80
-4
-5
0.1
G035
GAIN vs FREQUENCY OFFSET
GAIN vs FREQUENCY OFFSET
4
100
Figure 35.
5
Gain (dB)
18
Figure 33.
43
1
10
Frequency Offset (MHz)
100
Filter Ctrl 0
Filter Ctrl 1
Filter Ctrl 2
Filter Ctrl 3
-100
0.1
G036
Figure 36.
28
10 12 14 16
BB Gain Setting
1
10
100
Frequency Offset (MHz)
1000
G037
Figure 37. Bypass Mode
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TYPICAL CHARACTERISTICS (continued)
VCC = 5 V, LO power = 0 dBm, TA = 25°C, balun = Murata LDB212G4005C-001 (unless otherwise noted)
1-dB LPF CORNER FREQUENCY vs LPFADJ SETTING
GAIN vs FREQUENCY OFFSET
16
5
3
1-dB LPF Corner Frequency (MHz)
Filter Ctrl 0
Filter Ctrl 1
Filter Ctrl 2
Filter Ctrl 3
4
Gain (dB)
2
1
0
-1
-2
-3
-4
14
12
10
8
6
4
2
0
-5
0.1
1
10
Frequency Offset (MHz)
0
100
50
100
150
LPFADJ Setting
G038
Figure 38. Bypass Mode
RELATIVE LPF GROUP DELAY vs FREQUENCY OFFSET
G039
IMAGE REJECTION vs BB FREQUENCY OFFSET
0
See Note 8
Bypass
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
400
300
-10
Image Rejection (dB)
Relative LPF Group Delay (ns)
250
Figure 39.
500
200
100
0
-20
-30
-40
-50
-100
0.1
1
10
Frequency Offset (MHz)
-60
-25
100
-20
G040
-15
-10
-5
0
5
10
BB Frequency Offset (MHz)
Figure 40.
15
20
25
G041
Figure 41.
OUT-OF-BAND P1dB vs
REL OFFSET MULTIPLIER to CORNER FREQUENCY
DC OFFSET LIMIT vs TEMPERATURE
60
See Note 9
15
40
LPFADJ = 0
LPFADJ = 25
LPFADJ = 85
LPFADJ = 142
10
Out-of-Band P1dB (dBm)
DC Offset Limit (mV)
200
20
0
-20
-40
5
0
-5
-10
-15
-20
-60
-45 -35 -25 -15 -5
See Note 10
5 15 25 35 45 55 65 75 85
Temperature (°C)
G042
-25
0
0.5
1
1.5
2
2.5
3
3.5
4
Relative Offset Multiplier to Corner Frequency
Figure 42.
4.5
G043
Figure 43.
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REGISTER INFORMATION
SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION
The TRF371125 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift
register. There are three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin
46). DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of CLOCK. STROBE is asynchronous
to CLOCK, and at its rising edge the data in the shift register is loaded into the selected internal register. The first
two bits (DB0–DB1) are the address to select the available internal registers.
READBACK Mode
The TRF371125 implements the capability to read back the content of the serial programming interface registers.
In addition, it is possible to read back the status of the internal DAC registers that are automatically set after an
auto dc-offset calibration. Each readback is composed by two phases: writing followed by the actual reading of
the internal data (see timing diagram in Figure 44).
During the writing phase, a command is sent to the TRF371125 to set it in readback mode and to specify which
register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into
the READBACK pin and can be read at the following falling edge (LSB first). The first clock after LE goes high
(end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the
READBACK pin.
tsu1
t(CL)
t(CLK)
th
t(CH)
st
Register Write
CLOCK
DATA
nd
1
Write
CLOCK
Pulse
32
Write
CLOCK
Pulse
DB0 (LSB)
Address Bit 0
DB1
Address Bit 1
DB3
Address Bit 3
DB2
Address Bit 2
DB30
DB29
READBACK DATA READBACK DATA
Bit 30
Bit 29
DB31 (MSB)
READBACK DATA
Bit 31
tsu2
"End of Write
Cycle"Pulse
Latch
Enable
nd
CLOCK
32
Write
CLOCK
Pulse
tsu2
READBACK
tw
st
1
Read
CLOCK
Pulse
nd
nd
2
Read
CLOCK
Pulse
rd
32
Read
CLOCK
Pulse
33
Read
CLOCK
Pulse
tw
td
STROBE
"End of Write
Cycle" Pulse
READBACK
Data Bit 0
READBACK
DATA
READ
BACK
Data
Bit 1
READ
BACK
Data
Bit 29
READBACK
Data Bit 30
READBACK
Data Bit 31
T0265-02
Figure 44. Serial Programming Timing Diagram
30
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Table 1. Register Summary (1)
Bit #
Reg 1
Reg 2
Bit #
Bit0
Bit1
Register address
Register address
Bit1
Bit2
Reg 5
Bit3
SPI bank addr
SPI bank addr
Bit5
PWD RF
En auto-cal
Bit6
NU
Bit6
Bit7
PWD buf
Bit7
Bit8
P
Bit8
Bit9
NU
Bit9
Bit10
PWD DC OFF DIG
Bit11
NU
Bit4
Bit4
Register address
Register address
SPI bank addr
SPI bank addr
Mix GM trim
ILoadA
Mix LO trim
LO trim
Bit10
Bit11
Bit12
Mix buf trim
Bit12
Bit13
Bit13
Bit14
BB gain
Bit14
Bit1
ILoadB
Fltr trim
Bit3
Bit4
Bit5
Bit6
Bit9
Bit11
Bit13
Bit14
Bit17
Bit17
Bit17
Bit18
Bit18
Bit19
Bit20
Bit20
LPFADJ
Bit21
Bit22
IDet
Bit23
Bit24
Bit25
Bit26
DC detector
bandwidth
Bit27
Fast gain
Bit28
Gain sel
Bit29
Osc test
Bit30
NU
Bit31
En 3dB attn
Bit21
Bit21
Bit22
Bit22
Bit25
Cal clk sel
Bit26
NU
Bit24
Bit25
QLoadB
Bit26
Bit27
Bit27
Bit28
Bit28
Bit29
Osc trim
Bit30
Bit31
DC offset Q DAC
Bit23
Bit24
CLK div ratio
Bit16
Bit20
Bit23
Cal sel
Bit15
Bit19
QLoadA
NU
Bit12
Bit16
Bit19
ID
Bit10
Bit15
Out buf trim
SPI bank addr
Bit8
Bit16
Bit18
Register address
Bit7
Bit15
QDAC for dc offset
Reg 0
Bit2
Bit5
IDAC for dc offset
Bit #
Bit0
Bit2
Bit3
(1)
Reg 3
Bit0
Bypass
DC offset I DAC
Bit29
Bit30
Fltr ctrl
Bit31
Register 4 is not used.
Table 2. Register 1 Device Setup
REGISTER 1
NAME
RESET VALUE
Bit0
ADDR
1
WORKING DESCRIPTION
Bit1
ADDR
0
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
PWD_MIX
0
Mixer power down (Off = 1)
Bit6
NU
0
Not used
Bit7
PWD_BUF
1
Mixer out test buffer power down (Off = 1)
Bit8
PWD_FILT
0
Baseband filter power down (Off = 1)
Bit9
NU
0
Not used
Bit10
PWD_DC_OFF_DIG
1
DC offset calibration power down (Off = 1)
Register address
SPI bank address
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Table 2. Register 1 Device Setup (continued)
REGISTER 1
NAME
RESET VALUE
Bit11
NU
1
WORKING DESCRIPTION
Bit12
BBGAIN_0
1
Bit13
BBGAIN_1
1
Bit14
BBGAIN_2
1
Bit15
BBGAIN_3
1
Bit16
BBGAIN_4
0
Bit17
LPFADJ_0
0
Bit18
LPFADJ_1
0
Bit19
LPFADJ_2
0
Bit20
LPFADJ_3
0
Bit21
LPFADJ_4
0
Bit22
LPFADJ_5
0
Bit23
LPFADJ_6
0
Bit24
LPFADJ_7
1
Bit25
EN_FLT_B0
0
Bit26
EN_FLT_B1
0
Selects dc offset detector filter bandwidth.
Setting {00, 01, 11} = {10 MHz, 10 kHz, 1 kHz}
Bit27
EN_FASTGAIN
0
Enable external fast-gain control
Bit28
GAIN_SEL
0
Fast-gain control multiplier bit (×2 = 1)
Bit29
OSC_TEST
0
Enables osc out on readback pin if = 1
Bit30
NU
0
Not used
Bit31
EN 3dB Attn
0
Enables output 3-dB attenuator
Not used
Baseband gain setting. Default = 15. Range is from 0 (minimum gain
setting) to 24 (maximum gain setting). See the Application Information
section for more information on gain setting and fast gain control
options.
Sets programmable low-pass filter corner frequency. Range = 255
(lowest corner frequency) to 0 (highest corner frequency). Default value
is 128.
EN_FLT_B0/1: These bits control the bandwidth of the detector used to measure the dc offset during the
automatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0
controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dB cutoff
frequencies of the detector bandwidth are summarized in the following table (see the Application Information
section for more detail on the dc offset calibration and the detector bandwidth).
EN_FLT_B1
EN_FLT_B0
TYPICAL 3-dB CUTOFF FREQ
x
0
10 MHz
NOTES
Maximum bandwidth, bypass R, C
0
1
10 kHz
Enable R
1
1
1 kHz
Minimum bandwidth, enable R, C
Table 3. Register 2 Device Setup
32
REGISTER 2
NAME
RESET VALUE
Bit0
ADDR
0
Bit1
ADDR
1
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
EN_AUTOCAL
0
Bit6
IDAC_BIT0
0
Bit7
IDAC_BIT1
0
Bit8
IDAC_BIT2
0
Bit9
IDAC_BIT3
0
Bit10
IDAC_BIT4
0
Bit11
IDAC_BIT5
0
Bit12
IDAC_BIT6
0
Bit13
IDAC_BIT7
1
WORKING DESCRIPTION
Register address
SPI bank address
Enable autocal when = 1; reset to 0 when done.
I-DAC bits to be set during manual dc offset cal
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Table 3. Register 2 Device Setup (continued)
REGISTER 2
NAME
RESET VALUE
Bit14
QDAC_BIT0
0
WORKING DESCRIPTION
Bit15
QDAC_BIT1
0
Bit16
QDAC_BIT2
0
Bit17
QDAC_BIT3
0
Bit18
QDAC_BIT4
0
Bit19
QDAC_BIT5
0
Bit20
QDAC_BIT6
0
Bit21
QDAC_BIT7
1
Bit22
IDET_B0
1
Bit23
IDET_B1
1
Set reference current for digital calibration; Settings {00 to 11}
= {50 µA to 200 µA}. Setting 00 = highest resolution.
Bit24
CAL_SEL
1
DC offset calibration select. 0 = manual cal; 1 = autocal.
Bit25
Clk_div_ratio
0
Bit26
Clk_div_ratio
0
Bit27
Clk_div_ratio
0
Bit28
Cal_clk_sel
1
Bit29
Osc_trim
1
Bit30
Osc_trim
1
Bit31
Osc_trim
0
Q-DAC bits to be set during manual dc offset cal
Clk divider ratio. Setting {000 to 111} = {1, 8, 16, 128, 256, 1024, 2048,
16684}. A higher div ratio (slower clk) improves cal accuracy and
reduces speed.
Select internal oscillator when 1, SPI clk when 0
Internal oscillator frequency trimming; Setting {000} = ~300 kHz;
Setting {111} = ~1.8 MHz. Nominal setting {110} = ~900 kHz.
Table 4. Register 3 Device Setup
REGISTER 3
NAME
RESET VALUE
Bit0
ADDR
1
Bit1
ADDR
1
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
ILOAD_a
0
Bit6
ILOAD_a
0
Bit7
ILOAD_a
0
Bit8
ILOAD_a
0
Bit9
ILOAD_a
0
Bit10
ILOAD_a
0
Bit11
ILOAD_b
0
Bit12
ILOAD_b
0
Bit13
ILOAD_b
0
Bit14
ILOAD_b
0
Bit15
ILOAD_b
0
Bit16
ILOAD_b
0
Bit17
QLOAD_a
0
Bit18
QLOAD_a
0
Bit19
QLOAD_a
0
Bit20
QLOAD_a
0
Bit21
QLOAD_a
0
Bit22
QLOAD_a
0
WORKING DESCRIPTION
Register address
SPI bank address
I mixer offset side A
I mixer offset side B
Q mixer offset side A
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Table 4. Register 3 Device Setup (continued)
REGISTER 3
NAME
RESET VALUE
Bit23
QLOAD_b
0
WORKING DESCRIPTION
Bit24
QLOAD_b
0
Bit25
QLOAD_b
0
Bit26
QLOAD_b
0
Bit27
QLOAD_b
0
Bit28
QLOAD_b
0
Bit29
Bypass
0
Engage filter bypass
Bit30
Fltr Ctrl_b
1
Bit31
Fltr Ctrl_b
0
Used to adjust for filter peaking response; set to 0 in bypass mode, 1
otherwise
Q mixer offset side B
I/Q Mixer Load A/B: these bits adjust the load on the mixer output. All values should be 0. No modification is
necessary.
Register 4: No programming required for Register 4
Table 5. Register 5 Device Setup
REGISTER 5
NAME
RESET VALUE
Bit0
ADDR
1
Bit1
ADDR
0
Bit2
ADDR
1
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
MIX_GM_TRIM
1
Bit6
MIX_GM_TRIM
0
Bit7
MIX_LO_TRIM
1
Bit8
MIX_LO_TRIM
0
Bit9
LO_TRIM
1
Bit10
LO_TRIM
0
Bit11
MIX_BUFF_TRIM
1
Bit12
MIX_BUFF_TRIM
0
Bit13
FLTR_TRIM
1
Bit14
FLTR_TRIM
0
Bit15
OUT_BUFF_TRIM
1
Bit16
OUT_BUFF_TRIM
0
Bit17
0
Bit18
0
Bit19
0
Bit20
0
Bit21
0
Bit22
0
Bit23
Bit24
34
WORKING DESCRIPTION
Register address
SPI bank address
Mixer gm current trim
Mixer switch core VCM trim
LO buffers current trim
Mixer output buffer current trim
Filter current trim
Filter output buffer current trim
0
NU
0
Bit25
0
Bit26
0
Bit27
0
Bit28
0
Bit29
0
Bit30
0
Bit31
0
Not used
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Trims: the trim values allow for minor bias adjustments of internal stages. Generally it is recommended to leave
all trim values at the default value of 1. Linearity performance improvement over a small band of frequencies is
possible by selective adjustment of the trim values. Optimized intercept point within the band 2.5 GHz to 2.7 GHz
is achieved by setting trim values Mix GM trim, Mix LO Trim, LO Trim, Mix Buff Trim, Filter Trim, Out Buff Trim to:
2, 3, 0, 1, 2, 1, respectively.
Readback (Write Command)
0
0
0
1
0
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Zero Fill
Bit16
Bit17
Bit18
Bit19
Bit20
Bit21
Bit6
Bit7
Bit8
Bit9
Bit10
Bit11
Bit12
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Bit29
Bit30
Bit31
Bit12
Bit13
Bit14
Bit15
Bit29
Bit30
Bit31
Zero fill
Bit22
Bit13
Bit14
Register address
Bit15
1
Reg 0:DAC/Device ID Readback
Register Address
Bit0
Bit1
SPI Bank Addr
Bit2
Bit3
ID
Bit4
Bit5
NU
Bit6
Bit7
Bit8
Bit9
Bit10
DC offset Q DAC
Bit16
Bit17
Bit18
Bit19
Bit11
DC offset I DAC
Bit20
Bit21
Bit22
Bit23
Bit24
Bit25
Bit26
Bit27
Bit28
Table 6. Register 0 Device Setup (Read-Only)
READBACK REGISTER
NAME
RESET VALUE
Bit0
ADDR
0
Bit1
ADDR
0
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
ID
1
Bit6
ID
0
Bit7
0
Bit8
0
Bit9
0
Bit10
WORKING DESCRIPTION
Select SPI reg 1 to 5
Select SPI bank 1 to 3
Version ID: 01 = –25
0
Bit11
NU
0
Bit12
0
Bit13
0
Bit14
0
Bit15
0
Bit16
DC_OFFSET_Q
0
Bit17
DC_OFFSET_Q
0
Bit18
DC_OFFSET_Q
0
Bit19
DC_OFFSET_Q
0
Bit20
DC_OFFSET_Q
0
Bit21
DC_OFFSET_Q
0
Bit22
DC_OFFSET_Q
0
Bit23
DC_OFFSET_Q
1
Not used
DC offset DAC Q register
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Table 6. Register 0 Device Setup (Read-Only) (continued)
36
READBACK REGISTER
NAME
RESET VALUE
Bit24
DC_OFFSET_I
0
Bit25
DC_OFFSET_I
0
Bit26
DC_OFFSET_I
0
Bit27
DC_OFFSET_I
0
Bit28
DC_OFFSET_I
0
Bit29
DC_OFFSET_I
0
Bit30
DC_OFFSET_I
0
Bit31
DC_OFFSET_I
1
WORKING DESCRIPTION
DC offset DAC I register
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APPLICATION INFORMATION
Gain Control
The TRF371125 integrates a baseband programmable-gain amplifier (PGA) that provides 24 dB of gain range
with 1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 1 bits). Alternatively,
the PGA can be programmed by a combination of 5 bits programmed through the SPI and 3 parallel external bits
(pins Gain_B2, Gain_B1, Gain_B0). The external bits are used to reduce the PGA setting quickly without having
to reprogram the SPI registers. The fast gain control multiplier bit (register 1, bit 28) sets the step size of each bit
to either 1 dB or 2 dB. This allows a fast gain reduction of 0 dB to 7 dB in 1-dB steps or 0 dB to 14 dB in 2-dB
steps.
The PGA gain control word (BBgain) can be programmed to a setting between 0 and 24. This word is the
SPI programmed gain (register 1 bits) minus the parallel external 3 bits as shown in Figure 45. Note that
the PGA gain setting rails at 0 and does not go any lower. Typical applications set the nominal PGA gain setting
to 17 and use the fast-gain control bits to protect the analog-to-digital converter in the event of a strong input
jammer signal.
Composite
PGA Setting
(min: 0, max 24)
+
SPI
X
(x1, x2)
Gain_B0
Gain_B1
Gain_B2
Fast Gain Select
B0386-01
Figure 45. PGA Gain Control Word
For example, if a PGA gain setting of 19 is desired, then the SPI can be programmed directly to a value of 19.
Alternatively, the SPI gain register can be programmed to 24 and the parallel external bits set to 101 (binary)
corresponding to 5-dB reduction.
Automated DC Offset Calibration
The TRF371125 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q
paths. The internal calibration requires a clock in order to function. The TRF371125 can use the internal
relaxation oscillator or the external SPI clock. Using the internal oscillator is the preferred method, which is
selected by setting the Cal_Sel_Clk (register 2, bit 28) to 1. The internal oscillator frequency is set through the
Osc_Trim bits (register 2, bits ). The frequency of the oscillator is detailed in Table 7; however, it is
expected the actual frequency of operation can vary plus or minus 35% due to process variations. The oscillator
frequency can be monitored on the READBACK pin when the Osc_Test register (Register 1, bit 29) is set to 1.
Table 7. Internal Oscillator Frequency Control
Osc_Trim
Osc_Trim
Osc_Trim
FREQUENCY
0
0
0
300 kHz
0
0
1
500 kHz
0
1
0
700 kHz
0
1
1
900 kHz
1
0
0
1.1 MHz
1
0
1
1.3 MHz
1
1
0
1.5 MHz
1
1
1
1.8 MHz
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The default setting of these registers corresponds to a 900-kHz oscillator frequency. This is sufficient for
autocalibration; modification is not required except for faster calibration convergence.
The output full-scale range of the internal dc offset correction DACs is programmable (IDET_B
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