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TRF3765
SLWS230E – SEPTEMBER 2011 – REVISED DECEMBER 2015
TRF3765 Integer-N/Fractional-N PLL With Integrated VCO
1 Features
3 Description
•
•
The TRF3765 is a wideband Integer-N/Fractional-N
frequency synthesizer with an integrated, wideband
voltage-controlled oscillator (VCO). Programmable
output dividers enable continuous frequency
coverage from 300 MHz to 4.8 GHz. Four separate
differential, open-collector RF outputs allow multiple
devices to be driven in parallel without the need of
external splitters.
1
•
•
•
•
•
•
•
Output Frequencies: 300 MHz to 4.8 GHz
Low-Noise VCO: –133 dBc/Hz
(1-MHz Offset, fOUT = 2.65 GHz)
13-/16-Bit Reference/Feedback Divider
25-Bit Fractional-N and Integer-N PLL
Low RMS Jitter: 0.35 ps
Input Reference Frequency Range:
0.5 MHz to 350 MHz
Programmable Output Divide-by-1/-2/-4/-8
Four Differential LO Outputs
External VCO Input with Programmable VCO
On/Off Control
The TRF3765 also accepts external VCO input
signals and allows on/off control through a
programmable control output. For maximum flexibility
and wide reference frequency range, wide-range
divide ratio settings are programmable and an offchip loop filter can be used.
The TRF3765 is available in an RHB-32 VQFN
package.
2 Applications
•
•
•
•
Wireless Infrastructure
Wireless Local Loop
Point-to-Point Wireless Access
Wireless MAN Wideband Transceivers
Device Information(1)
PART NUMBER
TRF3765
PACKAGE
VQFN (32)
BODY SIZE (NOM)
5.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Block Diagram
STROBED ATA CLOCK
LD
VCCs
EXTVCO_IN
Lock
Detect
GNDs
Serial
Interface
REF_IN
R Div
Prescaler
div p/p_+1
N-Divider
From
4WI
SD
Control
From
4WI
CP_OUT
Charge
Pump
PFD
VTUNE_IN
RF
Divider
From
4WI
Divide-by
1/2/4/8
RF4OUT
RF3OUT
RF2OUT
RF1OUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TRF3765
SLWS230E – SEPTEMBER 2011 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
5
6
7
7
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
4WI Timing: Write Operation.....................................
Readback 4WI Timing...............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 21
7.1 Overview ................................................................. 21
7.2 Functional Block Diagram ....................................... 21
7.3 Feature Description................................................. 22
7.4 Device Functional Modes........................................ 24
7.5 Register Maps ......................................................... 29
8
Application and Implementation ........................ 39
8.1 Application Information............................................ 39
8.2 Typical Application .................................................. 39
9 Power Supply Recommendations...................... 42
10 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 43
10.2 Layout Example .................................................... 43
11 Device and Documentation Support ................. 44
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
44
44
44
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed Bit27 through Bit30 of Table 7 From: B[25.21] To: B[30..27] .............................................................................. 29
Changes from Revision C (December 2011) to Revision D
Page
•
Changed the Description of Bit25 and Bit26 in Register 6 ................................................................................................... 36
•
Changed the Description of Bit27 and Bit28 in Register 6 ................................................................................................... 36
•
Changed the Bit Name of Bit31 From: DIV_MUX_BIAS_OVRT To: DIV_MUX_BIAS_OVRD in Register 6....................... 36
•
Changed VCC_OSC From: +3.3V/5.0V To: +3.3V, and VCC_TK From: +3.3V To: +3.3V/5.0V in .................................... 39
Changes from Revision B (November 2011) to Revision C
•
2
Page
Changed Reference Oscillator Parameters, Reference input impedance parameter rows in Electrical Characteristics
table ........................................................................................................................................................................................ 6
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SLWS230E – SEPTEMBER 2011 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
LD
GND
REF_IN
GND
VCC_PLL
VCC_CP
CP_OUT
CP_REF
32
31
30
29
28
27
26
25
RHB Package
32-Pin VQFN
Top View
STROBE
5
20
VCC_TK
READBACK
6
19
EXTVCO_CTRL
VCC_DIV
7
18
EXTVCO_IN
GND_BUFF1
8
17
GND_BUFF2
16
VCC_OSC
LO4_OUTP
21
15
4
LO4_OUTM
CLOCK
14
GND_OSC
LO3_OUTM
22
13
3
LO3_OUTP
DATA
12
VTUNE_IN
LO2_OUTP
23
11
2
LO2_OUTM
VCC_DIG
10
VTUNE_REF
LO1_OUTM
24
9
1
LO1_OUTP
GND_DIG
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
4
CLOCK
I
Serial programming interface, clock input
26
CP_OUT
O
Charge pump output
25
CP_REF
—
Charge pump reference ground
3
DATA
I
Serial programming interface, data input
19
EXTVCO_CTRL
O
Digital control to enable/disable external VCO
18
EXTVCO_IN
I
External VCO input
29
GND
—
Ground
31
GND
—
Ground
8
GND_BUFF1
—
Output buffer ground
17
GND_BUFF2
—
Output buffer ground
1
GND_DIG
—
Digital ground
22
GND_OSC
—
VCO core ground
32
LD
O
Lock detector output
10
LO1_OUTM
O
LO1 output: negative pin
9
LO1_OUTP
O
LO1 output: positive pin
11
LO2_OUTM
O
LO2 output: negative pin
12
LO2_OUTP
O
LO2 output: positive pin
14
LO3_OUTM
O
LO3 output: negative pin
13
LO3_OUTP
O
LO3 output: positive pin
15
LO4_OUTM
O
LO4 output: negative pin
16
LO4_OUTP
O
LO4 output: positive pin
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SLWS230E – SEPTEMBER 2011 – REVISED DECEMBER 2015
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Pin Functions (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
6
READBACK
O
Serial programming interface, readback
30
REF_IN
I
Reference signal input
5
STROBE
I
Serial programming interface, latch enable
27
VCC_CP
—
Charge pump power supply
2
VCC_DIG
—
Digital power supply
7
VCC_DIV
—
Divider power supply
21
VCC_OSC
—
VCO core power supply
28
VCC_PLL
—
PLL power supply
20
VCC_TK
—
VCO LC tank power supply
23
VTUNE_IN
—
VCO control voltage
24
VTUNE_REF
—
VTUNE reference ground
4
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SLWS230E – SEPTEMBER 2011 – REVISED DECEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
All VCC pins except VCC_TK
–0.3
3.6
VCC_TK
–0.3
5.5
Digital I/O voltage
–0.3
VI + 0.5
V
Operating virtual junction temperature, TJ
–40
150
°C
Operating ambient temperature, TA
–40
85
°C
Storage temperature, Tstg
–40
150
°C
Supply voltage
(1)
(2)
(2)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
VCC
Power-supply voltage
3
3.3
3.6
UNIT
V
VCC_TK
3.3-V to 5.5-V power-supply voltage
3
3.3
5.5
V
TA
Operating ambient temperature
–40
85
°C
TJ
Operating virtual junction temperature
–40
150
°C
6.4 Thermal Information
TRF3765
THERMAL METRIC (1)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
31.6
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
21.6
°C/W
RθJB
Junction-to-board thermal resistance
5.6
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
5.5
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLWS230E – SEPTEMBER 2011 – REVISED DECEMBER 2015
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6.5 Electrical Characteristics
At TA = 25°C and power supply = 3.3 V, unless otherwise noted.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PARAMETERS
ICC
Total supply current
Internal VCO, 1 output buffer on, divide-by-1
115
Internal VCO, 4 output buffers on, divide-by-1
190
Internal VCO, 1 output buffer on, divide-by-8
120
Internal VCO, 4 output buffers on, divide-by-8
182
External VCO mode, 1 output buffer on, divide-by-1
mA
89
DIGITAL INTERFACE
VIH
High-level input voltage
2
VIL
Low-level input voltage
0
VOH
High-level output voltage
Referenced to VCC_DIG
VOL
Low-level output voltage
Referenced to VCC_DIG
3.3
0.8
0.8 × VCC
V
0.2 × VCC
REFERENCE OSCILLATOR PARAMETERS
fREF
Reference frequency
Reference input sensitivity
Reference input impedance
0.5 (1)
350 (1)
MHz
0.2
3.3
VPP
Parallel capacitance, 10 MHz
Parallel resistance, 10 MHz
2
pF
2500
Ω
PLL
fPFD
PFD frequency
ICP_OUT
65 (2)
0.5
Charge pump current
4WI programmable; ICP[4..0] = 00000
In-band normalized phase noise floor
Integer mode
(3)
MHz
1.94
mA
–221
dBc/Hz
INTERNAL VCO
fVCO
VCO frequency range
Divide-by-1
KV
VCO gain
VCP = 1 V
VCC_TK = 3.3 V
VCO free-running
phase noise,
fVCO = 2650 MHz
VCC_TK = 5 V
2400
4800
–65
At 10 kHz
–82
At 100 kHz
–110
At 1 MHz
–130
At 10 MHz
–149
At 40 MHz
–155
At 10 kHz
–89
At 100 kHz
–113
At 1 MHz
–133
At 10 MHz
–151
At 40 MHz
–156
Fractional mode, fOUT = 2.6 GHz, fPFD = 30.72 MHz (5)
0.36
Integer mode, fOUT = 2.6 GHz, fPFD = 1.6 MHz
0.52
MHz
MHz/V
dBc/Hz
dBc/Hz
CLOSED-LOOP PLL/VCO
Integrated RMS jitter (4)
ps
RF OUTPUT/INPUT
fOUT
PLO
Output frequency range
Output power
(6)
Divide-by-1
2400
4800
Divide-by-2
1200
2400
Divide-by-4
600
1200
Divide-by-8
300
600
Differential, divide-by-1, one output buffer on, maximum
BUFOUT_BIAS
External VCO input maximum frequency
20-dB gain loss, VCO pass-through, no PLL
External VCO input minimum frequency
20-dB gain loss, VCO pass-through, no PLL, divide-by-1
6.5
dBm
9000
MHz
15
MHz
0
dBm
External VCO input level
(1)
(2)
(3)
(4)
(5)
(6)
6
MHz
See Application Information for discussion of VCO calibration clock limitations on reference clock frequency.
See Application Information for discussion on PFD frequency selection and calibration logic frequency limitations.
See 4WI Register Descriptions for all possible programmable charge pump currents.
Integrated from 1 kHz to 10 MHz.
See Application Information for information on loop filter characteristics.
See Application Information for external output buffers details.
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6.6 4WI Timing: Write Operation
See Figure 1.
MIN
MAX
UNIT
th
Hold time, data to clock
20
ns
tsu1
Setup time, data to clock
20
ns
t(CH)
Clock low duration
20
ns
t(CL)
Clock high duration
20
ns
tsu2
Setup time, clock to enable
20
ns
t(CLK)
Clock period
50
ns
tw
Enable time
50
ns
tsu3
Setup time, latch to data
70
ns
6.7 Readback 4WI Timing
See Figure 2.
MIN
MAX
UNIT
th
Hold time, data to clock
20
ns
tsu1
Setup time, data to clock
20
ns
t(CH)
Clock low duration
20
ns
t(CL)
Clock high duration
20
ns
tsu2
Setup time, clock to enable
20
ns
tsu3
Setup time, enable to Readback clock
20
ns
td
Delay time, clock to Readback data output
10
ns
tw (1)
Enable time
50
ns
t(CLK)
Clock period
50
ns
(1)
Equals Clock period
tsu1
Register Write
t(CL)
t(CH)
1st
Write
Clock
Pulse
CLOCK
DATA
t(CLK)
th
DB0 (LSB)
Address Bit0
32nd
Write
Clock
Pulse
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
DB29
tsu3
DB30
DB31 (MSB)
tsu2
LATCH ENABLE
End of Write Cycle
Pulse
tw
Figure 1. 4WI Timing Diagram
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tsu1
Register Write
CLOCK
DATA
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t(CLK)
th
t(CL)
t(CH)
1st Write
Clock
Pulse
DB0 (LSB)
Address Bit0
DB1
Address Bit1
DB2
Address Bit2
DB3
Address Bit3
DB29
31st
Write
Clock
Pulse
DB31 (MSB)
DB30
LATCH ENABLE
tsu3
Readback
CLOCK
LATCH ENABLE
32nd
Write
Clock
Pulse
tsu2
1st Read
Clock
Pulse
End of Write Cycle
Pulse
32nd
Read
Clock
Pulse
2nd Read
Clock
Pulse
33rd
Read
Clock
Pulse
td
tw
READBACK DATA
Readback
Data Bit0
Read
back
Read
back
Data
Bit1
Data
Bit29
Readback
Data Bit30
Readback
Data Bit31
Figure 2. 4WI Readback Timing Diagram
8
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6.8 Typical Characteristics
Table 1. Table of Graphs
GRAPH NAME
FIGURE NO.
Open-Loop Phase Noise
vs Temperature (1)
Figure 3, Figure 4, Figure 5, Figure 6
Open-Loop Phase Noise
vs Voltage (1)
Figure 7, Figure 8, Figure 9, Figure 10
Open-Loop Phase Noise
vs Temperature
Open-Loop Phase Noise
vs Voltage (1) (2)
(1) (2)
Figure 11, Figure 12, Figure 13, Figure 14
(3)
Figure 19, Figure 20, Figure 21, Figure 22,
Figure 23, Figure 24, Figure 25
Figure 15, Figure 16, Figure 17, Figure 18
Closed-Loop Phase Noise
vs Temperature
Closed-Loop Phase Noise
vs Temperature (2) (3)
Closed-Loop Phase Noise
vs Divide Ratio (3)
Closed-Loop Phase Noise
vs Divide Ratio
Figure 26, Figure 27, Figure 28, Figure 29,
Figure 30, Figure 31, Figure 32
Figure 33
(2) (3)
Figure 34
(4)
Figure 35, Figure 36, Figure 37, Figure 38,
Figure 39, Figure 40, Figure 41
Closed-Loop Phase Noise
vs Temperature
Closed-Loop Phase Noise
vs Temperature (2) (4)
Closed-Loop Phase Noise
vs Divide Ratio (4)
Figure 49
Closed-Loop Phase Noise
vs Divide Ratio (2) (4)
Figure 50
PFD Spurs
vs Temperature
Figure 42, Figure 43, Figure 44, Figure 45,
Figure 46, Figure 47, Figure 48
(4)
Figure 51
Multiples of PFD Spurs (4)
Figure 52, Figure 53, Figure 54
Multiples of PFD Spurs (4) (5)
Fractional Spurs
Figure 55
vs LO Divider (3)
Figure 56
Fractional Spurs
vs RF Divider and Prescaler
Fractional Spurs
vs Temperature (3)
(3)
Figure 58
Multiples of PFD Spurs (3)
LO Harmonics
Figure 57
Figure 59
(4)
Figure 60
Output Power with Multiple Buffers (4)
Figure 61, Figure 62
Output Power
vs Output Port (4)
Figure 63
Output Power
vs Buffer Bias
(4)
Figure 64
VCO Gain (Kv)
vs Frequency
(1)
(2)
(3)
(4)
(5)
Figure 65
VCO_TRIM = 32, VTUNE_IN = 1.1 V, CP_TRISTATE = 3 (3-state), and CAL_BYPASS = On.
VCO_BIAS = 600 µA.
Reference frequency = 61.44 MHz; PFD frequency = 30.72 MHz.
Reference frequency = 40 MHz; PFD frequency = 1.6 MHz.
Performance change at frequencies above 1500 MHz results from PLL_DIV_SEL changing from divide-by-1 to divide-by-2.
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−10
−10
TA = −40°C
TA = 25°C
TA = 85°C
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −49.8
10kHz = −83
100kHz = −109.6
1MHz = −130.1
10MHz = −149
*See Note 1
−120
−130
−140
−150
−160
1k
10k
VCO Frequency = 3400 MHz
VCO_SEL = 1
VCC_TK = 3.3 V
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 2650 MHz
VCO_SEL = 0
VCC_TK = 3.3 V
−50
TA = −40°C
TA = 25°C
TA = 85°C
−20
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −45.1
10kHz = −81.6
100kHz = −107.9
1MHz = −128.1
10MHz = −147.3
*See Note 1
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
−160
40M
1k
10k
100k
1M
Frequency (Hz)
10M
40M
G001
Figure 3. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 0 and VCC_TK = 3.3 V)
G002
Figure 4. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 1 and VCC_TK = 3.3 V)
−10
−10
TA = −40°C
TA = 25°C
TA = 85°C
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −50.7
10kHz = −83.31
100kHz = −107.9
1MHz = −128.0
10MHz = −146.9
*See Note 1
−120
−130
−140
−150
−160
1k
10k
VCO Frequency = 4800 MHz
VCO_SEL = 3
VCC_TK = 3.3 V
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 4000 MHz
VCO_SEL = 2
VCC_TK = 3.3 V
−50
TA = −40°C
TA = 25°C
TA = 85°C
−20
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −38.3
10kHz = −70.6
100kHz = −104.2
1MHz = −125.5
10MHz = −145.2
*See Note 1
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
−160
40M
1k
10k
100k
1M
Frequency (Hz)
10M
40M
G003
Figure 5. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 2 and VCC_TK = 3.3 V)
G004
Figure 6. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 3 and VCC_TK = 3.3 V)
−10
−10
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −49.8
10kHz = −83.0
100kHz = −109.6
1MHz = −130.1
10MHz = −149.0
*See Note 1
−120
−130
−140
−150
−160
1k
10k
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −45.1
10kHz = −81.6
100kHz = −107.7
1MHz = −128.1
10MHz = −147.3
*See Note 1
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
40M
−160
G005
Figure 7. Open-Loop Phase Noise vs voltage
(VCO_SEL = 0)
10
VCO Frequency = 3400 MHz
VCO_SEL = 1
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 2650 MHz
VCO_SEL = 0
−50
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
−20
1k
10k
100k
1M
Frequency (Hz)
10M
40M
G006
Figure 8. Open-Loop Phase Noise vs Voltage
(VCO_SEL = 1)
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−10
−10
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −50.7
10kHz = −83.3
100kHz = −107.9
1MHz = −128.0
10MHz = −147.4
*See Note 1
−120
−130
−140
−150
−160
1k
10k
VCO Frequency = 4800 MHz
VCO_SEL = 3
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 4000 MHz
VCO_SEL = 2
−50
Vcc = 3.0 V, Vcc_TK = 3.0 V
Vcc = 3.3 V, Vcc_TK = 3.3 V
Vcc = 3.6 V, Vcc_TK = 3.6 V
−20
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −37.3
10kHz = −71.0
100kHz = −104.0
1MHz = −125.5
10MHz = −145.2
*See Note 1
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
−160
40M
1k
10k
100k
1M
Frequency (Hz)
10M
40M
G007
Figure 9. Open-Loop Phase Noise vs Voltage
(VCO_SEL = 2)
G008
Figure 10. Open-Loop Phase Noise vs Voltage
(VCO_SEL = 3)
−10
−10
TA = −40°C
TA = 25°C
TA = 85°C
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −58.0
10kHz = −89.0
100kHz = −112.6
1MHz = −133.1
10MHz = −151.2
*See Notes 1and 2
−120
−130
−140
−150
−160
1k
10k
VCO Frequency = 3400 MHz
VCO_SEL = 1
VCC_TK = 5.0 V
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 2650 MHz
VCO_SEL = 0
VCC_TK = 5.0 V
−50
TA = −40°C
TA = 25°C
TA = 85°C
−20
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −48.8
10kHz = −80.4
100kHz = −110.5
1MHz = −130.9
10MHz = −149.7
*See Notes 1and 2
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
−160
40M
1k
10k
100k
1M
Frequency (Hz)
10M
40M
G009
Figure 11. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 0 and VCC_TK = 5 V)
G010
Figure 12. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 1 and VCC_TK = 5 V)
−10
−10
TA = −40°C
TA = 25°C
TA = 85°C
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −54.3
10kHz = −86.2
100kHz = −97.2
1MHz = −130.8
10MHz = −149.0
*See Notes 1and 2
−120
−130
−140
−150
−160
1k
10k
VCO Frequency = 4800 MHz
VCO_SEL = 3
VCC_TK = 5.0 V
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 4000 MHz
VCO_SEL = 2
VCC_TK = 5.0 V
−50
TA = −40°C
TA = 25°C
TA = 85°C
−20
−60
−70
−80
−90
−100
−110
Note: At 25°C
1kHz = −40.3
10kHz = −73.1
100kHz = −106.8
1MHz = −128.4
10MHz = −147.5
*See Notes 1and 2
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
40M
−160
G011
Figure 13. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 2 and VCC_TK = 5 V)
1k
10k
100k
1M
Frequency (Hz)
10M
40M
G012
Figure 14. Open-Loop Phase Noise vs Temperature
(VCO_SEL = 3 and VCC_TK = 5 V)
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−10
−10
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −58.0
10kHz = −88.4
100kHz = −112.8
1MHz = −133.1
10MHz = −151.2
*See Notes 1and 2
−120
−130
−140
−150
−160
1k
10k
VCO Frequency = 3400 MHz
VCO_SEL = 1
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 2650 MHz
VCO_SEL = 0
−50
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
−20
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −48.8
10kHz = −81.5
100kHz = −110.5
1MHz = −130.9
10MHz = −149.8
*See Notes 1and 2
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
−160
40M
1k
10k
100k
1M
Frequency (Hz)
10M
40M
G013
G014
Figure 15. Open-Loop Phase Noise vs Voltage
(VCO_SEL = 0)
Figure 16. Open-Loop Phase Noise vs Voltage
(VCO_SEL = 1)
−10
−10
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
−20
−30
−40
−40
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −54.3
10kHz = −86.2
100kHz = −110.5
1MHz = −131.2
10MHz = −149.0
*See Notes 1and 2
−120
−130
−140
−150
−160
1k
10k
VCO Frequency = 4800 MHz
VCO_SEL = 3
−50
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−30
VCO Frequency = 4000 MHz
VCO_SEL = 2
−50
Vcc = 3.0 V, Vcc_TK = 4.5 V
Vcc = 3.3 V, Vcc_TK = 5.0 V
Vcc = 3.6 V, Vcc_TK = 5.5 V
−20
−60
−70
−80
−90
−100
−110
Note: At 3.3 V
1kHz = −40.3
10kHz = −73.1
100kHz = −106.7
1MHz = −128.4
10MHz = −147.5
*See Notes 1and 2
−120
−130
−140
−150
100k
1M
Frequency (Hz)
10M
−160
40M
1k
10k
100k
1M
Frequency (Hz)
G015
Figure 18. Open-Loop Phase Noise vs Voltage
(VCO_SEL = 3)
−60
−60
Phase Noise (dBc/Hz)
−80
TA = −40°C
TA = 25°C
TA = 85°C
Fractional Mode (EN_FRAC = 1)
LO_Out = 942.5 MHz
−70
−80
Phase Noise (dBc/Hz)
Fractional Mode (EN_FRAC = 1)
LO_Out = 725 MHz
−70
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−160
*See Note 3
1k
10k
100k
1M
Frequency (Hz)
10M
40M
−170
*See Note 3
1k
G023
Figure 19. Closed-Loop Phase Noise vs Temperature
(725 MHz, VCC_TK = 3.3 V, Fractional Mode)
12
40M
G016
Figure 17. Open-Loop Phase Noise vs Voltage
(VCO_SEL = 2)
−170
10M
10k
100k
1M
Frequency (Hz)
10M
40M
G022
Figure 20. Closed-Loop Phase NoisE vs Temperature
(942.5 MHz, VCC_TK = 3.3 V, Fractional Mode)
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SLWS230E – SEPTEMBER 2011 – REVISED DECEMBER 2015
At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−60
−60
Phase Noise (dBc/Hz)
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
1k
−110
−120
−130
−140
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Note 3
1k
10k
G021
100k
1M
Frequency (Hz)
10M
40M
G020
Figure 21. Closed-Loop Phase Noise vs Temperature
(1880 MHz, VCC_TK = 3.3 V, Fractional Mode)
Figure 22. Closed-Loop Phase Noise vs Temperature
(2120 MHz, VCC_TK = 3.3 V, Fractional Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Fractional Mode (EN_FRAC = 1)
LO_Out = 3500 MHz
−70
Phase Noise (dBc/Hz)
Fractional Mode (EN_FRAC = 1)
LO_Out = 2650 MHz
−80
Phase Noise (dBc/Hz)
−90
−100
−160
*See Note 3
−70
−160
*See Note 3
1k
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Note 3
1k
10k
G017
100k
1M
Frequency (Hz)
10M
40M
G018
Figure 23. Closed-Loop Phase Noise vs Temperature
(2650 MHz, VCC_TK = 3.3 V, Fractional Mode)
Figure 24. Closed-Loop Phase Noise vs Temperature
(3500 MHz, VCC_TK = 3.3 V, Fractional Mode)
−60
−60
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Fractional Mode (EN_FRAC = 1)
LO_Out = 725 MHz
−70
Phase Noise (dBc/Hz)
Fractional Mode (EN_FRAC = 1)
LO_Out = 4750 MHz
−70
Phase Noise (dBc/Hz)
TA = −40°C
TA = 25°C
TA = 85°C
−150
−160
−170
Fractional Mode (EN_FRAC = 1)
LO_Out = 2120 MHz
−70
Phase Noise (dBc/Hz)
Fractional Mode (EN_FRAC = 1)
LO_Out = 1880 MHz
−70
−160
*See Note 3
1k
10k
100k
1M
Frequency (Hz)
10M
40M
−170
*See Notes 2 and 3
1k
G019
Figure 25. Closed-Loop Phase Noise vs Temperature
(4750 MHz, VCC_TK = 3.3 V, Fractional Mode)
10k
100k
1M
Frequency (Hz)
10M
40M
G030
Figure 26. Closed-Loop Phase Noise vs Temperature
(725 MHz, VCC_TK = 5 V, Fractional Mode)
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−60
−60
Phase Noise (dBc/Hz)
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
1k
−120
−130
−140
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Notes 2 and 3
1k
10k
G029
100k
1M
Frequency (Hz)
10M
40M
G028
Figure 28. Closed-Loop Phase Noise vs Temperature
(1880 MHz, VCC_TK = 5 V, Fractional Mode)
−60
−60
Fractional Mode (EN_FRAC = 1)
LO_Out = 2120 MHz
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Fractional Mode (EN_FRAC = 1)
LO_Out = 2650 MHz
−70
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−110
Figure 27. Closed-Loop Phase Noise vs Temperature
(942.5 MHz, VCC_TK = 5 V, Fractional Mode)
−80
−160
*See Notes 2 and 3
1k
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Notes 2 and 3
1k
10k
G027
100k
1M
Frequency (Hz)
10M
40M
G024
Figure 29. Closed-Loop Phase Noise vs Temperature
(2120 MHz, VCC_TK = 5 V, Fractional Mode)
Figure 30. Closed-Loop Phase Noise vs Temperature
(2650 MHz, VCC_TK = 5 V, Fractional Mode)
−60
−60
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Fractional Mode (EN_FRAC = 1)
LO_Out = 4750 MHz
−70
Phase Noise (dBc/Hz)
Fractional Mode (EN_FRAC = 1)
LO_Out = 3500 MHz
−70
Phase Noise (dBc/Hz)
−90
−100
−160
*See Notes 2 and 3
−70
−160
*See Notes 2 and 3
1k
10k
100k
1M
Frequency (Hz)
10M
40M
−170
*See Notes 2 and 3
1k
G025
Figure 31. Closed-Loop Phase Noise vs Temperature
(3500 MHz, VCC_TK = 5 V, Fractional Mode)
14
TA = −40°C
TA = 25°C
TA = 85°C
−150
−160
−170
Fractional Mode (EN_FRAC = 1)
LO_Out = 1880 MHz
−70
Phase Noise (dBc/Hz)
Fractional Mode (EN_FRAC = 1)
LO_Out = 942.5 MHz
−70
10k
100k
1M
Frequency (Hz)
10M
40M
G026
Figure 32. Closed-Loop Phase Noise vs Temperature
(4750 MHz, VCC_TK = 5 V, Fractional Mode)
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−60
−60
Phase Noise (dBc/Hz)
−80
−90
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−80
−100
−110
−120
−130
−140
−150
1k
10k
100k
1M
Frequency (Hz)
−120
−130
−140
10M
40M
*See Notes 2 and 3
1k
10k
G031
100k
1M
Frequency (Hz)
10M
40M
G032
Figure 34. Closed-Loop Phase Noise vs Divide Ratio
(VCC_TK = 5 V, Fractional Mode)
−60
−80
TA = −40°C
TA = 25°C
TA = 85°C
Integer Mode (EN_FRAC = 0)
LO_Out = 942.5 MHz
−70
−80
Phase Noise (dBc/Hz)
Integer Mode (EN_FRAC = 0)
LO_Out = 728 MHz
−70
Phase Noise (dBc/Hz)
−110
−170
−60
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−160
*See Note 4
1k
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Note 4
1k
10k
G039
100k
1M
Frequency (Hz)
10M
40M
G038
Figure 35. Closed-Loop Phase Noise vs Temperature
(728 MHz, VCC_TK = 3.3 V, Integer Mode)
Figure 36. Closed-Loop Phase Noise vs Temperature
(942.5 MHz, VCC_TK = 3.3 V, Integer Mode)
−60
−60
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Integer Mode (EN_FRAC = 0)
LO_Out = 2140 MHz
−70
Phase Noise (dBc/Hz)
Integer Mode (EN_FRAC = 0)
LO_Out = 1842.5 MHz
−70
Phase Noise (dBc/Hz)
−100
−160
*See Note 3
Figure 33. Closed-Loop Phase Noise vs Divide Ratio
(VCC_TK = 3.3 V, Fractional Mode)
−170
−90
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−150
−160
−170
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 3600 MHz
−70
Phase Noise (dBc/Hz)
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 3600 MHz
−70
−160
*See Note 4
1k
10k
100k
1M
Frequency (Hz)
10M
40M
−170
*See Note 4
1k
G037
Figure 37. Closed-Loop Phase Noise vs Temperature
(1842.5 MHz, VCC_TK = 3.3 V, Integer Mode)
10k
100k
1M
Frequency (Hz)
10M
40M
G036
Figure 38. Closed-Loop Phase Noise vs Temperature
(2140 MHz, VCC_TK = 3.3 V, Integer Mode)
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−60
−60
Phase Noise (dBc/Hz)
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
1k
−120
−130
−140
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Note 4
1k
10k
G033
100k
1M
Frequency (Hz)
10M
40M
G034
Figure 40. Closed-Loop Phase Noise vs Temperature
(3500 MHz, VCC_TK = 3.3 V, Integer Mode)
−60
−60
Integer Mode (EN_FRAC = 0)
LO_Out = 4800 MHz
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Integer Mode (EN_FRAC = 0)
LO_Out = 728 MHz
−70
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
−110
Figure 39. Closed-Loop Phase Noise vs Temperature
(2600 MHz, VCC_TK = 3.3 V, Integer Mode)
−80
−160
*See Note 4
1k
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Notes 2 and 4
1k
10k
G035
100k
1M
Frequency (Hz)
10M
40M
G046
Figure 41. Closed-Loop Phase Noise vs Temperature
(4800 MHz, VCC_TK = 3.3 V, Integer Mode)
Figure 42. Closed-Loop Phase Noise vs Temperature
(728 MHz, VCC_TK = 5 V, Integer Mode)
−60
−60
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Integer Mode (EN_FRAC = 0)
LO_Out = 1842.5 MHz
−70
Phase Noise (dBc/Hz)
Integer Mode (EN_FRAC = 0)
LO_Out = 942.5 MHz
−70
Phase Noise (dBc/Hz)
−90
−100
−160
*See Note 4
−70
−160
*See Notes 2 and 4
1k
10k
100k
1M
Frequency (Hz)
10M
40M
−170
*See Notes 2 and 4
1k
G045
Figure 43. Closed-Loop Phase Noise vs Temperature
(942.5 MHz, VCC_TK = 5 V, Integer Mode)
16
TA = −40°C
TA = 25°C
TA = 85°C
−150
−160
−170
Integer Mode (EN_FRAC = 0)
LO_Out = 3500 MHz
−70
Phase Noise (dBc/Hz)
Integer Mode (EN_FRAC = 0)
LO_Out = 2600 MHz
−70
10k
100k
1M
Frequency (Hz)
10M
40M
G044
Figure 44. Closed-Loop Phase Noise vs Temperature
(1842.5 MHz, VCC_TK = 5 V, Integer Mode)
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−60
−60
Phase Noise (dBc/Hz)
−80
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
1k
−110
−120
−130
−140
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Notes 2 and 4
1k
10k
G043
100k
1M
Frequency (Hz)
10M
40M
G040
Figure 45. Closed-Loop Phase Noise vs Temperature
(2140 MHz, VCC_TK = 5 V, Integer Mode)
Figure 46. Closed-Loop Phase Noise vs Temperature
(2600 MHz, VCC_TK = 5 V, Integer Mode)
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
−80
−90
−100
−110
−120
−130
−140
−150
TA = −40°C
TA = 25°C
TA = 85°C
−90
−100
−110
−120
−130
−140
−150
−160
−170
Integer Mode (EN_FRAC = 0)
LO_Out = 4800 MHz
−70
Phase Noise (dBc/Hz)
Integer Mode (EN_FRAC = 0)
LO_Out = 3500 MHz
−80
Phase Noise (dBc/Hz)
−90
−100
−160
*See Notes 2 and 4
−70
−160
*See Notes 2 and 4
1k
10k
100k
1M
Frequency (Hz)
10M
−170
40M
*See Notes 2 and 4
1k
10k
G041
100k
1M
Frequency (Hz)
10M
40M
G042
Figure 47. Closed-Loop Phase Noise vs Temperature
(3500 MHz, VCC_TK = 5 V, Integer Mode)
Figure 48. Closed-Loop Phase Noise vs Temperature
(4800 MHz, VCC_TK = 5 V, Integer Mode)
−60
−60
−80
−90
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−100
−110
−120
−130
−140
−150
−160
−170
10k
−80
−90
100k
1M
Frequency (Hz)
10M
40M
−110
−120
−130
−140
−150
−170
*See Notes 2 and 4
1k
G047
Figure 49. Closed-Loop Phase Noise vs Divide Ratio
(VCC_TK = 3.3 V, Integer Mode)
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−100
−160
*See Note 4
1k
Integer Mode (EN_FRAC = 0)
LO_Out = 3600 MHz
−70
Phase Noise(dBc/Hz) (dB)
Integer Mode (EN_FRAC = 0)
VCO Frequency = 3600 MHz
−70
Phase Noise (dBc/Hz)
TA = −40°C
TA = 25°C
TA = 85°C
−150
−160
−170
Integer Mode (EN_FRAC = 0)
LO_Out = 2600 MHz
−70
Phase Noise (dBc/Hz)
Integer Mode (EN_FRAC = 0)
LO_Out = 2140 MHz
−70
10k
100k
1M
Frequency (Hz)
10M
40M
G048
Figure 50. Closed-Loop Phase Noise vs Divide Ratio
(VCC_TK = 5 V, Integer Mode)
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−60
−60
TA = −40°C
TA = 25°C
TA = 85°C
−65
−70
−75
−75
−80
−80
−85
−85
Spur (dBc)
Spur (dBc)
−70
−90
−95
−100
−90
−95
−100
−105
−105
−110
−110
−115
−115
−120
−120
−125
−130
PFD Spur 1x = 1.6 MHz
PFD Spur 2x = 3.2 MHz
PFD Spur 3x = 4.8 MHz
PFD Spur 4x = 6.4 MHz
−65
Integer Mode (EN_FRAC = 0)
PFD Spur = 1.6 MHz
*See Note 4
0
−125
−130
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (MHz)
*See Note 4
0
Integer Mode (EN_FRAC = 0)
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Frequency (MHz)
G049
G050
Figure 51. PFD Spurs vs Temperature
(Integer Mode)
Figure 52. Multiples of PFD Spurs
(Integer Mode)
−60
−60
PFD Spur /8 = 0.2 MHz
PFD Spur /4 = 0.4 MHz
PFD Spur /2 = 0.8 MHz
PFD Spur /1 = 1.6 MHz
−65
−70
−75
−75
−80
−80
−85
−85
PFD Spur (dBc)
PFD Spur (dBc)
−70
PFD Spur /4 = 0.4 MHz
PFD Spur /2 = 0.8 MHz
PFD Spur /1 = 1.6 MHz
−65
−90
−95
−100
−105
−90
−95
−100
−105
−110
−110
−115
−115
−120
−120
−125
Integer Mode (EN_FRAC = 0)
LO_DIV = 8
*See Note 4
−130
300
350
400
450
500
Frequency (MHz)
550
−125
*See Note 4
−130
600
600
700
Integer Mode (EN_FRAC = 0)
LO_DIV = 4
800
900
1000
Frequency (MHz)
1100
1200
G051
G052
Figure 53. Multiples of PFD Spurs
(LO_DIV = 8, Integer Mode)
Figure 54. Multiples of PFD spurs
(LO_DIV = 4, Integer Mode)
−60
−45
PFD Spur /2 = 0.8 MHz
PFD Spur /1 = 1.6 MHz
−65
−55
−60
−75
−65
−85
−90
−95
−100
−105
−75
−80
−85
−90
−95
−100
−105
−110
−110
−115
−115
−120
*See Notes 4 and 5
−130
1200
1400
−120
Integer Mode (EN_FRAC = 0)
LO_DIV = 2
1600
1800
2000
Frequency (MHz)
2200
−125
2400
−130
G053
Figure 55. Multiples of PFD Spurs
(LO_DIV = 2, Integer Mode)
18
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 2703 at NFRAC = 0
−70
Fractional Spur (dBc)
PFD Spur (dBc)
−80
−125
LO_Div = 1
LO_Div = 2
LO_Div = 4
LO_Div = 8
−50
−70
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*See Note 3
0
5M
10M
15M
20M
25M
30M
Fractional PLL N Divider Value (NFRAC)
35M
G054
Figure 56. Fractional Spurs vs LO divider
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
−55
−60
PLL_DIV_SEL = 0 (Div1), PRSC_SEL = 1 (8/9)
PLL_DIV_SEL = 1 (Div2), PRSC_SEL = 1 (8/9)
PLL_DIV_SEL = 2 (Div4), PRSC_SEL = 0 (4/5)
−65
−70
−65
−75
Integer Mode (EN_FRAC = 0)
VCO Frequency = 2703.36 at Div1,8/9
VCO Frequency = 4730.88 at Div2,8/9
VCO Frequency = 3686.40 at Div4,4/5
−85
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 2703 at NFRAC = 0
−70
Fractional Spur (dBc)
−80
Fractional Spur (dBc)
TA = −40°C
TA = 25°C
TA = 85°C
−60
−90
−95
−100
−105
−110
−75
−80
−85
−90
−95
−115
−100
−120
−125
−130
−105
*See Note 3
0
*See Note 3
5M
10M
15M
20M
25M
30M
Fractional PLL N Divider Value (NFRAC)
−110
35M
0
5M
10M
15M
20M
25M
30M
Fractional PLL N Divider Value (NFRAC)
35M
G055
G056
Figure 57. Fractional Spurs vs RF Divider and Prescaler
Figure 58. Fractional Spurs vs Temperature
0
−80
1xPFD Spur = 30.72 MHz
2xPFD Spur = 61.44 MHz
3xPFD Spur = 92.16 MHz
4xPFD Spur = 122.88 MHz
−82.5
−10
−15
−20
−85
−25
Carrier Harmonics (dBc)
Fractional Spur (dBc)
2nd Harmonic
3rd Harmonic
4th Harmonic
−5
−87.5
−90
−92.5
−30
−35
−40
−45
−50
−55
−60
−65
−95
−70
−75
−97.5
*See Note 3
−100
0
−80
Fractional Mode (EN_FRAC = 1)
VCO Frequency = 2703 at NFRAC = 0
5M
10M
15M
20M
25M
30M
Fractional PLL N Divider Value (NFRAC)
−85
−90
35M
*See Note 4
0
Integer Mode (EN_FRAC = 0)
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
LO_OUT Frequency (MHz)
G057
G058
Figure 59. Multiples of PFD Spurs
(Fractional Mode)
Figure 60. LO Harmonics
7
7
PWD_BUFF1 = ON
PWD_BUFF1,2 = ON
PWD_BUFF1,2,3 = ON
PWD_BUFF1,2,3,4 = ON
6
5
4
4
LO_Out Power (dBm)
LO1_OUT Power (dBm)
5
3
2
1
3
2
1
0
0
−1
−1
−2
−2
*See Note 4
−3
TA = −40°C
TA = 25°C
TA = 85°C
6
0
Integer Mode (EN_FRAC = 0)
*See Note 4
−3
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
LO_OUT Frequency (MHz)
G059
Figure 61. Output Power on LO1_OUTP With Multiple
Buffers
0
Integer Mode (EN_FRAC = 0)
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
LO_OUT Frequency (MHz)
G060
Figure 62. Output Power With Multiple Buffers
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At TA = 25°C, VCC = 3.3 V, VCC_TK = 3.3 V, LO1_OUTP (single-ended), PWD_BUFF2,3,4 = off, VCO_BIAS = 400 µA;
BUFOUT_BIAS = 600 µA, all other registers set per recommended programming in Serial Programming Interface Register
Definitions, and standard operating condition, unless otherwise noted.
7
8
LO1_OUT
LO2_OUT
LO3_OUT
LO4_OUT
6
5
BUFOUT_BIAS = 600µA
BUFOUT_BIAS = 500µA
BUFOUT_BIAS = 400µA
BUFOUT_BIAS = 300µA
7
6
5
4
LO_Out Power (dBm)
LO_Out Power (dBm)
4
3
2
1
0
3
2
1
0
−1
−2
−3
−4
−1
−5
−6
−2
*See Note 4
−3
0
−7
Integer Mode (EN_FRAC = 0)
−8
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
LO_OUT Frequency (MHz)
*See Note 4
0
Integer Mode (EN_FRAC = 0)
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
LO_OUT Frequency (MHz)
G061
G062
Figure 63. Output Power vs Output Port
Figure 64. Output Power vs Buffer Bias
−30
VCO_SEL = 0
VCO_SEL = 1
VCO_SEL = 2
VCO_SEL = 3
−35
−40
−45
VTUNE_IN = 1V
CP_TRISTATE = 3
−50
Kv (MHz/V)
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
2000
2400
2800
3200 3600 4000 4400
VCO Frequency (MHz)
4800
5200
G063
Figure 65. VCO Gain (Kv) vs Frequency
20
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7 Detailed Description
7.1 Overview
The TRF3765 device features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift
register. There are a total of three signals that must be applied: the clock (CLOCK, pin 4), the serial data (DATA,
pin 3); and the latch enable (STROBE, pin 5).
The serial data (DB0-DB31) are loaded least significant bit (LSB) first, and read on the rising edge of CLOCK.
STROBE is asynchronous to the CLOCK signal, at its rising edge, the data in the shift register are loaded into
the selected internal register. Figure 1 shows the timing for the 4WI. 4WI Timing: Write Operation lists the 4WI
timing for the write operation.
7.2 Functional Block Diagram
STROBED ATA CLOCK
LD
VCCs
EXTVCO_IN
Lock
Detect
GNDs
Serial
Interface
REF_IN
R Div
Prescaler
div p/p_+1
N-Divider
From
4WI
SD
Control
From
4WI
CP_OUT
Charge
Pump
PFD
VTUNE_IN
RF
Divider
From
4WI
Divide-by
1/2/4/8
RF4OUT
RF3OUT
RF2OUT
RF1OUT
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7.3 Feature Description
7.3.1 Lock Detect
The lock detect signal is generated in the phase frequency detector by comparing the VCO target phase against
the VCO actual phase. When the two compared phase signals remain aligned for several clock cycles, an
internal signal goes high. The precision of this comparison is controlled through the LD_ANA_PREC bits. This
internal signal is then averaged and compared against a reference voltage to generate the LD signal. The
number of averages used is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked,
LD is high. When the VCO frequency is not locked, LD may pulse high or exhibit periodic behavior.
By default, the internal lock detect signal is made available on the LD pin. Register bits MUX_CTRL_n can be
used to control a multiplexer to output other diagnostic signals on the LD output. The LD control signals are
shown in Table 2. Table 3 shows the LD Control Signal Mode settings.
Table 2. LD Control Signals
ADJUSTMENT
REGISTER BITS
Lock detect precision
LD_ANA_PREC_0
Reg4B19
BIT ADDRESSING
Unlock detect precision
LD_ANA_PREC_1
Reg4B20
LD averaging count
LD_DIG_PREC
Reg4B24
Diagnostic output
MUX_CTRL_n
Reg6B[18..16]
Table 3. LD Control Signal Mode Settings
CONDITION
RECOMMENDED SETTINGS
Integer mode
LD_ANA_PREC_0 = 0
LD_ANA_PREC_1 = 0
LD_DIG_PREC = 0
Fractional mode
LD_ANA_PREC_0 = 1
LD_ANA_PREC_1 = 1
LD_DIG_PREC = 0
7.3.2 LO Divider
The LO divider is shown in Figure 66. It frequency divides the VCO output. Only one of the dividers operates at a
time, and the appropriate output is selected by a mux. DIVn bits are controlled through LO_DIV_SEL_n. The
output is buffered and provided on output pins LOn_OUT_P and LOn_OUT_N. Outputs are phase-locked but not
phase-matched. The output level is controlled through BUFOUT_BIAS.
BUFOUT_BIAS
LO_OUT1
DIV8
DIV4
DIV2
DIV1
PWD1
PWD_LO_DIV
LO_OUT2
VCO, P/N
Buffer
PWD2
Div2
LO_OUT3
Div4
PWD3
Div8
LO_OUT4
Speedup
Bias
LO_DIV_IB
PWD4
Figure 66. LO Divider
22
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LO_DIV_IB determines the bias level for the divider blocks. The SPEEDUP control is used to bypass a
stabilization resistor and reach the final bias level faster after a change in the divider selection. SPEEDUP should
be disabled during normal operation.
7.3.3 Selecting the VCO and VCO Frequency Control
To achieve a broad frequency tuning range, the TRF3765 includes four VCOs. Each VCO is connected to a bank
of coarse tuning capacitors that determine the valid operating frequency of each VCO. For any given frequency
setting, the appropriate VCO and capacitor array must be selected.
The device contains logic that automatically selects the appropriate VCO and capacitor bank. Set bit EN_CAL to
initiate the calibration algorithm. During the calibration process, the device selects a VCO and a tuning capacitor
state such that VTUNE matches the reference voltage set by VCO_CAL_REF_n. Accuracy of the resulting tuning
word is increased through bits CAL_ACC_n at the expense of increased calibration time. A calibration begins
immediately when EN_CAL is set; as a result, all registers must contain valid values before a calibration is
initiated.
The calibration logic is driven by a CAL_CLK clock derived from the phase frequency detector frequency scaled
according to the setting in CAL_CLK_SEL. Faster CAL_CLK frequencies enable faster calibrations, but the logic
is limited to clock frequencies up to 600 kHz. The flag R_SAT_ERR is evaluated during the calibration process to
indicate calibration counter overflow errors, which occur if CAL_CLK runs too quickly. If R_SAT_ERR is set
during a calibration, the resulting calibration is not valid and CAL_CLK_SEL must be used to slow the CAL_CLK.
CAL_CLK frequencies should not be set below 0.05 MHz. Reference clock frequency is usually limited by the
calibration logic. fREF × CAL_CLK_SEL scaling factor > 0.01 MHz and fREF/(CAL_CLK_SEL scaling factor × fPFD)
< 8000 are required. For example, with fREF = 61.44 MHz, fPFD = 30.72 MHz and CAL_CLK_SEL at 1/128,
61.44/128 = 0.5 > 0.01 and 61.44/(30.72 × 1/128) = 256 < 8000.
When VCOSEL_MODE is 0, the device automatically selects both the VCO and capacitor bank within 46
CAL_CLK cycles. When VCOSEL_MODE is 1, the device uses the VCO selected in VCO_SEL_0 and
VCO_SEL_1 and automatically selects the capacitor array within 34 CAL_CLK cycles. The VCO and capacitor
array settings that result from a calibration cannot be read from the VCO_SEL_n and VCO_TRIM_n bits in
Registers 2 and 7. These settings can only be read from Register 0.
Automatic calibration can be disabled by setting CAL_BYPASS to 1. In this manual calibration mode, the VCO is
selected through register bits VCO_SEL_n, while the capacitor array is selected through register bits
VCO_TRIM_n. Calibration modes are summarized in Table 4. After calibration is complete, the PLL is released
from calibration mode and reaches phase lock.
Table 4. VCO Calibration Modes
CAL_BYPASS
VCOSEL_MODE
MAX CYCLES
CAL_CLK
CAPACITOR
ARRAY
0
0
46
0
1
34
VCO_SEL_n
Automatic
1
don't care
N/A
VCO_SEL_n
VCO_TRIM_n
VCO
Automatic
During the calibration process, the TRF3765 scans through many frequencies. RF and LO outputs should be
disabled until calibration is complete. At power-up, the RF and LO output are disabled by default. Once a
calibration has been performed at a given frequency setting, the calibration remains valid over all operating
temperature conditions.
7.3.4 External VCO
An external LO or VCO signal may be applied. EN_EXTVCO powers the input buffer and selects the buffered
external signal instead of an internal VCO. Dividers, phase-frequency detector, and charge pump remain enabled
and may be used to control VTUNE or an external VCO. NEG_VCO must correspond to the sign of the external
VCO tuning characteristic. EXT_VCO_CTRL = 1 asserts a logic 1 output level at the corresponding output pin.
This configuration can be used to enable or disable the external VCO circuit or module.
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7.4 Device Functional Modes
7.4.1 VCO_TEST_MODE
Setting VCO_TEST_MODE forces the currently selected VCO to the edge of its frequency range by
disconnecting the charge pump input from the phase detector and loop filter, and forcing its output high or low.
The upper or lower edge of the VCO range is selected through COUNT_MODE_MUX_SEL.
VCO_TEST_MODE also reports the value of a frequency counter in COUNT, which can be read back in Register
0. COUNT reports the number of digital N divider cycles in the PLL, directly related to the period of fN, that occur
during each CAL_CLK cycle. Counter operation is initiated through the bit EN_CAL. Table 5 summarizes the
settings for VCO_TEST_MODE.
Table 5. VCO_TEST_MODE Settings
VCO_TEST_MODE
COUNT_MODE_MUX_SEL
VCO OPERATION
REGISTER 0 B[30..13]
B[30..24] = undefined
B[23..22] = VCO_SEL selected during autocal
B21 = undefined
B[20..15] = VCO_TRIM selected during autocal
B[14..13] = undefined
0
Don't care
Normal
1
0
Max frequency
B[30..13] = Max frequency counter
1
1
Min frequency
B[30..13] = Min frequency counter
7.4.2 Readback Mode
Register 0 functions as a readback register. The TRF3765 implements the capability to read back the content of
any serial programming interface register by initializing Register 0.
Each read-back operation consists of two phases: a write followed by the actual reading of the internal data. This
sequence is described in the timing diagram (see Figure 2). During the write phase, a command is sent to
TRF3765 Register 0 to set it to readback mode and to specify which register is to be read. In the proper reading
phase, at each rising clock edge, the internal data are transferred to the READBACK pin where it can be read at
the following falling edge (LSB first). The first clock after the latch enable STROBE, pin 5, goes high (that is, the
end of the write cycle) is idle and the following 32 clock pulses transfer the internal register contents to the
READBACK pin (pin 6).
7.4.3 Integer and Fractional Mode Selection
The PLL is designed to operate in either Integer mode or Fractional mode. If the desired local oscillator (LO)
frequency is an integer multiple of the phase frequency detector (PFD) frequency, fPFD, then Integer mode can be
selected. The normalized in-band phase noise floor in Integer mode is lower than in Fractional mode. In Integer
mode, the feedback divider is an exact integer, and the fraction is zero. While operating in Integer mode, the
register bits corresponding to the fractional control are don’t care.
In Fractional mode, the feedback divider fractional portion is non-zero on average. With 25-bit fractional
resolution, RF stepsize fPFD/225 is less than 1 Hz with a fPFD up to 33 MHz. The appropriate fractional control bits
in the serial register must be programmed.
24
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7.4.4 PLL Architecture
Figure 67 shows a diagram of the PLL loop.
EXT_VCO
LO1
VCO0
fREF
REFIN
Divide by
R
LO2
fPFD
Phase Frequency
Detector and
Charge Pump
fCOMP
Loop Filter
Z(f)
CP_OUT
Divide-by
1/2/4/8
VCO1
VTUNE
fVCO
LO3
VCO2
LO4
VCO3
RF
Divider
Dig Divider
Divide-by
NF
fN
Prescaler
4/5 or 8/9
Divide-by
1/2/4
NINT and NFRAC Dividers
Figure 67. PLL Architecture
The output frequency is given by Equation 1:
fREF
NFRAC
fVCO =
(PLL_DIV_SEL) NINT +
RDIV
225
(1)
The rate at which phase comparison occurs is fREF/RDIV. In Integer mode, the fractional setting is ignored and
Equation 2 is applied.
fVCO
= NINT ´ PLL_DIV_SEL
fPFD
(2)
The feedback divider block consists of a programmable RF divider, a prescaler divider, and an NF divider. The
prescaler can be programmed as either a 4/5 or an 8/9 prescaler. The NF divider includes an A counter and an
M counter.
7.4.4.1 Selecting PLL Divider Values
Operation of the PLL requires the LO_DIV_SEL, RDIV, PLL_DIV_SEL, NINT, and NFRAC bits to be calculated.
The LO or mixer frequency is related to fVCO according to divide-by-1/-2/-4/-8 blocks and the operating range of
fVCO.
a. LO_DIV_SEL
1 2400 MHz £ fRF £ 4800 MHz
LO_DIV_SEL =
2
1200 MHz £ fRF £ 2400 MHz
3
600 MHz £ fRF £ 1200 MHz
4
300 MHz £ fRF £ 600 MHz
Therefore:
fVCO = LO_DIV_SEL ´ fRF
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b. PLL_DIV_SEL
Given fVCO, select the minimum value for PLL_DIV_SEL so that the programmable RF divider limits the input
frequency into the prescaler block, fPM, to a maximum of 3000 MHz.
PLL _ DIV _ SEL = min(1, 2, 4) such that fPM ≤ 3000 MHz
This calculation can be restated as Equation 3.
PLL_DIV_SEL = Ceiling
(
LO_DIV_SEL ´ fRF
3000 MHz
(
(3)
Higher values of fPFD correspond to better phase noise performance in Integer mode or Fractional mode.
fPFD, along with PLL_DIV_SEL, determines the fVCO stepsize in Integer mode. Therefore, in Integer mode,
select the maximum fPFD that allows for the required RF stepsize, as shown by Equation 4.
fVCO, Stepsize
f
´ LO_DIV_SEL
= RF, Stepsize
fPFD =
PLL_DIV_SEL
PLL_DIV_SEL
(4)
In Fractional mode, a small RF stepsize is accomplished through the Fractional mode divider. A large fPFD
should be used to minimize the effects of fractional controller noise in the output spectrum. In this case, fPFD
may vary according to the reference clock and fractional spur requirements; for example, fPFD = 20 MHz.
c. RDIV, NINT, NFRAC, PRSC_SEL
fREF
RDIV =
fPFD
(
NINT = floor
fVCORDIV
fREFPLL_DIV_SEL
NFRAC = floor
((
(
fVCORDIV
fREFPLL_DIV_SEL
(
- NINT 225
(
The P/(P+1) programmable prescaler is set to 8/9 or 4/5 through the PRSC_SEL bit. To allow proper
fractional control, set PRSC_SEL according to Equation 5.
8
NINT ³ 75 in Fractional Mode or NINT ³ 72 in Integer mode
9
PRSC_SEL =
4
23 £ NINT < 75 in Fractional mode or 20 £ NINT < 72 in Integer mode
5
(5)
The PRSC_SEL limit at NINT < 75 applies to Fractional mode with third-order modulation. In Integer mode,
the PRSC_SEL = 8/9 should be used with NINT as low as 72. The divider block accounts for either value of
PRSC_SEL without requiring NINT or NFRAC to be adjusted. Then, calculate the maximum frequency to be
input to the digital divider at fN. Use the lower of the possible prescaler divide settings, P = (4,8), as shown
by Equation 6.
fVCO
fN,Max =
PLL_DIV_SEL ´ P
(6)
Verify that the frequency into the digital divider, fN, is less than or equal to 375 MHz. If fN exceeds 375 MHz,
choose a larger value for PLL_DIV_SEL and recalculate fPFD, RDIV, NINT, NFRAC, and PRSC_SEL.
26
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7.4.4.2 Setup Example for Integer Mode
Suppose the following operating characteristics are desired for Integer mode operation:
• fREF = 40 MHz (reference input frequency)
• Step at RF = 2 MHz (RF channel spacing)
• fRF = 1600 MHz (RF frequency)
The VCO range is 2400 MHz to 4800 MHz. Therefore:
• LO_DIV_SEL = 2
• fVCO = LO_DIV_SEL × 1600 MHz = 3200 MHz
To keep the frequency of the prescaler below 3000 MHz:
• PLL_DIV_SEL = 2
The desired stepsize at RF is 2 MHz, so:
• fPFD = 2 MHz
• fVCO, stepsize = PLL_DIV_SEL × fPFD = 4 MHz
Using the reference frequency along with the required fPFD gives:
• RDIV = 20
• NINT = 800
NINT ≥ 75; therefore, select the 8/9 prescaler.
fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz
This example shows that Integer mode operation gives sufficient resolution for the required stepsize.
7.4.4.3 Setup Example for Fractional Mode
Suppose the following operating characteristics are desired for Fractional mode operation:
• fREF = 40 MHz (reference input frequency)
• Step at RF = 5 MHz (RF channel spacing)
• fRF = 1,600,000,045 Hz (RF frequency)
The VCO range is 2400 MHz to 4800 MHz. Therefore:
• LO_DIV_SEL = 2
• fVCO = LO_DIV_SEL × 1,600,000,045 Hz = 3,200,000,090 Hz
To keep the frequency of the prescaler below 3000 MHz:
• PLL_DIV_SEL = 2
Using a typical fPFD of 20 MHz:
• RDIV = 20
• NINT = 80
• NFRAC = 75
NINT ≥ 75; therefore, select the 8/9 prescaler.
fN,Max = 3200 MHz/(2 × 8) = 200 MHz < 375 MHz
The actual frequency at RF is:
• fRF = 1600000044.9419 Hz
For a frequency error of –0.058 Hz.
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7.4.5 Fractional Mode Setup
Optimal operation of the PLL in Fractional mode requires several additional register settings. Recommended
values are listed in Register Maps. Optimal performance may require tuning the MOD_ORD, ISOURCE_SINK,
and ISOURCE_TRIM values according to the chosen frequency band.
Table 6. Fractional Mode Register Settings
REGISTER BIT
EN_ISOURCE
EN_DITH
RECOMMENDED VALUE
Reg4B18
1
Reg4B25
1
MOD_ORD
Reg4B[27..26]
B[27..26] = [10]
DITH_SEL
Reg4B28
0
DEL_SD_CLK
Reg4B[30..29]
B[30..29] = [10]
EN_FRAC
Reg4B31
1
EN_LD_ISOURCE
Reg5B31
0
ISOURCE_SINK
Reg6B19
0
Reg6B[22..20]
B[22..20] = [100] or [111]; see
Typical Characteristics
Reg1B26
0
ISOURCE_TRIM
ICPDOUBLE
28
REGISTER ADDRESSING
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7.5 Register Maps
7.5.1 PLL 4WI Registers
7.5.1.1 Register 1
Figure 68. PLL 4WI Register 1
31
30
RSV
15
14
29
28
VCO CAL CLK
DIV/MULT
13
12
27
26
CP
DOUBLE
25
24
23
22
21
CHARGE PUMP CURRENT
11
10
9
8
REFERENCE CLOCK DIVIDER
7
6
20
VCO
NEG
5
4
19
REF
INV
18
RSV
17
16
REF CLOCK
DIV
3
2
1
REGISTER ADDRESS
0
Table 7. PLL 4WI Register 1
Bit
Field
Reset Value
Bit0
ADDR_0
1
Description
Bit1
ADDR_1
0
Bit2
ADDR_2
0
Bit3
ADDR_3
1
Bit4
ADDR_4
0
Bit5
RDIV_0
1
Bit6
RDIV_1
0
Bit7
RDIV_2
0
Bit8
RDIV_3
0
Bit9
RDIV_4
0
Bit10
RDIV_5
0
Bit11
RDIV_6
0
Bit12
RDIV_7
0
Bit13
RDIV_8
0
Bit14
RDIV_9
0
Bit15
RDIV_10
0
Bit16
RDIV_11
0
Bit17
RDIV_12
0
Bit18
RSV
0
Reserved
Bit19
REF_INV
0
Invert Reference Clock polarity; 1 = use falling edge
Bit20
NEG_VCO
1
VCO polarity control; 1= negative slope (negative KV)
Bit21
ICP_0
0
Bit22
ICP_1
1
Bit23
ICP_2
0
Bit24
ICP_3
1
Bit25
ICP_4
0
Bit26
ICPDOUBLE
0
Bit27
CAL_CLK_SEL_0
0
Bit28
CAL_CLK _SEL_1
0
Bit29
CAL_CLK _SEL_2
0
Bit30
CAL_CLK _SEL_3
1
Bit31
RSV
0
Register address bits
13-bit Reference Divider value
Program Charge Pump dc current, ICP
1.94 mA, B[25..21] = [00 000]
0.65 mA, B[25..21] = [11 111]
0.97 mA, default value, B[25..21] = [01 010]
1 = Set ICP to double the current
Multiplication or division factor to create VCO calibration clock from PFD
frequency
Fastest clock, B[25..21] = [00 000]
Slowest clock, B[25..21] = [11 111]
Reserved
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7.5.1.1.1 CAL_CLK_SEL[3..0]
Set the frequency divider value used to derive the VCO calibration clock from the phase detector frequency.
Table 8 shows the calibration clock scale factors.
Table 8. Calibration Clock Scale Factors
CAL_CLK_SEL
SCALING FACTOR
1111
1/128
1110
1/64
1101
1/32
1100
1/16
1011
1/8
1010
1/4
1001
1/2
1000
1
0110
2
0101
4
0100
8
0011
16
0010
32
0001
64
0000
128
7.5.1.1.2 ICP[4..0]
Set the charge pump current. Table 9 lists the charge pump current settings.
Table 9. Charge Pump Current Settings
30
ICP[4..0]
CURRENT (mA)
00 000
1.94
00 001
1.76
00 010
1.62
00 011
1.49
00 100
1.38
00 101
1.29
00 110
1.21
00 111
1.14
01 000
1.08
01 001
1.02
01 010
0.97
01 011
0.92
01 100
0.88
01 101
0.84
01 110
0.81
01 111
0.78
10 000
0.75
10 001
0.72
10 010
0.69
10 011
0.67
10 100
0.65
10 101
0.63
10 110
0.61
10 111
0.59
11 000
0.57
11 001
0.55
11 010
0.54
11 011
0.52
11 100
0.51
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Table 9. Charge Pump Current Settings (continued)
ICP[4..0]
CURRENT (mA)
11 101
0.5
11 110
0.48
11 111
0.47
7.5.1.2 Register 2
Figure 69. PLL 4WI Register 2
31
EN
CAL
15
30
29
CAL
ACCURACY
14
13
28
27
VCO
SEL
MODE
26
VCO SELECT
12
25
24
RSV
RSV
11
10
9
N-DIVIDER VALUE
8
23
PRESCAL
ER
SELE
CT
7
22
21
20
19
PLL DIVIDER
SETTING
6
5
18
17
16
N-DIVIDER VALUE
4
3
2
1
REGISTER ADDRESS
0
Table 10. PLL 4WI Register 2
Bit
Field
Reset Value
Bit0
ADDR_0
0
Description
Bit1
ADDR_1
1
Bit2
ADDR_2
0
Bit3
ADDR_3
1
Bit4
ADDR_4
0
Bit5
NINT_0
0
Bit6
NINT_1
0
Bit7
NINT_2
0
Bit8
NINT_3
0
Bit9
NINT_4
0
Bit10
NINT_5
0
Bit11
NINT_6
0
Bit12
NINT_7
1
Bit13
NINT_8
0
Bit14
NINT_9
0
Bit15
NINT_10
0
Bit16
NINT_11
0
Bit17
NINT_12
0
Bit18
NINT_13
0
Bit19
NINT_14
0
Bit20
NINT_15
0
Bit21
PLL_DIV_SEL0
1
Bit22
PLL_DIV_SEL1
0
Bit23
PRSC_SEL
1
Set prescaler modulus (0 → 4/5; 1 → 8/9)
Bit24
RSV
0
Reserved
Bit25
RSV
0
Reserved
Bit26
VCO_SEL_0
0
Bit27
VCO_SEL_1
1
Selects between the four integrated VCOs
00 = lowest frequency VCO; 11= highest frequency VCO
Bit28
VCOSEL_MODE
0
Single VCO auto-calibration mode (1 = active)
Bit29
CAL_ACC_0
0
Bit30
CAL_ACC_1
0
Error count during the cap array calibration
Recommended programming [00].
Bit31
EN_CAL
0
Register address bits
PLL N-divider division setting
Select division ratio of divider in front of prescaler
Execute a VCO frequency auto-calibration. Set to 1 to initiate a calibration.
Resets automatically.
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7.5.1.2.1 PLL_DIV
Select division ratio of divider in front of prescaler, according to Table 11.
Table 11. PLL_DIV Selection
PLL_DIV
FREQUENCY DIVIDER
00
1
01
2
10
4
7.5.1.2.2 VCOSEL_MODE
When VCOSEL_MODE is set to 1, the cap array calibration is executed on the VCO selected through bits
VCO_SEL[1:0].
7.5.1.3 Register 3
Figure 70. PLL 4WI Register 3
31
RSV
30
RSV
29
28
27
26
25
24
23
22
21
FRACTIONAL N-DIVIDER VALUE
15
14
13
12
11
10
9
8
FRACTIONAL N-DIVIDER VALUE
7
6
5
20
4
19
18
17
3
2
1
REGISTER ADDRESS
16
0
Table 12. PLL 4WI Register 3
32
Bit
Field
Reset Value
Bit0
ADDR_0
1
Bit1
ADDR_1
1
Bit2
ADDR_2
0
Bit3
ADDR_3
1
Bit4
ADDR_4
0
Bit5
NFRAC
0
Bit6
NFRAC
0
Bit7
NFRAC
0
Bit8
NFRAC
0
Bit9
NFRAC
0
Bit10
NFRAC
0
Bit11
NFRAC
0
Bit12
NFRAC
0
Bit13
NFRAC
0
Bit14
NFRAC
0
Bit15
NFRAC
0
Bit16
NFRAC
0
Bit17
NFRAC
0
Bit18
NFRAC
0
Bit19
NFRAC
0
Bit20
NFRAC
0
Bit21
NFRAC
0
Bit22
NFRAC
0
Bit23
NFRAC
0
Bit24
NFRAC
0
Bit25
NFRAC
0
Bit26
NFRAC
0
Bit27
NFRAC
0
Bit28
NFRAC
0
Bit29
NFRAC
0
Description
Register address bits
Fractional PLL N divider value
0 to 0.99999
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Table 12. PLL 4WI Register 3 (continued)
Bit
Field
Reset Value
Bit30
RSV
0
Reserved
Description
Bit31
RSV
0
Reserved
7.5.1.4 Register 4
Figure 71. PLL 4WI Register 4
31
EN
FRAC
T
MODE
30
29
28
27
ΔΣ MOD CONTROLS
26
25
24
23
ΔΣ MOD ORDER
15
14
13
12
POWER-DOWN OUTPUT
BUFFERS
11
10
22
21
20
19
18
PLL TESTS CONTROL
9
8
7
6
POWER-DOWN PLL BLOCKS
5
PD
PLL
4
17
16
EXT VCO
3
2
1
0
REGISTER ADDRESS
Table 13. PLL 4WI Register 4
Bit
Field
Reset Value
Bit0
ADDR_0
0
Description
Bit1
ADDR_1
0
Bit2
ADDR_2
1
Bit3
ADDR_3
1
Bit4
ADDR_4
0
Bit5
PWD_PLL
0
Power-down all PLL blocks (1 = off)
Bit6
PWD_CP
0
When 1, charge pump is off
Bit7
PWD_VCO
0
When 1, VCO is off
Bit8
PWD_VCOMUX
0
Power-down the four VCO mux blocks (1 = off)
Bit9
PWD_DIV124
0
Power-down programmable RF divider in PLL feedback path (1 = off)
Bit10
PWD_PRESC
0
Power-down programmable prescaler (1 = off)
Bit11
PWD_LO_DIV
1
Power-down LO divider block (1 = off)
Bit12
PWD_BUFF_1
1
Power-down LO output buffer 1 (1 = off)
Bit13
PWD_BUFF_2
1
Power-down LO output buffer 2 (1 = off)
Bit14
PWD_BUFF_3
1
Power-down LO output buffer 3 (1 = off)
Bit15
PWD_BUFF_4
1
Power-down LO output buffer 4 (1 = off)
Bit16
EN_EXTVCO
0
Enable external VCO input buffer (1 = enabled)
Bit17
EXT_VCO_CTRL
0
Can be used to enable/disable an external VCO through pin EXTVCO_CTRL
(1 = high).
Bit18
EN_ISOURCE
0
Enable offset current at Charge Pump output (to be used in Fractional mode
only; 1 = on).
Bit19
LD_ANA_PREC_0
0
Bit20
LD_ANA_PREC_1
0
Bit21
CP_TRISTATE_0
0
Bit22
CP_TRISTATE_1
0
Bit23
SPEEDUP
0
Speed up PLL block by bypassing bias stabilizer capacitors.
Bit24
LD_DIG_PREC
0
Lock detector precision
(increases sampling time if set to 1)
Bit25
EN_DITH
1
Enable ΔΣ modulator dither (1 = on)
Bit26
MOD_ORD_0
0
Bit27
MOD_ORD_1
1
ΔΣ modulator order (1 through 4). Not used in Integer mode.
First order, B[27..26] = [00]
Second order, B[27..26] = [01]
Third order, B[27..26] = [10]
Fourth order, B[27..26] = [11]
Register address bits
Control precision of analog lock detector
1 = low; 0 = high
Set the charge pump output into 3-state mode.
Normal, B[22..21] = [00]
Down, B[22..21] = [01]
Up, B[22..21] = [10]
3-state, B[22..21] = [11]
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Table 13. PLL 4WI Register 4 (continued)
Bit
Field
Reset Value
Description
Select dither mode for ΔΣ modulator
(0 = pseudo-random; 1 = constant)
Bit28
DITH_SEL
0
Bit29
DEL_SD_CLK_0
0
Bit30
DEL_SD_CLK_1
1
ΔΣ modulator clock delay. Not used in Integer mode.
Min delay = 00; Max delay = 11
Bit31
EN_FRAC
0
Enable Fractional mode (1 = fractional enabled)
7.5.1.5 Register 5
Figure 72. PLL 4WI Register 5
31
EN_L
D
ISRC
30
RSV
15
14
VCOBUF BIAS
29
28
27
VCO BIAS
VOLTAGE
13
26
VCOMUX
AMPL
12
11
VCO CURRENT
10
25
24
23
VCO CAL REF
9
8
PLL_R_TRIM
7
22
21
20
BIAS
SEL
RSV
RSV
6
5
VCO_R_TRIM
4
19
18
OUTBUF BIAS
17
16
VCOMUX BIAS
3
2
1
REGISTER ADDRESS
0
Table 14. PLL 4WI Register 5
34
Bit
Field
Reset Value
Bit0
ADDR_0
1
Description
Bit1
ADDR_1
0
Bit2
ADDR_2
1
Bit3
ADDR_3
1
Bit4
ADDR_4
0
Bit5
VCOBIAS_RTRIM_0
0
Bit6
VCOBIAS_RTRIM_1
0
Bit7
VCOBIAS_RTRIM_2
1
Bit8
PLLBIAS_RTRIM_0
0
Bit9
PLLBIAS_RTRIM_1
1
Bit10
VCO_BIAS_0
0
Bit11
VCO_BIAS_1
0
Bit12
VCO_BIAS_2
0
Bit13
VCO_BIAS_3
1
Bit14
VCOBUF_BIAS_0
0
Bit15
VCOBUF _BIAS_1
1
Bit16
VCOMUX_BIAS_0
0
Bit17
VCOMUX _BIAS_1
1
Bit18
BUFOUT_BIAS_0
1
Bit19
BUFOUT_BIAS_1
0
Bit20
RSV
0
Reserved
Bit21
RSV
1
Reserved
Bit22
VCO_CAL_IB
0
Select bias current type for VCO calibration circuitry
0 = PTAT; 1 = constant over temperature. Recommended programming [0].
Bit23
VCO_CAL_REF_0
0
Bit24
VCO_CAL_REF_1
0
Bit25
VCO_CAL_REF_2
1
Register address bits
VCO bias resistor trimming.
Recommended programming [100].
PLL bias resistor trimming.
Recommended programming [10].
VCO bias reference current.
300 μA, B[13..10] = [00 00]
600 μA, B[13..10] = [11 11]
Bias current varies directly with reference current
Recommended programming:
400 μA, B[13..10] = [0101] with VCC_TK = 3.3 V
600 μA, B[13..10] = [1111] with VCC_TK = 5.0V
VCO buffer bias reference current.
300 μA, B[15..14] = [00]
600 μA, B[15..14] = [11]
Bias current varies directly with reference current
Recommended programming [10]
VCO muxing buffer bias reference current.
300 μA, B[17..16] = [00]
600 μA, B[17..16] = [11]
Bias current varies directly with reference current
Recommended programming [10]
PLL output buffer bias reference current.
300 μA, B[19..18] = [00]
600 μA, B[19..18] = [11]
Bias current varies directly with reference current
VCO calibration reference voltage trimming.
0.9 V, B[25..23] = [000]
1.4 V, B[25..23] = [111]
Recommended programming 1.11 V, B[25..23] = [011]
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Table 14. PLL 4WI Register 5 (continued)
Bit
Field
Reset Value
Bit26
VCO_AMPL_CTRL_0
0
Bit27
VCO_AMPL_CTRL_1
1
Bit28
VCO_VB_CTRL_0
0
Bit29
VCO_VB_CTRL _1
1
Bit30
RSV
0
Reserved
1
Enable monitoring of LD to turn on ISOURCE when in frac-n mode
(EN_FRAC=1).
0 = ISOURCE set by EN_ISOURCE
1 = ISOURCE set by LD
Recommended programming [0]
Bit31
EN_LD_ISOURCE
Description
Adjust the signal amplitude at the VCO mux input.
[00] = maximum voltage swing
[11] = minimum voltage swing
Recommended programming [11]
VCO core bias voltage control
1.2 V, B[29..28] = [00]
1.35 V, B[29..28] = [01]
1.5 V, B[29..28] = [10]
1.65 V, B[29..28] = [11]
Recommended programming [01]
7.5.1.6 Register 6
Figure 73. PLL 4WI Register 6
31
VCO
BIAS
SEL
15
CAL
BYPA
SS
30
29
DC OFF REF
14
13
VCO
LD
TEST
MODE
MODE
28
27
VCO MUX
BIAS
12
11
26
25
24
LO DIV BIAS
10
23
8
21
20
OFFSET CURRENT
ADJUST
LO DIV
9
22
7
VCO CAP ARRAY CONTROL
6
5
RSV
RSV
19
18
ISRC
SINK
4
3
17
16
MUX CONTROL
2
1
0
REGISTER ADDRESS
Table 15. PLL 4WI Register 6
Bit
Field
Reset Value
Bit0
ADDR_0
0
Description
Bit1
ADDR_1
1
Bit2
ADDR_2
1
Bit3
ADDR_3
1
Bit4
ADDR_4
0
Bit5
RSV
0
Reserved
Bit6
RSV
0
Reserved
Bit7
VCO_TRIM_0
0
Bit8
VCO_TRIM_1
0
Bit9
VCO_TRIM_2
0
Bit10
VCO_TRIM_3
0
Bit11
VCO_TRIM_4
0
Bit12
VCO_TRIM_5
1
Bit13
EN_LOCKDET
0
Initiate automatic calibration if LD indicates loss of lock.
(1 = Initiate calibration if LD is low)
Bit14
VCO_TEST_MODE
0
Counter mode: measure maximum/minimum frequency of each VCO
Bit15
CAL_BYPASS
0
Bypass of VCO auto-calibration. When 1, VCO_TRIM and VCO_SEL bits are used to
select the VCO and the capacitor array setting
Bit16
MUX_CTRL_0
1
Bit17
MUX_CTRL_1
0
Bit18
MUX_CTRL_2
0
Bit19
ISOURCE_SINK
0
Register address bits
VCO capacitor array control bits; used in manual cal mode
Select signal for test output (pin 5, LD).
[000] = Ground
[001] = Lock detector
[010] = NDIV counter output
[011] = Ground
[100] = RDIV counter output
[101] = Ground
[110] = A_counter output
[111] = Logic high
Charge pump offset current polarity. 0 = source
ISOURCE current enabled by EN_ISOURCE.
Recommended programming [0].
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Table 15. PLL 4WI Register 6 (continued)
Bit
Field
Reset Value
Bit20
ISOURCE_TRIM_0
0
Bit21
ISOURCE_TRIM_1
0
Bit22
ISOURCE_TRIM_2
1
Bit23
LO_DIV_SEL_0
0
Bit24
LO_DIV_SEL_1
0
Bit25
LO_DIV_IB_0
0
Bit26
LO_DIV_IB_1
0
Bit27
DIV_MUX_REF
0
Bit28
DIV_MUX_REF
1
Bit29
DIV_MUX_OUT
0
Bit30
DIV_MUX_OUT
1
Bit31
DIV_MUX_BIAS_OVRD
0
Description
Adjust ISOURCE bias current.
Minimum value, ISOURCE_TRIM = 0, B[22..20] = [000]
Maximum value, ISOURCE_TRIM = 7, B[22..20] = [111]
ISOURCE current enabled by EN_ISOURCE.
Adjust LO path divider
Divide-by-1, [B24..23] =
Divide-by-2, [B24..23] =
Divide-by-4, [B24..23] =
Divide-by-8, [B24..23] =
[00]
[01]
[10]
[11]
Adjust LO divider bias current. [B26..25] =
[00] = 25 μA
[01] = 37.5 μA
[10] = 50 μA
[11] = 62.5 μA
Sets reference bias current of DIV_MUX buffer when bit 31=1;
[00] = 500 μA
[01] = 400 μA
[10] = 300 μA
[11] = 200 μA
Recommended programming [10]
Set multiply factor for DIV_MUX_REF current.
x16, B[30..29] = 00
x24, B[30..29] = 01
x32, B[30..29] = 10
x40, B[30..29] = 11
Recommended programming [10]
Overrides DIV_MUX auto-bias current control.
When set to 1, DIV_MUX bias current is set by [B30..27].
7.5.2 Readback from the Internal Register Banks
The TRF3765 integrates eight registers: Register 0 (000) to Register 7 (111). Registers 1 through 6 are used to
set up and control the TRF3765 functions, Register 7 is used for factory functions, and Register 0 is used for the
readback function, as shown in Readback Mode.
Register 0 must be programmed with a specific command that sets the TRF3765 into readback mode and
specifies the register to be read, according to the following parameters:
• Set B[31] to 1 to put TRF3765 into readback mode.
• Set B[30,28] equal to the address of the register to be read (000 to 111).
• Set B27 to control the VCO frequency counter in VCO test mode.
36
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7.5.2.1 Register 0 Write
Figure 74. Register 0 Write
31
30
RB_
ENAB
LE
15
29
28
RB_REG
14
13
12
27
COUN
T_
MODE
_
MUX_
SEL
26
11
10
N/C
25
24
23
22
21
20
19
18
17
16
N/C
9
8
7
6
5
4
3
2
1
REGISTER ADDRESS
0
Table 16. Register 0 Write
Type
Address
Data Field
Bit
Field
Reset Value
Bit0
ADDR
0
Bit1
ADDR
0
Bit2
ADDR
0
Bit3
ADDR
1
Bit4
ADDR
0
Bit5
N/C
0
Bit6
N/C
0
Bit7
N/C
0
Bit8
N/C
0
Bit9
N/C
0
Bit10
N/C
0
Bit11
N/C
0
Bit12
N/C
0
Bit13
N/C
0
Bit14
N/C
0
Bit15
N/C
0
Bit16
N/C
0
Bit17
N/C
0
Bit18
N/C
0
Bit19
N/C
0
Bit20
N/C
0
Bit21
N/C
0
Bit22
N/C
0
Bit23
N/C
0
Bit24
N/C
0
Bit25
N/C
0
Bit26
N/C
0
Bit27
COUNT_MODE_MUX
_SEL
0
Bit28
RB_REG
X
Bit29
RB_REG
X
Bit30
RB_REG
X
Bit31
RB_ENABLE
1
Description
Register 0 to be programmed to set the TRF3765 into readback mode.
Select Readback for VCO maximum frequency or minimum frequency.
0 = Maximum
1 = Minimum
Three LSBs of the address for the register that is being read
Register 1, B[30..28] = [000]
Register 7, B[30..28] = [111]
1 → Put the device into readback mode
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7.5.2.1.1 Register 0 Read
Figure 75. Register 0 Read
31
COUN
T
MODE
MUX_
SEL
30
29
28
27
26
25
24
12
R_SA
T_ER
R
11
22
COUNT910/VCO_SEL
COUNT11-17
15
14
13
COUNT0-7/VCO_TRIM
23
10
9
8
NOT USED
7
6
21
20
19
COUN
T8/
NU
5
CHIP_
ID
18
17
16
COUNT0-7/VCO_TRIM
4
3
2
1
REGISTER ADDRESS
0
Figure 76. PLL 4WI Register 6
Table 17. Register 0 Read
38
Bit
Field
Reset Value
Bit0
ADDR_0
0
Bit1
ADDR_1
0
Bit2
ADDR_2
0
Bit3
ADDR_3
1
Bit4
ADDR_4
0
Bit5
CHIP_ID
1
Bit6
NU
x
Bit7
NU
x
Bit8
NU
x
Bit9
NU
x
Bit10
NU
x
Bit11
NU
x
Bit12
R_SAT_ERR
x
Bit13
count_0/NU
x
Bit14
count_1/NU
x
Bit15
count_2/VCO_TRIM_0
x
Bit16
count_3/VCO_TRIM_1
x
Bit17
count_4/VCO_TRIM_2
x
Bit18
count_5/VCO_TRIM_3
x
Bit19
count_6/VCO_TRIM_4
x
Bit20
count_7/VCO_TRIM_5
x
Bit21
count_8/NU
x
Bit22
count_9/VCO_sel_0
x
Bit23
count_10/VCO_sel_1
x
Bit24
count
x
Bit25
count
x
Bit26
count
x
Bit27
count
x
Bit28
count
x
Bit29
count
x
Bit30
count
x
Bit31
COUNT_MODE_MUX_SEL
x
Description
Register address bits
Error flag for calibration speed
B[30..13] = VCO frequency counter high when
COUNT_MODE_MUX_SEL = 0 and VCO_TEST_MODE = 1
B[30..13] = VCO frequency counter low when
COUNT_MODE_MUX_SEL = 1 and VCO_TEST_MODE = 1
B[20..15] = Autocal results for VCO_TRIM
B[23..22] = Autocal results for VCO_SEL when VCO_TEST_MODE = 0
0 = Minimum frequency
1 = Maximum frequency
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TRF3765 is a wideband integer-N/Fractional-N frequency synthesizer with an integrated, wideband voltagecontrolled oscillator (VCO). Programmable output dividers enable continuous frequency coverage from 300 MHz
to 4.8GHz. Four separate differential, open-collector RF outputs allow multiple devices to be driven in parallel
without the need of external splitters. TRF3765 is applicable to the wireless infrastructure standards such as
CDMA, TDMA, WCDMA, LTE and Advanced-LTE. It can also be used in wireless point-to-point access and
wireless local loop communication links.
8.2 Typical Application
Figure 77 shows an example block diagram for multi-band and multi-mode for 2G, 3G, and 4G cellular
transmitters. By adopting DAC38J84 and TRF3720, number of transmitter can be increased up to 8 antenna
system as each of DAC38J84 can supports 2 transmitters of I/Q pair and each of TRF3765 can provide 4 high
sampling clocks with 4 DAC38J84 devices. TRF3720 is an IQ modulator with fully integrated PLL/VCO and LO
frequency ranges from 300 MHz to 4.8 GHz.
This is a good example of improved transmitter diversity to service multiple users simultaneously. The internal
PLL of TRF3765 can be used to generate four high sampling clocks up to 4.8 GHz.
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Typical Application (continued)
TRF3765
REF_IN
VCO, PFD, CP, Prescaler, Divider
RF1_out
RF2_out RF3_out
RF4_out
3.6864 Gsps
16-bit
8
Data
TRF3720
PA
TRF3720
PA
16-bit
ADC12J4000
16-bit
SYNC
16-bit
3.6864 Gsps
SYSREF
16-bit
8
Data
TRF3720
PA
TRF3720
PA
16-bit
ADC12J4000
16-bit
SYNC
16-bit
3.6864 Gsps
SYSREF
C
P
R
I
FPGA
16-bit
8
Data
TRF3720
PA
TRF3720
PA
16-bit
ADC12J4000
16-bit
SYNC
16-bit
3.6864 Gsps
SYSREF
16-bit
8
Data
TRF3720
PA
TRF3720
PA
16-bit
ADC12J4000
16-bit
SYNC
16-bit
Reference
Input
SYSREF
SYSREF
LMK04828
FPGA Clock
Reference
Clock
Figure 77. TRF3765 Application Block Diagram
40
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the input parameters in Table 18.
Table 18. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.3 V
Current
121 mA
Input reference frequency
122.88 MHz
Output frequency
900 MHz
Table 19. Termination Requirements and Interfacing
PIN
NAME
3
DATA
4WI data input: digital input, high impedance
DESCRIPTION
4
CLOCK
4WI clock input: digital input, high impedance
5
STROBE
6
READBACK
Readback output; digital output pins can source or sink up to 8 mA
of current
9 through 16
LO_OUT
Local oscillator output: open-collector output. A pullup resistor is
required, normally ac-coupled. Any unused output differential pairs
may be left open.
18
EXTVCO_IN
External local oscillator input: high impedance, normally ac-coupled
19
EXTVCO_CTRL
Power-down control pin for optional external VCO; digital output pins
can source or sink up to 8 mA of current
30
REF_IN
32
LD
4WI latch enable: digital input, high impedance
Reference clock input: high impedance, normally ac-coupled
Lock detector digital output, as configured by MUX_CTRL; digital
output pins can source or sink up to 8 mA of current
8.2.2 Detailed Design Procedures
8.2.2.1 Power Supply
A clean power supply is critical to optimal phase noise performance of synthesizer. Linear power supplies are the
best sources available. Switching power supplies degrade in-band phase noise by 10 dB compared to linear
laboratory supplies. VCC3 can be used to drive VCC_TK, a 3.3-V or 5-V tolerant supply on the TRF3765.
VCC_TK is normally driven by the 3.3 V VCC2 supply, but some applications perform better with 5 V supply on
VCC_TK. A power supply filter can be used for TRF3765 and this filter reduces in-band frequency noise from a
switching power supply so that external supply can drive 5 V on VCC_TK.
8.2.2.2 Loop Filter
Loop-filter components are also critical to optimal phase noise performance. The loop filter must be matched to
the selected phase noise frequency detector (PFD) frequency. To use different PFD frequency, the loop-filter
components must be updated. Below is an example of loop filter design.
8.2.2.3 Reference Clock
External oscillator or the output of PLL device can be installed for the reference clock input to TRF3765 device.
The external reference clock is AC-coupled to the TRF3765 input pin. The range is reference frequency is from
0.5 MHz to 350 MHz. The minimum of reference input sensitivity is 0.2 Vpp and 3.3 Vpp for the maximum value.
8.2.3 Application Curves
The phase noise performance of 900-MHz output is shown in Figure 78. Figure 79 shows phase noise
performances from different power supplies such as 3.3 V, 2.7 V, 2.5 V, 2.2 V, 2.1 V and 2 V at room
temperature.
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Figure 78. Phase Noise Curve for 900MHz
Figure 79. Different Supply vs Output Power at Different
Temperatures
9 Power Supply Recommendations
Power-supply distribution for the TRF3765 is shown in Table 20. Proper isolation and filtering of the supplies are
critical for low phase noise operation of the device. Each supply pin should be supplied with local decoupling
capacitance and isolated with a ferrite bead.
Table 20. Power-Supply Distribution
PINS
SUPPLY
BLOCKS
Fractional divider
2
VCC_DIG
7
VCC_DIV
20
VCC_TK
VCO tank
21
VCC_OSC
VCO bias
27
VCC_CP
N-Divider
LO_OUT buffers
LO 1/2/4/8 divider
Charge pump
4WI
LD
Prescaler
28
VCC_PLL
REF_IN buffer
ISource
RF-Divider
R-Divider
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10 Layout
10.1 Layout Guidelines
Layout of the application board significantly impacts the analog performance of the TRF3765 device. Noise and
high-speed signals should be prevented from leaking onto power-supply pins or analog signals. Follow these
recommendations:
• Place supply decoupling capacitors physically close to the device, on the same side of the board. Each
supply pin should be isolated with a ferrite bead.
• Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal
lines. Place reference plane vias or decoupling capacitors near any signal line reference transition.
• The pad on the bottom of the device must be electrically grounded. Connect GND pins directly to the pad on
the surface layer. Connect the GND pins and pad directly to surface ground where possible.
• Power planes should not overlap each other or high-speed signal lines.
• Isolate REF_IN routing from loop filter lines, control lines, and other high-speed lines.
See Figure 80 for an example of critical component layout (for the top PCB layer).
10.2 Layout Example
Figure 80. Layout of Critical TRF3765 Components
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TRF3765IRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TRF3765
IRHB
TRF3765IRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TRF3765
IRHB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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