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TS3DS10224
SCDS324E – AUGUST 2011 – REVISED OCT 2019
TS3DS10224 High-Speed Differential Crosspoint, 1:4 Differential Multiplexer and
Demultiplexer, 2 Channel Differential 1:2 Multiplexer and Demultiplexer, or Fan-Out Switch
1 Features
3 Description
•
The TS3DS10224 device is a bidirectional differential
crosspoint, 1:4, or 1:2 multiplexer and demultiplexer;
or fan-out switch for high-speed differential signal
applications (up to 720 Mbps). The TS3DS10224
logic table can route any input to any output creating
a wide range of possible switching or multiplexing
configurations. Common configurations include:
differential crosspoint switching, differential 1:4 mux,
or differential 2-channel 1:2 multiplexer and
demultiplexer. The TS3DS10224 offers a high BW of
1.2 GHz with channel RON of 13 Ω (typical).
•
•
•
The TS3DS10224 operates with a 3-V to 3.6-V power
supply. It features ESD protection of up to ±8-kV
contact discharge and 2-kV human-body model on its
I/O pins.
The TS3DS10224 provides fail-safe protection by
isolating the I/O pins with high impedance when the
power supply (VCC) is not present.
Device Information(1)
PART NUMBER
3.00 mm × 3.00 mm
Functional Block Diagram
OUTA1+
Differential Crosspoint Switching
Desktop and Notebook Computers
DisplayPort Auxiliary Channel Multiplexing
USB 2.0 Multiplexing
Netbooks, eBooks, and Tablets
BODY SIZE (NOM)
WQFN (20)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
TS3DS10224
Select A Input (SAI)
ENA
•
•
The TS3DS10224 can also be used to fan out a
differential signal pair to two ports simultaneously
(fan-out configuration). The BW performance is lower
in this configuration.
OUTA0+
OUTA0-
•
•
Can be configured for
– Differential Crosspoint Switching
– Differential Single Channel 1:4 Multiplexer and
Demultiplexer
– Differential 2-Channel 1:2 Multiplexer and
Demultiplexer
– Differential Fan-Out of Signal Pair to Two Ports
Simultaneously
Bidirectional Operation
Fail-Safe Protection: IOFF Protection Prevents
Current Leakage in Powered-Down State
(VCC = 0 V)
High BW (1.2 GHz Typical)
Low RON and CON:
– 13-Ω RON Typical
– 9-pF CON Typical
ESD Performance (I/O Pins)
– ±8-kV Contact Discharge (IEC61000-4-2)
– 2-kV Human-Body Model per JESD22-A114E
(to GND)
ESD Performance (All Pins)
– 2-kV Human-Body Model per JESD22-A114E
Small WQFN package (3.00 mm × 3.00 mm,
0.4-mm pitch)
OUTA1-
1
Select A Output (SAO)
INA+
INA-
1
1
0
0
Channel A
SAO
SAI
SBI
SBO
Channel B
1
ENB
Select B Output (SBO)
OUTB1+
Select B Input (SBI)
0
OUTB0+
OUTB0-
1
OUTB1-
0
INB+
INB-
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS3DS10224
SCDS324E – AUGUST 2011 – REVISED OCT 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics:
Differential 1:4 or 2‑Channel 1:2 Configurations........
6.6 Electrical Characteristics: Fan-Out 1:2
Configurations ............................................................
6.7 Switching Characteristics:
Differential 1:4 or 2‑Channel 1:2 Configurations........
6.8 Switching Characteristics: Fan-Out 1:2
Configurations ............................................................
6.9 Dynamic Characteristics:
Differential 1:4 or 2‑Channel 1:2 Configurations........
6.10 Dynamic Characteristics: Fan-Out 1:2
Configurations ............................................................
6.11 Typical Characteristics ............................................
7
8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
13
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Applications ................................................ 19
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
5
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
5
12 Device and Documentation Support ................. 25
5
6
6
6
7
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2019) to Revision E
•
Changed mapping for OUTB0, and OUTB1 in Table 6 ....................................................................................................... 18
Changes from Revision C (November 2017) to Revision D
•
Page
Changed Figure 2 .................................................................................................................................................................. 7
Changes from Revision B (December 2016) to Revision C
•
Page
Page
Changed columns OUTA1, OUTB0, and OUTB1 in Table 6 .............................................................................................. 18
Changes from Revision A (May 2013) to Revision B
Page
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table,
Detailed Description section, Application and Implementation section, Power Supply Recommendations section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section .................................................................................................................................................................................... 1
•
Added Thermal Information table ........................................................................................................................................... 4
•
Changed RθJA value From: 82.7 To: 45.2 ............................................................................................................................... 4
Changes from Original (June 2011) to Revision A
•
2
Page
Replaced 1 page preview with full document ......................................................................................................................... 1
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SCDS324E – AUGUST 2011 – REVISED OCT 2019
5 Pin Configuration and Functions
INA+
1
INA–
2
OUTA1+
OUTA1–
OUTA0+
OUTA0–
ENA
20
19
18
17
16
RUK Package
20-Pin WQFN
Top View
Thermal
Pad
15
SAO
14
SAI
13
VCC
SBI
GND
5
11
SBO
ENB
OUTB0–
OUTB0+
OUTB1–
OUTB1+
10
12
9
4
8
INB–
7
3
6
INB+
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
INA+
I/O
A channel signal path
2
INA–
I/O
A channel signal path
3
INB+
I/O
B channel signal path
4
INB–
I/O
B channel signal path
5
GND
—
Ground
6
OUTB1+
I/O
B channel signal path
7
OUTB1–
I/O
B channel signal path
8
OUTB0+
I/O
B channel signal path
9
OUTB0–
I/O
B channel signal path
10
ENB
I
Enable B channel: LOW = disables channel B and places the signal path in high impedance state,
HIGH = enables channel B.
11
SBO
I
Select B channel output, controls output selection: LOW = selects OUTB0 signals,
HIGH = selects OUTB1 signals.
12
SBI
I
Select B channel input, controls input selection: LOW = selects INA signals to pass through the B channel,
HIGH = selects INB signals to pass through the B channel.
13
VCC
—
14
SAI
I
Select A channel input, controls input selection: LOW = selects INB signals to pass through the A channel,
HIGH = selects INA signals to pass through the A channel.
15
SAO
I
Select A channel output, controls output selection: LOW = selects OUTA0 signals,
HIGH = selects OUTA1 signals.
16
ENA
I
Enable A channel: LOW = disables channel A and places the signal path in high impedance state,
HIGH = enables channel A.
17
OUTA0–
I/O
A channel signal path
18
OUTA0+
I/O
A channel signal path
19
OUTA1–
I/O
A channel signal path
20
OUTA1+
I/O
A channel signal path
Power supply
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
Supply voltage
Analog I/O voltage
(2) (3) (4)
Control input voltage (2) (4), VIN
MIN
MAX
UNIT
–0.3
4
V
–0.3
VCC + 0.3
V
–0.3
VCC + 0.3
V
±100
mA
±100
mA
150
°C
ON-state switch current (5), IIO
Continuous current through VCC or GND
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
VI and VO are used to denote specific conditions for VIO.
The input and output voltage rating may be exceeded if the input and output clamp-current ratings are observed.
II and IO are used to denote specific conditions for IIO.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 or
ANSI/ESDA/JEDEC JS-002 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). (1) (2)
MIN
MAX
3
3.6
V
High-level control input voltage
0.75 × VCC
VCC
V
VIL
Low-level control input voltage
0
0.6
V
VIO
Input and output voltage
0
VCC
V
TA
Operating free-air temperature
–40
85
°C
VCC
Supply voltage
VIH
(1)
(2)
UNIT
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or
Floating CMOS Inputs (SCBA004).
TI recommends pulling down to ground unused I/O pins through a 1-kΩ resistor.
6.4 Thermal Information
TS3DS10224
THERMAL METRIC (1)
RUK (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
45.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.8
°C/W
RθJB
Junction-to-board thermal resistance
17.1
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
17.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: Differential 1:4 or 2‑‑Channel 1:2 Configurations
Minimum and maximum values are at TA = –40°C to 85°C; typical values are at TA = 25°C (unless otherwise noted). (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
–1.2
–0.9
MAX
UNIT
VIK
Digital input clamp voltage
VCC = 3.6 V, II = –18 mA
IIN
Digital input leakage current
VCC = 3.6 V, VIN = 0 to 3.6 V
±2
µA
V
IOZ
OFF-state leakage current (2)
VCC = 3.6 V, VO = 0 V to 3.6 V, VI = 0 V, Switch OFF
±2
µA
IOFF
Power off leakage current
VCC = 0 V, VIN = VCC or GND,VIO = 0 V to 3.6 V
±5
µA
ICC
Supply current
VCC = 3.6 V, IIO = 0, Switch ON or OFF
50
100
µA
CIN
Digital input capacitance
VCC = 3.3 V, VIN = VCC or GND
3
5
pF
CIO(OFF)
OFF capacitance
VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch OFF
6
7
pF
CIO(ON)
ON capacitance
VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch ON
9
10
pF
VCC = 3.6 V, VI = VCC, IO = –30 mA
13
19
Ω
VCC = 3.3 V, VI = 0.5 V, IO = –30 mA
10
rON
ON-state resistance
ΔrON
ON-state resistance match
between channels
VCC = 3 V, VI = 0 to VCC, IO = –30 mA
2
2.5
Ω
rON(flat)
ON-state resistance flatness
VCC = 3 V, VI = 1.5 V and VCC, IO = –30 mA
4
6
Ω
MIN
TYP
MAX
–1.2
–0.9
(1)
(2)
Ω
VIN and IIN refer to the digital control input pins.
For I/O ports, the parameter IOZ includes the input leakage current.
6.6 Electrical Characteristics: Fan-Out 1:2 Configurations
TA = –40°C to 85°C; typical values are at VCC = 3.3 V, TA = 25°C (unless otherwise noted). (1)
PARAMETER
TEST CONDITIONS
UNIT
VIK
Digital input clamp voltage
VCC = 3.6 V, II = –18 mA
IIN
Digital input leakage current
VCC = 3.6 V, VIN = 0 to 3.6 V
±2
µA
IOZ
OFF-state leakage current (2)
VCC = 3.6 V, VO = 0 V to 3.6 V, VI= 0 V, Switch OFF
±2
µA
IOFF
Power off leakage current
VCC = 0 V, VIN = VCC or GND, VIO = 0 V to 3.6 V
±5
µA
ICC
Supply current
VCC = 3.6 V, IIO = 0, Switch ON or OFF
50
100
µA
CIN
Digital input capacitance
VCC = 3.3 V, VIN = VCC or GND
3
5
pF
CIO(OFF)
OFF capacitance
VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch OFF
6
7
pF
CIO(ON)
ON capacitance
VCC = 3.3 V, VIO = 3.3 V or 0, f = 10 MHz, Switch ON
12
13
pF
rON
ON-state resistance
VCC = 3.6 V, VI = VCC, IO = –30 mA
13
19
Ω
ΔrON
ON-state resistance match
between channels
VCC = 3 V, VI = 0 to VCC, IO = –30 mA
2
2.5
Ω
rON(flat)
ON-state resistance flatness
VCC = 3 V, VI = 1.5 V and VCC, IO = –30 mA
4
6
Ω
TYP
MAX
(1)
(2)
V
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
For I/O ports, the parameter IOZ includes the input leakage current.
6.7 Switching Characteristics: Differential 1:4 or 2‑‑Channel 1:2 Configurations
TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
UNIT
tpd
Propagation delay (1)
RL = 50 Ω, CL = 2 pF
50
tON
SAI, SAO, SBI, or SBO to OUTAx or OUTBx
RL = 50 Ω, CL = 2 pF
40
100
ns
tOFF
SAI, SAO, SBI, or SBO to OUTAx or OUTBx
RL = 50 Ω, CL = 2 pF
20
30
ns
tsk(o)
Timing difference between output channels (2)
RL = 50 Ω, CL = 2 pF
40
ps
tsk(p)
Timing difference between propagation delays (3)
RL = 50 Ω, CL = 2 pF
40
ps
(1)
(2)
(3)
ps
The propagation delay is the calculated RC time constant of the typical ON-State resistance of the switch and the specified load
capacitance when driven by an ideal voltage source(zero output impedance).
Output skew between center channel and any other channel.
Skew between opposite transitions of the same output ( |tPHL – tPLH| ).
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6.8 Switching Characteristics: Fan-Out 1:2 Configurations
TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
tpd
Propagation delay
RL = 50 Ω, CL = 2 pF
140
tON
SAI, SAO, SBI, or SBO to OUTAx or OUTBx
R = 50 Ω, CL = 2 pF
40
100
ns
tOFF
SAI, SAO, SBI, or SBO to OUTAx or OUTBx
RLL = 50 Ω, CL = 2 pF
20
30
ns
tsk(o)
Timing difference between output channels (2)
RL = 50 Ω, CL = 2 pF
60
ps
RL = 50 Ω, CL = 2 pF
60
ps
tsk(p)
(1)
(2)
(3)
Timing difference between propagation delays
(3)
ps
The propagation delay is the calculated RC time constant of the typical ON-State resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Output skew between center channel and any other channel.
Skew between opposite transitions of the same output ( |tPHL – tPLH| ).
6.9 Dynamic Characteristics: Differential 1:4 or 2‑‑Channel 1:2 Configurations
TA = –40°C to 85°C; typical values are at VCC = 3.3 V ± 10% and TA = 25°C (unless otherwise noted).
TYP
UNIT
BW
Bandwidth
PARAMETER
RL = 50 Ω, Switch ON
TEST CONDITIONS
1.2
GHz
OISO
OFF Isolation
RL = 50 Ω , f = 250 MHz
–30
dB
XTALK
Crosstalk
RL = 50 Ω , f = 250 MHz
–30
dB
TYP
UNIT
6.10 Dynamic Characteristics: Fan-Out 1:2 Configurations
TA = –40°C to 85°C; typical values are at VCC = 3.3 V ± 10% and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
BW
Bandwidth
RL = 50 Ω, Switch ON
500
MHz
OISO
OFF Isolation
RL = 50 Ω , f = 250 MHz
–30
dB
XTALK
Crosstalk
RL = 50 Ω , f = 250 MHz
–30
dB
6
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6.11 Typical Characteristics
6.11.1 Single-Channel 1:4 or Dual-Channel 1:2 Configurations
0
12
Single 1:4
-2
Dual 1:2
-4
Insertion Loss - dB
10
Ron - Ω
8
6
4
-6
-8
-10
2
-12
-14
1.00E+06
0
0
3
2
1
Vin - V
Figure 1. ON-Resistance vs VIN
1.00E+08
1.00E+07
Frequency - Hz
1.00E+09
1.00E+10
Figure 2. Insertion Loss vs Frequency
0
0
-10
-20
-30
-40
Crosstalk - dB
Off Isolation - dB
-20
-60
-40
-50
-60
-80
-70
-100
-80
-120
1.00E+06
1.00E+08
1.00E+07
Frequency - Hz
1.00E+09
1.00E+10
-90
1.00E+06
Figure 3. Off Isolation vs Frequency
1.00E+08
1.00E+07
Frequency - Hz
1.00E+09
1.00E+10
Figure 4. Crosstalk vs Frequency
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6.11.2 Fan-Out 1:2 Configurations
0
12
-2
10
Insertion Loss - dB
-4
Ron - Ω
8
6
4
-6
-8
-10
2
-12
0
0
0.5
1
1.5
Vin - V
2
2.5
-14
1.00E+06
3
Figure 5. ON-Resistance vs VIN
1.00E+08
1.00E+07
Frequency - Hz
1.00E+09
1.00E+10
Figure 6. Insertion Loss vs Frequency
0
0
-10
-20
-40
-30
Crosstalk - dB
Off Isolation - dB
-20
-60
-80
-40
-50
-60
-70
-100
-80
-120
1.00E+06
1.00E+08
1.00E+07
Frequency - Hz
1.00E+09
1.00E+10
-90
1.00E+06
Figure 7. Off Isolation vs Frequency
8
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1.00E+08
1.00E+07
Frequency - Hz
1.00E+09
1.00E+10
Figure 8. Crosstalk vs Frequency
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7 Parameter Measurement Information
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
S1
RL
VO
VI
GND
50 Ω
CL
(see Note A)
50 Ω
VG2
RL
TEST
VCC
S1
RL
Vin
CL
V∆
t PLZ/t PZL
3.3 V ± 0.3 V
2 × VCC
50 Ω
GND
2 pF
0.3 V
t PHZ/t PZH
3.3 V ± 0.3 V
GND
50 Ω
VCC
2 pF
0.3 V
VSEL
VO
VCC
Output Control
(VIN)
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
t PZL
t PLZ
VOH
VCC/2
t PZH
VO
Open
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
t PHZ
VCC/2
VOH - 0.3 V
VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics:PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tOFF.
F. tPZL and tPZH are the same as tON.
Figure 9. Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
50 Ω
RL
S1
RL
Vin
CL
t sk(o)
3.3 V ± 0.3 V
Open
50 Ω
VCC or GND
2 pF
t sk(p)
3.3 V ± 0.3 V
Open
50 Ω
VCC or GND
2 pF
VCC
3.0 V
1.5 V
0V
Data In at
Ax or Ay
t PLHx
t PHLx
VOH
(VOH + VOL)/2
VOL
Data Out at
XB 1 or XB 2
t sk(o)
VO
CL
(see Note A)
50 Ω
TEST
VO
Open
GND
VG2
VI
RL
VO
VI
S1
Input
t sk(o)
VOH
(VOH + VOL)/2
VOL
Data Out at
YB 1 or YB 2
t PLHy
3.0 V
1.5 V
0V
t PHLy
t PLH
VOH
(VOH + VOL)/2
VOL
Output
t sk(o) = t PLHy − tPLHx or t PHLy − tPHLx
VOLTAGE WAVEFORMS
OUTPUT SKEW (t sk(o))
t PHL
t sk(p) = t PHL − tPLH
VOLTAGE WAVEFORMS
PULSE SKEW [t sk(p)]
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 10. Test Circuit and Voltage Waveforms
10
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Parameter Measurement Information (continued)
Network Analyzer
P1
Network Analyzer
P1 50 W
P2
50Ω
P2
50Ω
50 W
VDD
ENA
VCC
OUTA1+
INA+
50 W
ENA
OUTA1-
OUTA1+
OUTA1-
OUTA0+
INA-
INA+
OUTA0-
OUTA0+
INAOUTB1+
INB+
OUTB1-
NB-
SAO=SAI=SBO=SBI=1
ENB=0 for Single 1:4 and
Dual 1:2 configurations
ENB=1 for Fan out 1:2
configuration
SAO=SAI=SBO=SBI=1
OUTB1+
INB+
OUTB0+
GND
OUTA0-
OUTB1-
NB-
OUTB0-
OUTB0+
ENB
Figure 11. Frequency Response (BW)
GND
OUTB0-
Figure 12. Off Isolation (OISO)
Network Analyzer
P2
P1 50 W
50 W
VCC
ENA
OUTA1+
50 W
OUTA1INA+
OUTA0+
INA-
50 W
OUTA0-
OUTB1+
INB+
OUTB1-
NB-
OUTB0+
ENB
GND
SAO=SAI=SBO=SBI=1
OUTB0-
Figure 13. Crosstalk (XTALK)
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8 Detailed Description
8.1 Overview
The TS3DS10224 is a 3-V, bidirectional, differential crosspoint, differential 1:4, 2-channel differential 1:2
multiplexer and demultiplexer, or fan-out switch for high-speed differential signal applications. The TS3DS10224
can route any input to any output creating a wide range of possible switching or multiplexing configurations.
Differential crosspoint switching, differential 1:4 mux, or 2-channel differential 1:2 multiplexer and demultiplexer
are commonly used configurations of the device. Additionally the TS3DS10224 can also be used to fan out a
differential signal pair to two ports simultaneously (fan-out configuration). However, the BW performance is lower
in this configuration.
Select A Input (SAI)
ENA
OUTA0+
OUTA0-
OUTA1-
OUTA1+
8.2 Functional Block Diagram
Select A Output (SAO)
INA+
INA-
1
1
0
0
Channel A
SAO
SAI
SBI
SBO
Channel B
0
0
1
1
ENB
OUTB0+
OUTB0-
Select B Output (SBO)
OUTB1+
Select B Input (SBI)
OUTB1-
INB+
INB-
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Fail-Safe Protection
IOFF protection prevents current leakage in powered down state (VCC = 0 V).
The TS3DS10224 device places the signal paths in a high-impedance state when the device is not powered.
This isolates the data bus if the IC loses power on the supply pin.
12
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8.4 Device Functional Modes
8.4.1 Enable and Disable
The TS3DS10224 has two enable pins (ENA and ENB). Setting these pins LOW disables the signal path and
place them in a high-impedance (Hi-Z) state.
Table 1. Enable and Disable Function Table
ENA
ENB
INA
INB
OUTA0
OUTA1
OUTB0
OUTB1
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
1
Hi-Z
Enabled
Hi-Z
Hi-Z
Enabled
Enabled
1
0
Enabled
Hi-Z
Enabled
Enabled
Hi-Z
Hi-Z
1
1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
8.4.2 Differential Crosspoint Switch
The TS3DS10224 can be configured as a differential crosspoint switch. Crosspoint switches are particularly
helpful when traces have to cross in simplifying layouts, and when switching the top and bottom signals of the
reversible connector in USB Type-C applications.
Table 2 shows that the inputs INA and INB can be routed to OUTA or OUTB. This is accomplished by setting the
Select A Output (SAO) and Select B Output (SBO) LOW and selecting which input goes to the output by toggling
the Select A Input (SAI) and Select B Input (SBI) pins.
Table 2. Differential Crosspoint Switch Function Table
LOGIC CONTROL SETTING
SIGNAL ROUTING
SAI
SBI
SAO
SBO
INA
INB
0
0
0
0
OUTB0
OUTA0
1
1
0
0
OUTA0
OUTB0
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TS3DS10224
Select A Input (SAI)
ENA
OUTA0-
OUTA0+
OUTA1-
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OUTA1+
SCDS324E – AUGUST 2011 – REVISED OCT 2019
Select A Output (SAO)
INA+
INA-
1
1
0
0
Logic Control
Channel A
Channel B
0
0
1
1
^>}Á_
SAI
^>}Á_
SBI
^>}Á_
SBO
^>}Á_
ENB
OUTB0+
OUTB0-
Select B Output (SBO)
OUTB1+
Select B Input (SBI)
OUTB1-
INB+
INB-
SAO
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Differential Crosspoint Switch Block Diagram
14
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8.4.3 2-Channel 1:2 Mux
The TS3DS10224 can be configured to be differential 2-channel 1:2 mux.
Table 3 shows that the inputs INA and INB can be routed to 2 different places. This is accomplished by setting
the Select A Input (SAI) and Select B Input (SBI) HIGH and selecting an output by toggling the Select A Output
(SAO) and Select B Output (SBO) pins.
Table 3. 2-Channel 1:2 Mux Function Table
LOGIC CONTROL SETTING
SIGNAL ROUTING
SBO
INA
INB
0
0
OUTA0
OUTB0
1
1
0
1
OUTA0
OUTB1
1
1
1
0
OUTA1
OUTB0
1
1
1
1
OUTA1
OUTB1
Select A Input (SAI)
ENA
OUTA0+
OUTA0-
SAO
1
OUTA1-
SBI
1
OUTA1+
SAI
Select A Output (SAO)
INA+
INA-
1
1
0
0
Logic Control
Channel A
SAO ^>}Á }Œ ,]PZ_
SAI ^,]PZ_
SBI ^,]PZ_
SBO ^>}Á }Œ ,]PZ_
Channel B
0
0
1
1
ENB
OUTB0+
OUTB0-
Select B Output (SBO)
OUTB1+
Select B Input (SBI)
OUTB1-
INB+
INB-
Copyright © 2016, Texas Instruments Incorporated
Figure 15. 2-Channel 1:2 Block Diagram
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8.4.4 1-Channel 1:4 Mux
The TS3DS10224 can be configured as differential 1-channel 1:4 mux.
The truth table below shows that the inputs INA can be routed to 4 different places. This is accomplished by
setting the Select A Input (SAI) and Select B Input (SBI) HIGH and selecting an output by toggling the Select A
Output (SAO) and Select B Output (SBO) pins.
Unused pins INB+ and INB– must be left floating in this configuration.
Table 4. 1-Channel 1:4 Mux Function Table
LOGIC CONTROL SETTINGS
SIGNAL ROUTING
SBO
INA
INB
1
1
0
—
OUTA0
—
1
1
1
—
OUTA1
—
0
0
—
0
OUTB0
—
0
0
—
1
OUTB1
—
Select A Input (SAI)
ENA
SAO
OUTA0+
OUTA0-
SBI
OUTA1+
OUTA1-
SAI
Select A Output (SAO)
INA+
INA-
1
1
0
0
Logic Control
Channel A
SAO ^>}Á }Œ ,]PZ_
SAI ^,]PZ_
SBI ^>}Á }Œ ,]PZ_
SBO ^>}Á }Œ ,]PZ_
Channel B
0
0
1
1
ENB
OUTB0+
OUTB0-
Select B Output (SBO)
OUTB1+
Select B Input (SBI)
OUTB1-
INB+
INB-
Copyright © 2016, Texas Instruments Incorporated
Figure 16. 1-Channel 1:4 Mux Functional Block Diagram
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8.4.5 Fan-Out 1:2 Configuration
The TS3DS10224 can be configured in a differential fan-out 1:2 mux.
The truth table below shows that the inputs INA or INB can be routed to output A or output B simultaneously.
This is accomplished by setting the Select A Input (SAI) and Select B Input (SBI) HIGH and selecting an output
by toggling the Select A Output (SAO) and Select B Output (SBO) pins.
Unused pins INB+ and INB– must be left floating in this configuration.
Table 5. Fan-Out 1:2 Function Table
LOGIC CONTROL SETTINGS
SIGNAL ROUTING
SBO
INA
INB
1
0
0
0
OUTA0 and OUTB0
—
1
0
0
1
OUTA0 and OUTB1
—
1
0
1
0
OUTA1 and OUTB0
—
1
0
1
1
OUTA1 and OUTB1
—
Select A Input (SAI)
ENA
SAO
OUTA0+
OUTA0-
SBI
OUTA1+
OUTA1-
SAI
Select A Output (SAO)
INA+
INA-
1
1
0
0
Logic Control
Channel A
SAO ^>}Á }Œ ,]PZ_
SAI ^,]PZ_
SBI ^>}Á }Œ ,]PZ_
SBO ^>}Á }Œ ,]PZ_
Channel B
0
0
1
1
ENB
OUTB0+
OUTB0-
Select B Output (SBO)
OUTB1+
Select B Input (SBI)
OUTB1-
INB+
INB-
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Fan-Out 1:2 Functional Block Diagram
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Table 6.
18
SAI
SBI
SA0
SBO
OUTA0
OUTA1
OUTB0
OUTB1
0
0
0
0
INB
—
INA
—
0
0
0
1
INB
—
—
INA
1-channel 1:4 mux
0
0
1
0
—
INB
INA
—
1-channel 1:4 mux
0
0
1
1
—
INB
—
INA
1-channel 1:4 mux
0
1
0
0
INB
—
INB
—
0
1
0
1
INB
—
—
INB
0
1
1
0
—
INB
INB
—
0
1
1
1
—
INB
—
INB
1
0
0
0
INA
—
INA
—
Fan-out 1:2 configuration
1
0
0
1
INA
—
—
INA
Fan-out 1:2 configuration
1
0
1
0
—
INA
INA
—
Fan-out 1:2 configuration
1
0
1
1
—
INA
—
INA
Fan-out 1:2 configuration
1
1
0
0
INA
—
INB
—
1
1
0
1
INA
—
—
INB
2-channel 1:2 mux,1-channel 1:4 mux
1
1
1
0
—
INA
INB
—
2-channel 1:2 mux,1-channel 1:4 mux
1
1
1
1
—
INA
—
INB
2-channel 1:2 mux,1-channel 1:4 mux
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FUNCTIONAL MODE
Crosspoint, 1-channel 1:4 mux
Crosspoint, 2-channel 1:2 mux, 1-channel 1:4
mux
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TS3DS10224 device can be configured for a variety of applications which makes this a great utility device.
The most unique feature of this device is the ability to operate as a differential crosspoint switch.
9.2 Typical Applications
9.2.1 1-Channel Differential 1:4 Mux
VDD
USB
2.0
PHY
2
INA
2
USB 2.0
Connector 1
OUTA0
2
INB
Processor
USB 2.0
Connector 2
OUTA1
TS3DS10224
GPIO
ENA
GPIO
ENB
GPIO
SAO
GPIO
SBO
GPIO
SAI
2
USB 2.0
Connector 3
OUTB0
2
USB 2.0
Connector 4
OUTB1
SBI
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 18. 1-Channel Differential 1:4 Mux Application
9.2.1.1 Design Requirements
TI recommends that the digital control pins SAI, SBI, SAO, and SBO be pulled up to VCC or down to GND to
avoid undesired switch positions that could result from a floating pin. Unused pins for the signal paths INA, INB,
OUTAx, and OUTBx must be terminated with a 50-Ω resistor to ground to reduce signal reflections in high-speed
applications.
The thermal pad may be left floating or connected to ground.
9.2.1.2 Detailed Design Procedure
The TS3DS10224 can be properly operated without any external components. TI recommends placing a bypass
capacitor on the VCC pin.
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Typical Applications (continued)
Differential Signal (V)
Differential Signal (V)
9.2.1.3 Application Curves
Time, ns
Time, ns
Figure 20. 480-Mbps USB 2.0 Eye Diagram With Device
Figure 19. 480-Mbps USB 2.0 Eye Diagram Through Path
With No Device
9.2.2 2-Channel Differential Crosspoint Switch
VDD
USB
2.0
PHY
2
INA
2
I2C Device
OUTA0
2
2
I C PHY
INB
Processor
OUTA1
TS3DS10224
GPIO
ENA
GPIO
ENB
2
OUTB0
USB 2.0
Connector
SAO
SBO
OUTB1
SAI
SBI
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 21. 2-Channel Differential Crosspoint Switch Schematic
20
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Typical Applications (continued)
9.2.2.1 Design Requirements
TI recommends that the digital control pins SAI, SBI, SAO, and SBO be pulled up to VCC or down to GND to
avoid undesired switch positions that could result from a floating pin. Unused pins for the signal paths INA, INB,
OUTAx, and OUTBx must be terminated with a 50-Ω resistor to ground to reduce signal reflections in high-speed
applications.
9.2.3 Fan-Out Switch
VDD
2
Differential
Clock
INA
2
Differential
Clock
OUTA0
INB
Processor
OUTA1
TS3DS10224
GPIO
ENA
GPIO
ENB
VDD
2
OUTB0
Differential
Clock
SAO
SBO
OUTB1
SAI
SBI
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Fan-Out Switch Schematic
9.2.3.1 Design Requirements
TI recommends that the digital control pins SAI, SBI, SAO, and SBO be pulled up to VCC or down to GND to
avoid undesired switch positions that could result from the floating pin. Unused pins for the signal paths INA,
INB, OUTAx, OUTBx must be terminated with a 50-Ω resistor to ground to reduce signal reflections in highspeed applications.
The bandwidth performance is lower in this application (500 MHz).
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Typical Applications (continued)
9.2.4 2-Channel Differential 1:2 SPDT Switch
VDD
USB
2.0
PHY
2
INA
2
2
2
INB
GPIO
ENA
GPIO
ENB
GPIO
SAO
GPIO
SBO
I C PHY
USB 2.0
Connector 1
OUTA0
2
Processor
USB 2.0
Connector 2
OUTA1
TS3DS10224
2
I2C
Device 1
OUTB0
VDD
2
OUTB1
I2C
Device 1
SAI
SBI
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 23. 2-Channel Differential 1:2 SPDT Switch Schematic
10 Power Supply Recommendations
Power to the device is supplied through the VCC pin and must be within the recommended operating voltage
range. TI recommends a bypass capacitor be placed as close to the supply pin (VCC) as possible to help smooth
out lower frequency noise and to provide better load regulation across the frequency spectrum.
22
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
The thermal pad may be left floating or connected to the ground plane
Place supply-bypass capacitors as close to the VCC pin as possible and avoid placing the bypass capacitors
near the positive and negative traces.
The high-speed positive and negative traces must always be matched and the lengths must not exceed 4
inches; otherwise, the eye diagram performance may be degraded. In layout, the impedance of positive and
negative traces must match the cable characteristic differential impedance for optimal performance.
Route the high-speed signals using a minimum of vias and corners to reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted
pair lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices, or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signal traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high-frequency signal traces, TI recommends a printed-circuit board with at least four layers; two
signal layers separated by a ground and power layer as shown in Figure 24.
Signal 1
GND Plane
Power Plane
Signal 2
Figure 24. Four-Layer Board Stack-Up
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
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To Device A0
To Device A1
11.2 Layout Example
To Controller
To System
ENA
OUTA0-
OUTA0+
OUTA1-
OUTA1+
= VIA to GND Plane
INA+
SAO
INA-
SAI
INB+
VCC
INB-
SBI
GND
SBO
To Controller
To System A
VCC
0603 Cap
To System B
ENB
OUTB0-
OUTB0+
OUTB1-
OUTB1+
To Controller
To Controller
To Device B0
To Device B1
Figure 25. WQFN Layout Example
24
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TS3DS10224RUKR
ACTIVE
WQFN
RUK
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ZTB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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