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TS3USB221ERSER

TS3USB221ERSER

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    UQFN10

  • 描述:

    IC USB SWITCH DUAL 1X2 10-QFN

  • 数据手册
  • 价格&库存
TS3USB221ERSER 数据手册
Product Folder Order Now Support & Community Tools & Software Technical Documents TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 TS3USB221E High-Speed USB 2.0 (480-Mbps) 1:2 Multiplexer – Demultiplexer Switch With Single Enable and IEC Level 3 ESD Protection 1 Features 3 Description • • • • • • • • • The TS3USB221E is a high-bandwidth switch specially designed for the switching of high-speed USB 2.0 signals in handset and consumer applications, such as cell phones, digital cameras, and notebooks with hubs or controllers with limited USB I/Os. The wide bandwidth (1 GHz) of this switch allows signals to pass with minimum edge and phase distortion. The device multiplexes differential outputs from a USB host device to one of two corresponding outputs. The switch is bidirectional and offers little or no attenuation of the high-speed signals at the outputs. The TS3USB221E is designed for low bit-tobit skew and high channel-to-channel noise isolation, and is compatible with various standards, such as high-speed USB 2.0 (480 Mbps). 1 • • VCC operation of 2.3 V to 3.6 V Switch I/Os accept signals up to 5.5 V 1.8-V compatible control-pin inputs Low-power mode when OE Is disabled (1 μA) rON = 6 Ω maximum ΔrON = 0.2 Ω typical Cio(on) = 7 pF maximum Low power consumption (30 μA maximum) ESD performance tested per JESD 22 – 7000-V human body model (A114-B, Class II) – 1000-V charged-device model (C101) ESD performance I/O port to GND – 12-kV human body model (A114-B, Class II) – ±7-kV contact discharge (IEC 61000-4-2) High bandwidth (1 GHz typical) The TS3USB221E integrates ESD protection cells on all pins, is available in a SON package (3 mm × 3 mm) as well as in a tiny μQFN package (2 mm × 1.5 mm) and is characterized over the free-air temperature range from –40°C to 85°C. Device Information(1) 2 Applications • • • • • • PART NUMBER Routes signals for USB 1.0, 1.1, and 2.0 Mobile phones Digital cameras Notebooks USB I/O expansion MHL 1.0 Block Diagram TS3USB221E PACKAGE BODY SIZE (NOM) VSON (10) 3.00 mm × 3.00 mm UQFN (10) 1.50 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic, Each FET Switch (SW) D+ 1D+ D− 1D− A 2D+ B VCC 2D− Digital Control Charge Pump S OE EN (see Note A) A. EN is the internal enable signal applied to the switch. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics .......................................... Dynamic Electrical Characteristics, VCC = 3.3 V ±10% ......................................................................... 6.7 Dynamic Electrical Characteristics, VCC = 2.5 V ±10% ......................................................................... 6.8 Switching Characteristics, VCC = 3.3 V ±10%........... 6.9 Switching Characteristics, VCC = 2.5 V ±10% .......... 6.10 Typical Characteristics ............................................ 7 8 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 12 Application and Implementation ........................ 13 9.1 Application Information............................................ 13 9.2 Typical Application ................................................. 13 10 Power Supply Recommendations ..................... 15 11 Layout................................................................... 15 11.1 Layout Guidelines ................................................. 15 11.2 Layout Example .................................................... 16 12 Device and Documentation Support ................. 17 6 6 6 6 7 Parameter Measurement Information .................. 8 Detailed Description ............................................ 12 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 17 13 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2015) to Revision D • Page Changed VCC Operation FROM 2.5 V to 3.3 V TO 2.3 V to 3.6 V ......................................................................................... 1 Changes from Revision B (July 2012) to Revision C Page • Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................ 1 • Removed Ordering Information table ..................................................................................................................................... 1 Changes from Revision A (February 2010) to Revision B • 2 Page Updated TOP-SIDE MARKING for RSE package in Ordering Information table ................................................................... 1 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 5 Pin Configuration and Functions DRC Package 10-Pin VSON (Top View) RSE Package 10-Pin UQFN (Top View) 1D+ 1 10 VCC 1D– 2 9 S 2D+ 3 8 D+ 2D– 4 7 D– GND 5 6 OE VCC 10 9 S 2 8 D+ 2D+ 3 7 D– 2D– 4 6 OE 1D+ 1 1D– 5 GND RSE Package 10-Pin UQFN (Bottom View) VCC S 9 D+ 10 1 1D+ 8 2 1D– D– 7 3 2D+ OE 6 4 2D– 5 GND Pin Functions PIN NAME NO. I/O DESCRIPTION 1D+ 1 I/O 1D– 2 I/O USB port 1 2D+ 3 I/O 2D– 4 I/O GND 5 — OE 6 I Bus-switch enable D– 7 I/O Common USB port D+ 8 I/O S 9 I VCC 10 — USB port 2 Ground Select input Supply voltage Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 3 TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.5 4.6 V VIN Control input voltage (2) (3) –0.5 7 V VI/O Switch I/O voltage (2) (3) (4) –0.5 7 V IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA II/O ON-state switch current (5) ±120 mA Continuous current through VCC or GND ±100 mA VCC Supply voltage θJA Package thermal impedance (6) Tstg Storage temperature (1) (2) (3) (4) (5) (6) DRC package 48.7 RSE package 243 –65 °C/W 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) V(ESD) (1) (2) Electrostatic discharge All pins except GND, OE, S and VCC ±12000 Pins GND, OE, S and VCC ±7000 All pins except GND, OE, Charged-device model (CDM), per JEDEC S and VCC specification JESD22-C101 (2) Pins GND, OE, S and VCC UNIT V ±7000 ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions See VCC (1) . Supply voltage VIH High-level control input voltage VIL Low-level control input voltage VI/O Data input/output voltage TA Operating free-air temperature (1) 4 MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V 0.46 × VCC VCC = 2.7 V to 3.6 V 0.46 × VCC UNIT V V VCC = 2.3 V to 2.7 V 0.25 × VCC VCC = 2.7 V to 3.6 V 0.25 × VCC V 0 5.5 V –40 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 6.4 Thermal Information TS3USB221E THERMAL METRIC (1) DRC (VSON) RSE (UQFN) 10 PINS 10 PINS RθJA Junction-to-ambient thermal resistance 57.7 169.8 RθJC(top) Junction-to-case (top) thermal resistance 87.7 84.7 RθJB Junction-to-board thermal resistance 32.6 94.9 ψJT Junction-to-top characterization parameter 8.2 5.7 ψJB Junction-to-board characterization parameter 32.8 94.9 RθJC(bot) Junction-to-case (bottom) thermal resistance 18.5 N/A (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) (1) PARAMETER VIK Control inputs IIN IOZ (3) IOFF TEST CONDITIONS UNIT –1.8 V VIN = 0 V to 3.6 V ±1 μA VIN = VCC or GND, Switch OFF ±1 μA VI/O = 0 V to 5.25 V ±2 VI/O = 0 V to 3.6 V ±2 VI/O = 0 V to 2.7 V ±1 II = –18 mA VCC = 3.6 V, 2.7 V, 0 V, VCC = 3.6 V, 2.7 V, VO = 0 V to 5.25 V, VI = 0 V, VCC = 0 V TYP (2) MAX VCC = 3.6 V, 2.7 V, MIN μA ICC VCC = 3.6 V, 2.7 V, VIN = VCC or GND, II/O = 0 V, Switch ON or OFF 30 μA ICC (low power mode) VCC = 3.6 V, 2.7 V, VIN = VCC or GND Switch disabled (OE in high state) 1 μA ICC (4) Control inputs One input at 1.8 V, Other inputs at VCC or GND VCC = 3.6 V 20 VCC = 2.7 V 0.5 Cin Control inputs VCC = 3.3 V, 2.5 V, VIN = 3.3 V or 0 V VCC = 3.3 V, 2.5 V, VI/O = 3.3 V or 0 V, Switch OFF VCC = 3.3 V, 2.5 V, VI/O = 3.3 V or 0 V, VI = 0 V, VI = 2.4 V, Cio(OFF ) Cio(ON) rON (5) VCC = 3 V, 2.3 V ΔrON VCC = 3 V, 2.3 V rON(flat) VCC = 3 V, 2.3 V (1) (2) (3) (4) (5) μA 1.5 2.5 pF 3.5 5 pF Switch ON 6 7.5 pF IO = 30 mA 3 6 IO = –15 mA 3.4 6 VI = 0 V, IO = 30 mA 0.2 VI = 1.7, IO = –15 mA 0.2 VI = 0 V, IO = 30 mA 1 VI = 1.7, IO = –15 mA 1 Ω Ω Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 5 TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com 6.6 Dynamic Electrical Characteristics, VCC = 3.3 V ±10% over operating range, TA = –40°C to 85°C, VCC = 3.3 V ±10%, GND = 0 V PARAMETER TYP (1) TEST CONDITIONS XTALK Crosstalk RL = 50 , f = 250 MHz –40 OIRR OFF isolation RL = 50 , f = 250 MHz –40 BW Bandwidth (–3 dB) RL = 50 (1) UNIT dB dB 1 GHz For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type. 6.7 Dynamic Electrical Characteristics, VCC = 2.5 V ±10% over operating range, TA = –40°C to 85°C, VCC = 2.5 V ±10%, GND = 0 V PARAMETER TYP (1) TEST CONDITIONS XTALK Crosstalk RL = 50 , f = 250 MHz -39 OIRR OFF isolation RL = 50 , f = 250 MHz -40 BW Bandwidth (3 dB) RL = 50 (1) 1 UNIT dB dB GHz For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type. 6.8 Switching Characteristics, VCC = 3.3 V ±10% over operating range, TA = –40°C to 85°C, VCC = 3.3 V ±10%, GND = 0 V PARAMETER tpd Propagation delay MIN (2) (3) Line enable time tOFF Line disable time tSK(O) Output skew between center port to any other port (2) (1) (2) (3) MAX 0.25 tON tSK(P) TYP (1) ns S to D, nD 30 OE to D, nD 17 S to D, nD 12 OE to D, nD 10 Skew between opposite transitions of the same output (tPHL– tPLH) (2) UNIT ns ns 0.1 0.2 ns 0.1 0.2 ns For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type. Specified by design The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Because this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side. 6.9 Switching Characteristics, VCC = 2.5 V ±10% over operating range, TA = –40°C to 85°C, VCC = 2.5 V ±10%, GND = 0 V PARAMETER tpd Propagation delay MIN (2) (3) 50 OE to D, nD 32 S to D, nD 23 OE to D, nD 12 tOFF Line disable time tSK(O) Output skew between center port to any other port (2) 6 Skew between opposite transitions of the same output (tPHL– tPLH) (2) UNIT ns S to D, nD Line enable time (1) (2) (3) MAX 0.25 tON tSK(P) TYP (1) ns ns 0.1 0.2 ns 0.1 0.2 ns For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type. Specified by design The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Because this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 6.10 Typical Characteristics 0 –20 –1 –30 –40 Attenuation (dB) Gain (dB) –2 –3 –4 –5 –50 –60 –70 –80 –6 –90 –7 –100 1E+6 1E+7 1E+8 1E+9 1E+6 1E+10 1E+7 1E+8 1E+9 1E+10 Frequency (Hz) Frequency (Hz) Figure 2. OFF Isolation vs Frequency Figure 1. Gain vs Frequency 3.5 -25 3.4 -35 3.3 -55 ron (Ω) Attenuation (dB) -45 -65 3.2 3.1 -75 3.0 -85 2.9 -95 -105 1E+6 VCC = 3.0 V VCC = 2.3 V 2.8 1E+7 1E+8 1E+9 0.0 1E+10 0.5 1.0 Frequency 1.5 2.0 2.5 3.0 3.5 VIN (V) Figure 3. Crosstalk vs Frequency Figure 4. Ron vs VIN (IOUT = –15 mA) 3.5 3.4 ron (Ω) 3.3 3.2 3.1 3.0 2.9 VCC = 3.0 V VCC = 2.3 V 2.8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VIN (V) Figure 5. Ron vs VIN (IOUT = –30 mA) Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 7 TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com 7 Parameter Measurement Information VCC VOUT1 or VOUT2 1D or 2D TEST RL CL VCOM tON 500 Ω 50 pF V+ tOFF 500 Ω 50 pF V+ D VIN CL(2) 1D or 2D RL S VCTRL CL(2) Logic Input(1) 1.8 V Logic Input (VI) RL GND 50% 50% 0 tON Switch Output (VOUT1 or VOUT2) (1) (2) tOFF 90% 90% VOH VOL All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50W, t r < 5 ns, t f < 5 ns. CL includes probe and jig capacitance. Figure 6. Turnon (TON) and Turnoff Time (TOFF) VCC Network Analyzer Channel OFF: 1D to D 50 Ω VOUT1 1D VCTRL = VCC or GND VIN D Source Signal 50 Ω 2D Network Analyzer Setup Source Power = 0 dBm (632-mV P-P at 50-Ω load) VCTRL S 50 Ω + GND DC Bias = 350 mV Figure 7. OFF Isolation (OISO) VCC Network Analyzer Channel ON: 1D to D 50 Ω VOUT1 1D Channel OFF: 2D to D VIN Source Signal VCTRL = VCC or GND VOUT2 2D 50 VCTRL S 50 Ω + GND Network Analyzer Setup Source Power = 0 dBm (632-mV P-P at 50-Ω load) DC Bias = 350 mV Figure 8. Crosstalk (XTALK) 8 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 Parameter Measurement Information (continued) VCC Network Analyzer 50 Ω VOUT1 1D Channel ON: 1D to D D Source Signal VIN VCTRL = VCC or GND 2D Network Analyzer Setup 50 Ω VCTRL + Source Power = 0 dBm (632-mV P-P at 50-Ω load) S GND DC Bias = 350 mV Figure 9. Bandwidth (BW) 400 mV Figure 10. Propagation Delay Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 9 TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com Parameter Measurement Information (continued) 800 mV 50% 50% Input 400 mV tPLH tPHL VOH 50% Output VOL tSK(P) = | tPHL – tPLH | PULSE SKEW tSK(P) 800 mV 50% 50% Input 400 mV tPLH1 tPHL1 VOH 50% 50% Output 1 VOL tSK(O) tSK(O) VOH 50% 50% Output 2 tPLH2 VOL tPHL2 tSK(O) = | tPLH1 – tPLH2 | or | tPHL1 – tPHL2 | OUTPUT SKEW tSK(P) Figure 11. Skew Test VCC VOUT1 1D D + VIN Channel ON VOUT2 2D r on – VCTRL IIN S VIN VOUT2 or VOUT1 Ω IIN VCTRL = VIH or VIL + GND Figure 12. ON-State Resistance (Ron) 10 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 Parameter Measurement Information (continued) VCC VOUT1 1D D + VOUT2 2D VCTRL VIN + S OFF-State Leakage Current Channel OFF VCTRL = VIH or VIL + GND Figure 13. OFF-State Leakage Current VCC VOUT1 1D Capacitance Meter VBIAS VBIAS = VCC or GND VOUT2 2D VCTRL = VCC or GND VIN D Capacitance is measured at 1D, 2D, D, and S inputs during ON and OFF conditions. VCTRL S GND Figure 14. Capacitance Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 11 TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com 8 Detailed Description 8.1 Overview The TS3USB221E device is a 2-channel SPDT switch specially designed for the switching of high-speed USB 2.0 signals in handset and consumer applications, such as cell phones, digital cameras, and notebooks with hubs or controllers with limited USB I/Os. The wide bandwidth (1 GHz) of this switch allows signals to pass with minimum edge and phase distortion. The device multiplexes differential outputs from a USB host device to one of two corresponding outputs. The switch is bidirectional and offers little or no attenuation of the high-speed signals at the outputs. The device also has a low power mode that reduces the power consumption to 1 μA for portable applications with a battery or limited power budget. The device is designed for low bit-to-bit skew and high channel-to-channel noise isolation, and is compatible with various standards, such as high-speed USB 2.0 (480 Mbps). The TS3USB221E device integrates ESD protection cells on all pins, is available in a tiny μQFN package (2 mm × 1.5 mm) and is characterized over the free-air temperature range from –40°C to 85°C. 8.2 Functional Block Diagram D+ 1D+ D− 1D− 2D+ 2D− Digital Control S OE 8.3 Feature Description 8.3.1 Low Power Mode The TS3USB221E has a low power mode that reduces the power consumption to 1 μA when the device is not in use. To put the device in low power mode and disable the switch, the bus-switch enable pin OE must be supplied with a logic high signal. 8.4 Device Functional Modes Table 1. Truth Table 12 S OE FUNCTION X H Disconnect L L D = 1D H L D = 2D Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os. The TS3USB221E solution can effectively expand the limited USB I/Os by switching between multiple USB buses in order to interface them to a single USB hub or controller. TS3USB221E can also be used to connect a single controller to two USB connectors. 9.2 Typical Application 3.3 V 0.1 μF 0.1 μF VCC System Controller Switch Control Logic USB Controller TS3USB221E 2-channel SPDT S OE 1D+ 1DD+ USB Port 1 D2D+ 2D- USB Port 2 GND Figure 15. Simplified Schematic 9.2.1 Design Requirements Design requirements of the USB 1.0, 1.1, and 2.0 standards should be followed. TI recommends that the digital control pins S and OE be pulled up to VCC or down to GND to avoid undesired switch positions that could result from the floating pin. 9.2.2 Detailed Design Procedure The TS3USB221E can be properly operated without any external components. However, it is recommended that unused pins should be connected to ground through a 50-Ω resistor to prevent signal reflections back into the device. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 13 TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com Typical Application (continued) 0.5 0.5 0.4 0.4 0.3 0.3 Differential Signal (V) Differential Signal (V) 9.2.3 Application Curves 0.2 0.1 0.0 –0.1 –0.2 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0.0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 –9 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0 –9 Time (X 10 ) (s) Time (X 10 ) (s) Figure 16. Eye Pattern: 480-Mbps USB Signal With No Switch (Through Path) Figure 17. Eye Pattern: 480-Mbps USB Signal With Switch 1D Path 0.5 0.4 Differential Signal (V) 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0.0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0 –9 Time (X 10 ) (s) Figure 18. Eye Pattern: 480-Mbps USB Signal With Switch 2D Path 14 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 10 Power Supply Recommendations Power to the device is supplied through the VCC pin and should follow the USB 1.0, 1.1, and 2.0 standards. TI recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth out lower frequency noise to provide better load regulation across the frequency spectrum. 11 Layout 11.1 Layout Guidelines Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the D+/D– traces. The high speed D+/D– traces should always be matched lengths and must be no more than 4 inches; otherwise, the eye diagram performance may be degraded. A high-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic impedance. In layout, the impedance of D+ and D– traces should match the cable characteristic differential impedance for optimal performance. Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then the stub should be less than 200 mm. Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch, commonly found with plane splits. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is recommended; two signal layers separated by a ground and power layer as shown in Figure 19. Signal 1 GND Plane Power Plane Signal 2 Figure 19. Four-Layer Board Stack-Up The majority of signal traces should run on a single layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies. For more information on layout guidelines, see High Speed Layout Guidelines (SCAA082) and USB 2.0 Board Design and Layout Guidelines (SPRAAR7). Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 15 TS3USB221E SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 www.ti.com 11.2 Layout Example LEGEND VIA to Power Plane Polygonal Copper Pour VIA to GND Plane Bypass Capacitor V+ To Microcontroller 10 1 1D+ VCC S 9 2 1D- D+ 8 3 2D+ D- 7 USB Port 1 To USB Host USB Port 2 4 2D- OE 6 GND 5 To Microcontroller Figure 20. Package Layout Diagram 16 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E TS3USB221E www.ti.com SCDS263D – SEPTEMBER 2009 – REVISED SEPTEMBER 2019 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • Implications of Slow or Floating CMOS Inputs, SCBA004 • High Speed Layout Guidelines, SCAA082 • USB 2.0 Board Design and Layout Guidelines, SPRAAR7 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TS3USB221E 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TS3USB221EDRCR ACTIVE VSON DRC 10 3000 RoHS & Green NIPDAU TS3USB221ERSER ACTIVE UQFN RSE 10 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 ZVM Level-1-260C-UNLIM -40 to 85 (LGO, LGR, LGV) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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TS3USB221ERSER
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