TSB41AB1ZQE-64

     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 D Fully Supports Provisions of IEEE D D D D D D D D D Failsafe Circuitry Senses Sudden Loss of 1394-1995 Standard for High Performance Serial Bus† and IEEE 1394a-2000 Fully Interoperable With FireWire and i.LINK Implementation of IEEE Std 1394 Fully Compliant With OpenHCI Requirements Provides One IEEE 1394a-2000 Fully Compliant Cable Port at 100/200/400 Megabits Per Second (Mbits/s) Full IEEE 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and IEEE 1394a-2000 Features IEEE 1394a-2000 Compliant Common Mode Noise Filter on Incoming TPBIAS Extended Resume Signaling for Compatibility With Legacy DV Devices, and Terminal- and Register-Compatibility With TSB41LV01, Allow Direct Isochronous Transmit to Legacy DV Devices With Any Link Layer Even When Root Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down D D D D D D D D D D D D D D Power to the Device and Disables the Port to Ensure That the Device Does Not Load TPBIAS of the Connected Device and Blocks Any Leakage Path From the Port Back to the Device Power Plane Software Device Reset (SWR) Industry Leading Low Power Consumption Ultralow-Power Sleep Mode Cable Power Presence Monitoring Cable Ports Monitor Line Conditions for Active Connection to Remote Node Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz Interface to Link Layer Controller Supports Low Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation Interoperable With Link-Layer Controllers Using 3.3 V Single 3.3-V Supply Operation Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz Low-Cost High-Performance 48/64-Pin TQFP (PHP/PAP) Thermally Enhanced Packages Increase Thermal Performance by up to 210% Meets Intel Mobile Power Guideline 2000 Available in 80-Ball, MicroStar Junior BGA (GQE) Package Available in 64-Ball, Pb-Free, MicroStar Junior BGA (ZQE) Package Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. FireWire is a trademark of Apple Computer, Incorporated. i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. Intel is a trademark of Intel Corporation. Other trademarks are the property of their respective owners. MicroStar Junior is a trademark of Texas Instruments Incorporated. Copyright  2000 − 2004, Texas Instruments Incorporated 
 
  ! "#$ !  %#&'" ($) (#"! "  !%$""! %$ *$ $! 
$+! !#$! !(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 description The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO terminal on the PHY must be high. Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB1 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB1 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is typically VDD−0.2 V when the port is not connected to another node. The line drivers in the TSB41AB1 operate in a high-impedance current mode, and are designed to work with external 112-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 description (continued) connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the external line termination resistors are designed to meet IEEE Std 1394-1995 when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current-setting resistor has a value of 6.34 kΩ ±1.0%. When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD through a 1-kΩ resistor, SE should be tied to ground through a 1-kΩ resistor, and SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0– PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or for bus manager (BM). The TSB41AB1 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly connected ports to be placed into a low-power state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS. When the port of the TSB41AB1 is suspended, all circuits except the band gap reference generator and bias detection circuit is powered down, resulting in significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The cable-not-active (CNA) output terminal (64-terminal PAP package only) is asserted high when there are no twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41AB1. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB1 internal logic. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB1 continues the necessary repeater functions • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 description (continued) required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB1 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41AB1 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active. PHP package terminal diagram XI PLLGND PLLVDD FILTER1 FILTER0 RESET LREQ DGND DGND DVDD DVDD XO PHP PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 SYSCLK CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PD 1 36 2 35 3 34 4 33 5 32 6 7 TSB41AB1 31 30 8 29 9 28 10 27 11 26 25 12 AGND AVDD R1 R0 AGND TPBIAS TPA+ TPA− TPB+ TPB− AGND AVDD LPS DGND C/LKON PC0 PC1 PC2 ISO CPS DV DD TESTM SE SM 13 14 15 16 17 18 19 20 21 22 23 24 NOTE A: For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PAP package terminal diagram 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 50 31 51 30 52 29 53 28 54 27 55 26 56 TSB41AB1 57 25 24 58 23 59 22 60 21 61 20 62 19 63 18 64 1 2 3 4 5 17 6 7 8 9 10 11 12 13 14 15 16 AGND AVDD AVDD SM SE TESTM DVDD DVDD CPS ISO PC2 PC1 PC0 C/LKON DGND DGND LREQ SYSCLK CNA CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PD LPS NC AGND AGND AVDD AVDD RESET FILTER0 FILTER1 PLLVDD PLLGND PLLGND XI XO DVDD DVDD DGND DGND TPB− AGND AGND NC NC NC NC NC AVDD R1 R0 AGND TPBIAS TPA+ TPA− TPB+ PAP PACKAGE (TOP VIEW) NOTES: A. Pin 16 (NC) could be tied to VDD for backward compatibility with the TSB41LV02A device. B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 GQE package terminal diagram—NC connections (top view) GQE PACKAGE TERMINAL DIAGRAM DGND PC0 PC1 /ISO PC2 DVDD CPS SE TESTM AVDD SM AGND (TOP VIEW) TPB− J C/LKON TPB+ NC NC3 H LPS TPA− NC NC4 NC4 NC4 NC NC G D7 PD TPA+ NC NC2 NC2 NC3 NC3 NC F D5 D6 TPBIAS NC2 B NC2 NC2 NC2 NC1 NC1 E R0 AGND NC NC2 NC1 NC1 NC1 D AVDD R1 NC NC NC1 NC C D4 D3 D2 D1 D0 CTL1 AGND NC1 B CTL0 AGND A 2 CNA LREQ 3 DGND DVDD 4 XO 5 PLLGND XI 6 PLLVDD PLLGND 7 FILTER0 FILTER1 8 AVDD RESET 9 NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 SYSCLK 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 ZQE package terminal diagram—NC connections (top view) ZQE PACKAGE TERMINAL DIAGRAM DGND PC0 PC1 /ISO PC2 DVDD CPS SE TESTM AVDD SM AGND (TOP VIEW) TPB− J C/LKON TPB+ NC NC3 H LPS TPA− NC G D7 PD TPA+ NC NC2 NC3 NC3 F D5 D6 TPBIAS B NC2 NC2 NC2 NC1 E R0 AGND NC2 NC1 D AVDD R1 C D4 D3 D2 D1 D0 CTL1 AGND NC1 B CTL0 AGND A 3 2 SYSCLK 1 CNA LREQ XO 4 DGND DVDD 5 PLLGND XI 6 PLLVDD PLLGND 7 FILTER0 FILTER1 8 AVDD RESET 9 NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 GQE package terminal diagram—NC connections (bottom view) GQE PACKAGE TERMINAL DIAGRAM AGND SM AVDD TESTM SE CPS DVDD PC2 /ISO PC1 PC0 DGND (BOTTOM VIEW) TPB− C/LKON J LPS NC3 G NC NC NC4 NC4 NC4 NC F NC NC3 NC3 NC2 NC2 NC E NC1 NC1 B TPB+ H NC2 NC2 NC2 NC2 NC TPA− D7 PD TPA+ D5 D6 TPBIAS D4 D3 D2 D1 D0 CTL1 R0 AGND NC1 D NC1 NC1 NC2 NC AVDD R1 C NC B NC1 NC1 NC NC AGND CTL0 AGND 7 8 9 RESET AVDD 6 FILTER1 FILTER0 5 PLLGND PLLVDD 4 XI PLLGND 3 XO 2 LREQ CNA 1 DVDD DGND SYSCLK A NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor. 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 ZQE package terminal diagram—NC connections (bottom view) ZQE PACKAGE TERMINAL DIAGRAM AGND SM AVDD TESTM SE CPS DVDD PC2 /ISO PC1 PC0 DGND (BOTTOM VIEW) TPB− C/LKON J TPB+ LPS NC3 H NC TPA− D7 PD NC G D5 D6 NC3 NC3 NC2 NC E NC1 B TPA+ F NC2 NC2 NC2 TPBIAS D4 D3 D2 D1 D0 CTL1 R0 AGND NC1 D NC2 AVDD R1 C AGND CTL0 NC1 B AGND 7 8 9 RESET AVDD 6 FILTER1 FILTER0 5 PLLGND PLLVDD 4 XI PLLGND 3 XO 2 LREQ CNA 1 DVDD DGND SYSCLK A NOTES: A. NC − not connected B. For latch-up considerations, it is recommended that the TESTM terminal have a pullup resistor. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 9 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 functional block diagram CPS LPS ISO CNA† Received Data Decoder/Retimer Link Interface I/O SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 TPA+ TPA− Cable Port TPB+ Arbitration and Control State Machine Logic TPB− PC0 PC1 PC2 C/LKON Bias Voltage and Current Generator R0 R1 TPBIAS Transmit Data Encoder PD RESET † CNA output is only available in the 64-pin PAP package 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Crystal Oscillator, PLL System, and Clock Generator XI XO FILTER0 FILTER1 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 Terminal Functions TERMINAL NAME TYPE I/O DESCRIPTION A9, B9, D9, J8 Supply − Analog circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. 25, 35 B8, C8, H7 Supply − Analog circuit power terminals. A combination of high frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and DVDD inside the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. 15 J1 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset, this terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this terminal should be programmed low, and that the contender status be set via the C register bit. NUMBER PAP PHP GQE/ZQE AGND 32, 33, 39, 48, 49, 50 26, 32, 36 AVDD 30, 31, 42, 51, 52 19 C/LKON If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring LKON and also setting the contender status, then a 1-kΩ series resistor should be placed on the LKON line between the PHY and LLC to prevent bus contention. Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high-impedance. The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when: a) the PHY receives a link-on PHY packet addressed to this node, or b) the PEI (port-event interrupt) register bit is 1, or c) any of the CTOI (configuration-time-out interrupt), CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. Once activated, the link-on output continues active until the LLC becomes active (both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus reset occurs unless the link-on output would otherwise be active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). NOTE: If an interrupt condition exists which would otherwise cause the link-on output to be activated if the LLC were inactive, the link-on output is activated when the LLC subsequently becomes inactive. CNA 3 N/A B2 CMOS O Cable-not-active output. This terminal is asserted high when there is no incoming bias voltage. CNA is not valid at intial power up until a device hard reset is performed. CPS 24 20 J5 CMOS I Cable power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. This terminal should be tied directly to DGND through a 1-kΩ resistor if the application does not require it to be used. CTL0 CTL1 4 5 2 3 B1 C2 CMOS I/O Control I/Os. These bidirectional signals control communication between the TSB41AB1 and the LLC. Bus holders are built into these terminals. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 11 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 Terminal Functions (Continued) TERMINAL NUMBER TYPE I/O DESCRIPTION C1 D2 D1 E2 E1 F1 F2 G1 CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the LLC. Bus holders are built into these terminals. 14, 46, 47 B3, H2 Supply − Digital circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. 25, 26, 61, 62 21, 44, 45 A3, H5 Supply − Digital circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AVDD inside the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board. FILTER0 FILTER1 54 55 38 39 B7 A7 CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter required for stable operation of the internal frequency multiplier PLL running from the crystal oscillator. A 0.1-µF ±10% capacitor is the only external component required to complete this filter. ISO 23 19 H4 CMOS I Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL and D terminals. If an optional Annex J type isolation barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO terminal should be tied high through a pullup to disable the differentiation logic. For additional information see the TI application note Galvanic Isolation of the IEEE 1394-1995 Serial Bus, literature number SLLA011. LPS 15 13 H1 CMOS I Link power status input. This terminal monitors the active/power status of the link layer controller and controls the state of the PHY-LLC interface. This terminal should be connected through a 10-kΩ resistor either to the VDD supplying the LLC, or to a pulsed output which is active when the LLC is powered (see Figure 13). A pulsed signal should be used when an isolation barrier exists between the LLC and PHY (see Figure 14). NAME PAP PHP GQE/ZQE 6 7 8 9 10 11 12 13 4 5 6 7 8 9 10 11 DGND 17, 18, 63, 64 DVDD D0 D1 D2 D3 D4 D5 D6 D7 The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns to assure that a high is observed by the PHY. When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. LREQ 12 1 48 A2 CMOS I LLC request input. The LLC uses this input to initiate a service request to the TSB41AB1. Bus holder is built into this terminal. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 Terminal Functions (Continued) TERMINAL NUMBER TYPE I/O F8, G8, H8 − − Each of these terminals is not connected to the silicon device. B4, C5, D3, D4, D5, E3, E4 B4, D5, E4 Supply − Each of these terminals is not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the GND plane in application board. NC: Group 2 D6, E5, E6, E7, E8, F6, F7 D6, E5, E6, E8, F6 Supply − Each of these terminals is not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the VDD−supply plane in application board. NC: Group 3 F4, F5, H3 F4, F5, H3 Supply − Each of these terminals is not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the GND plane in application board. NC: Group 4 G5, G6, G7 − Supply − Each of these terminals are not connected to the silicon device, but they are connected to each other. It is recommended this group of terminals be used for a via connection to the VDD−supply plane in application board. NAME PAP PHP GQE ZQE NC C4, C6, C7, D7, F3, F8, G3, G4, G8, H8 NC: Group 1 DESCRIPTION PC0 PC1 PC2 20 21 22 16 17 18 J2 J3 J4 J2 J3 J4 CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying these terminals high or low. See Table 9 for encoding. PD 14 12 G2 G2 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output (64-terminal PAP package only). Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend/resume LPS and C/LKON features.) PLLGND 57, 58 41 A6, B5 A6, B5 Supply − PLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. PLLVDD 56 40 B6 B6 Supply − PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. This supply terminal is separated from DVDD and AVDD inside the device to provide noise isolation. It should be tied at a low-impedance point on the circuit board. R0 R1 40 41 33 34 D8 C9 D8 C9 Bias − Current setting resistor terminals. These terminals are connected through an external resistor to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ ±1.0% is required to meet the IEEE Std 1394-1995 output voltage limits. NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures. Signals tied to ground may be tied directly. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 13 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 Terminal Functions (Continued) TERMINAL NUMBER TYPE I/O DESCRIPTION A8 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. 23 H6 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal may be tied to GND through a 1-kΩ pulldown resistor or it may be tied to GND directly. 29 24 J7 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to GND. SYSCLK 2 1 A1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. TESTM 27 22 J6 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For normal, use this terminal should be tied to VDD through a 1-kΩ resistor. TPA+ 37 30 F9 Cable I/O TPA− 36 29 G9 Cable I/O Twisted-pair cable A differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. TPB+ 35 28 H9 Cable I/O TPB− 34 27 J9 Cable I/O TPBIAS 38 31 E9 Cable I/O Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. XI XO 59 60 42 43 A5 A4 Crystal − Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Application Information section). When an external clock source is used, XI should be the input and XO should be left open, and the clock must be supplied before the device is taken out of reset. NAME PAP PHP GQE/ZQE RESET 53 37 SE 28 SM Twisted-pair cable B differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures. Signals tied to ground may be tied directly. 14 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING PAP§ PAP¶ 4.78 W 38 mW/°C 3.06 W 2.13 W 17 mW/°C 1.36 W PAP# PHP§ 2.08 W 16 mW/°C 1.33 W 3.92 W 31.4 mW/°C 2.51 W PHP¶ PHP# 1.9 W 10.4 mW/°C 1.22 W PACKAGE 1.45 W 11 mW/°C 0.93 W GQE|| GQE# 1.76 W 17.6 mW/°C 0.97 W 0.84 W 8.4 mW/°C 0.46 W ZQE|| ZQE# 1.71 W 17.1 mW/°C 0.94 W 0.83 W 8.4 mW/°C 0.45 W ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). § 1 oz. trace and copper pad with solder ¶ 1 oz. trace and copper pad without solder # Standard JEDEC low-K board || Standard JEDEC high-K board For more information, refer to TI technical brief PowerPAD Thermally Enhanced Package, TI literature number SLMA002. PowerPAD is a trademark of Texas Instruments. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 15 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 recommended operating conditions TYP† MIN Source power node Supply voltage, VDD 3 2.7‡ Non-source power node LREQ, CTL0, CTL1, D0 −D7 High-level input voltage, VIH 3.3 3.6 3 3.6 2.6 C/LKON, PC0, PC1, PC2, ISO, PD 0.7 VDD RESET 0.6 VDD LREQ, CTL0, CTL1, D0 −D7 Low-level input voltage, VIL MAX V V 1.2 0.2 VDD RESET 0.3 VDD TPBIAS outputs Maximum junction temperature, TJ (see RθJA values listed in thermal characteristics table) 64PAP RθJA = 26.1°C/W, Maximum junction temperature, TJ (see RθJA values listed in thermal characteristics table) 48PHP RθJA = 31.9°C/W, −5.6 1.3 TA = 70°C TA = 70°C 78.9 TA = 70°C TA = 70°C 90.5 92.5 RθJA = 85.6°C/W, TA = 70°C TA = 70°C Maximum junction temperature, TJ (see RθJA JA values listed in thermal characteristics table) 80GQE RθJA = 56.61°C/W, TA = 70°C 80.19 RθJA = 118.12°C/W, TA = 70°C 91.26 Maximum junction temperature, TJ (see RθJA JA values listed in thermal characteristics table) 64ZQE RθJA = 58.32°C/W, TA = 70°C 80.50 RθJA = 119.63°C/W, TA = 70°C 91.53 Differential input voltage, VID RθJA = 58.6°C/W, RθJA = 60.1°C/W, RθJA = 65.8°C/W, 90 118 260 Cable inputs, during arbitration 168 265 2.515 2.015‡ TPB cable inputs, source power node 0.4706 TPB cable inputs, nonsource power node 0.4706 Power-up reset time, t(pu) RESET input Receive input skew 2 16 ± 0.5 ± 0.315 Between TPA and TPB cable inputs, S100 operation ± 0.8 Between TPA and TPB cable inputs, S200 operation ± 0.55 Between TPA and TPB cable inputs, S400 operation ± 0.5 • • °C C °C C °C °C mV V ± 1.08 TPA, TPB cable inputs, S400 operation POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 V mA ms TPA, TPB cable inputs, S200 operation † All typical values are at VDD = 3.3 V and TA = 25°C. ‡ For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000. V 99.3 Cable inputs, during data reception TPA, TPB cable inputs, S100 operation V 80.9 Common-mode input voltage, VIC Receive input jitter V V C/LKON, PC0, PC1, PC2, ISO, PD Output current, IO UNIT ns ns 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential output voltage 56 Ω, See Figure 1 172 265 mV I(DIFF) Driver difference current, TPA+, TPA−, TPB+, TPB− Drivers enabled, speed signaling off −1.05† 1.05† mA I(SP200) I(SP400) Common mode speed signaling current, TPB+, TPB− S200 speed signaling enabled S400 speed signaling enabled −2.53‡ −8.1‡ mA Common mode speed signaling current, TPB+, TPB− −4.84‡ −12.4‡ VOD mA V(OFF) Off state differential voltage Drivers disabled, See Figure 1 20 mV † Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents. ‡ Limits defined as absolute limit of each of TPB+ and TPB− driver currents receiver PARAMETER zid TEST CONDITIONS Differential impedance MIN TYP 4 7 Drivers disabled MAX UNIT kΩ 4 20 pF kΩ zic Common-mode impedance Drivers disabled 24 pF V(TH−R) V(TH−CB) Receiver input threshold voltage Drivers disabled −30 30 mV Cable bias detect threshold, TPB cable inputs Drivers disabled 0.6 1 V V(TH+) Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV V(TH−) Negative arbitration comparator threshold voltage Drivers disabled −168 −89 mV V(TH−SP200) Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 49 131 mV V(TH−SP400) Speed signal threshold TPBIAS−TPA common-mode voltage, drivers disabled 314 396 mV • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 17 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued) device PARAMETER IDD TEST CONDITIONS Supply current MIN TYP MAX UNIT See Note 2 48 See Note 3 42 See Note 4 41 150 µA 150 µA mA IDD(ULP) Supply current, ultralow-power mode VDD = 3.3 V, TA = 25°C, Port disabled or unconnected, PD = 0 V, LPS = 0 V IDD(PD) Supply current, power-down mode PD = VDD, TA= 25°C V(TH) Power status threshold, CPS input† 400-kΩ resistor† 4.7 High-level output voltage, CTL0, CTL1, D0 −D7, CNA, C/LKON, SYSCLK outputs VDD = 2.7 V, IOH = − 4 mA VDD = 3 to 3.6 V, IOH = − 4 mA 2.2 VOH VOL Low-level output voltage, CTL0, CTL1, D0 −D7, CNA, C/LKON, SYSCLK outputs IOL = 4 mA VOH(AJ) High-level Annex J output voltage, CTL0, CTL1, D0 −D7, C/LKON, SYSCLK outputs Annex J: IOH = − 9 mA, ISO = 0 V, VDD ≥ 3 V VOL(AJ) Low-level Annex J output voltage, CTL0, CTL1, D0−D7, C/LKON, SYSCLK outputs Annex J: IOL = 9 mA, ISO = 0 V, VDD ≥ 3 V I(BH+) Positive peak bus holder current, D0 −D7, CTL0 , CTL1, LREQ ISO = 3.6 V, VDD = 3.6 V, VI = 0 V to VDD 0.05 1 mA I(BH−) Negative peak bus holder current, D0 −D7, CTL0, CTL1, LREQ ISO = 3.6 V, VDD = 3.6 V, VI = 0 V to VDD −1.0 −0.05 mA II Input current, LREQ, LPS, PD, TESTM, SM, PC0 – PC2 inputs ISO = 0 V, 5 µA IOZ Off-state output current, CTL0, CTL1, D0 – D7, C/LKON I/Os VO = VDD or 0 V ±5 µA −90 −20 µA 5 50 µA I(IRST) I(SE−Pd) VIT+ VIT − VO Pullup current, RESET input Pullup/pulldown current, SE input VDD = 3.3 V, 7.5 V 2.8 0.4 VDD−0.4 VI = 1.5 V or 0 V VI = VDD/2 or VDD Positive input threshold voltage, LREQ, CTL0, CTL1, D0 – D7 inputs‡ ISO = 0 V, Positive input threshold voltage, LPS inputs ISO = 0 V, VDD = 3 V to 3.6 V Vref = 0.4 VDD Negative input threshold voltage, LREQ, CTL0, CTL1, D0 – D7 inputs‡ ISO= 0 V, Negative input threshold voltage, LPS inputs ISO= 0 V, Vref = 0.4 VDD, VDD = 3 V to 3.6 V VDD = 3 V to 3.6 V VDD = 3 V to 3.6 V TPBIAS output voltage§ VDD/2+0.3 V V 0.4 VDD = 3.6 V V V VDD/2+0.9 V VREF+1 VDD/2−0.9 VDD/2−0.3 V Vref+0.2 At rated IO current 1.665 2.015 V † Measured at cable power side of resistor ‡ This parameter applicable only when ISO low § TPBIAS is typically VDD−0.2 V when the port is not connected. NOTES: 2. Transmit maximum packet (one port transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous interval, S400, data value of CCCCCCCCh), VDD = 3.3 V, TA = 25°C. 3. Receive typical packet (one port receiving DV packets on every isochronous interval, S100), VDD = 3.3 V, TA = 25°C. 4. Idle (one port transmitting cycle starts), VDD = 3.3 V, TA = 25°C. 18 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 thermal characteristics, PAP package TEST CONDITIONS† PARAMETER RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case-thermal resistance RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case thermal resistance RθJA Junction-to-ambient thermal resistance MIN TYP MAX UNIT 26 °C/W 5.9 °C/W Board-mounted, no air flow, high conductivity TI-recommended test board with thermal land, but no solder or grease thermal connection to thermal land with 1 oz. copper 58.6 °C/W 5.9 °C/W Board-mounted, no air flow, low conductivity JEDEC test board with 1 oz. copper 60.1 °C/W 5.9 °C/W Board-mounted, no air flow, high conductivity TI-recommended test board, chip soldered or greased to thermal land with 1 oz. copper RθJC Junction-to-case thermal resistance † Use of thermally enhanced PowerPad PAP package is assumed in all three test conditions. thermal characteristics, PHP package TEST CONDITIONS† PARAMETER MIN TYP MAX UNIT Board-mounted, no air flow, high conductivity TI-recommended test board, chip soldered or greased to thermal land with 1 oz. copper 31.9 °C/W 6.2 °C/W Board-mounted, no air flow, high conductivity TI-recommended test board with thermal land, but no solder or grease thermal connection to thermal land with 1 oz. copper 65.8 °C/W 6.2 °C/W Junction-to-ambient thermal resistance Board-mounted, no air flow, low conductivity JEDEC test board with 1 oz. copper RθJC Junction-to-case thermal resistance † Use of thermally enhanced PowerPad PHP package is assumed in all three test conditions. 85.7 °C/W 6.2 °C/W RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case-thermal resistance RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case thermal resistance RθJA thermal characteristics, GQE package PARAMETER TEST CONDITIONS RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case-thermal resistance RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case-thermal resistance MIN TYP MAX UNIT Board-mounted, no air flow, JEDEC low-k test board, no thermal vias used on board 118.12 °C/W 38.62 °C/W Board-mounted, no air flow, JEDEC high-k test board, no thermal vias used on board 56.61 °C/W 38.62 °C/W thermal characteristics, ZQE package PARAMETER TEST CONDITIONS RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case-thermal resistance RθJA Junction-to-ambient thermal resistance RθJC Junction-to-case-thermal resistance MIN TYP MAX UNIT Board-mounted, no air flow, JEDEC low-k test board, no thermal vias used on board 119.63 °C/W 39.03 °C/W Board-mounted, no air flow, JEDEC high-k test board, no thermal vias used on board 58.32 °C/W 39.09 °C/W • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 19 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 switching characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Jitter, transmit Between TPA and TPB ± 0.15 ns Skew, transmit Between TPA and TPB ± 0.1 ns th tsu Hold time, CTL0, CTL1, D0 – D7, LREQ after SYSCLK 50% to 50%, See Figure 2 2 ns Setup time, CTL0, CTL1, D0 – D7, LREQ to SYSCLK 50% to 50%, See Figure 2 Delay time, SYSCLK to CTL0, CTL1, D0 – D7 50% to 50%, See Figure 3 5 2‡ ns td tr TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns 90% to 10%, at 1394 connector 0.5 1.2 ns tf TP differential fall time, transmit ‡ Test Conditions: 3.3 VCC, TA = 25°C 20 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • ns 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PARAMETER MEASUREMENT INFORMATION TPA+ TPB+ 56 Ω TPA− TPB− Figure 1. Test Load Diagram SYSCLK th tsu Dx, CTLx, LREQ Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms SYSCLK td Dx, CTLx Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 21 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection Details regarding connection of components to the various terminals of the TSB41AB1 are discussed primarily in entries for each terminal in the terminal functions table. Figure 4, Figure 5, Figure 6, and Figure 8 are diagrammatic views showing the connections for all required external components. Note: All component connection diagrams are top view. 6.34 kΩ ± 1% 12 pF¶ 12 pF¶ 60 24.576 MHz 61 VDD 62 0.001 µF 63 64 TPB− TPA+ TPBIAS R0 AGND R1 AVDD NC NC NC NC NC AGND PLLGND CPS PLLGND ISO XI PC2 XO PC1 DVDD PC0 DVDD C/LKON DGND DGND DGND LREQ 0.1 µF DVDD TSB41AB1 2 3 4 5 6 7 8 CNA OUT 1 DGND 9 † See Figure 10, Figure 11, and Figure 12. NC 59 PLLVDD LPS 58 DVDD PD 57 FILTER1 10 11 12 13 14 15 16 POWER DOWN 0.01 µF TESTM D7 1.0 µF FILTER0 D6 56 SE D5 VDD 55 RESET D4 0.1 µF SM D3 54 AVDD AVDD D2 53 AVDD D1 0.1 µF AVDD D0 52 AGND AGND CTL1 51 AGND CTL0 VDD 50 CNA 0.001 µF SYSCLK 49 0.001 µF 0.1 µF AGND 36 35 34 33 48 47 46 45 44 43 42 41 40 39 38 37 TPA− VDD TP Cables Interface Connection † 0.001 µF TPB+ 0.001 µF 0.1 µF ‡ ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. ¶ See crystal selection section for more details Figure 4. External Component Connections (PAP) 22 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 32 0.001 µF 31 0.1 µF 0.001 µF 30 VDD 29 28 27 1 kΩ (Optional) § 1 kΩ VDD 0.001 µF 26 25 24 23 0.001 µF DGND 400 kΩ Cable Power ISO 22 21 20 Power-Class Programming LKON Bus Manager 19 18 17 0.1 µF 10 kΩ 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection (continued) 0.001 µF 0.1 µF VDD 0.001 µF TP Cables Interface Connection † 6.34 kΩ ± 1% 44 12 pF¶ 45 VDD 46 0.1 µF 0.001 µF 47 AVDD TPB− AGND TPA− TPBIAS TPA+ R0 TPB+ ISO TSB41AB1 XO PC2 DVDD PC1 DVDD PC0 DGND C/LKON DGND DGND LREQ LPS 1 CTL0 SYSCLK 48 XI 2 3 4 5 6 7 8 9 1 kΩ (Optional) § 23 22 1 kΩ VDD 0.001 µF 21 20 19 400 kΩ 0.001 µF 0.1 µF Cable Power DGND ISO 18 17 Power-Class Programming 16 LKON Bus Manager 15 10 kΩ 14 13 ‡ PD 24.576 MHz CPS 24 10 11 12 POWER DOWN 12 pF¶ 43 DVDD PLLGND D7 42 PLLVDD D6 41 D5 0.01 µF TESTM FILTER1 D4 1.0 µF SE D3 40 FILTER0 D2 VDD 39 SM D1 0.1 µF RESET D0 38 CTL1 37 AGND AVDD AGND 0.1 µF R1 36 35 34 33 32 31 30 29 28 27 26 25 † See Figure 10, Figure 11, and Figure 12. ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. ¶ See crystal selection section for more details Figure 5. External Component Connections (PHP) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 23 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection (continued) 6.34 k B C D TPB− TPB+ TPA− TPA+ TPBIAS AGND R0 F A 0.1 TP Cables Interface Connections † 0.001 AVDD AGND F R1 0.001 AVDD 0.1 F AGND VDD E F G H NC NC NC NC J 9 F /RESET 0.1 F FILTER0 8 AGND FILTER1 PLLVDD VDD  F 7 NC NC NC NC SM NC SE 24.576 MHz NC NC NC NC NC TESTM 5 NC NC NC NC NC CPS 0.1 0.001 F DGND VDD 1k 0.001 F 0.001 F VDD F /ISO 4 NC NC NC NC NC NC NC NC /ISO PC2 NC DVDD 3 400 k NC NC PC1 Power−Class Programming LREQ 2 PC0 LKON Bus Manager 1 DGND LPS POWER DOWN D7 PD D6 D5 D3 D4 D1 D2 CTL1 CNA OUT D0 CNA CTL0 SYSCLK C/LKON † See Figure 10, Figure 11, and Figure 12. ‡ ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. ¶ See crystal selection section for more details Figure 6. External Component Connections (GQE) 24 0.1 Cable Power XO F 0.1 F DVDD 12 pF ¶ VDD F (Optional) § 1 k
6 XI 12 pF ¶ 0.001 F AVDD  F PLLGND PLLGND 0.001 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 10 k 400 k 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection (continued) DGND PC0 PC1 /ISO PC2 DVDD CPS SE TESTM AVDD SM AGND GQE package terminal diagram (TOP VIEW) TPB− J C/LKON TPB+ NC3 NC H LPS TPA− NC NC4 NC4 NC4 NC NC G D7 PD TPA+ NC NC2 NC2 NC3 NC3 NC F D5 D6 TPBIAS NC2 NC2 B NC2 NC2 NC1 NC1 E R0 AGND NC NC2 NC1 NC1 NC1 D AVDD R1 NC NC NC1 NC C D4 D3 D2 D1 D0 CTL1 AGND NC1 B CTL0 AGND A 4 XO 2 3 SYSCLK 1 CNA LREQ 5 DGND DVDD 6 PLLGND XI 7 FILTER0 FILTER1 AVDD RESET 8 PLLVDD PLLGND 9 NOTE: NC − not connected Figure 7. Recommended Application Board Layout for GQE Package • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 25 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection (continued) 6.34 k C D TPB− TPB+ TPA+ TPBIAS R0 B AGND R1 AVDD AGND F A 0.1 TP Cables Interface Connections † 0.001 F TPA− 0.001 AVDD 0.1 F AGND VDD E F G H NC NC NC NC J 9 F /RESET 0.1 F FILTER0 8 AGND FILTER1 PLLVDD VDD  F 7 SM SE 24.576 MHz NC NC NC TESTM 5 NC NC NC CPS 0.1 0.001 F DGND VDD 1k 0.001 F 0.001 F VDD F /ISO 4 NC NC 400 k /ISO PC2 NC DVDD 3 NC PC1 Power−Class Programming LREQ 2 PC0 LKON Bus Manager 1 DGND LPS POWER DOWN D7 PD D6 D5 D3 D4 D1 D2 CTL1 CNA OUT D0 CNA CTL0 SYSCLK C/LKON † See Figure 10, Figure 11, and Figure 12. ‡ ‡ See Figure 13 and Figure 14. § See Terminal Functions Table. ¶ See crystal selection section for more details Figure 8. External Component Connections (ZQE) 26 0.1 Cable Power XO F 0.1 F DVDD 12 pF ¶ VDD F (Optional) § 1 k
6 XI 12 pF ¶ 0.001 F AVDD  F PLLGND PLLGND 0.001 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 10 k 400 k 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection (continued) DGND PC0 PC1 /ISO PC2 DVDD CPS SE TESTM AVDD SM AGND ZQE Package Terminal Diagram (TOP VIEW) TPB− J C/LKON TPB+ NC3 NC H LPS TPA− NC G D7 PD TPA+ NC NC2 NC3 NC3 F D5 D6 TPBIAS NC2 B NC2 NC2 NC1 E R0 AGND NC2 NC1 D AVDD R1 C D4 D3 D2 D1 D0 CTL1 AGND NC1 B CTL0 AGND A 4 XO 2 3 SYSCLK 1 CNA LREQ 5 DGND DVDD 6 PLLGND XI 7 FILTER0 FILTER1 AVDD RESET 8 PLLVDD PLLGND 9 NOTE: NC − not connected Figure 9. Recommended Application Board Layout for ZQE Package • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 27 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection (continued) Outer Shield Termination TSB41AB1 400 kΩ CPS TPBIAS 56 Ω‡ 1 µF Cable Power Pair 56 Ω‡ TPA+ Cable Pair A TPA− Cable Port TPB+ Cable Pair B TPB− 56 Ω‡ 56 Ω‡ 220 pF † 5 kΩ † The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended. ‡ ± 0.5% to meet 1394−1995 specification. Figure 10. TP Cable Connections Outer Cable Shield 1 MΩ 0.01 µF 0.001 µF Chassis GND Figure 11. Compliant DC Isolated Outer Shield Termination 28 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION component connection (continued) Outer Shield Termination Chassis GND Figure 12. Nonisolated Outer Shield Termination 10 kΩ Link Power LPS Square Wave Input LPS 10 kΩ Figure 13. Nonisolated Circuit Connection Variations for LPS PHY VDD 13.7 kΩ LPS Square Wave Signal 0.033 µF 10 kΩ PHY GND NOTE: As long as the resistance ratio is maintained between 1.61:1 and 1.33:1, any values of resistors may be used. Figure 14. Isolated Circuit Connection for LPS crystal selection The TSB41AB1 and other TI PHY devices are designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates. A variation of less than ± 100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data. For the TSB41AB1, the SYSCLK output may be used to measure the frequency accuracy and stability of the internal oscillator and PLL from which it is derived. The frequency of the SYSCLK output must be within ± 100 ppm of the nominal frequency of 49.152 MHz. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 29 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION crystal selection (continued) The following are some typical specifications for crystals used with the physical layers from TI in order to achieve the required frequency accuracy and stability: D Crystal mode of operation: Fundamental D Frequency tolerance at 25°C: Total frequency variation for the complete circuit is ± 100 ppm. A crystal with ± 30-ppm frequency tolerance is recommended for adequate margin. D Frequency stability (over temperature and age): A crystal with ± 30-ppm frequency stability is recommended for adequate margin. NOTE:The total frequency variation must be kept below ± 100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ± 100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation. D Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function not only of the discrete load capacitors, but also of the board layout and circuit. It may be necessary to select discrete load capacitors iteratively until the SYSCLK output is within specification. It is recommended that load capacitors with a maximum of ± 5% tolerance be used. As an example, for the OHCI + 41AB1 evaluation module (EVM), which uses a crystal specified for 12 pF loading, load capacitors (C9 and C10 in Figure 15) of 16 pF each were appropriate for the layout of that particular board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals (C(PHY)), and the loading of the board itself (C(BD)). The value of C(PHY) is typically about 1 pF, and C(BD) is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is: C + ƪ(C9 L C10 ) ń (C9 ) C10 )ƫ ) C (PHY) )C (1) (BD) C9 XI 24.576 MHz X1 C(PHY) + C(BD) XO C10 Figure 15. Load Capacitance for the TSB41AB1 PHY 30 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION crystal selection (continued) The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHYs phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors should be considered as a unit during layout. The crystal and load capacitors should be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Figure 16 depicts a layout that meets these guidelines. C9 C10 X1 Figure 16. Recommended Crystal and Capacitor Layout It is strongly recommended that part of the verification process for the design be to measure the frequency of the SYSCLK output of the PHY. This should be done with a frequency counter with an accuracy of six digits or better. If the SYSCLK frequency is more than the crystal tolerance from 49.152 MHz, the load capacitance of the crystal may be varied to improve frequency accuracy. If the frequency is too high, add more load capacitance; if the frequency is too low, decrease load capacitance. Typically, changes should be done to both load capacitors (C9 and C10, see Figure 15) at the same time, and both should be of the same value. Additional design details and requirements may be provided by the crystal vendor. For more information, see Selection and Specification of Crystals for Texas Instruments IEEE 1394 Physical Layers, TI literature number SLLA051. EMI guidelines For electromagnetic interference (EMI) guidelines and recommendations, check the web site http://www.ti.com/1394emi−guidelines designing with the PowerPad package The TSB41AB1 is housed in high-performance, thermally enhanced, 48/64-terminal PHP/PAP PowerPAD packages. Use of a PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed metallic pad on the bottom of the device, is a thermal and electrical conductor. This exposed pad is connected inside the package to the substrate of the silicon die; it is not connected to any terminal of the package. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required of the keep-out area is 8 mm × 8 mm for the 64-terminal PAP PowerPAD package, and 5 mm × 5 mm for the 48-terminal PHP PowerPAD package. It is recommended that there be a thermal land, which is an area of solder-tinned-copper (see Figure 17), underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 31 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION designing with the PowerPad package (continued) Other requirements for thermal lands and thermal vias are detailed in the PowerPAD Thermally Enhanced Package technical brief, TI literature number SLMA002, available via the TI Web pages beginning at URL http://www.ti.com. Figure 17. Example of a Thermal Land for the TSB41AB1PAP PHY For the TSB41AB1, this thermal land should be grounded to the low-impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size should be as large as possible without shorting device signal terminals. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques. While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More information may be obtained from the TI application report Recommendations for PHY Layout, TI literature number SLLA020. internal register configuration There are 16 accessible internal registers in the TSB41AB1. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0 through 7, is currently selected. The selected page is set in base register 7. The configuration of the base registers is shown in Table 1, and corresponding field descriptions are given in Table 2. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved or Rsvd in register configuration tables) is read as 0, but is subject to future usage. All registers in pages 2 through 6 are reserved. Table 1. Base Register Configuration ADDRESS BIT POSITION 0 1 2 0000 0001 3 RHB 0010 IBR 6 7 R CPS Gap_Count Num_Ports (00001b) PHY_Speed (010b) Rsvd 0100 LCtrl C Jitter (000b) 0101 RPIE ISBR CTOI CPSI 0110 0111 5 Extended (111b) 0011 32 4 Physical ID Delay (0000b) Pwr_Class STOI PEI EAA Reserved Page_Select Rsvd • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Port_Select EMC 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration (continued) Table 2. Base Register Field Descriptions SIZE TYPE DESCRIPTION Physical ID FIELD 6 Rd This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. R 1 Rd Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during tree-ID if this node becomes root. CPS 1 Rd Cable power status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable power voltage has dropped below its threshold for reliable operation. RHB 1 Rd/Wr Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB is reset to 0 by hardware reset and is unaffected by bus reset. IBR 1 Rd/Wr Initiate bus reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR bit is reset to 0 by hardware reset or bus reset. Gap_Count 6 Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count may be set either by a write to this register or by reception or transmission of a PHY_CONFIG packet. The gap count is set to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). Extended 3 Rd Extended register definition. For the TSB41AB1 this field is 111b, indicating that the extended register set is implemented. Num_Ports 5 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41AB1 this field is 1. PHY_Speed 3 Rd PHY speed capability. For the TSB41AB1 PHY this field is 010b, indicating S400 speed capability. Delay 4 Rd PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed as 144+(Delay*20) ns. For the TSB41AB1 this field is 0. LCtrl 1 Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is considered active only if the LPS input is active and the LCtrl bit is set. The LCtrl bit provides a software controllable means to indicate the LLC active /status in lieu of using the LPS input. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset. NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received packets and status information continue to be presented on the interface, and any requests indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0. C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state specified by the C/LKON input terminal upon hardware reset and is unaffected by bus reset. Jitter 3 Rd PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data delay, expressed as (Jitter+1)×20 ns. For the TSB41AB1 this field is 0. Pwr_Class 3 Rd/Wr Node power class. This field indicates this node’s power consumption and source characteristics, and is replicated in the pwr field (bits 21– 23) of the self-ID packet. This field is set to the state specified by the PC0– PC2 input terminals upon hardware reset and is unaffected by bus reset (see Table 9). • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 33 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION Table 2. Base Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION RPIE 1 Rd/Wr Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set whenever resume operations begin on any port. This bit also enables the C/LKON output signal to be activated whenever the LLC is inactive and any of the CTOI, CPSI, or STOI interrupt bits are set. This bit is reset to 0 by hardware reset and is unaffected by bus reset. ISBR 1 Rd/Wr Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.30 µs) arbitrated bus reset at the next opportunity. This bit is reset to 0 by bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed. CTOI 1 Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the CTOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. NOTE: If the network is configured in a loop, only those nodes that are part of the loop generate a configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus reset. CPSI 1 Rd/Wr Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared by writing a 1 to this register bit. If the CPSI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. STOI 1 Rd/Wr State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the STOI and RPIE bits are both set and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. PEI 1 Rd/Wr Port event interrupt. This bit is set to 1 upon a change in the bias, connected, disabled, or fault bits for any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on the port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the PEI bit is set (regardless of the state of the RPEI bit) and the LLC is or becomes inactive, the PHY activates the C/LKON output to notify the LLC to service the interrupt. EAA 1 Rd/Wr Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in IEEE 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The EAA bit should be set only if the attached LLC is IEEE 1394a-2000 compliant. If the LLC is not IEEE 1394a-2000 compliant, use of the arbitration acceleration enhancements may interfere with isochronous traffic by excessively delaying the transmission of cycle-start packets. EMC 1 Rd/Wr Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in IEEE 1394a-2000. This bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be IEEE 1394a-2000 compliant. Page_Select 3 Rd/Wr Page select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by hardware reset and is unaffected by bus reset. Port_Select 4 Rd/Wr Port select. This field selects the port when accessing per-port status or control (for example, when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by hardware reset and is unaffected by bus reset. 34 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration (continued) The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is shown in Table 3, and corresponding field descriptions are given in Table 4. If the selected port is unimplemented, all registers in the port status page are read as 0. Table 3. Page 0 (Port Status) Register Configuration BIT POSITION ADDRESS 1000 1001 0 1 2 Astat 3 Bstat Peer_Speed PIE 5 6 7 Con Bias Dis Fault 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved • 4 Ch POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • Reserved 35 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration (continued) Table 4. Page 0 (Port Status) Register Field Descriptions SIZE TYPE Astat FIELD 2 Rd TPA line state. This field indicates the TPA line state of the selected port, encoded as follows: Code Line State 00 invalid 01 1 10 0 11 Z DESCRIPTION Bstat 2 Rd TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the Astat field. Ch 1 Rd Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus reset until tree-ID has completed. Con 1 Rd Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341 ms for the con bit to be set to 1. The con bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The con bit indicates that the port is physically connected to a peer PHY, but the port is not necessarily active. Bias 1 Rd Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 52 µs for the bias bit to be set to 1. Dis 1 Rd/Wr Port disabled control. If 1, the selected port is disabled. The dis bit is reset to 0 by hardware reset (all ports are enabled for normal operation following hardware reset). The dis bit is not affected by bus reset. Peer_Speed 3 Rd Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the selected port, encoded as follows: Code Peer Speed 000 S100 001 S200 010 S400 011–111 invalid The Peer_Speed field is invalid after a bus reset until self-ID has completed. NOTE: Peer speed codes higher than 010b (S400) are defined in IEEE 1394a-2000. However, the TSB41AB1 is only capable of detecting peer speeds up to S400. PIE 1 Rd/Wr Port event interrupt enable. When set to 1, a port event on the selected port sets the port event interrupt (PEI) bit and notifies the link. This bit is reset to 0 by hardware reset and is unaffected by bus reset. Fault 1 Rd/Wr Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus reset. 36 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration (continued) The vendor identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. The configuration of the vendor identification page is shown in Table 5, and corresponding field descriptions are given in Table 6. Table 5. Page 1 (Vendor ID) Register Configuration BIT POSITION ADDRESS 0 1 2 3 4 1000 5 6 7 Compliance 1001 Reserved 1010 Vendor_ID[0] 1011 Vendor_ID[1] 1100 Vendor_ID[2] 1101 Product_ID[0] 1110 Product_ID[1] 1111 Product_ID[2] Table 6. Page 1 (Vendor ID) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Compliance 8 Rd Compliance level. For the TSB41AB1 this field is 01h, indicating compliance with IEEE 1394a-2000. Vendor_ID 24 Rd Manufacturer’s organizationally unique identifier (OUI). For the TSB41AB1 this field is 08 0028h (Texas Instruments) (the MSB is at register address 1010b). Product_ID 24 Rd Product identifier. For the TSB41AB1 this field is 42 XXXXh (the MSB is at register address 1101b). The vendor-dependent page provides access to the special control features of the TSB41AB1, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. The configuration of the vendor-dependent page is shown in Table 7, and corresponding field descriptions are given in Table 8. Table 7. Page 7 (Vendor-Dependent) Register Configuration BIT POSITION ADDRESS 1000 0 1 2 3 NPA 4 Reserved 1001 Reserved for test 1010 Reserved for test 1011 Reserved for test 1100 Reserved for test 1101 Reserved for test 1110 SWR 5 6 7 Link_Speed Reserved for test 1111 Reserved for test • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 37 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION internal register configuration (continued) Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions SIZE TYPE DESCRIPTION NPA FIELD 1 Rd/Wr Null-packet actions flag. This bit instructs the PHY not to clear fair and priority requests when a null packet is received with arbitration acceleration enabled. If 1, then fair and priority requests are cleared only when a packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and malformed packets (less than 8 data bits) do not clear fair and priority requests. If 0, then fair and priority requests are cleared when any non-ACK packet is received, including null packets or malformed packets of less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus reset. Link_Speed 2 Rd/Wr Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows: Code Speed 00 S100 01 S200 10 S400 11 illegal This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs during self-ID; the TSB41AB1 PHY identifies itself as S400 capable to its peers regardless of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus reset. SWR 1 Rd/Wr Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (just as momentarily asserting the RESET terminal low). This bit is always read as a 0. power-class programming The PC0– PC2 terminals are programmed to set the default value of the power class indicated in the pwr field (bits 21 – 23) of the transmitted self-ID packet. Descriptions of the various power classes are given in Table 9. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 9. Power Class Descriptions PC0−PC2 38 DESCRIPTION 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. 100 Node may be powered from the bus for the PHY only using up to 3 W and may also provide power to the bus. The amount of bus power that it provides can be found in the configuration ROM. 101 Reserved 110 Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. 111 Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION using the TSB41AB1 with a non-IEEE 1394a-2000 link layer The TSB41AB1 implements the PHY-LLC interface specified in IEEE 1394a-2000. This interface is based upon the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in older TI PHY devices. The PHY-LLC interface specified in IEEE 1394a-2000 is completely compatible with the older Annex J interface. IEEE 1394a-2000 includes enhancements to the Annex J interface that must be comprehended when using the TSB41AB1 with a non-IEEE 1394a-2000 LLC device. D A new LLC service request was added which allows the LLC to enable and disable asynchronous arbitration accelerations temporarily. If the LLC does not implement this new service request, the arbitration enhancements should not be enabled (see the EAA bit in PHY register 5). D The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, multispeed concatenation should not be enabled in the PHY (see the EMC bit in PHY register 5). D In order to accommodate the higher transmission speeds expected in future revisions of the standard, IEEE 1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new IEEE 1394a-2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB41AB1 correctly interprets both 7-bit bus requests (with 2-bit speed codes) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (for example, a register read or write request), the TSB41AB1 correctly interprets both requests. Although the TSB41AB1 correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 results in the TSB41AB1 transmitting a null packet (data-prefix followed by data-end, with no data in the packet). More explanation is included in the TI application note IEEE 1394a Features Supported by TI TSB41LV0X Physical Layer Devices, TI literature number SLLA019. using the TSB41AB1 with a lower-speed link layer Although the TSB41AB1 is an S400 capable PHY, it may be used with lower speed LLCs, such as the S200 capable TSB12LV31. In such a case, the LLC has fewer data terminals than the PHY, and some Dn terminals on the TSB41AB1 remain unused. Unused Dn terminals should be pulled to ground through 10-kΩ resistors. The TSB41AB1 transfers all received packet data to the LLC, even if the speed of the packet exceeds the capability of the LLC to accept it. Some lower speed LLC designs do not properly ignore packet data in such cases. On the rare occasions that the first 16 bits of partial data accepted by such an LLC match the bus ID and node ID for that node, spurious header CRC or tcode errors may result. During bus initialization following a bus reset, each PHY transmits a self-ID packet that indicates, among other information, the speed capability of the PHY. The bus manager (if one exists) builds a speed map from the collected self-ID packets. This speed map gives the highest possible speed that can be used on the node-to-node communication paths between every pair of nodes in the network. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 39 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION using the TSB41AB1 with a lower-speed link layer (continued) In the case of a node consisting of a higher-speed PHY and a lower-speed LLC, the speed capability of the node (PHY and LLC in combination) is that of the lower-speed LLC. A sophisticated bus manager may be able to determine the LLC speed capability by reading the configuration ROM Bus_Info_Block, or by sending asynchronous request packets at different speeds to the node and checking for an acknowledge; the speed map may then be adjusted accordingly. The speed map should reflect that communication to such a node must be done at the lower speed of the LLC, instead of the higher speed of the PHY. However, speed-map entries for paths that merely pass through the node PHY, but do not terminate at that node, should not be restricted by the lower speed of the LLC. To assist in building an accurate speed map, the TSB41AB1 can indicate a speed capability other than S400 in its transmitted self-ID packet. This is controlled by the Link_Speed field in register 8 of the vendor-dependent page (page 7). Setting the Link_Speed field affects only the speed indicated in the self-ID packet; it has no effect on the speed signaled to peer PHYs during self-ID. The TSB41AB1 identifies itself as S400 capable to its peers regardless of the value in the Link_Speed field. Generally, the Link_Speed field should not be changed from its power-on default value of S400 unless it is determined that the speed map (if one exists) is incorrect for path entries terminating in the local node. If the speed map is incorrect, it can be assumed that the bus manager has used only the self-ID packet information to build the speed map. In this case, the node may update the Link_Speed field to reflect the lower speed capability of the LLC and then initiate another bus reset to cause the speed map to be rebuilt. Note that in this scenario any speed-map entries for node-to-node communication paths that pass through the local node’s PHY are restricted by the lower speed. In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the speed of the LLC without first checking the speed map. Changing the Link_Speed field in a leaf node can only affect those paths that terminate at that node. Because no other paths can pass through a leaf node, it can have no effect on other paths in the speed map. For hardware configurations, which can only be a leaf node (all ports but one are unimplemented), it is recommended that the Link_Speed field be updated immediately after power on or hardware reset. power-up reset To ensure proper operation of the TSB41AB1, the RESET terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage. When using a passive capacitor on the RESET terminal to generate a power-on reset signal, the minimum reset time is assured if the capacitor has a minimum value of 0.1 µF and also satisfies the following equation: C min + 0.0077 T ) 0.085 (2) where Cmin is the minimum capacitance on the RESET terminal in µF, and T is the VDD ramp time, 10%– 90%, in milliseconds. bus reset In the TSB41AB1, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and gap-count register, as required by IEEE 1394a-2000 (this configuration also maintains compatibility with older TI PHY designs which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995). Therefore, whenever the IBR bit is written, the RHB and gap count are also necessarily written. 40 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 APPLICATION INFORMATION bus reset (continued) The RHB and gap count may also be updated by PHY-config packets. The TSB41AB1 is IEEE 1394a-2000 compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and gap count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received PHY-config packets. The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening write to the gap count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config packet to be transmitted and then a bus reset initiated to verify that all nodes on the bus have updated their RHBs and gap-count values, without having the gap count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus have their gap-count values set to 63, while the gap count of this node remains set to the value just loaded by the write to PHY register 1. Therefore, in order to maintain consistent gap counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and gap count in PHY register 1: D Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and gap-count values, and to ensure that a subsequent new connection to the bus causes the gap count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1, the RHB and gap-count register must also be loaded with the correct values consistent with the just transmitted PHY-config packet. In the TSB41AB1, the RHB and gap count have been updated to their correct values upon the transmission of the PHY-config packet, and so these values may first be read from register 1 and then rewritten. D Other than to initiate the bus reset which must follow the transmission of a PHY-config packet, whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 to be consistent with other nodes on the bus, and the RHB should be maintained with its current value. D The PHY register 1 should not be written to except to set the IBR bit. The RHB and gap count should not be written without also setting the IBR bit to 1. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 41 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION PHY-Link layer interface The TSB41AB1 is designed to operate with an LLC such as the Texas Instruments TSB12LV21, TSB12LV22 TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. Details of operation for the Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. The interface to the LLC consists of the SYSCLK, CTL0 , CTL1, D0 – D7, LREQ, LPS, C/LKON, and ISO terminals on the TSB41AB1, as shown in Figure 18. Link Layer Controller TSB41AB1 SYSCLK CTL0−CTL1 D1−D7 LREQ LPS C/LKON ISO ISO ISO Figure 18. PHY-LLC Interface The SYSCLK terminal provides a 49.152-MHz interface clock. All control and data signals are synchronized to, and sampled on, the rising edge of SYSCLK. The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data between the TSB41AB1 and LLC. The D0 – D7 terminals form a bidirectional data bus, which is used to transfer status information, control information, or packet data between the devices. The TSB41AB1 supports S100, S200, and S400 data transfers over the D0– D7 data bus. In S100 operation, only the D0 and D1 terminals are used; in S200 operation, only the D0 – D3 terminals are used; and in S400 operation, all D0 – D7 terminals are used for data transfer. When the TSB41AB1 is in control of the D0 – D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When the LLC is in control of the D0– D7 bus, unused Dn terminals are ignored by the TSB41AB1. The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration. The LPS and C/LKON terminals are used for power management of the PHY and LLC. The LPS terminal indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SYSCLK. The C/LKON terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC either when LPS is inactive or when the PHY register LCtrl bit is zero. The ISO terminal is used to enable the output differentiation logic on the CTL0 , CTL1 and D0 – D7 terminals. Output differentiation is required when an Annex J type isolation barrier is implemented between the PHY and LLC. The TSB41AB1 normally controls the CTL0– CTL1 and D0– D7 bidirectional buses. The LLC is allowed to drive these buses only after the LLC has been granted permission to do so by the PHY. There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration. 42 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION PHY-Link layer interface (continued) The PHY may initiate a status transfer either autonomously or in response to a register read request from the LLC. The PHY initiates a receive operation whenever a packet is received from the serial bus. The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. The encoding of the CTL0 −CTL1 bus is shown in Table 10 and Table 11. Table 10. CTL Encoding When PHY Has Control of the Bus CTL0 CTL1 NAME 0 0 Idle DESCRIPTION 0 1 Status 1 0 Receive 1 1 Grant No activity (this is the default mode) Status information is being sent from the PHY to the LLC. An incoming packet is being sent from the PHY to the LLC. The LLC has been given control of the bus to send an outgoing packet. Table 11. CTL Encoding When LLC Has Control of the Bus CTL0 CTL1 NAME 0 0 Idle The LLC releases the bus (transmission has been completed). DESCRIPTION 0 1 Hold The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to be transmitted (concatenated) without arbitrating. 1 0 Transmit An outgoing packet is being sent from the LLC to the PHY. 1 1 Reserved None output differentiation When an Annex J type isolation barrier is implemented between the PHY and LLC, the CTL0, CTL1, D0 – D7, and LREQ signals must be digitally differentiated so that the isolation circuits function correctly. Digital differentiation is enabled on the TSB41AB1 when the ISO terminal is low. The differentiation operates such that the output is driven either low or high for one clock period whenever the signal changes logic state, but otherwise places the output in a high-impedance state for as long as the signal logic state remains constant. On input, hysteresis buffers are used to convert the signal to the correct logic state when the signal is high impedance; the biasing network of the Annex J type isolation circuit pulls the signal voltage level between the hysteresis thresholds of the input buffer so that the previous logic state is maintained. The correspondence between the output logic state and the output signal level is shown in Figure 19. Logic State 0 1 1 0 0 0 1 0 0 L H Z O Z Z H L Z Signal Level Figure 19. Signal Transformation for Digital Differentiation • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 43 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION output differentiation The TSB41AB1 implements differentiation circuitry functionally equivalent to that shown in Figure 20 on the bidirectional CTL0 , CTL1, and D0 – D7 terminals. The TSB41AB1 also implements an input hysteresis buffer on the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also implement similar output differentiation and input hysteresis circuitry on its CTL and D terminals and output differentiation circuitry on its LREQ terminal. Input Buffer With Hysteresis DIN Q D D Terminal DOUT D Q To/From Internal Device Logic 3-State Output Driver ISO D OUTEN Q INIT SYSCLK Figure 20. Input/Output Differentiation Logic LLC service request To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 21. LR0 LR1 LR2 LR3 LR(n-2) LR(n-1) NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 21. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 12. Table 12. Request Stream Bit Length REQUEST TYPE NUMBER OF BITS Bus request 44 7 or 8 Read register request 9 Write register request 17 Acceleration control request 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION LLC service request (continued) Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Encoding for the request type is shown in Table 13. Table 13. Request Type Encoding LR1 – LR3 NAME DESCRIPTION 000 ImmReq Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration. 001 IsoReq Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. 010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. 011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol. 100 RdReg The PHY returns the specified register contents through a status transfer. 101 WrReg Write to the specified register 110 AccelCtl Enable or disable asynchronous arbitration acceleration 111 Reserved Reserved For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14. Table 14. Bus Request BIT(S) NAME 0 Start bit 1−3 Request type 4−6 Request speed 7 Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1). Indicates the type of bus request. See Table 13. Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this field. Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted. The 3-bit request speed field used in bus requests is shown in Table 15. Table 15. Bus Request LR4 – LR6 DATA RATE 000 S100 010 S200 100 S400 All Others Invalid NOTE: The TSB41AB1 does accept a bus request with an invalid speed code and process the bus request normally. However, during packet transmission for such a request, the TSB41AB1 ignores any data presented by the LLC and transmits a null packet. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 45 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION LLC service request (continued) For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 16. Table 16. Read Register Request BIT(S) NAME 0 Start bit DESCRIPTION 1 −3 Request type 4 −7 Address Identifies the address of the PHY register to be read 8 Stop bit Indicates the end of the transfer (always 0) Indicates the beginning of the transfer (always 1) A 100 indicating this is a read register request For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 17. Table 17. Write Register Request BIT(S) NAME 0 Start bit 1 −3 Request type 4 −7 Address 8−15 Data DESCRIPTION Indicates the beginning of the transfer (always 1) A 101 indicating this is a write register request Identifies the address of the PHY register to be written to Gives the data that is to be written to the specified register address For an acceleration control request, the length of the LREQ bit stream is 6 bits as shown in Table 18. Table 18. Acceleration Control Request BIT(S) NAME DESCRIPTION 0 Start bit 1 −3 Request type Indicates the beginning of the transfer (always 1) 4 Control Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0. 5 Stop bit Indicates the end of the transfer (always 0) A 110 indicating this is an acceleration control request For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the PHY-LLC interface becomes idle. If the CTL terminals are asserted receive (10b) by the PHY, then any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if receive is asserted while the LLC is sending the request. The LLC may then reissue the request one clock after the next interface idle. The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears an isochronous request only when the serial bus has been won. To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released the LLC may proceed with another request. 46 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION LLC service request (continued) The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The TSB41AB1 includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41AB1 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then reenables the enhancements when it receives a cycle start message. The acceleration control request may be made at any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be reenabled, if the EAA bit is set. status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting status (01b) on the CTL terminals, along with the first two bits of status information on the D0 and D1 terminals. The PHY maintains CTL = status for the duration of the status transfer. The PHY may prematurely end a status transfer by asserting something other than status on the CTL terminals. This occurs if a packet is received before the status transfer completes. The PHY continues to attempt to complete the transfer until all status information has been successfully transmitted. There is at least one idle cycle between consecutive status transfers. The PHY normally sends just the first four bits of status to the LLC. These bits are status flags that are needed by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags are considered to have been successfully transmitted to the LLC immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed. The definitions of the bits in the status transfer are shown in Table 19, and the timing is shown in Figure 22. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 47 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION status transfer (continued) Table 19. Status Bits BIT(S) NAME DESCRIPTION 0 Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in IEEE Std 1394-1995). This bit is used by the LLC in the busy/retry state machine. 1 Subaction gap Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in IEEE Std 1394-1995). This bit is used by the LLC to detect the completion of an isochronous cycle. 2 Bus reset Indicates that the PHY has entered the bus reset start state. 3 Interrupt Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, cable-power voltage falling too low, a state time-out, or a port status change. 4 −7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC. 8 −15 Data This field holds the register contents. SYSCLK (1) (2) 00 CTL0, CTL1 00 01 D0, D1 00 S[0:1] S[14:15] 00 Figure 22. Status Transfer Timing The sequence of events for a status transfer is as follows: 1. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only two bits of status are transferred per cycle). Normally (unless interrupted by a receive operation), a status transfer is either two or eight cycles long. A 2-cycle (4 bit) transfer occurs when only status information is to be sent. An 8-cycle (16 bit) transfer occurs when register data is to be sent in addition to any status information. 2. Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines. The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin a receive operation. The PHY asserts at least one cycle of idle between consecutive status transfers. receive Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 20) on the D terminals, followed by packet data. The PHY holds the CTL terminals in receive until the last symbol of the packet has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the calculation of CRC or any other data protection mechanisms. 48 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION receive (continued) Table 20. Receive Speed Codes D0 −D7 DATA RATE 00XX XXXX S100 0100 XXXX S200 0101 0000 S400 1YYY YYYY data-on indication NOTE: X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC. It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D terminals, followed by idle on the CTL terminals, without any speed code or data being transferred. In all cases, the TSB41AB1 sends at least one data-on indication before sending the speed code or terminating the receive operation. The TSB41AB1 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to the LLC. This packet is transferred to the LLC just as any other received self-ID packet. Figure 23 is the reception timing diagram for normal packets, and Figure 24 is the reception timing diagram for null packets. SYSCLK (1) CTL0, CTL1 00 01 10 (2) D0–D7 XX FF (Data-On) 00 (3) (4) SPD d0 (5) dn 00 Figure 23. Normal Packet Reception Timing The sequence of events for a normal packet reception is as follows: 1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle until receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. 2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles preceding the speed code. 3. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates a speed higher than that which the link is capable of handling, the link should ignore the subsequent data. 4. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. 5. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one cycle of idle following a receive operation. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 49 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION receive (continued) SYSCLK (1) CTL0, CTL1 00 01 10 00 (2) D0–D7 XX FF (Data-On) (3) 00 Figure 24. Null Packet Reception Timing The sequence of events for a null packet reception is as follows: 1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle until receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. 2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. 3. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one cycle of idle following a receive operation. transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless the LLC is immediately releasing the interface, the LLC may assert idle for at most one clock before it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (that is, the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time. When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. A transmit is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts idle for one additional cycle before releasing the interface bus and placing its CTL and D terminals in high-impedance. The PHY then regains control of the interface bus. The hold asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request by waiting the required minimum packet separation time and then asserting grant as before. This function may be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is set), the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed code that precedes received packet data as given in Table 20. 50 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION transmit (continued) After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals. Figure 25 is the transmission timing diagram for normal packets, and Figure 26 is the transmission timing diagram for cancelled or null packets. SYSCLK (1) CTL0, CTL1 00 11 (2) 00 00 (3) 01 (4) (5) 10 01 00 d0 SPD 00 (7) 00 00 00 00 (6) D0–D7 00 00 dn Link Controls CTL and D PHY CTL and D Outputs are High IMpedance NOTE: SPD = Speed code, see Table 20 d0 −dn = Packet data Figure 25. Normal Packet Transmission Timing The sequence of events for a normal packet transmission is as follows: 1. Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link so that the link may transmit a packet. The PHY releases control of the interface (that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle. 2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit. 3. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These hold cycle(s) are optional; the link is not required to assert hold preceding transmit. 4. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with the data on the D lines. 5. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and the PHY may release the serial bus. The link then asserts idle for one more cycle following this cycle of hold or idle before releasing the interface and returning control to the PHY. 6. Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, the link asserts a speed code on the D lines when it asserts hold to terminate packet transmission. This speed code indicates the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated packet speed code is the same as the encoding for the received packet speed code (see Table 20). The link may not concatenate an S100 packet onto any higher-speed packet. 7. After regaining control of the interface, the PHY shall assert at least one cycle of idle before any subsequent status transfer, receive operation, or transmit operation. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 51 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION transmit (continued) SYSCLK (1) CTL0, CTL1 00 D0–D7 00 11 00 (2) (3) (4) (5) 00 01 00 00 00 00 Link Controls CTL and D PHY CTL and D Outputs are High Impedance Figure 26. Cancelled/Null Packet Transmission Timing The sequence of events for a cancelled/null packet transmission is as follows: 1. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. 2. Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle is optional; the link is not required to assert idle preceding hold. 3. Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold cycle(s) are optional; the link is not required to assert hold preceding idle. 4. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert hold. (It is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold cycles are asserted. This assures that either the link or PHY controls the interface in all cycles.) 5. After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status transfer, receive operation, or transmit operation. interface reset and disable The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface is not operational (whether reset, disabled, or in the process of initialization) the PHY cancels any outstanding bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status information generated by the PHY is not queued, and thus does not cause a status transfer upon restoration of the interface to normal operation. The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY and LLC (whether of the TI bus-holder type or Annex J type) the LPS signal must be pulsed. In a direct connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are given in Table 21. 52 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable (continued) Table 21. LPS Timing Parameters PARAMETER DESCRIPTION MIN MAX UNIT 0.09 2.6 µs 0.021 2.6 µs TLPSL TLPSH LPS low time (when pulsed)† LPS high time (when pulsed)† TLPS_DUTY LPS duty cycle (when pulsed)‡ 20% 55% TLPS_RESET Time for PHY to recognize LPS deasserted and reset the interface 2.6 2.68 µs TLPS_DISABLE Time for PHY to recognize LPS deasserted and disable the interface 26.03 26.11 µs TRESTORE Time to permit optional isolation circuits to restore during an interface reset 15 23§ µs 60 ns TCLK_ACTIVATE Time for SYSCLK to be activated from reassertion of LPS 5.3 7.3 ms PHY not in low-power state PHY in low-power state † The specified TLPSL and TLPSH times are worst-case values appropriate for operation with the TSB41AB1. These values are broader than those specified for the same parameters in IEEE 1394a-2000 (that is, an implementation of LPS that meets the requirements of IEEE 1394a-2000 operates correctly with the TSB41AB1). ‡ A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when using an isolation barrier on the LPS signal (for example, as shown in Figure 14). § The maximum value for TRESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less than TLPS_DISABLE. The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request activity. When the PHY observes that LPS has been deasserted for TLPS_RESET, it resets the interface. When the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity on the LREQ signal. The timing for interface reset is shown in Figure 27 and Figure 28. ISO (low) (3) (1) SYSCLK CTL0, CTL1 D0−D7 (2) LREQ (4) LPS TLPS_RESET TLPSL TRESTORE TLPSH Figure 27. Interface Reset, ISO Low • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 53 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for resetting the PHY-LLC interface when it is in the differentiated mode of operation (ISO terminal is low) is as follows: 1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line. 2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC should terminate any output signal activity such that signals end in a logic 0 state). 3. Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state. 4. Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. The minimum TRESTORE interval provides sufficient time for the biasing networks used in Annex J type isolation barrier circuits to stabilize and reach a quiescent state if the isolation barrier has somehow become unbalanced. When LPS is asserted, the interface is initialized. ISO (high) (3) (1) SYSCLK CTL0, CTL1 D0−D7 (2) LREQ (4) LPS TLPS_RESET TRESTORE Figure 28. Interface Reset, ISO High 54 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for resetting the PHY-LLC interface when it is in the nondifferentiated mode of operation (ISO terminal is high) is as follows: 1. Normal operation. Interface is operating normally, with LPS asserted, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line. In Figure 28, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required when using an isolation barrier (whether of the TI bus-holder type or Annex J type). 2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. 3. Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. 4. Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. When LPS is asserted, the interface is initialized. If the LLC continues to keep the LPS signal deasserted, it requests that the interface be disabled. The PHY disables the interface when LPS has been deasserted for TLPS_DISABLE. When the interface is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops SYSCLK activity. The interface is also placed into the disabled condition upon a hardware reset of the PHY. The timing for interface disable is shown in Figure 29 and Figure 30. When the interface is disabled, the PHY enters a low-power state if none of its ports is active. ISO (low) (3) (1) (4) SYSCLK CTL0, CTL1 D0−D7 (2) LREQ LPS TLPSL TLPS_RESET TLPSH TLPS_DISABLE Figure 29. Interface Disable, ISO Low • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 55 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for disabling the PHY-LLC interface when it is in the differentiated mode of operation (ISO terminal is low) is as follows: 1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line. 2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC should terminate any output signal activity such that signals end in a logic 0 state). 3. Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface is now in the reset state. 4. Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates SYSCLK activity by placing the SYSCLK output into a high-impedance state. The PHY-LLC interface is now in the disabled state. ISO (high) (3) (1) SYSCLK CTL0, CTL1 D0− D7 (2) LREQ LPS TLPS_RESET TLPS_DISABLE Figure 30. Interface Disable, ISO High 56 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • (4) 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for disabling the PHY-LLC interface when it is in the nondifferentiated mode of operation (ISO terminal is high) is as follows: 1. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line. 2. LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. 3. Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. 4. Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, the PHY terminates SYSCLK activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled state. After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal operation when LPS is reasserted by the LLC. The timing for interface initialization is shown in Figure 31 and Figure 32. ISO (low) 7 Cycles SYSCLK 5 ns, Min 10 ns, Max (3) CTL0 (2) (4) CTL1 D0−D7 LREQ (1) LPS TCLK_ACTIVE Figure 31. Interface Initialization, ISO Low • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 57 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for initialization of the PHY-LLC interface when the interface is in the differentiated mode of operation (ISO terminal is low) is as follows: 1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by reactivating the LPS signal. In Figure 31 the interface is shown in the disabled state with SYSCLK high-impedance inactive. However, the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled. 2. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3 ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns. The PHY commences SYSCLK activity by driving the SYSCLK output low for half a cycle. Thereafter, the SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz ±100 ppm (period of 20.345 ns). Upon the first full cycle of SYSCLK, the PHY drives the CTL and D terminals low for one cycle. The LLC is also required to drive its CTL, D, and LREQ outputs low during one of the first six cycles of SYSCLK (this is shown in Figure 31 as occurring in the first SYSCLK cycle). 3. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles (because the interface is in the differentiated mode of operation, the CTL and D lines are in the high-impedance state after the first cycle). 4. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY now accepts requests from the LLC via the LREQ line. ISO (high) 7 Cycles SYSCLK (3) (2) CTL0 (4) CTL1 D0−D7 LREQ (1) LPS TCLK_ACTIVE Figure 32. Interface Initialization, ISO High 58 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
     


 SLLS423I − JUNE 2000 − REVISED MARCH 2005 PRINCIPLES OF OPERATION interface reset and disable (continued) The sequence of events for initialization of the PHY-LLC interface when the interface is in the nondifferentiated mode of operation (ISO terminal is high) is as follows: 1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS signal. (In Figure 32, the interface is shown in the disabled state with SYSCLK low inactive. However, the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled.) 2. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3 ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns. The SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz ± 100 ppm (period of 20.345 ns). During the first seven cycles of SYSCLK, the PHY continues to drive the CTL and D terminals low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles of SYSCLK but otherwise to place its CTL and D outputs in a high-impedance state. The LLC continues to drive its LREQ output low during this time. 3. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles. 4. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY now accepts requests from the LLC via the LREQ line. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 59 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TSB41AB1PAP ACTIVE HTQFP PAP 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TSB41AB1 TSB41AB1PHP ACTIVE HTQFP PHP 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TSB41AB1 TSB41AB1PHPG4 ACTIVE HTQFP PHP 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TSB41AB1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of