TSC2007IYZGR

Burr Brown Products from Texas Instruments TS C2 ® 007 TSC2007 SBAS405 – MARCH 2007 1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Micro TOUCH SCREEN CONTROLLER with I2C™ Interface FEATURES • • • • • • • 4-Wire Touch Screen Interface Single 1.2V to 3.6V Supply/Reference Ratiometric Conversion Effective Throughput Rate: – Up to 20kHz (8-Bit) or 10kHz (12-Bit) Preprocessing to Reduce Bus Activity I2C Interface Supports: – Standard, Fast, and High-Speed Modes Simple, Command-Based User Interface: – TSC2003 Compatible – 8- or 12-Bit Resolution On-Chip Temperature Measurement Touch Pressure Measurement Digital Buffered PENIRQ On-Chip, Programmable PENIRQ Pullup Auto Power-Down Control Low Power: – 32.24µA at 1.2V, Fast Mode, 8.2kHz Eq Rate – 39.31µA at 1.8V, Fast Mode, 8.2kHz Eq Rate – 53.32µA at 2.7V, Fast Mode, 8.2kHz Eq Rate Enhanced ESD Protection: – ±8kV HBM – ±1kV CDM – ±25kV Air Gap Discharge – ±15kV Contact Discharge 1.5 x 2 WCSP-12 and 5 x 6.4 TSSOP-16 Packages APPLICATIONS • • • • • Cellular Phones PDA, GPS, and Media Players Portable Instruments Point-of-Sale Terminals Multiscreen Touch Control DESCRIPTION The TSC2007 is a very low-power touch screen controller designed to work with power-sensitive, handheld applications that are based on an advanced low-voltage processor. It works with a supply voltage as low as 1.2V, which can be supplied by a single-cell battery. It contains a complete, ultra-low power, 12-bit, analog-to-digital (A/D) resistive touch screen converter, including drivers and the control logic to measure touch pressure. In addition to these standard features, the TSC2007 offers preprocessing of the touch screen measurements to reduce bus loading, thus reducing the consumption of host processor resources that can then be redirected to more critical functions. The TSC2007 supports an I2C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. It offers programmable resolution of 8 or 12 bits to accommodate different screen sizes and performance needs. The TSC2007 is available in a 12-lead, (1.555 ±0.055mm) x (2.055 ±0.055mm), 3 x 4 array, wafer chip-scale package (WCSP), and a 16-pin, TSSOP package. The TSC2007 is characterized for the –40°C to +85°C industrial temperature range. VDD/REF PENIRQ • • • • • • • • U.S. Patent NO. 6246394; other patents pending. Preprocessing X+ XY+ Y- Touch Screen Drivers Interface TEMP Mux SAR ADC AUX Internal Clock I2C Serial Interface and Control SCL SDA A[0:1] GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TSC2007 www.ti.com SBAS405 – MARCH 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TYPICAL INTEGRAL LINEARITY (LSB) TYPICAL GAIN ERROR (LSB) NO MISSING CODES RESOLUTION (BITS) PACKAGE TYPE 16-Pin, 5 x 6.4 TSSOP TSC2007I ±1.5 0.1 11 12-Pin, 3 x 4 Matrix, 1.5 x 2 WCSP PACKAGE DESIGNATOR PW SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING TSC2007I ORDERING NUMBER TSC2007IPW TSC2007IPWR TSC2007IYZGT YZG –40°C to +85°C TSC2007I TSC2007IYZGR TRANSPORT MEDIA, QUANTITY Tube, 90 Tape and Reel, 2000 Small Tape and Reel, 250 Tape and Reel, 3000 PRODUCT (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted) TSC2007 Voltage Voltage range Digital input voltage to GND Digital output voltage to GND Power dissipation TSSOP Package Thermal impedance, θJA Operating free-air temperature range, TA Storage temperature range, TSTG Junction temperature, TJ Max Lead temperature (1) Vapor phase (60 sec) Infrared (15 sec) WCSP package Low-K High-K Analog input X+, Y+, AUX to GND Analog input X–, Y– to GND VDD to GND –0.4 to VDD + 0.1 –0.4 to VDD + 0.1 –0.3 to +5 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 (TJ Max - TA)/θJA 86 113 62 –40 to +85 –65 to +150 +150 +215 +220 °C °C °C °C °C °C/W UNIT V V V V V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TSC2007 PARAMETER AUXILIARY ANALOG INPUT Input voltage range Input capacitance Input leakage current A/D CONVERTER Resolution No missing codes Integral linearity Offset error VDD = 1.8V VDD = 3.0V VDD = 1.8V VDD = 3.0V TA = +25°C, VDD = 1.8V, command '1011' set '0000' TA = +25°C, VDD = 1.8V, command '1011' set '0001' Programmable: 8 or 12 bits 12-bit resolution 11 ±1.5 –1.2 –3.1 0.7 0.1 12 Bits Bits LSB (1) LSB LSB LSB LSB kΩ kΩ Ω Ω 50 mA °C °C/LSB °C/LSB °C/LSB °C/LSB °C/LSB °C/LSB °C/LSB °C/LSB MHz MHz MHz MHz MHz MHz MHz MHz %/°C %/°C –1 0 12 +1 VDD V pF µA TEST CONDITIONS MIN TYP MAX UNIT Gain error TOUCH SENSORS PENIRQ Pull-Up Resistor, RIRQ Switch On-Resistance Y+, X+ Y–, X– current (2) 51 90 6 5 Switch drivers drive 100ms duration INTERNAL TEMPERATURE SENSOR Temperature range Differential method (3) Resolution TEMP1 (4), Differential method (3) Accuracy TEMP1 (4) INTERNAL OSCILLATOR VDD = 1.2V 8-Bit VDD = 1.8V VDD = 2.7V VDD = 3.6V VDD = 1.2V 12-Bit VDD = 1.8V VDD = 2.7V VDD = 3.6V Frequency drift VDD = 1.6V VDD = 3.0V 3.19 3.66 3.78 3.82 1.6 1.83 1.88 1.91 0.0056 0.012 VDD = 3V VDD = 1.6V VDD = 3V VDD = 1.6V VDD = 3V VDD = 1.6V VDD = 3V VDD = 1.6V –40 1.94 1.04 0.35 0.19 ±2 ±2 ±3 ±3 +85 Internal clock frequency, fCCLK (1) (2) (3) (4) LSB means Least Significant Bit. With VDD (REF) = +1.6V, one LSB is 391µV. Assured by design, but not tested. Exceeding 50mA source current may result in device degradation. Difference between TEMP1 and TEMP2 measurement; no calibration necessary. Temperature drift is –2.1mV/°C. Submit Documentation Feedback 3 TSC2007 www.ti.com SBAS405 – MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, unless otherwise noted. TSC2007 PARAMETER DIGITAL INPUT/OUTPUT Logic family VIH VIL Logic level IIL CIN VOH VOL ILEAK COUT Data format POWER-SUPPLY REQUIREMENTS Power-supply voltage VDD Specified performance VDD = 1.2V Quiescent supply current (VDD with sensor off) 12-bit Fast mode (clock = 400kHz) PD[1:0] = 0,0 VDD = 1.8V VDD = 2.7V Power down supply current Not addressed, SCL =SDA = 1 32.56k eq rate 8.2k eq rate 34.42k eq rate 8.2k eq rate 34.79k eq rate 8.2k eq rate 1.2 128 32.24 165 39.31 226.2 53.32 0 0.8 335 240 3.6 190 V µA µA µA µA µA µA µA 1.2V ≤ VDD < 1.6V 1.6V ≤ VDD ≤ 3.6V 1.2V ≤ VDD < 1.6V 1.6V ≤ VDD ≤ 3.6V SCL and SDA pins SCL and SDA pins IOH = 2 TTL loads IOL = 2 TTL loads Floating output Floating output Straight Binary VDD– 0.2 0 –1 0.7 × VDD 0.7 × VDD –0.3 –0.3 –1 CMOS VDD + 0.3 VDD + 0.3 0.2 × VDD 0.3 × VDD 1 10 VDD 0.2 1 10 V V V V µA pF V V µA pF TEST CONDITIONS MIN TYP MAX UNIT 4 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 PIN CONFIGURATION PW PACKAGE TSSOP-16 (TOP VIEW) VDD/REF X+ Y+ XYGND NC NC 1 2 3 4 TSC2007 5 6 7 8 12 SCL 11 SDA 16 AUX YZG PACKAGE WCSP-12 (TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE) X+ 3 15 NC 14 A0 13 A1 Y+ X- Y- Rows VDD/REF 2 AUX 1 A A0 A1 GND PENIRQ SDA SCL B Columns C D 10 PENIRQ 9 NC (FRONT VIEW) PIN ASSIGNMENTS PIN NO. TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 WCSP A2 A3 B3 C3 D3 D2 — — — B1 C1 D1 C2 B2 — A1 PIN NAME VDD/REF X+ Y+ X– Y– GND NC NC NC PENIRQ SDA SCL A1 A0 NC AUX I A O I/O I/O I I D D D D D I I I I A A A A I/O A/D DESCRIPTION Supply voltage and external reference input X+ channel input Y+ channel input X– channel input Y– channel input Ground No connection No connection No connection Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity with active low. Serial data I/O Serial clock. This pin is normally an input, but acts as an output when the device stretches the clock to delay a bus transfer. Address input bit 1 Address input bit 0 No connection Auxiliary channel input Submit Documentation Feedback 5 TSC2007 www.ti.com SBAS405 – MARCH 2007 TIMING INFORMATION SDA tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA tSU, STO tBUF SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. Detailed I/O Timing TIMING REQUIREMENTS: I2C Standard Mode (SCL = 100kHz) All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted. 2-WIRE STANDARD MODE PARAMETERS SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition Low period of SCL clock High period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Rise time for both SDA and SCL clock signals (receiving) Fall time for both SDA and SCL clock signals (receiving) Fall time for both SDA and SCL clock signals (transmitting) Setup time for STOP condition Capacitive load for each bus line Cycle time 8 bits 12 bits 8 bits 12 bits 8 bits 12 bits fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tOF tSU, STO Cb Cb = total capacitance of one bus line in pF 40 SCL + 127 CCLK, VDD = 1.8V 49 SCL + 148 CCLK, VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V 434.7 570.9 2.3 1.75 16.1 12.26 Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance 4.0 400 TEST CONDITIONS MIN 0 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 250 3.45 TYP MAX 100 UNIT kHz µs µs µs µs µs µs ns ns ns ns µs pF µs µs kSPS kSPS kHz kHz Effective throughput Equivalent rate = effective throughput × 7 6 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 TIMING REQUIREMENTS: I2C Fast Mode (SCL = 400kHz) All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted. 2-WIRE FAST MODE PARAMETERS SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition Low period of SCL clock High period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Rise time for both SDA and SCL clock signals (receiving) Fall time for both SDA and SCL clock signals (receiving) Fall time for both SDA and SCL clock signals (transmitting) Setup time for STOP condition Capacitive load for each bus line Cycle time 8 bits 12 bits 8 bits 12 bits 8 bits 12 bits fSCL tBUF tHD, STA TEST CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1×Cb 20+0.1×Cb 20+0.1×Cb 0.6 TYP MAX 400 UNIT kHz µs µs µs µs µs tLOW tHIGH tSU, STA tHD, tR tF tOF tSU, STO Cb Cb = total capacitance of one bus line in pF 40 SCL + 127 CCLK, VDD = 1.8V 49 SCL + 148 CCLK, VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V DAT 0.9 µs ns ns ns ns µs tSU, DAT Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance 300 300 250 400 134.7 203.4 7.42 4.92 51.97 34.42 pF µs µs kSPS kSPS kHz kHz Effective throughput Equivalent rate = effective throughput × 7 TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 1.7MHz) All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted. 2-WIRE HIGH-SPEED MODE PARAMETERS SCL clock frequency Hold time (repeated) START condition Low period of SCL clock High period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Rise time for SCL clock signal (receiving) Rise time for SDA clock signal (receiving) Fall time for SCL clock signal (receiving) Fall time for SDA clock signal (receiving) Fall time for both SDA and SCL clock signals (transmitting) Setup time for STOP condition Capacitive load for each bus line Cycle time 8 bits 12 bits 8 bits 12 bits 8 bits 12 bits fSCL tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tR tF tF tOF tSU, STO Cb Cb = total capacitance of one bus line in pF 40 SCL + 127 CCLK, VDD = 1.8V 49 SCL + 148 CCLK, VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V 58.2 109.7 17.17 9.12 120.22 63.81 Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance TEST CONDITIONS MIN 0 160 320 120 160 0 10 20 20 20 20 10 160 400 80 160 80 160 80 150 TYP MAX 1.7 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns pF µs µs kSPS kSPS kHz kHz Effective throughput Equivalent rate = effective throughput × 7 Submit Documentation Feedback 7 TSC2007 www.ti.com SBAS405 – MARCH 2007 TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 3.4MHz) All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted. 2-WIRE HIGH-SPEED MODE PARAMETERS SCL clock frequency Hold time (repeated) START condition Low period of SCL clock High period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Rise time for SCL clock signal (receiving) Rise time for SDA clock signal (receiving) Fall time for SCL clock signal (receiving) Fall time for SDA clock signal (receiving) Fall time for both SDA and SCL clock signals (transmitting) Setup time for STOP condition Capacitive load for each bus line Cycle time 8 bits 12 bits 8 bits 12 bits 8 bits 12 bits fSCL tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tR tF tF tOF tSU, STO Cb Cb = total capacitance of one bus line in pF 40 SCL + 127 CCLK, VDD = 1.8V 49 SCL + 148 CCLK, VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V VDD = 1.8V 46.5 95.3 21.52 10.49 150.65 73.46 Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance Cb = total bus capacitance TEST CONDITIONS MIN 0 160 160 60 160 0 10 10 10 10 10 10 160 100 40 80 40 80 80 ns ns pF µs µs kSPS kSPS kHz kHz ns 70 TYP MAX 3.4 UNIT MHz ns ns ns ns ns ns ns Effective throughput Equivalent rate = effective throughput × 7 8 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 TYPICAL CHARACTERISTICS At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, and non-continuous AUX measurement, unless otherwise noted. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 100 350 High-Speed Mode = 3.4MHz 300 80 VDD = 3.6V 60 VDD = 3.0V SUPPLY CURRENT vs TEMPERATURE Power-Down Supply Current (nA) Supply Current (mA) 250 Fast Mode = 400kHz 200 150 100 50 0 40 VDD = 1.6V 20 Standard Mode = 100kHz 0 -40 -20 0 20 40 60 80 100 Temperature (°C) -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 2. SUPPLY CURRENT AUX CONVERSION 600 High-Speed Mode = 3.4MHz 500 250 300 Figure 3. SUPPLY CURRENT vs SUPPLY VOLTAGE TA = +25°C I2C Speed = 400kHz PD1 = PD0 = 0 X, Y, Z Conversion at 200SSPS with MAV MAV Bypassed Touch Sensor Modeled By: 2kW for X-Plane 2kW for Y-Plane 1kW for Z(Touch Resistance) 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Supply Current (mA) 400 Fast Mode = 400kHz 300 200 Standard Mode = 100kHz 100 0 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Supply Current (mA) 200 150 100 50 0 Figure 4. SUPPLY CURRENT (Part Not Addressed) vs TEMPERATURE 70 60 250 Figure 5. SUPPLY CURRENT (Part Not Addressed) vs SUPPLY VOLTAGE Supply Current (mA) Supply Current (mA) 50 40 30 20 High-Speed Mode = 3.4MHz 200 150 High-Speed Mode = 3.4MHz 100 Standard Mode = 100kHz 50 Fast Mode = 400kHz 0 Fast Mode = 400kHz 10 0 -40 -20 0 20 40 Temperature (°C) 60 80 100 Standard Mode = 100kHz 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 6. Figure 7. Submit Documentation Feedback 9 TSC2007 www.ti.com SBAS405 – MARCH 2007 TYPICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, and non-continuous AUX measurement, unless otherwise noted. CHANGE IN GAIN vs TEMPERATURE 6 VDD = 1.8V 4 4 6 VDD = 1.8V CHANGE IN OFFSET vs TEMPERATURE Delta from +25°C (LSB) 2 0 -2 -4 -6 -40 -20 0 20 40 Temperature (°C) 60 80 100 Delta from +25°C (LSB) 2 0 -2 -4 -6 -40 -20 0 20 40 Temperature (°C) 60 80 100 Figure 8. SWITCH ON-RESISTANCE vs SUPPLY VOLTAGE 11 10 9 5 6 Figure 9. SWITCH ON-RESISTANCE vs TEMPERATURE X+, Y+: VDD = 3.0V to Pin X-, Y-: Pin to GND Y- Y+ RON (W) RON (W) 8 7 Y6 Y+ 5 4 3 1.2 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 XX+ X+ 4 X- 3 2 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 10. SWITCH ON-RESISTANCE vs TEMPERATURE 8 7 6 X+, Y+: VDD = 1.8V to Pin X-, Y-: Pin to GND 850 Y+ 800 Figure 11. TEMP DIODE VOLTAGE vs TEMPERATURE Measurement Includes A/D Converter Offset and Gain Errors TEMP Diode Voltage (mV) TEMP2 94.2mV 750 700 650 600 550 500 450 RON (W) Y- X+ 5 X4 3 2 -40 -20 0 20 40 60 80 100 Temperature (°C) TEMP1 137.5mV VDD = 1.8V 400 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 12. 10 Figure 13. Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 TYPICAL CHARACTERISTICS (continued) At TA = –40°C to +85°C, VDD = +1.2V to +3.6V, PD1 = PD0 = 0, Fast mode, 12-bit mode, and non-continuous AUX measurement, unless otherwise noted. TEMP1 DIODE VOLTAGE vs SUPPLY VOLTAGE 588 704 Measurement Includes A/D Converter Offset and Gain Errors TEMP2 DIODE VOLTAGE vs SUPPLY VOLTAGE Measurement Includes A/D Converter Offset and Gain Errors TEMP1 Diode Voltage (mV) 584 582 580 578 576 574 1.2 VDD = VREF 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 TEMP2 Diode Voltage (mV) 586 702 700 698 696 694 692 690 1.2 VDD = VREF 1.6 2.0 2.4 VDD (V) 2.8 3.2 3.6 Figure 14. INTERNAL OSCILLATOR CLOCK FREQUENCY vs TEMPERATURE Internal Oscillator Clock Frequency (MHz) Internal Oscillator Clock Frequency (MHz) 3.40 3.30 3.20 3.10 3.00 2.90 2.80 VDD = 1.2V 2.70 -40 -20 0 20 40 Temperature (°C) 60 80 100 3.70 Figure 15. INTERNAL OSCILLATOR CLOCK FREQUENCY vs TEMPERATURE 3.65 VDD = 1.8V 3.60 -40 -20 0 20 40 Temperature (°C) 60 80 100 Figure 16. INTERNAL OSCILLATOR CLOCK FREQUENCY vs TEMPERATURE Internal Oscillator Clock Frequency (MHz) 3.90 Figure 17. 3.85 3.80 3.75 VDD = 3.0V 3.70 -40 -20 0 20 40 Temperature (°C) 60 80 100 Figure 18. Submit Documentation Feedback 11 TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW The TSC2007 is an analog interface circuit for a human interface touch screen device. All peripheral functions are controlled through the command byte and onboard state machines. The TSC2007 features include: • Very low-power touch screen controller • Very small onboard footprint • Relieves host from tedious routine tasks by preprocessing, thus saving resources for more critical tasks • Ability to work on very low supply voltage • Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required • Miniature, yet complete; requires no external supporting component. • Enhanced ESD The TSC2007 consists of the following blocks (refer to the block diagram on the front page): • Touch Screen Sensor Interface • Auxiliary Input (AUX) • Temperature Sensor • Acquisition Activity Preprocessing • Internal Conversion Clock • I2C Interface Communication with the TSC2007 is done via an I2C serial interface. The TSC2007 is an I2C slave device; therefore, data is shifted into or out of the TSC2007 under control of the host microprocessor, which also provides the serial data clock. Control of the TSC2007 and its functions is accomplished by writing to the command register of an internal state machine. A simple command protocol compatible with I2C is used to address this register. A typical application of the TSC2007 is shown in Figure 19. 1.8VDC 1m F GND 0.1mF 1.2kW 1.2kW Host Processor GPIO VDD/REF PENIRQ X+ Y+ XTouch Screen Y- TSC2007 SDA SCL SDA SCL GND AUX A1 GND Auxilary Input Figure 19. Typical Circuit Configuration 12 Submit Documentation Feedback A0 TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) TOUCH SCREEN OPERATION A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The change in the resistance ratio marks the location on the touch screen. The TSC2007 supports the resistive 4-wire configurations, as shown in Figure 20. The circuit determines location in two coordinate pair dimensions, although a third dimension can be added for measuring pressure. 4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT A 4-wire touch screen is typically constructed as shown in Figure 20. It consists of two transparent resistive layers separated by insulating spacers. Conductive Bar Transparent Conductor (ITO) Bottom Side Y+ X+ Transparent Conductor (ITO) Top Side Silver Ink XY- ITO = Indium Tin Oxide Insulating Material (Glass) Figure 20. 4-Wire Touch Screen Construction The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network. The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of the Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the Y+ and Y– drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect the conversion because of the high input impedance of the A/D converter. Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X position on the screen. This process provides the X and Y coordinates to the associated processor. Measuring touch pressure (Z) can also be done with the TSC2007. To determine pen or finger touch, the pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this test; therefore, 8-bit resolution mode may be sufficient (however, data sheet calculations will be shown with the 12-bit resolution mode). There are several different ways of performing this measurement. The TSC2007 supports two methods. The first method requires knowing the X-plate resistance, the measurement of the X-Position, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 21). Equation 1 calculates the touch resistance: R TOUCH + RX−plate @ XPostition Z 2 *1 4096 Z 1 (1) Submit Documentation Feedback 13 TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position and Y-Position, and Z1. Equation 2 also calculates the touch resistance: RX−plate @ XPostition 4096 Y R TOUCH + *1 *R Y−plate @ 1* Position 4096 4096 Z1 Measure X-Position X+ Touch Y+ (2) X-Position XY- Measure Z1-Position X+ Touch Y+ Z1-Position XY- X+ Touch Y+ Z2-Position XYMeasure Z2-Position Figure 21. Pressure Measurement When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the touch panel will often overshoot and then slowly settle down (decay) to a stable DC value. This effect is a result of mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed. This settling time must be accounted for, or else the converted value will be in error. Therefore, a delay must be introduced between the time the driver for a particular measurement is turned on, and the time a measurement is made. In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of these capacitors provides a low-pass filter to reduce the noise, but will cause an additional settling time requirement when the panel is touched. The setlling time will typically show up as gain error. To solve this problem, the TSC2007 can be commanded to turn on the drivers only, without performing a conversion. Time can then be allowed to perform a conversion before the command is issued. The TSC2007 touch screen interface can measure position (X,Y) and pressure (Z). 14 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) INTERNAL TEMPERATURE SENSOR In some applications, such as battery recharging, an ambient temperature measurement is required. The temperature measurement technique used in the TSC2007 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The ambient temperature can be predicted in applications by knowing the +25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The TSC2007 offers two modes of temperature measurement. The first mode requires calibration at a known temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in Figure 22, is used during this measurement cycle. This voltage is typically 580mV at +25°C with a 10µA current. The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage would be stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.35°C/LSB (1LSB = 732µV with VREF = 3.0V). VDD +IN TEMP1 TEMP2 Converter -IN GND Figure 22. Functional Block Diagram of Temperature Measurement Mode The second mode does not require a test temperature calibration, but uses a two-measurement (differential) method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 80 times larger than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is represented by: DV + kT @ ln(N) q (3) Where: N = the resistance ratio = 80. k = Boltzmann's constant = 1.3807 × 10-23 J/K (joules/kelvins). q = the electron charge = 1.6022 × 10-19 C (coulombs). T = the temperature in kelvins (K). This method can provide much improved absolute temperature measurement, but a lower resolution of 1.6°C/LSB. The resulting equation to solve for T is: q @ DV T+ k @ ln(N) (4) Where: ∆V = VBE (TEMP2) – VBE(TEMP1) (in mV) ∴ T = 2.648 ⋅ ∆V (in K) or T = 2.648 ⋅ ∆V – 273 (in °C) Temperature 1 and temperature 2 measurements have the same timing as Figure 33 and Figure 34. Submit Documentation Feedback 15 TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) ANALOG-TO-DIGITAL CONVERTER Figure 23 shows the analog inputs of the TSC2007. The analog inputs (X, Y, and Z touch panel coordinates, chip temperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The A/D architecture is based on capacitive redistribution architecture, which inherently includes a sample-and-hold function. VDD/REF PENIRQ 50kW RIRQ 90kW Pen Touch Control Logic MAV TEMP1 TEMP2 C3-C0 X+ X- GND VDD Y+ Y+IN -IN +REF Converter -REF GND AUX GND Figure 23. Simplified Diagram of the Analog Input Section A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the converter and a differential reference input architecture, it is possible to negate errors caused by the driver switch on-resistances. 16 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) Reference The TSC2007 uses an external voltage reference that is applied to the VDD/REF pin. The upper reference voltage range is the same as the supply voltage range, which allows for simple, 1.2V to 3.6V single-supply operation of the chip. Reference Mode There is a critical item regarding the reference when making measurements while the switch drivers are on. For this discussion, it is useful to consider the basic operation of the TSC2007 (see Figure 19). This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y– drivers, and digitizing the voltage on X+, as shown in Figure 24. For this measurement, the resistance in the X+ lead does not affect the conversion; it does affect the settling time, but the resistance is usually small enough that this is not a concern. However, because the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. The TSC2007 does not support single-ended reference mode. VDD/REF Y+ +IN X+ -IN +REF Converter -REF Y- GND Figure 24. Simplified Diagram of Single-Ended Reference This situation is remedied, as shown in Figure 25, by using the differential mode; the +REF and –REF inputs are connected directly to Y+ and Y–, respectively. This makes the A/D converter ratiometric. The result of the conversion is always a percentage of the external reference, regardless of how it changes in relation to the on-resistance of the internal switches. VDD/REF Y+ +IN X+ -IN +REF Converter -REF Y- GND Figure 25. Simplified Diagram of Differential Reference (Y Switches Enabled, X+ is Analog Input) Submit Documentation Feedback 17 TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) Touch Screen Settling In some applications, external capacitors may be required across the touch screen to filter noise picked up by the touch screen (that is, noise generated by the LCD panel or backlight circuitry). These capacitors provide a low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched. The settling time will typically show up as a gain error. The problem is that the input and/or reference has not settled to its final steady-state value prior to the A/D converter sampling the input(s), and providing the digital output. Additionally, the reference voltage may still be changing during the measurement cycle. To resolve these settling-time problems, the TSC2007 can be commanded to turn on the drivers only without performing a conversion (see Table 3). Time can then be allowed, before the command is issued, to perform a conversion. Generally, the time it takes to communicate the conversion command over the I2C bus is adequate for the touch screen to settle. Variable Resolution The TSC2007 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowers power consumption. 8-Bit Conversion The TSC2007 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed, and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a conversion result can be read by transferring only one data byte. The internal clock will run twice as fast at 4MHz. The faster clock shortens each conversion by four bits and reduces data transfer time, which results in fewer clock cycles and provides lower power consumption. Conversion Clock and Conversion Time The TSC2007 contains an internal clock, which is used to drive the state machines inside the device that perform the many functions of the part. This clock is divided down to provide a clock that runs the A/D converter. The frequency of this clock is 4MHz clock for 8-bit mode, and 2MHz for the 12-bit mode. Data Format The TSC2007 output data is in Straight Binary format as shown in Figure 26. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = VREF(1) 1LSB = VREF(1)/4096 1LSB 11...111 11...110 Output Code 11...101 00...010 00...001 00...000 0V Input Voltage (2) FS - 1LSB (V) (1) (2) Reference voltage at converter: +REF – (–REF). See Figure 23. Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 23. Figure 26. Ideal Input Voltages and Output Codes 18 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) Touch Detect The PENIRQ can be used as an interrupt to the host. RIRQ is an internal pull up with a programmable value of either 50kΩ (default) or 90kΩ. Write command '1011' (setup command) followed by data '0001' sets the pullup to 90kΩ. NOTE: The first three bits must be '0's and the select bit is the last bit. To change the pullup back to 50kΩ, issue write command '1011' followed by data '0000'. An example for the Y-position measurement is detailed in Figure 27. The PENIRQ output is pulled high by an internal pullup. While in power-down mode with PD0 = 0, the Y– driver is on and connected to GND, and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground through the touch screen, and PENIRQ output goes low because of the current path through the panel to GND, initiating an interrupt to the processor. During the measurement cycle for X-, Y-, and Z-Position, the X+ input is disconnected from the PENIRQ pull-down transistor to eliminate any pull-up resistor leakage current from flowing through the touch screen, thus causing no errors. In addition to the measurement cycles for X-, Y-, and Z-Position, commands that activate the X-drivers, Y-drivers, and Y+ and X-drivers without performing a measurement, also disconnect the X+ input from the PENIRQ pull-down transistor and disable the pen-interrupt output function, regardless of the value of the PD0 bit. Under these conditions, the PENIRQ output will be forced low. Furthermore, if the last command byte written to the TSC2007 contains PD0 = 1, the pen-interrupt output function will be disabled and will not be able to detect when the panel is touched. In order to re-enable the pen-interrupt output function under these circumstances, a command byte must be written to the TSC2007 with PD0 = 0. When the bus master sends the address byte with R/W bit = 0, and the TSC2007 sends an acknowledge, the pen-interrupt function is disabled. If the command that follows the address byte contains PD0 = 0, then the pen-interrupt function will be enabled at the end of a conversion. This is approximately 100µs (12-bit mode) or 50µs (8-bit mode) after the TSC2007 receives a STOP/START condition, following the receipt of a command byte (see Figure 31 and Figure 30 for further details about when the conversion cycle begins). In both cases previously listed, it is recommended that whenever the host writes to the TSC2007, the master processor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts when the PENIRQ line is disabled in the cases previously listed. Connect to Analog Supply PENIRQ VDD RIRQ Y+ Pen Touch Control Logic VDD/REF TEMP1 X+ Sense GND Y- ON High when the X+ or Y+ driver is on, or when any sensor connection/shortcircuit tests are activated. GND Vias go to system analog ground plane. GND Figure 27. Example of a Pen-Touch Induced Interrupt via the PINTDAV Pin TEMP2 High when the X+ or Y+ driver is on. Submit Documentation Feedback 19 TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) Preprocessing The TSC2007 has a combined MAV filter (median value filter and averaging filter). MAV Filter In case the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate the data without noise. In this case, the median value filter operation helps remove the noise. The array of seven converted results is sorted first. The middle three values are then averaged to produce the output value of the MAV filter. The MAV filter is applied to all measurments for all analog inputs including the touch screen inputs, temperature measurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter may be bypassed though the setup command; see Table 3 and Table 4. 7 measurements input into temporary array 7 Acquired Data Sort by descending order Averaging output from window of 3 7 7 3 Figure 28. MAV Filter Operation 20 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) I C INTERFACE The TSC2007 supports the I2C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2007 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL. The following bus protocol has been defined (see Figure 29): • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy Both data and clock lines remain HIGH. Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the I2C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz clock rate), and a high-speed mode (1.7MHz or 3.4MHz clock rate) are each defined. The TSC2007 works in all three modes. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 2 Submit Documentation Feedback 21 TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) Figure 29 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte. 2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends with a STOP condition or a repeated START condition. Because a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. The TSC2007 may operate in the following two modes: 1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. 2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the TSC2007 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. I2C Fast or Standard Mode (F/S Mode) In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information section. In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high, as shown in Figure 29. The bus is free for another transmission after a stop condition has occurred. Figure 29 shows the complete F/S mode transfer on the I2C, 2-wire serial interface. The address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word plus acknowledge bit). SDA MSB Slave Address R/W Direction Bit Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver SCL START Condition 1 2 6 7 8 9 ACK 1 2 3-8 8 9 ACK Repeated If More Bytes Are Transferred STOP Condition or Repeated START Condition Figure 29. Complete Fast- or Standard-Mode Transfer 22 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 OVERVIEW (continued) I C High-Speed Mode (Hs Mode) The TSC2007 can operate with high-speed I2C masters. To do so, the pull-up resistor on SCL must be changed to an active pull-up, as recommended in the I2C specification. Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist: 1. START condition (S) 2. 8-bit master code (00001xxx) 3. Not-acknowledge bit (N) Figure 30 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge bit (N). After the not-acknowledge bit (N) and SCL have been pulled-up to a HIGH level, the master switches to Hs-mode and enables the current-source pull-up circuit for SCL (at time tH; shown in Figure 30). Because other devices can delay the serial transfer before tH by stretching the LOW period of SCL, the master enables the current-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus speeding up the last part of the rise time of the SCL. The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up circuit. This disabling enables other devices, such as the TSC2007, to delay the serial transfer (until the converted data are stored in the TSC internal shift register) by stretching the LOW period of SCL. The master re-enables its current-source pull-up circuit again when all devices have released, and SCL reaches a HIGH level, which speeds up the last part of the SCL signal rise time. Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, it is possible for the master to link a number of Hs mode transfers, separated by repeated START conditions (Sr). S SDA 8-Bit Master Code 00001xxx N tH 2 SCL 1 2 to 5 6 Fast or Standard Mode 7 8 9 Sr 7-Bit Slave Address R/W A n x (8-Bit DATA + A/N) Sr P SDA SCL 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9 If P then Fast or Standard Mode If Sr (dotted lines) then High-Speed Mode tFS High-Speed Mode tH = Current Source Pull-Up = Resistor Pull-Up A = Acknowledge (SDA LOW) N = Not Acknowledge (SDA HIGH) S = START Condition P = STOP Condition Sr = Repeated START Condition Figure 30. Complete High-Speed Mode Transfer Submit Documentation Feedback 23 TSC2007 www.ti.com SBAS405 – MARCH 2007 DIGITAL INTERFACE ADDRESS BYTE The TSC2007 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are factory-preset to comply with the I2C standard for A/D converters and are always set at '10010'. The logic state of the address input pins (A1-A0) determine the two LSBs of the device address to activate communication. Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one time. The A1-A0 address inputs are read whenever an address byte is received, and should be connected to the supply (VDD), or the ground (GND). The slave address is latched into the TSC2007 on the falling edge of SCL after the read/write bit has been received by the slave. The last bit of the address byte (R/W) defines the operation to be performed. When set to a '1', a read operation is selected; when set to a ‘0’, a write operation is selected. Following the START condition, the TSC2007 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line. Table 1. I2C Slave Address Byte MSB D7 1 D6 0 D5 0 D4 1 D3 0 D2 A1 D1 A0 LSB D0 R/W Bit D0: R/W 1: I2C master read from TSC (I2C read addressing). 0: I2C master write to TSC (I2C write addressing). COMMAND BYTE Table 2. Command Byte Definition (Excluding the Setup Command) (1) BIT D7-D4 D3-D2 NAME C3-C0 PD1-PD0 DESCRIPTION All Converter Function Select bits as detailed in Table 3, except for the setup command ('1011'). 00: 01: 10: 11: Power down between cycles. PENIRQ enabled. A/D converter on. PENIRQ disabled. A/D converter off. PENIRQ enabled. A/D converter on. PENIRQ disabled. D1 D0 (1) M X 0: 12-bit (Lower speed referred to as the 2MHz clock). 1: 8-bit (Higher speed referred to as the 4MHz clock). Don't care. The command byte definition for the setup command is shown in Table 4. Bits D7-D4: C3-C0—Converter function select bits. These bits select the input to be converted and the converter function to be executed, activate the drivers, and configure the PENIRQ pullup resitor (RIRQ). Table 3 lists the possible converter functions. Bits D3-D2: PD1-PD0—Power-down bits. These two bits select the power-down mode that the TSC2007 will be in after the current command completes, as shown in Table 2. It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. If multiple X-, Y-, and Z-position measurements will be done one right after another (such as when averaging), PD0 =1 will leave the touch screen drivers on at the end of each conversion cycle. Bit D1: M—Mode bit. If M = 0, the TSC2007 is in 12-bit mode. If M = 1, 8-bit mode is selected. Bit D0: X—Don’t care. 24 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 When the TSC2007 powers up, the power-down bits must be written to ensure that the device is placed into the mode that achieves the lowest power. Therefore, immediately after power-up, send a command byte that sets PD1 = PD0 = 0, so that the device will be in the lowest power mode, powering down between conversions. Table 3. Converter Function Select INPUT TO A/D CONVERTER TEMP0 N/A AUX N/A TEMP1 N/A N/A N/A N/A N/A N/A N/A Y+ X+ X+ Y– REFERENCE MODE Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended Differential Differential Differential N/A Differential Differential Differential Differential C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (1) C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Measure TEMP0 Reserved Measure AUX Reserved Measure TEMP1 Reserved Reserved Reserved Activate X-drivers Activate Y-drivers Activate Y+, X-drivers Setup command (1) Measure X position Measure Y position Measure Z1 position Measure Z2 position X-DRIVERS OFF OFF OFF OFF OFF OFF OFF OFF ON OFF X– ON OFF ON OFF X– ON X– ON Y-DRIVERS OFF OFF OFF OFF OFF OFF OFF OFF OFF ON Y+ ON OFF OFF ON Y+ ON Y+ ON ACK Y N Y N Y N N N Y Y Y N Y Y Y Y The setup command has an additional four bits of data. These data are static; that is, they are not changed by other commands, except for the power-on reset. The default value for these bits after power-on reset is 0000. Table 4 shows the definition of these data bits. Table 4. Command Byte Definition for the Setup Command BIT D7-D4 D3-D2 D1 D0 NAME C3-C0 = '1011' PD1-PD0 = '00' Filter control PENIRQ pullup resistor (RIRQ) select DESCRIPTION Setup command; must write '1011'. Reserved; must write '00'. 0: Use the onboard MAV filter (default). 1: Bypass the onboard MAV filter. 0: RIRQ = 50kΩ (default). 1: RIRQ = 90kΩ. Submit Documentation Feedback 25 TSC2007 www.ti.com SBAS405 – MARCH 2007 START A CONVERTER FUNCTION/WRITE CYCLE A conversion/write cycle begins when the master issues the address byte containing the slave address of the TSC2007, with the eighth bit equal to a 0 (R/W = 0), as shown in Table 1. Once the eighth bit has been received, and the address matches the A1-A0 address input pin setting, the TSC2007 issues an acknowledge. When the master receives the acknowledge bit from the TSC2007, the master writes the command byte to the slave (see Table 2). After the command byte is received by the slave, the slave issues another acknowledge bit. The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in Figure 31. SCL Address Byte R/W 0 Command Byte SDA 1 0 0 1 0 A1 A0 0 C3 C2 C1 C0 PD1 PD0 M X 0 TSC2007 ACK START TSC2007 ACK Acquisition Conversion STOP or Repeated START Figure 31. Complete I2C Serial Write Transmission If the master sends additional command bytes after the initial byte, but before sending a STOP or repeated START condition, the TSC2007 will not acknowledge those bytes. The input multiplexer channel for the A/D converter is selected when bits C3 through C0 are clocked in. If the selected channel is an X-,Y-, or Z-position measurement, the appropriate drivers will turn on once the acquisition period begins. When R/W = 0, the input sample acquisition period starts on the falling edge of SCL when the C0 bit of the command byte has been latched, and ends when a STOP or repeated START condition has been issued. A/D conversion starts immediately after the acquisition period. The multiplexer inputs to the A/D converter are disabled once the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respective touch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 31. 26 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 READ A CONVERSION/READ CYCLE For best performance, the I2C bus should remain in an idle state while an A/D conversion is taking place. This idling prevents digital clock noise from affecting the bit decisions being made by the TSC2007. The master should wait for at least 10µs before attempting to read data from the TSC2007 to realize this best performance. However, the master does not need to wait for a completed conversion before beginning a read from the slave, if full 12-bit performance is not necessary. Data access begins with the master issuing a START condition followed by the address byte (see Table 1) with R/W = 1. When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first byte of serial data will follow (D11-D4, MSB first). After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge. The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0, followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to indicate that the last data byte has been received. If the master somehow acknowledges the second data byte, invalid data will be returned (FFh). This applies to both 12-and 8-bit modes. See Figure 32 for a complete I2C read transmission. SCL Address Byte Data Byte 1 Data Byte 2 SDA 1 0 0 1 0 A1 A0 R/W 1 0 D11 D10 D9 D8 D7 D6 D5 D4 0 D3 D2 D1 D0 0 0 0 0 1 START TSC2007 ACK MASTER ACK MASTER STOP or NACK Repeated START Figure 32. Complete I2C Serial Read Transmission Submit Documentation Feedback 27 TSC2007 www.ti.com SBAS405 – MARCH 2007 THROUGHPUT RATE AND I2C BUS TRAFFIC Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The throughput is further limited by the I2C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bit resolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I2C bandwidth for the system to use on other devices. Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal 4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency drops down to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate. To send the conversion result across the I2C bus takes 49 bus clocks (SCL clock). Each write cycle takes 20 I2C cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 29 I2C cycles (START, STOP, address byte, 3 ACKs, and data bytes 1 and 2). Seven sample-and-conversions take 19 x 7 internal clocks (12-bit), or 16 x 7 (8-bit) to convert. The MAV filter loop takes 19 internal clocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 5. Because the first acquisition cycle is overlapped with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 12-bit mode, it requires (19 × 7 + 19) – 4 = 148 CCLKs plus I/O. For 8-bit mode, it requires (16 × 7 + 19) – 4 = 127 CCLKs plus I/O. Table 5. Measurement Cycle Time Calculations STANDARD MODE: 100kHz (Period = 10µs) 8-Bit 12-Bit 8-Bit 12-Bit 8-Bit 12-Bit 8-Bit 12-Bit 40 × 10µs + 127 × 313ns = 439.8µs (2.27kSPS through the I2C bus) 49 × 10µs + 148 × 625ns = 582.5µs (1.72kSPS through the I2C bus) 40 × 2.5µs + 127 × 313ns = 139.8µs (7.15kSPS through the I2C bus) 49 × 2.5µs + 148 × 625ns = 215µs (4.65kSPS through the I2C bus) 40 × 588ns + 127 × 313ns = 63.3µs (15.79kSPS through the I2C bus) 49 × 588ns + 148 × 625ns = 121.3µs (8.24kSPS through the I2C bus) 40 × 294ns + 127 × 313ns = 51.6µs (19.39kSPS through the I2C bus) 49 × 294ns + 148 × 625ns = 106.9µs (9.35kSPS through the I2C bus) FAST MODE: 400kHz (Period = 2.5µs) HIGH-SPEED MODE: 1.7MHz (Period = 588ns) HIGH-SPEED MODE: 3.4MHz (Period = 294ns) As an example, use VDD = 1.2V and 12-bit mode with the Fast-mode I2C clock (fSCL = 400kHz). The equivalent TSC throughput is at least seven times faster than the effective throughput across the bus (4.65k x 7 = 32.55kSPS). The supply current to the TSC for this rate and configuration is 128µA. To achieve an equivalent sample throughput of 8.2kSPS using the device without preprocessing, the TSC2007 merely consumes (8.2/32.55) × 128µA = 32.24µA. 28 Submit Documentation Feedback TSC2007 www.ti.com SBAS405 – MARCH 2007 Table 6. Effective and Equivalent Throughput Rates SUPPLY VOLTAGE I2C BUS SPEED (fSCL) 100kHz Standard 400kHz Fast 2.7V 1.7MHz High-Speed 3.4MHz High-Speed 100kHz Standard 400kHz Fast 1.8V 1.7MHz High-Speed 3.4MHz High-Speed 100kHz Standard 400kHz Fast 1.2V 1.7MHz High-Speed 3.4MHz High-Speed TSC CONVERSION CYCLE TIME (µs) 433.6 568.7 133.6 201.2 57.1 107.5 45.4 93.1 434.7 570.9 134.7 203.4 58.2 109.7 46.5 95.3 439.8 582.5 139.8 215.0 63.3 121.3 51.6 106.9 EFFECTIVE THROUGHPUT (kSPS) 2.31 1.76 7.49 4.97 17.50 9.30 22.04 10.74 2.30 1.75 7.42 4.92 17.17 9.12 21.52 10.49 2.27 1.72 7.15 4.65 15.79 8.24 19.39 9.35 EQUIVALENT THROUGHPUT (kSPS) 16.14 12.31 52.40 34.79 122.53 65.09 154.31 75.16 16.10 12.26 51.97 34.42 120.22 63.81 150.65 73.46 15.92 12.02 50.07 32.56 110.51 57.70 135.72 65.47 # OF SCL 40 49 40 49 40 49 40 49 40 49 40 49 40 49 40 49 40 49 40 49 40 49 40 49 # OF CCLK 127 148 127 148 127 148 127 148 127 148 127 148 127 148 127 148 127 148 127 148 127 148 127 148 fCCLK (kHz) 3780 1880 3780 1880 3780 1880 3780 1880 3660 1830 3660 1830 3660 1830 3660 1830 3190 1600 3190 1600 3190 1600 3190 1600 CCLK PERIODS (ns) 264.6 531.9 264.6 531.9 264.6 531.9 264.6 531.9 273.2 546.4 273.2 546.4 273.2 546.4 273.2 546.4 313.5 625.0 313.5 625.0 313.5 625.0 313.5 625.0 RESOLUTION 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit 8-bit 12-bit Submit Documentation Feedback 29 30 I2C Read Clock Stretched TSC2007 SBAS405 – MARCH 2007 I2C Write SCL CCLK Command Byte Address Byte Address Byte Data Byte 1 0 C3 C2 C1 C0 PD1 PD0 M X 1 1 0 A0 0 0 0 A1 D11 D10 Data Byte 2 SDA TSC2007 ACK Acquisition 1 6 SCLs Conversion 1 15 CCLKs ) STOP or REPEATED START ( Acquisition 2 4 CCLKs Conversion 2 15 CCLKs 1 0 0 0 1 0 A1 A0 R/W 0 D9 D8 D7 D6 D5 D4 D3 0 D2 R/W 1 D1 D0 0 0 0 0 1 TSC2007 ACK TSC2007 ACK Conversion 7 15 CCLKs MAV Filter 19 CCLKs MASTER ACK MASTER NACK STOP or REPEATED START START Figure 33. Data Acquisition Cycle (Filter Enabled) 148 CCLKs (Filter is Enabled, 12-Bit Mode) Submit Documentation Feedback I2C Write Clock Stretched SCL CCLK Address Byte SDA 1 1 0 A0 0 0 0 A1 C3 C2 R/W 0 C1 I2C Read Command Byte C0 PD1 PD0 M X 0 1 0 Address Byte R/W 0 1 0 A1 A0 1 0 D11 D10 Data Byte 1 D9 D8 D7 D6 D5 D4 0 D3 D2 Data Byte 2 D1 D0 0 0 0 0 1 TSC2007 ACK START TSC2007 ACK Acquisition 1 6 SCLs STOP or REPEATED START ( ) TSC2007 ACK Conversion 1 15 CCLKs MASTER ACK MASTER NACK STOP or REPEATED START Figure 34. Data Acquisition Cycle (Filter Disabled) 15 CCLKs (Filter is Disabled, 12-Bit Mode) www.ti.com TSC2007 www.ti.com SBAS405 – MARCH 2007 LAYOUT The following layout suggestions should obtain optimum performance from the TSC2007. However, many portable applications have conflicting requirements for power, cost, size, and weight. In general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the TSC2007 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the SCL input. With this in mind, power to the TSC2007 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor may also be needed if the impedance of the connection between VDD/REF and the power supply is high. A bypass capacitor is generally not needed on the VDD/REF pin because the internal reference is buffered by an internal op amp. If an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. The TSC2007 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input, which is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. Some package options have pins labeled as VOID. Avoid any active trace going under those pins marked as VOID unless they are shielded by a ground or power plane. The GND pin should be connected to a clean ground point. In many cases, this point will be the analog ground. Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Loose connections can be a source of error when the contact resistance changes with flexing or vibrations. As indicated previously, noise can be a major source of error in touch-screen applications (for example, applications that require a back-lit LCD panel). This electromagnetic interfence (EMI) noise can be coupled through the LCD panel to the touch screen and cause flickering of the converted ADC data. Several things can be done to reduce this error, such as using a touch screen with a bottom-side metal layer connected to ground, which will couple the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y–, X+, and X– to ground, can also help. Note, however, that the use of these capacitors increases screen settling time and requires a longer time for panel voltages to stabilize. The resistor value varies depending on the touch screen sensor used. The PENIRQ pullup resistor (RIRQ) may be adequate for most of sensors. Submit Documentation Feedback 31 PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 PACKAGING INFORMATION Orderable Device TSC2007IPW TSC2007IPWG4 TSC2007IPWR TSC2007IPWRG4 TSC2007IYZGR TSC2007IYZGT (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type TSSOP TSSOP TSSOP TSSOP DSBGA DSBGA Package Drawing PW PW PW PW YZG YZG Pins Package Eco Plan (2) Qty 16 16 16 16 12 12 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU SNAGCU SNAGCU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Device Package Pins Site Reel Diameter (mm) 330 Reel Width (mm) 12 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8 W Pin1 (mm) Quadrant 12 PKGORN T1TR-MS P PKGORN T1TR-MS P PKGORN T1TR-MS P TSC2007IPWR PW 16 MLA 7.0 5.6 1.6 TSC2007IYZGR YZG 12 UNITIVE 177 8 1.65 1.65 0.71 4 8 TSC2007IYZGT YZG 12 UNITIVE 177 8 1.65 1.65 0.71 4 8 TAPE AND REEL BOX INFORMATION Device TSC2007IPWR TSC2007IYZGR TSC2007IYZGT Package PW YZG YZG Pins 16 12 12 Site MLA UNITIVE UNITIVE Length (mm) 342.9 195.2 195.2 Width (mm) 336.6 193.7 193.7 Height (mm) 20.6 34.9 34.9 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0°– 8° 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D: E: 1.57 mm + 30 µm 2.07 mm + 30 µm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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