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TUSB2077A
SLLS414F – MARCH 2000 – REVISED AUGUST 2015
TUSB2077A 7-Port Hub for the Universal Serial Bus With Optional
Serial EEPROM Interface
1 Features
2 Applications
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3 Description
The TUSB2077A hub is a 3.3-V CMOS device that
provides up to seven downstream ports in compliance
with the USB 2.0 specification. Because this device is
implemented with a digital state machine instead of a
microcontroller, no software programming is required.
Fully compliant USB transceivers are integrated into
the ASIC for all upstream and downstream ports. The
downstream ports support full-speed and low-speed
devices by automatically setting the slew rate
according to the speed of the device attached to the
ports. The configuration of the BUSPWR terminal
selects either the bus-powered or self-powered mode.
The introduction of the DP0 pull-up resistor disable
terminal, DP0PUR, makes it much easier to
implement an onboard bus/self-power dynamicswitching circuitry. The three-LED indicator control
output pins also enable the implementation of
visualized status monitoring of the hub and its
downstream ports. With these new function pins, the
end equipment vendor can considerably reduce the
total board cost while adding additional product value.
Device Information(1)
PART NUMBER
TUSB2077A
PACKAGE
LQFP (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
USB-Tiered Configuration Example
Printer with
TUSB2077A
7-Port Hub
Personal
Computer
Monitor with
TUSB2077A
7-Port Hub
Digital Scanner
...
•
Computer Systems
Docking Stations
Scanner
Modem
Right Speaker
Keyboard with
TUSB2077A
7-Port Hub
...
•
•
•
Fully Compliant With the USB Specification as a
Full-Speed Hub: TID #20240226
Integrated USB Transceivers
3.3-V Low-Power ASIC Logic
Two Power Source Modes
– Self-Powered Mode Supporting Seven
Downstream Ports
– Bus-Powered Mode Supporting Four
Downstream Ports
All Downstream Ports Support Full-Speed and
Low-Speed Operations
Power Switching and Overcurrent Reporting Is
Provided Ganged or Per Port
Supports Suspend and Resume Operations
Suspend Status Pin Available for External Logic
Power Down
Supports Custom Vendor ID and Product ID With
External Serial EEPROM
3-State EEPROM Interface Allows EEPROM
Sharing
Push-Pull Outputs for PWRON Eliminate the Need
for External Pullup Resistors
Noise Filtering on OVRCUR Provides Immunity to
Voltage Spikes
Supports 6-MHz Operation Through a Crystal
Input or a 48-MHz Input Clock
New Functional Pins Introduced to Reduce the
Board Material Cost
– 3 LED Indicator Control Outputs Enable
Visualized Monitoring of 6 Different Hub/Port
Status (HUBCFG, PORTPWR, PORTDIS)
– Output Pin Available to Disable External Pullup
Resistor on DP0 for 15 ms After Reset or After
Change on BUSPWR and Enable Easy
Implementation of Onboard Bus/Self-Power
Dynamic Switching Circuitry
No Special Driver Requirements; Works
Seamlessly With Any Operating System With USB
Stack Support
Available in 48-Pin LQFP Package
JEDEC Descriptor S−PQFP−G for Low-Profile
Quad Flatpack (LQFP).
...
1
Mouse
Left Speaker
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB2077A
SLLS414F – MARCH 2000 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
6
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Differential Driver Switching Characteristics (FullSpeed Mode) .............................................................
7.7 Differential Driver Switching Characteristics (LowSpeed Mode) .............................................................
7.8 Typical Characteristics ..............................................
8
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
8.5 Programming........................................................... 11
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
10 Power Supply Recommendations ..................... 17
10.1 TUSB2077A Power Supply ................................... 17
10.2 Downstream Port Power ....................................... 17
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
7
7
8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2013) to Revision F
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Description (Continued)
The EXTMEM pin (pin 47) enables or disables the optional EEPROM interface. When EXTMEM is high, the
vendor and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is
General Purpose USB Hub.
The TUSB2077A supports bus-powered and self-powered modes. External power-management devices, such as
the TPS2044, are required to control the 5-V power source switching (on/off) to the downstream ports and to
detect an overcurrent condition from the downstream ports individually or ganged. An individually port power
controlled hub switches power on or off to each downstream port as requested by the USB host. Also when an
individually port power controlled hub senses an overcurrent event, only power to the affected downstream port
will be switched off. A ganged hub switches on power to all its downstream ports when power must be on for any
port. The power to the downstream ports is not switched off unless all ports are in a state that allows power to be
removed. Also, when a ganged hub senses an overcurrent event, power to all downstream ports will be switched
off.
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6 Pin Configuration and Functions
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
PWRON7
DP6
DM6
OVRCUR6
PWRON6
DP5
DM5
OVRCUR5
PWRON5
DP4
DM4
OVRCUR4
DM1
DP1
PWRON2
OVRCUR2
DM2
DP2
PWRON3
OVRCUR3
DM3
DP3
PWRON4
GND
13
14
15
16
17
18
19
20
21
22
23
24
SUSPND
DP0PUR
DP0
DM0
GND
RESET
EECLK
EEDATA/GANGED
VCC
BUSPWR
PWRON1
OVRCUR1
46
45
44
43
42
41
40
39
38
37
48
47
MODE
EXTMEM
VCC
XTAL1/CLK48
XTAL2
GND
PORTDIS
PORTPWR
HUBCFG
DP7
DM7
OVRCUR7
PT Package
48-Pin LQFP
Top View
NC - No internal connection
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Power source indicator. BUSPWR is an active-low input that indicates whether the downstream ports source their
power from the USB cable or a local power supply. For the bus-power mode, this terminal must be pulled low, and for
the self-powered mode, this terminal must be pulled to 3.3 V. Input must not change dynamically during operation.
BUSPWR
10
I
DM0
4
I/O
Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
DM1
13
DM2
17
DM3
21
DM4
26
I/O
USB differential data minus. DM1–DM7 paired with DP1–DP7 support up to four downstream USB ports.
DM5
30
DM6
34
DM7
38
I/O
Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
I/O
USB differential data plus. DP1–DP7 paired with DM1–DM7 support up to four downstream USB ports.
DP0
3
DP1
14
DP2
18
DP3
22
DP4
27
DP5
31
DP6
35
DP7
39
DP0PUR
2
O
Pullup resistor connection. When a system reset happens (RESET being driven to low, but not USB reset) or any logic
level change on BUSPWR terminal, DP0PUR output is inactive (floating) until the internal counter reaches a 15-ms
time period. After the counter expires, DP0PUR is driven to the VCC (3.3 V) level thereafter until the next system reset
event occurs or there is a BUSPWR logic level change.
EECLK
7
O
EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK terminal is disabled and
must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial clock output to the
EEPROM with a 100-μA internal pulldown.
EEDATA/
GANGED
8
I/O
EEPROM serial data/power-management mode indicator. When EXTMEM is high, EEDATA/GANGED selects between
ganged or per-port power overcurrent detection for the downstream ports. When EXTMEM is low, EEDATA/GANGED
acts as a serial data I/O for the EEPROM and is internally pulled down with a 100-μA pulldown. This standard TTL
input must not change dynamically during operation.
4
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Pin Functions (continued)
PIN
NAME
NO.
EXTMEM
I/O
47
GND
I
5, 24, 43
DESCRIPTION
When EXTMEM is high, the serial EEPROM interface of the device is disabled. When EXTMEM is low, pins 7 and 8
are configured as the clock and data terminals of the serial EEPROM interface, respectively.
GND pins must be tied to ground for proper operation.
40
O
Hub configured. Used to control LED indicator. When the hub is configured, HUBCFG is high, which can be used to
turn on a green LED. When the hub is not configured, HUBCFG is low, which can be used to turn on a red LED.
MODE
48
I
Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal core of the
chip and 6-MHz crystal or oscillator can used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock
source and 48-MHz oscillator or other onboard clock source can be used.
OVRCUR1
12
OVRCUR2
16
OVRCUR3
20
OVRCUR4
25
I
OVRCUR5
29
Overcurrent input. OVRCUR1–OVRCUR7 are active low. For per-port overcurrent detection, one overcurrent input is
available for each of the seven downstream ports. In the ganged mode, any OVRCUR input may be used and all
OVRCUR pins must be tied together. OVRCUR terminals are active low inputs with noise filtering logic.
OVRCUR6
33
41
O
Any port powered. Used to control LED indicator. When any port is powered on, PORTPWR is high, which can be used
to turn on a green LED. When all ports are off, PORTPWR is low, which can be used to turn on a red LED.
PORTDIS (1)
42
O
No ports disabled. PORTDIS is used for LED indicator control. When no port is disabled, PORTDIS is high, which can
be used to turn on a green LED. When any port is disabled, PORTDIS is low, which can be used to turn on a red LED.
PWRON1
11
PWRON2
15
PWRON3
19
PWRON4
23
O
PWRON5
28
Power-on/-off control signals. PWRON1–PWRON7 are active low, push-pull outputs that enables the external power
switch device. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However, the external
power switches that connect to these terminals must be able to operate with 3.3-V inputs because these outputs
cannot drive 5-V signals.
PWRON6
32
PWRON7
36
RESET
6
I
RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted, all
logic is initialized. Generally, a reset with a pulse width between 100 μs and 1 ms is recommended after 3.3-V VCC
reaches its 90%. Clock signal has to be active during the last 60 μs of the reset window.
SUSPND
1
O
Suspend status. SUSPND is an active high output available for external logic power-down operations. During the
suspend mode, SUSPND is high. SUSPND is low for normal operation.
HUBCFG
(1)
OVRCUR7
PORTPWR
37
(1)
VCC
9, 46
3.3-V supply voltage
XTAL1/CLK48
45
I
Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An
internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When MODE is high,
XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed.
XTAL2
44
O
Crystal 2. XTAL2 is a 6-MHz crystal output. This pin must be left open when using an oscillator.
(1)
All LED controls are 3-stated during low-power suspend.
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage (2)
–0.5
3.6
V
VI
Input voltage
–0.5
VCC + 0.5
V
VO
Output voltage
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0 V or VI < VCC
±20
mA
IOK
Output clamp current
VO < 0 V or VO < VCC
TA
Operating free-air temperature
Tstg
Storage temperature
(1)
(2)
±20
mA
0
70
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage levels are with respect to GND.
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
V
VI
Input voltage, TTL/LVCMOS (1)
0
VCC
V
0
VCC
V
2
VCC
V
0.8
V
V
(2)
VO
Output voltage, TTL/LVCMOS
VIH(REC)
High-level input voltage, signal-ended receiver
VIL(REC)
Low-level input voltage, signal-ended receiver
(1)
UNIT
VIH(TTL)
High-level input voltage, TTL/LVCMOS
2
VCC
VIL(TTL)
Low-level input voltage, TTL/LVCMOS (1)
0
0.8
V
TA
Operating free-air temperature
0
70
°C
R(DRV)
External series, differential driver resistor
f(OPRH)
Operating (dc differential driver) high speed mode
12
Mb/s
f(OPRL)
Operating (dc differential driver) low speed mode
1.5
Mb/s
VICR
Common mode, input range, differential receiver
2.5
V
tt
Input transition times, TTL/LVCMOS
TJ
Junction temperature (3)
(1)
(2)
(3)
(1)
Ω
22
0.8
0
25
ns
0
115
°C
Applies for input and bidirectional buffers.
Applies for output and bidirectional buffers.
These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
7.4 Thermal Information
TUSB2077A
THERMAL METRIC (1)
PT (LQFP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
66.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
21.1
°C/W
RθJB
Junction-to-board thermal resistance
37.8
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
31.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITION
TTL/LVCMOS
VOH
High-level output voltage
USB data lines
TTL/LVCMOS
VOL
Low-level output voltage
VIT+
Positive input threshold
VIT–
Negative-input threshold
Vhys
Input hysteresis (1)
(VT+ – VT–)
IOZ
High-impedance output current
IIL
IIH
USB data lines
MIN
IOH = –4 mA
MAX
VCC – 0.5
R(DRV) = 15 kΩ to GND
2.8
IOH = –12 mA (without R(DRV))
V
VCC – 0.5
IOL = 4 mA
0.5
R(DRV) = 1.5 kΩ to 3.6 V
0.3
IOL = 12 mA (without R(DRV))
0.5
TTL/LVCMOS
Single-ended
UNIT
V
1.8
0.8 V ≤ VICR ≤ 2.5 V
V
1.8
TTL/LVCMOS
0.8
V
0.8 V ≤ VICR ≤ 2.5 V
1
0.3
0.7
Single-ended
0.8 V ≤ VICR ≤ 2.5 V
300
500
TTL/LVCMOS
V = VCC or GND (2)
±10
USB data lines
0 V ≤ VO ≤ VCC
±10
Low-level input current
TTL/LVCMOS
VI = GND
–1
μA
High-level input current
TTL/LVCMOS
VI = VCC
1
μA
z0(DRV)
Driver output impedance
USB data lines
Static VOH or VOL
7.1
19.9
Ω
VID
Differential input voltage
USB data lines
0.8 V ≤ VICR ≤ 2.5 V
0.2
ICC
(1)
(2)
Single-ended
TTL/LVCMOS
μA
V
Normal operation
Input supply current
mV
Suspend mode
40
mA
1
μA
Applies for input buffers with hysteresis.
Applies for open-drain buffers.
7.6 Differential Driver Switching Characteristics (Full-Speed Mode)
over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tr
Transition rise time for DP or DM
See Figure 1 and Figure 2
4
20
ns
tf
Transition fall time for DP or DM
See Figure 1 and Figure 2
4
20
ns
t(RFM)
Rise/fall time matching (1)
(tr/tf) × 100
90%
110%
VO(CRS)
Signal crossover output voltage (1)
1.3
2.0
(1)
V
Characterized only. Limits are approved by design and are not production tested.
7.7 Differential Driver Switching Characteristics (Low-Speed Mode)
over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted)
MIN
MAX
UNIT
tr
Transition rise time for DP or DM (1)
PARAMETER
CL = 200 pF to 600 pF, See Figure 1 and Figure 2
TEST CONDITIONS
75
300
ns
tf
Transition fall time for DP or DM (1)
CL = 200 pF to 600 pF, See Figure 1 and Figure 2
75
300
ns
80%
120%
1.3
2.0
(1)
t(RFM)
Rise/fall time matching
VO(CRS)
Signal crossover output voltage (1)
(1)
(tr/tf) × 100
CL = 200 pF to 600 pF
V
Characterized only. Limits are approved by design and are not production tested.
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22 Ω
1.5 kΩ
15 kΩ
22 Ω
15 kΩ
Figure 1. Differential Driver Switching Load
Figure 2. Differential Driver Timing Waveforms
VCC
Vhys
Logic high
VIH
VIT+
VIT-
VIL
Logic low
0V
Figure 3. Single-Ended Receiver Input Signal Parameter Definitions
V ID - Diff erential Receiver Input Sensitivity - V
7.8 Typical Characteristics
1.5
1.3
1
0.5
0.2
0
0
3
1
2
3.6
0.8
2.5
VICR - Common Mode Input Rang e - V
4
Figure 4. Differential Receiver Input Sensitivity vs Common Mode Input Range
8
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8 Detailed Description
8.1 Overview
The TUSB2077A hub is a 3.3-V CMOS device that provides up to seven downstream ports in compliance with
the USB 2.0 specification. Because this device is implemented with a digital state machine instead of a
microcontroller, no software programming is required. Fully compliant USB transceivers are integrated into the
ASIC for all upstream and downstream ports. The downstream ports support full-speed and low-speed devices
by automatically setting the slew rate according to the speed of the device attached to the ports.
8.2 Functional Block Diagram
DP0
3
DM0
4
USB
Transceiver
1
SUSPND
1
Hub Repeater
M
U
X
Suspend /Resume
Logic and
Frame Timer
45
0
OSC/PLL
44
SIE
48
6
2
47
8
SIE Interface
Logic
Serial
EEPROM
Interface
7
XTAL1/CLK48
XTAL2
MODE
RESET
DP0PUR
EXTMEM
EEDATA/GANGED
EECLK
Port 1
Logic
40
Hub /Device
Command
Decoder
42
41
10
Port 4
Logic
USB
Transceiver
39
38
USB
Transceiver
14
Hub
Power
Logic
HUBCFG
PORTDIS
PORTPWR
BUSPWR
12, 16, 20, 25, 29, 33, 37
OVRCUR1 - OVRCUR7
13
11, 15, 19, 23,28, 32, 36
DP7
DM7
DP1
PWRON1 - PWRON7
DM1
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8.3 Feature Description
8.3.1 USB Power Management
The TUSB2077A supports both bus-powered and self-powered modes. External power-management devices,
such as the TPS2044, are required to control the 5-V power source switching (on/off) to the downstream ports
and to detect an overcurrent condition from the downstream ports individually or ganged. Outputs from external
power devices provide overcurrent inputs to the TUSB2077A OVRCUR pins in case of an overcurrent condition,
the corresponding PWRON pins are disabled by the TUSB2077A. In the ganged mode, all PWRON signals
transition simultaneously, and any OVRCUR input can be used. In the nonganged mode, the PWRON outputs
and OVRCUR inputs operate on a per-port basis.
Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two types
of protection are individual-port management (individual-port basis) or ganged-port management (multiple-port
basis). Individual-port management requires power-management devices for each individual downstream port,
but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host only
powers down the port that has the condition. The ganged configuration uses fewer power management devices
and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports, all
the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2077A supports four modes of
power management: bus-powered hub with either individual-port power management or ganged-port power
management, and the self-powered hub with either individual-port power management or ganged-port power
management. Texas Instruments supplies the complete hub solution because we offer this TUSB2077A along
with the power-management devices needed to implement a fully USB compliant system.
8.3.2 Clock Generation
The TUSB2077A provides the flexibility of using either a 6-MHz or a 48-MHz clock. The logic level of the MODE
terminal controls the selection of the clock source. When MODE is low, the output of the internal APLL circuitry is
selected to drive the internal core of the chip. When MODE is high, the XTAL1 input is selected as the input
clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered
down while MODE is high. For 6-MHz operation, TUSB2077A requires a 6-MHz clock signal on XTAL1 terminal
(with XTAL2 for a crystal) from which its internal APLL circuitry generates a 48-MHz internal clock to sample the
data from the upstream port. For 48-MHz operation, the clock cannot be generated with a crystal, using the
XTAL2 output, because the internal oscillator cell only supports the fundamental frequency. If low-power suspend
and resume are desired, a passive crystal or resonator must be used, although the hub supports the flexibility of
using any device that generates a 6-MHz clock. Because most oscillators cannot be stopped while power is on,
their use prohibits low-power suspend, which depends on disabling the clock. When the oscillator is used, by
connecting its output to the XTAL1 terminal and leaving the XTAL2 terminal open, its TTL output level cannot
exceed 3.6 V. If a 6-MHz oscillator is used, it must be stopped at logic low whenever SUSPND is high. For
crystal or resonator implementations, the XTAL1 terminal is the input and the XTAL2 terminal is used as the
feedback path. A sample crystal tuning circuit is shown in Figure 5.
CL
XTAL1
XTAL2
C1
C2
NOTE: This figure assumes a 6-MHz fundamental crystal that is parallel loaded. The component values of C1, C2, and Rd
are determined using a crystal from Fox Electronics – part number HC49U-6.00MHz 30\50\0±70\20, which means
±30 ppm at 25°C and ±50 ppm from 0°C to 70°C. The characteristics for the crystal include a load capacitance (CL) of
20 pF, maximum shunt capacitance (Co) of 7 pF, and the maximum ESR of 50 Ω. In order to insure enough negative
resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the gain, and Rd = 1.5 kΩ is recommended.
Figure 5. Crystal Tuning Circuit
10
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8.4 Device Functional Modes
8.4.1 Vendor ID and Product ID With External Serial EEPROM
The EXTMEM (pin 47) enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor
and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is General
Purpose USB Hub. For this configuration, pin 8 functions as the GANGED input pin and EECLK (pin 7) is
unused. If custom VID and PID descriptors are desired, the EXTMEM must be tied low (EXTMEM = 0) and a
SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID, PID, and GANGED values. For
this configuration, pin 7 and 8 function as the EEPROM interface signals with pin 7 as EECLK and pin 8 as
EEDATA, respectively. A block diagram example of how to connect the external EEPROM if a custom product ID
and vendor ID are desired is shown in Figure 6.
TUSB2077A USB Hub
6-MHz Clock
Signal
Bus or Local Power
5 V GND
45
XTAL1
44
XTAL2
9, 46
VCC
Regulator
3.3 V
6
System
Power-On Reset
RESET
GND
5, 24, 43
47
EXTMEM
3
DP0
4
EEPROM
6
D
ORG
8
5
VCC
Q
EEDATA
VSS
C
4
13, 17, 21, 26, 30, 34, 38
7
12, 16, 20, 25, 29, 33, 37
8
1 kΩ
7
DM1 - DM7
DM0
3
14, 18, 22, 27, 31, 35, 39
DP1 - DP7
7
EECLK
OVRCUR1 –
OVRCUR7
PWRON1 –
PWRON7
11, 15, 19, 23, 28, 32, 36
7
Power
Switching
7
GND
USB Data lines
and Power to
Downstream
Ports
Vbus
2
S
1
Figure 6. Typical Application of the TUSB2077A USB Hub
8.5 Programming
An SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID and PID. When the
EEPROM interface is enabled (EXTMEM = 0), the EECLK and EEDATA are internally pulled down (100 μA)
inside the TUSB2077A. The internal pulldowns are disabled when the EEPROM interface is disabled
(EXTMEM = 1).
The EEPROM is programmed with the three 16-bit locations as shown in Table 1. Connecting terminal 6 of the
EEPROM high (ORG = 1) organizes the EEPROM memory into 64×16-bit words.
Table 1. EEPROM Memory Map
ADDRESS
D15
D14
D13
D12–D8
D7–D0
00000
0
GANGED
00000
00000
00000000
00001
VID High-byte
00010
PID High-byte
VID Low-byte
PID Low-byte
XXXXXXXX
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The D and Q signals of the EEPROM must be tied together using a 1-kΩ resistor with the common I/O
operations forming a single-wire bus. After system power-on reset, the TUSB2077A performs a one-time access
read operation from the EEPROM if the EXTMEM terminal is pulled low and the chip select(s) of the EEPROM is
connected to the system power-on reset. Initially, the EEDATA terminal is driven by the TUSB2077A to send a
start bit (1) which is followed by the read instruction (10) and the starting-word address (00000). Once the read
instruction is received, the instruction and address are decoded by the EEPROM, which then sends the data to
the output shift register. At this point, the hub stops driving the EEDATA terminal and the EEPROM starts driving.
A dummy (0) bit is then output and the first three 16-bit words in the EEPROM are output with the most
significant bit (MSB) first.
The output data changes are triggered by the rising edge of the clock provided by the TUSB2077A on the
EECLK terminal. The SGS-Thompson M936C46 EEPROM is recommended because it advances to the next
memory location by automatically incrementing the address internally. Any EEPROM used must have the
automatic internal address advance function. After reading the three words of data from the EEPROM, the
TUSB2077A puts the EEPROM interface into a high-impedance condition (pulled down internally) to allow other
logic to share the EEPROM. The EEPROM read operation is summarized in Figure 7. For more details on
EEPROM operation, refer to SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM data
sheet.
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D
C
S
Start
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A5
Hub Driving Data Line
Read OP Code(10)
Other
Address
Bits
A1
6 Bit Address (000000)
A0
Dummy
Bit
MSB of The
First Word
D15
Other
LSB of
Data Bits Third Word
D0
EEPROM Driving Data Line
D14
48 Data Bits
MSB of
Fourth Word
XX
Don’t Care
3-Stated
With Internal
Pulldown
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TUSB2077A
Figure 7. EEPROM Read Operation Timing Diagram
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to a
single personal computer.
Another advantage of USB is that all peripherals are connected using a standardized four-wire cable that
provides both communication and power distribution. The power configurations are bus-powered and selfpowered modes. The maximum current that may be drawn from the USB 5-V line during power up is 100 mA.
For the bus-powered mode, a hub can draw a maximum of 500 mA from the 5-V line of the USB cable. A buspowered hub must always be connected downstream to a self-powered hub unless it is the only hub connected
to the PC and there are no high-powered functions connected downstream. In the self-powered mode, the hub is
connected to an external power supply and can supply up to 500 mA to each downstream port. High-powered
functions may draw a maximum of 500 mA from each downstream port and may only be connected downstream
to self-powered hubs. Per the USB specification, in the bus-powered mode, each downstream port can provide a
maximum of 100 mA of current, and in the self-powered mode, each downstream port can provide a maximum of
500 mA of current.
9.2 Typical Application
A common application for the TUSB2077A is as a self-powered USB hub product. The product is powered by an
external 5-V DC Power adapter. In this application, using a USB cable TUSB2077A’s upstream port is plugged
into a USB Host controller. The downstream ports of the TUSB2077A are exposed to users for connecting USB
cameras, keyboards, printers, and so forth.
USB
Type B
Connector
DC
Power
US Port
TUSB2077A
USB
Power Switch
USB
Power Switch
DS Port 1
DS Port 2
USB Type A
Connector
USB Type A
Connector
...
DS Port 6
DS Port 7
USB Type A
Connector
USB Type A
Connector
Figure 8. Self-Powered USB Hub Product
14
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Typical Application (continued)
9.2.1 Design Requirements
For this example, use the parameters listed in Table 2.
Table 2. Design Parameters
DESIGN PARAMETERS
VALUE
VCC Supply
3.3 V
Downstream Ports
7
Power Management
Individual Port
Clock Source
6-MHz Crystal
External EEPROM
No
Power Source Mode
Self-Powered
9.2.2 Detailed Design Procedure
In a self-powered configuration, the TUSB2077A can be implemented for individual-port power management
when used with the TPS2044 because it is capable of supplying 500 mA of current to each downstream port and
can provide current limiting on a per-port basis. When the hub detects a fault on a downstream port, power is
removed from only the port with the fault and the remaining ports continue to operate normally. Self-powered
hubs are required to implement overcurrent protection and report overcurrent conditions. The SN75240 transient
suppressors reduce inrush current and voltage spikes on the data lines.
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TUSB2077A
EEDATA/GANGED
DP0PUR
Upstream
Port
DP0
D-
A C
B D
0.1 mF
GND
D+
D-
DM1
15 kΩ
15 kΩ
DP2
5V
100 mF‡
15 kΩ
15 kΩ
4.7 mF
GND
SN75240†
5V
3.3 V
A C
B D
DM2
3.3 V LDO §
4.7 mF
¶
DM0
SN75240†
5V
Downstream
Ports
3.3 V
DP1
1.5 kΩ
D+
BUSPWR
VCC
D+
DP6
GND
D-
DM6
15 kΩ
15 kΩ
A C
B D
GND
SN75240†
5V
DP7
DM7
XTAL1
XTAL2
MODE
3.3 V
100 mF‡
15 kΩ
15 kΩ
6-MHz Clock
Signal
PWRON1
EN1
PWRON2
EN2
TPS2044†
D+
D-
EN3
EXTMEM
GND
EN4
System
Power-On Reset
PWRON6
OUT1
PWRON7
OUT2
5V
OUT3
RESET
OVRCUR1
OC1 OUT4
OVRCUR2
OC2
GND
OC3
100 mF‡
D+
IN1
D-
IN2
GND
OC4
OVRCUR6
0.1 mF
5V
OVRCUR7
100 mF‡
5-V Board Power
Supply
NOTES: † TPS2042 and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for the TPS2044.
‡ 120 µF per hub is the minimum required per the USB specification. However, TI recommends a 100-µF, low ESR,
tantalum capacitor per port for immunity to voltage droop.
§ LDO is a 5-V-to-3.3-V voltage regulator. TPS76333 from Texas Instruments can be used.
¶
All USB DP, DM signal pairs require series resistors of approximately 27Ω to ensure proper termination. An optional filter
capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub
terminal and the series resistor, as per section 7.1.6 of the USB specification.
Figure 9. TUSB2077A Self-Powered Hub, Individual-Port Power-Management Application
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9.2.3 Application Curve
Figure 10. Downstream Port
10 Power Supply Recommendations
10.1 TUSB2077A Power Supply
VCC should be implemented as a single power plane.
• The VCC pins of the TUSB2077A supply 3.3-V power rail to the I/O of the TUSB2077A. This power rail can be
isolated from all other power rails by a ferrite bead to reduce noise.
• All power rails require a 10-μF capacitor or 1-μF capacitors for stability and noise immunity. These bulk
capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as
close to the TUSB2077A power pins as possible with an optimal grouping of two of differing values per pin.
10.2 Downstream Port Power
•
•
•
The downstream port power, VBUS, must be supplied by a source capable of supplying 5 V and up to 500
mA per port. Downstream port power switches can be controlled by the TUSB2077A signals. It is also
possible to leave the downstream port power always enabled.
A large bulk low-ESR capacitor of 22 μF or larger is required on each downstream port’s VBUS to limit in-rush
current.
The ferrite beads on the VBUS pins of the downstream USB port connections are recommended for both
ESD and EMI reasons. A 0.1-μF capacitor on the USB connector side of the ferrite provides a low impedance
path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.
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11 Layout
11.1 Layout Guidelines
11.1.1 Placement
1. A 0.1-μF should be placed as close as possible on VCC power pin.
2. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.
3. If a crystal is used, it must be placed as close as possible to the XTAL1 and XTAL2 pins of the TUSB2077A.
4. Place voltage regulators as far away as possible from the TUSB2077A, the crystal, and the differential pairs.
5. In general, the large bulk capacitors associated with the power rail should be placed as close as possible to
the voltage regulators.
11.1.2 Differential Pairs
1. Must be designed with a differential impedance of 90 Ω ±10%.
2. Route all differential pairs on the same layer adjacent to a solid ground plane.
3. Do not route differential pairs over any plane split.
4. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stub on the differential pair.
5. Avoid 90-degree turns in trace. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore
minimize the impact bends have on EMI.
6. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for USB
2.0 differential pair signals is 8 inches. Longer trace lengths require very careful routing to assure proper
signal integrity.
7. Match the etch lengths of the differential pair traces. The USB 2.0 differential pairs should not exceed 50 mils
relative trace length difference.
8. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Any vias used should be placed as
close as possible to the TUSB2077A device.
9. Do not place power fuses across the differential pair traces.
11.1.3 Ground
TI recommends using only one board ground plane in the design. This provides the best image plane for signal
traces running above the plane. The thermal pad of the TUSB2077A and any of the voltage regulators should be
connected to this plane with vias. An earth or chassis ground is implemented only near the USB port connectors
on a different plane for EMI and ESD purposes.
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11.2 Layout Example
Figure 11. TUSB2077 Layout Example
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TUSB2077APT
ACTIVE
LQFP
PT
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB2077A
TUSB2077APTR
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB2077A
TUSB2077APTRG4
ACTIVE
LQFP
PT
48
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
0 to 70
TUSB2077A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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