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TUSB501-Q1
SLLSET3 – MAY 2016
TUSB501-Q1 USB 3.0 Single-Channel Redriver with Equalization
1 Features
•
•
1
•
•
•
•
•
•
•
Q100 Automotive Qualified
Aggressive Low-Power Architecture (Typical):
– 126 mW Active Power
– 20 mW in U2/U3
– 4 mW with No Connection
Automatic LFPS DE Control
Excellent Jitter and Loss Compensation
– 32 inches of FR4 4 mil Stripline
– 3 m of 30 AWG cable
Integrated Termination
Small 2 x 2 mm QFN Package
Selectable Receiver Equalization, Transmitter DeEmphasis and Output Swing
Hot-Plug Capable
ESD Protection ±5 kV HBM and 1500 V CDM
2 Applications
•
•
•
•
•
•
Cell Phones
Computers
Docking Stations
TVs
Active Cables
Backplanes
After power up, the TUSB501-Q1 periodically
performs receiver detection on the TX pair. If it
detects a SuperSpeed USB receiver, RX termination
becomes enabled, and the TUSB501-Q1 is ready to
redrive.
The receiver equalizer has three gain settings that
are controlled by pin EQ: 3 dB, 6 dB, and 9 dB. This
should be set based on amount of loss before the
TUSB501-Q1. Likewise, the output driver supports
configuration of De-Emphasis and Output Swing (pins
DE and OS). These settings allow the TUSB501-Q1
to be flexibly placed in the SuperSpeed USB path,
with optimal performance.
Over previous generations, the TUSB501-Q1 features
reduced power in all link states, a stronger OS option,
improved receiver equalization settings, and an
intelligent LFPS Controller. This controller senses the
low frequency signals and automatically disables
driver de-emphasis, for full USB 3.0 compliance.
The TUSB501-Q1 is packaged in a small 2 x 2 mm
QFN, and operates through an industrial temperature
range of –40°C to 105°C.
Device Information(1)
PART NUMBER
TUSB501-Q1
BODY SIZE (NOM)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simple Application
3 Description
The TUSB501-Q1 is a 3rd generation 3.3-V USB 3.0
single-channel redriver. When 5 Gbps SuperSpeed
USB signals travel across a PCB or cable, signal
integrity degrades due to loss and inter-symbol
interference. The TUSB501-Q1 recovers incoming
data by applying equalization that compensates
channel loss, and drives out signals with a high
differential voltage. This extends the possible channel
length, and enables systems to pass USB 3.0
compliance. The TUSB501-Q1 advanced state
machine makes it transparent to hosts and devices.
PACKAGE
WSON
USB Host
TUSB501-Q1
TUSB501-Q1
USB Connector
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB501-Q1
SLLSET3 – MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions......................
Thermal Information ..................................................
Power Supply Characteristics ..................................
DC Electrical Characteristics ....................................
AC Electrical Characteristics.....................................
Typical Characteristics ..............................................
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
11
11
12
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Application ............................................... 13
11 Power Supply Recommendations ..................... 14
12 Layout................................................................... 15
12.1 Layout Guidelines ................................................. 15
12.2 Layout Example .................................................... 16
13 Device and Documentation Support ................. 17
13.1
13.2
13.3
13.4
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
2
DATE
REVISION
NOTES
April 2016
*
Initial release.
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5 Device Comparison Table
USB3.0 Re-drivers (5 Gbps)
FEATURE
TUSB501-Q1
TUSB551
SN65LVPE502A
SN65LVPE512
Package
8 Pin WSON
12 Pin X2QFN
24 Pin VQFN
24 Pin WQFN
Package Size
2 mm x 2 mm
1.6 mm x 1.6 mm
3 mm x 3 mm, 4 mm x 4
mm
3 mm x 3 mm
Package Pitch
0.5 mm
0.4 mm
0.4 mm, 0.5 mm
0.4 mm
1
1
2
2
Active Power (Typical)
126 mW
< 130 mW
315 mW
315 mW
U2/U3
20 mW
< 22 mW
70 mW
70 mW
4 mW (NC)
< 8 mW (NC)
3.6 µW (Sleep)
3.6 µW (Sleep)
Channels
Low Power
EQ Settings (dB)
ESD Protection
Power Supply
3, 6, 9
3, 6, 9
0, 7, 15
0, 7, 15
5 kV HBM
2 kV HBM
5 kV HBM
5 kV HBM
3.3 VDC
1.8 VDC
3.3 VDC
3.3 VDC
6 Pin Configuration and Functions
DRF Package
8-Pin (WSON)
(Top View)
VCC
1
8
DE
RXP
2
7
TXP
GND
RXN
3
6
TXN
OS
4
5
EQ
Pin Functions
PIN
NAME
NO.
RXP
2
RXN
3
TXN
6
TXP
7
EQ
5
DE
OS
8
TYPE
DESCRIPTION
Differential input pair for 5 Gbps SuperSpeed USB signals.
Differential I/O
Differential output pair for 5 Gbps SuperSpeed USB signals.
Sets the receiver equalizer gain. 3-state input with integrated pull-up and pulldown resistors.
CMOS Input
Sets the output swing (differential voltage amplitude). 2-state input with an
integrated pull-down resistor.
4
VCC
1
GND
Thermal Pad
Sets the output de-emphasis gain. 3-state input with integrated pull-up and pulldown resistors.
Power
3.3-V power supply
Reference ground
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SLLSET3 – MAY 2016
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7 Specifications
7.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
VCC
–0.5
4
V
Differential I/O
–0.5
4
V
CMOS inputs
–0.5
VCC + 0.5
V
Storage temperature, TSTG
–65
150
°C
Maximum junction temperature, TJ
-40
125
°C
Supply voltage range
(2)
Voltage range at any input or output
terminal
(1)
(2)
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±5000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Main power supply
TA
Operating free-air temperature
CAC
AC coupling capacitor
MIN
NOM
MAX
3
3.3
3.6
V
105
°C
200
nF
–40
75
100
UNIT
7.4 Thermal Information
THERMAL METRIC (1)
TUSB501-Q1
DRF (WSON)
UNITS
RθJA
Junction-to-ambient thermal resistance
105.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
47.5
°C/W
RθJB
Junction-to-board thermal resistance
70.9
°C/W
ψJT
Junction-to-top characterization parameter
10.0
°C/W
ψJB
Junction-to-board characterization parameter
70.9
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
51.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5
SLLSET3 – MAY 2016
Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC-ACTIVE
Average active current
TEST CONDITIONS
MIN
TYP (1)
MAX (2)
UNIT
Link in U0 with SuperSpeed USB
data transmission, OS = Low
38.1
Link in U0 with SuperSpeed USB
data transmission, OS = High
43.8
29.8
mA
mA
65
ICC-IDLE
Average current in idle state
Link has some activity, not in U0,
OS = Low
ICC-U2U3
Average current in U2/U3
Link in U2 or U3
6.1
mA
ICC-NC
Average current with no connection
No SuperSpeed USB device is
connected to TXP, TXN
1.3
mA
PD
Power Dissipation in U0
OS = Low
126
OS = High
145
234
TYP
MAX
(1)
(2)
mW
TYP values use VCC = 3.3 V, TA = 25°C.
MAX values use VCC = 3.6 V, TA = –40°C.
7.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
3-State CMOS Inputs (EQ, DE)
VIH
High-level input voltage
VIM
Mid-level input voltage
VIL
Low-level input voltage
VF
Floating voltage
RPU
2.8
V
VCC / 2
V
0.6
VIN = High impedance
V
VCC / 2
V
Internal pull-up resistance
190
kΩ
RPD
Internal pull-down resistance
190
kΩ
IIH
High-level input current
VIN = 3.6 V
IIL
Low-level input current
VIN = GND, VCC = 3.6 V
36
-36
µA
µA
2-State CMOS Input (OS)
VIH
High-level input voltage
VIL
Low-level input voltage
2
VF
Floating voltage
RPD
Internal pull-down resistance
IIH
High-level input current
VIN = 3.6 V
IIL
Low-level input current
VIN = GND
V
0.5
VIN = High impedance
GND
V
270
kΩ
26
-1
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V
µA
µA
5
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SLLSET3 – MAY 2016
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7.7 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
AC-coupled differential peak-to-peak
signal
100
TYP
MAX
UNIT
1200
mVpp
Differential Receiver (RXP, RXN)
VDIFF-pp
Input differential voltage swing
VCM-RX
Common-mode voltage bias in the
receiver (DC)
ZRX-DIFF
Differential input impedance (DC)
Present after a SuperSpeed USB
device is detected on TXP/TXN
72
91
120
Ω
ZRX-CM
Common-mode input impedance
(DC)
Present after a SuperSpeed USB
device is detected on TXP, TXN
18
22.8
30
Ω
ZRX-HIGH-
Common-mode input impedance
with termination disabled (DC)
Present when no SuperSpeed USB
device is detected on TXP, TXN.
Measured over the range of 0-500
mV with respect to GND.
25
35
Low Frequency Periodic Signaling
(LFPS) Detect Threshold
Below the minimum is squelched
IMP-DC-POS
VRX-LFPSDET-DIFF-pp
3.3
100
V
kΩ
300
mVpp
Differential Transmitter (TXP, TXN)
VTX-DIFF-PP
Transmitter differential voltage swing OS = Low, No load
(transition-bit)
OS = High, No load
VTX-DE-
Transmitter de-emphasis
DE = Floating, OS = Low
CTX
TX input capacitance to GND
At 2.5 GHz
ZTX-DIFF
Differential impedance of the driver
ZTX-CM
Common-mode impedance of the
driver
Measured with respect to AC ground
over 0-500 mV
ITX-SC
TX short circuit current
TX ± shorted to GND
VCM-TX
Common-mode voltage bias in the
transmitter (DC)
VCM-TX-AC
AC common-mode voltage swing in
active mode
Within U0 and within LFPS
VTX-IDLE-
Differential voltage swing during
electrical idle
Tested with a high-pass filter
Absolute delta of DC CM voltage
during active and idle states
Restrict the test condition to meet
100 mV
DC electrical idle differential output
voltage
Voltage must be low pass filtered to
remove any AC component
930
mVpp
1300
-3.5
dB
RATIO
DIFF -AC-pp
VTX-CMDeltaU1-U0
VTX-idle-diffDC
1.25
75
93
18.75
1.2
0
0
pF
125
Ω
31.25
Ω
60
mA
2.5
V
100
mVpp
10
mVpp
100
mV
12
mV
Differential Transmitter (TXP, TXN)
tR, tF
Output rise, fall time
see Figure 6
20%-80% of differential voltage
measured 1 inch from the output pin
tRF-MM
Output Rise, Fall time mismatch
20%-80% of differential voltage
measured 1 inch from the output pin
tdiff-LH,
tdiff-HL
Differential propagation delay
see Figure 4
De-emphasis = -3.5 dB propagation
delay between 50% level at input
and output
tidleEntry,
tidleExit
Idle entry and exit times
see Figure 5
6
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80
ps
20
ps
290
ps
3.6
ns
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AC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Timing
tREADY
Time from power applied until RX
termination
Apply 0 V to VCC, connect
SuperSpeed USB termination to
TX±, apply 3.3 V to VCC, and
measure when ZRX-DIFF is enabled.
9
ms
Jitter
(1) (2)
TJTX-EYE
Total jitter
DJTX
Deterministic jitter
RJTX
(1)
(2)
(3)
(4)
Random jitter
(2)
(2) (4)
EQ = Floating, OS = High,
DE = High
See Figure 3.
0.213
UI
(3)
0.197
UI
(3)
0.016
UI
(3)
Includes RJ at 10-12.
Measured at the ends of reference channel in Figure 3 with K28.5 pattern, VID = 1000 mVpp, 5 Gbps, -3.5 dB de-emphasis from source.
UI = 200 ps.
Rj calculated as 14.069 times the RMS random jitter for 10-12 BER.
7.8 Typical Characteristics
TA = 25°C
TA = 25°C
EQ = NC
Figure 1. Input for Typical Output Measurement
at TUSB501-Q1
DE = HIGH
OS = HIGH
Figure 2. Typical Output Eye for Jitter Measurement Setup
in Figure 3
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8 Parameter Measurement Information
Jitter
Measurement
A
TUSB501-Q1
AWG
Up to3m
(30AWG)
24"
4"
1"-6"
Figure 3. Jitter Measurement Setup
spacer
IN
Tdiff_HL
Tdiff_LH
OUT
Figure 4. Propagation Delay
IN+
Vcm
VRX-LFPS-DET-DIFF-pp
INtidleExit
t idleEntry
OUT+
Vcm
OUT-
Figure 5. Electrical Idle Mode Exit and Entry Delay
spacer
8
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Parameter Measurement Information (continued)
80%
20%
tr
tf
Figure 6. Output Rise and Fall Times
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9 Detailed Description
9.1 Overview
When 5 Gbps SuperSpeed USB signals travel across a PCB or cable, signal integrity degrades due to loss and
inter-symbol interference. The TUSB501-Q1 recovers incoming data by applying equalization that compensates
for channel loss, and drives out signals with a high differential voltage. This extends the possible channel length,
and enables systems to pass USB 3.0 compliance.
The TUSB501-Q1 advanced state machine makes it transparent to hosts and devices. After power up, the
TUSB501-Q1 periodically performs receiver detection on the TX pair. If it detects a SuperSpeed USB receiver,
the RX termination is enabled, and the TUSB501-Q1 is ready to re-drive.
The device aggressive Low-Power Architecture operates at a 3.3-V power supply and achieves enhanced
performance, as lower as 3 mW with no connection and 126 mW in active state. The receiver equalizer has three
gain settings that are controlled by terminal EQ: 3 dB, 6 dB, and 9 dB. The equalization should be set based on
amount of insertion loss in the channel before the TUSB501-Q1. Likewise, the output driver supports
configuration of De-Emphasis and Output Swing (terminals DE and OS). The automatic LFPS De-Emphasis
control further enables the system to be USB3.0 compliant. The TUSB501-Q1 operates over the industrial
temperature range of -40ºC to 85ºC in a small 2 x 2 mm WSON package.
Table 1. Control Pin Effects (Typical Values)
PIN
DESCRIPTION
LOGIC STATE
GAIN
Low
3 dB
EQ
Equalization Amount
Floating
6 dB
High
9 dB
DESCRIPTION
LOGIC STATE
OS
Output Swing
Amplitude
Low
930 mVpp
High
1300 mVpp
PIN
DESCRIPTION
LOGIC STATE
DE
(1)
10
OUTPUT DIFFERENTIAL VOLTAGE
FOR THE TRANSITION BIT
PIN
De-Emphasis
Amount
DE-EMPHASIS RATIO
(1)
FOR OS = LOW
FOR OS = HIGH
Low
0 dB
–2.6 dB
Floating
–3.5 dB
–5.9 dB
High
–6.2 dB
–8.3 dB
Typical values
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9.2 Functional Block Diagram
EQ
DE
OS
Driver
Detect
Receiver/
Equalizer
Termination
TX+
Termination
RX+
TX-
RX-
VCC
GND
3rd Generation
State Machine
LFPS
Controller
Copyright
Copyright©
©2016,
2016,Texas
TexasInstruments
InstrumentsIncorporated
Incorporated
9.3 Feature Description
9.3.1 Receiver Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TUSB501-Q1. The receiver overcomes these losses by attenuating the low
frequency components of the signals with respect to the high frequency components. The proper gain setting
should be selected to match the channel insertion loss before the input of the TUSB501-Q1.
9.3.2 De-Emphasis Control and Output Swing
The differential driver output provides selectable de-emphasis and output swing control in order to achieve
USB3.0 compliance. The TUSB501-Q1 offers a unique way to adjust output de-emphasis and transmitter swing
based on the OS and DE terminals. The level of de-emphasis required in the system depends on the channel
length after the output of the re-driver.
Transition
bit
Transition
bit
Consecutive bits
Consecutive bits
DE = 0dB
415mV
DE = -3.5dB
DE = -6.2dB
VTX-DIFF- PP
0V
DE = -6.2dB
DE = -3.5dB
DE = 0dB
-415mV
0ps
200ps
400ps
600ps
800ps
1000ps
1200ps
Figure 7. Transmitter Differential Voltage, OS = L
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Feature Description (continued)
9.3.3 Automatic LFPS Detection
The TUSB501-Q1 features an intelligent low frequency periodic signaling (LFPS) controller. The controller
senses the low frequency signals and automatically disables the driver de-emphasis, for full USB3.0 compliance.
9.3.4 Automatic Power Management
The TUSB501-Q1 deploys RX detect, LFPS signal detection and signal monitoring to implement an automatic
power management scheme to provide active, U2/U3 and disconnect modes. The automatic power management
is driven by an advanced state machine, which is implemented to manage the device such that the re-driver
operates smoothly in the links.
9.4 Device Functional Modes
9.4.1 Disconnect Mode
The Disconnect mode is the lowest power state of the TUSB501-Q1. In this state, the TUSB501-Q1 periodically
checks for far-end receiver termination on both TX. Upon detection of the far-end receiver’s termination on both
ports, the TUSB501-Q1 will transition to U0 mode.
9.4.2 U Modes
9.4.2.1 U0 Mode
The U0 mode is the highest power state of the TUSB501-Q1. Anytime super-speed traffic is being received,
theTUSB501-Q1 remains in this mode.
9.4.2.2 U2/U3 Mode
Next to the disconnect mode, the U2/U3 mode is next lowest power state. While in this mode, the TUSB501-Q1
periodically performs far-end receiver detection.
12
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
One example of the TUSB501-Q1 used in a Host application on transmit and receive channels is shown in
Figure 8. The re-driver is needed on the transmit path to pass transmitter compliance due to loss between the
Host and connector. The re-driver uses the equalization to recover the insertion loss and re-drive the signal with
boosted swing down the remaining channel, through the USB3.0 cable, and into the device PCB. Additionally,
the TUSB501-Q1 is needed on the receive channel for the Host to pass receiver jitter tolerance. The re-driver
recovers the loss from the Device PCB, connector, and USB 3.0 cable and re-drives the signal going into the
Host receiver. The equalization, output swing, and de-emphasis settings are dependent upon the type of USB3.0
signal path and end application.
10.2 Typical Application
U2
1
R11
4.98K
5
DE1_PU
8
VDD33
U4B
OS
OS
EQ
EQ
DE
DE
TUSB501-Q1
4
1
R12
4.98K
5
8
VBUS
2
2
U3B
4
DE2_PU
1
VDD33
USB2.0_D_N
TUSB501-Q1
2
3
5
GND
EN
N/C
4
4
1
VOUT
1
VIN
C6
1.0uF
Device TX
Host RX
C7
10uF
2
2
2
2
1
1
2
7
6
HOST_USB3.0_TX_P 1
2
GND
2
5
USB3_RX_N
DEVICE_USB3.0_RX_P
1
C9
0.01uF
2
1
C8
0.1uF
2
2
9
1
VCC_TUSB501-Q1
TXN RXN
3
6
7
Host TX
C10
1.0uF
USB3_RX_P
TUSB501-Q1
C15 0.1uF
VCC
TXP RXP
DEVICE_USB3.0_RX_N
C14 0.1uF
U3C
GND_PAD
USB2_D_P
U3A
HOST_USB3.0_TX_N 1
LP5907
1
3
VDD33
U5
C5
1.0uF
USB2_D_N
USB High Speed Line
USB2.0_D_P
VBUS
VBUS_PWR
Device RX
GND_DRAIN
U4A
TUSB501-Q1
HOST_USB3.0_RX_N
3
HOST_USB3.0_RX_P
2
RXN TXN
6
1
2
DEVICE_USB3.0_TX_N8
USB3_TX_N
C1 0.1uF
RXP TXP
TUSB501-Q1
7
1
2
DEVICE_USB3.0_TX_P9
10
SHIELD1
1
C12
0.01uF
2
1
C11
0.1uF
2
9
VCC_TUSB501-Q1
2
GND_PAD
1
1
U4C
VCC
USB3_TX_P
C2 0.1uF
11
C13
1.0uF
SHIELD2
TUSB501-Q1
USB3_STANDARD_TYPE-A_RECEPTACLE
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Application Schematic
10.2.1 Design Requirements
For this design example, use the parameter shown in Table 2.
Table 2. Design Parameters
PARAMETER
VALUE
VCC
3.3 V
Supply nominal current
250 mA
Operating free-air temperature
TA = 25°C
CAC AC coupling capacitor
100 nF
Pull-up resistors
4.98 kΩ
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10.2.2 Detailed Design Procedure
To
•
•
•
begin the design process, determine the following:
Equalization (EQ) setting
De-Emphasis (DE) setting
Output Swing Amplitude (OS) setting
The equalization should be set based on the insertion loss in the pre-channel (channel before the TUSB501-Q1
device). The input voltage to the device is able to have a large range because of the receiver sensitivity and the
available EQ settings. The EQ terminal can be pulled high through a resistor to VCC, low through a resistor to
ground, or left floating. The application schematic above shows the implementation.
The De-Emphasis setting should be set based on the length and characteristics of the post channel (channel
after the TUSB501-Q1 device). Output de-emphasis can be tailored using the DE terminal. This terminal should
be pulled high through a resistor to VCC, low through a resistor to ground, or left floating. Figure 8 shows the
implementation. The output swing setting can also be configured based on the amplitude needed to pass the
compliance test. This setting will also be based on the length of interconnect or cable the TUSB501-Q1 is driving.
This terminal should be pulled low through a resistor to ground or left floating. Figure 8 shows the
implementation.
10.2.3 Application Curves
DE = 0 dB
EQ = 6 dB
8 Input Trace
DE = 0 dB
Figure 9. Eye Diagram
EQ = 6 dB
8 Input Trace
Figure 10. SigTest CP1 Eye Diagram
11 Power Supply Recommendations
This device is designed to operate with a 3.3-V supply. If using a higher voltage system power supply such as
VBUS, a voltage regulator can be used to step down to 3.3 V. Decoupling capacitors may be used to reduce
noise and improve power supply integrity.
14
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12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The 100-nF capacitors on the TXP and SSTXN nets should be placed close to the USB connector (Type A,
Type B, and so forth).
The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB
connector.
Place voltage regulators as far away as possible from the differential pairs.
In general, the large bulk capacitors associated with each power rail should be placed as close as possible to
the voltage regulators.
It is recommended that small decoupling capacitors for the 1.8-V power rail be placed close to the TUSB501Q1 as shown in Figure 11.
The SuperSpeed differential pair traces for RXP/N and TXP/N must be designed with a characteristic
impedance of 90 Ω ±10%. The PCB stack-up and materials determines the width and spacing needed for a
characteristic impedance of 90 Ω.
The SuperSpeed differential pair traces should be routed parallel to each other as much as possible. It is
recommended the traces be symmetrical.
In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each
pair should be separated by at least 5 times the signal trace width. Separating with ground also helps
minimize cross talk.
Route all differential pairs on the same layer adjacent to a solid ground plane.
Do not route differential pairs over any plane split.
Adding test points will cause impedance discontinuity and will therefore negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes stub on the differential pair.
Avoid 90 degree turns in traces. The use of bends in differential traces should be kept to a minimum. When
bends are used, the number of left and right bends should be as equal as possible and the angle of the bend
should be ≥ 135 degrees. This will minimize any length mismatch caused by the bends and therefore
minimize the impact bends have on EMI.
Match the etch lengths of the differential pair traces. There should be less than 5 mils difference between a
SS differential pair signal and its complement. The USB 2.0 differential pairs should not exceed 50 mils
relative trace length difference.
The etch lengths of the differential pair groups do not need to match (that is, the length of the RXP/N pair to
that of the TXP/N pair), but all trace lengths should be minimized.
Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure
that the same via type and placement are used for both signals in a pair. Any vias used should be placed as
close as possible to the TUSB501-Q1 device.
To ease routing, the polarity of the SS differential pairs can be swapped. This means that TXP can be routed
to TXN or RXN can be routed to RXP.
Do not place power fuses across the differential pair traces.
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12.2 Layout Example
Figure 11. Example Layout
16
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TUSB501TDRFRQ1
ACTIVE
WSON
DRF
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
501Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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