TVP5147M1IPFPR

TVP5147M1 NTSC/PAL/SECAM 2 11-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, and 5-Line Comb Filter Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES140G July 2005 – Revised February 2012 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Contents 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2 Functional Description 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3 ........................................................................................................................ 8 Features ...................................................................................................................... 8 Description ................................................................................................................. 10 Applications ................................................................................................................ 11 Related Products .......................................................................................................... 11 Ordering Information ...................................................................................................... 11 Functional Block Diagram ................................................................................................ 12 Terminal Assignments .................................................................................................... 13 Terminal Functions ........................................................................................................ 14 ....................................................................................................... 16 Analog Processing and A/D Converters ................................................................................ 2.1.1 Video Input Switch Control .................................................................................... 2.1.2 Analog Input Clamping ......................................................................................... 2.1.3 Automatic Gain Control ........................................................................................ 2.1.4 Analog Video Output ........................................................................................... 2.1.5 A/D Converters .................................................................................................. Digital Video Processing .................................................................................................. 2.2.1 2x Decimation Filter ............................................................................................ 2.2.2 Composite Processor .......................................................................................... 2.2.2.1 Color Low-Pass Filter .............................................................................. 2.2.2.2 Y/C Separation ..................................................................................... 2.2.3 Luminance Processing ......................................................................................... 2.2.4 Color Transient Improvement ................................................................................. Clock Circuits .............................................................................................................. Real-Time Control (RTC) ................................................................................................. Output Formatter .......................................................................................................... 2.5.1 Separate Syncs ................................................................................................. 2.5.2 Embedded Syncs ............................................................................................... I2C Host Interface .......................................................................................................... 2.6.1 Reset and I2C Bus Address Selection ....................................................................... 2.6.2 I2C Operation .................................................................................................... 2.6.3 VBUS Access ................................................................................................... VBI Data Processor ....................................................................................................... 2.7.1 VBI FIFO and Ancillary Data in Video Stream .............................................................. 2.7.2 VBI Raw Data Output .......................................................................................... Reset and Initialization .................................................................................................... Adjusting External Syncs ................................................................................................. Internal Control Registers ................................................................................................ Register Definitions ....................................................................................................... VBUS Register Definitions ............................................................................................... Electrical Specifications 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 16 17 17 17 17 18 18 18 18 20 21 22 22 23 23 24 25 30 30 31 31 32 33 34 35 35 36 37 41 86 ..................................................................................................... 93 Absolute Maximum Ratings .............................................................................................. Recommended Operating Conditions .................................................................................. Crystal Specifications ..................................................................................................... Electrical Characteristics ................................................................................................. DC Electrical Characteristics ............................................................................................. Analog Processing and A/D Converters ................................................................................ Clocks, Video Data, Sync Timing ....................................................................................... I2C Host Port Timing ...................................................................................................... Thermal Specifications .................................................................................................... 4 Example Register Settings 2 Contents 93 94 94 95 95 95 96 96 97 .................................................................................................. 98 Copyright © 2005–2012, Texas Instruments Incorporated TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 4.1 Example 1 .................................................................................................................. 98 4.1.1 Assumptions ..................................................................................................... 98 4.1.2 Recommended Settings ....................................................................................... 98 Example 2 .................................................................................................................. 99 4.2.1 Assumptions ..................................................................................................... 99 4.2.2 Recommended Settings ....................................................................................... 99 Example 3 ................................................................................................................. 100 4.3.1 Assumptions ................................................................................................... 100 4.3.2 Recommended Settings ...................................................................................... 100 4.2 4.3 5 Application Information 5.1 5.2 .................................................................................................... 101 Application Example ..................................................................................................... 101 Designing With PowerPAD™ Devices ................................................................................ 102 Revision History ....................................................................................................................... 103 Copyright © 2005–2012, Texas Instruments Incorporated Contents 3 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com List of Figures 1-1 Functional Block Diagram ....................................................................................................... 13 1-2 Terminal Assignments Diagram ................................................................................................ 13 2-1 Analog Processors and A/D Converters 2-2 Digital Video Processing Block Diagram ...................................................................................... 18 2-3 Composite and S-Video Processing Block Diagram ......................................................................... 19 2-8 Luminance Edge-Enhancer Peaking Block Diagram ........................................................................ 22 2-9 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling ............................................................ 22 2-10 Reference Clock Configurations................................................................................................ 23 2-11 ....................................................................................................................... Vertical Synchronization Signals for 525-Line System ...................................................................... Vertical Synchronization Signals for 625-Line System ...................................................................... Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode .................................................................. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode .................................................................. VSYNC Position With Respect to HSYNC .................................................................................... VBUS Access ..................................................................................................................... Reset Timing ...................................................................................................................... Teletext Filter Function .......................................................................................................... Clocks, Video Data, and Sync Timing ......................................................................................... I2C Host Port Timing ............................................................................................................. Example Application Circuit ................................................................................................... 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 3-1 3-2 5-1 4 RTC Timing List of Figures ...................................................................................... 16 24 27 28 29 30 30 33 36 75 96 96 101 Copyright © 2005–2012, Texas Instruments Incorporated TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 List of Tables 1-1 Terminal Functions ............................................................................................................... 14 2-1 Output Format .................................................................................................................... 24 2-2 Summary of Line Frequencies, Data Rates, and Pixel/Line Counts ....................................................... 25 2-3 EAV and SAV Sequence ........................................................................................................ 30 2-4 I2C Host Interface Terminal Description ....................................................................................... 31 2-5 I2C Address Selection 31 2-6 Supported VBI System 33 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35 2-36 2-37 2-38 2-39 2-40 2-41 2-42 2-43 2-44 2-45 2-46 ........................................................................................................... .......................................................................................................... Ancillary Data Format and Sequence ......................................................................................... VBI Raw Data Output Format .................................................................................................. Reset Sequence .................................................................................................................. I2C Register Summary ........................................................................................................... VBUS Register Summary ....................................................................................................... Input Select Register ............................................................................................................ Analog Channel and Video Mode Selection .................................................................................. AFE Gain Control Register ..................................................................................................... Video Standard Select Register ............................................................................................... Operation Mode Control Register ............................................................................................. Autoswitch Mask Register ...................................................................................................... Color Killer Register ............................................................................................................. Luminance Processing Control 1 Register ................................................................................... Luminance Processing Control 2 Register ................................................................................... Luminance Processing Control 3 Register ................................................................................... Luminance Brightness Register ............................................................................................... Luminance Contrast Register .................................................................................................. Chrominance Saturation Register ............................................................................................. Chroma Hue Register ........................................................................................................... Chrominance Processing Control 1 Register ................................................................................ Chrominance Processing Control 2 Register ................................................................................ R/Pr Gain (Color Saturation) Register ........................................................................................ G/Y Gain (Contrast) Register .................................................................................................. B/Pb Gain (Color Saturation) Register ........................................................................................ G/Y Offset Register ............................................................................................................. AVID Start Pixel Register ....................................................................................................... AVID Stop Pixel Register ....................................................................................................... HSYNC Start Pixel Register .................................................................................................... HSYNC Stop Pixel Register .................................................................................................... VSYNC Start Line Register .................................................................................................... VSYNC Stop Line Register ..................................................................................................... VBLK Start Line Register ....................................................................................................... VBLK Stop Line Register ....................................................................................................... Embedded Sync Offset Control 1 Register .................................................................................. Embedded Sync Offset Control 2 Register .................................................................................. CTI Delay Register .............................................................................................................. CTI Control Register ............................................................................................................ Brightness and Contrast Range Extender Register ......................................................................... Sync Control Register ........................................................................................................... Output Formatter Control 1 Register .......................................................................................... Copyright © 2005–2012, Texas Instruments Incorporated List of Tables 34 35 35 37 40 41 41 42 42 43 43 44 44 45 45 45 46 46 46 47 47 47 48 48 48 49 49 49 50 50 50 50 51 51 51 52 52 52 53 53 5 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com .......................................................................................... .......................................................................................... Output Formatter Control 4 Register .......................................................................................... Output Formatter Control 5 Register .......................................................................................... Output Formatter Control 6 Register .......................................................................................... Clear Lost Lock Detect Register ............................................................................................... Status 1 Register ................................................................................................................ Status 2 Register ................................................................................................................ AGC Gain Status Register ..................................................................................................... Video Standard Status Register ............................................................................................... GPIO Input 1 Register .......................................................................................................... GPIO Input 2 Register .......................................................................................................... AFE Coarse Gain for CH 1 Register .......................................................................................... AFE Coarse Gain for CH 2 Register .......................................................................................... AFE Coarse Gain for CH 3 Register .......................................................................................... AFE Coarse Gain for CH 4 Register .......................................................................................... AFE Fine Gain for Pb Register ................................................................................................ AFE Fine Gain for Y_Chroma Register ....................................................................................... AFE Fine Gain for Pr Register ................................................................................................. AFE Fine Gain for CVBS_Luma Register .................................................................................... Field ID Control Register ....................................................................................................... F-Bit and V-Bit Decode Control 1 Register ................................................................................... Back-End AGC Control Register .............................................................................................. AGC Decrement Speed Register .............................................................................................. ROM Version Register .......................................................................................................... RAM Version MSB Register .................................................................................................... AGC White Peak Processing Register ....................................................................................... F-Bit and V-Bit Control 2 Register ............................................................................................. VCR Trick Mode Control Register ............................................................................................. Horizontal Shake Increment Register ......................................................................................... AGC Increment Speed Register ............................................................................................... AGC Increment Delay Register ................................................................................................ Analog Output Control 1 Register ............................................................................................. Chip ID MSB Register .......................................................................................................... Chip ID LSB Register ........................................................................................................... RAM Version LSB Register .................................................................................................... Color PLL Speed Control Register ............................................................................................ Status Request Register ........................................................................................................ Vertical Line Count Register ................................................................................................... AGC Decrement Delay Register ............................................................................................... VDP TTX Filter and Mask Register ........................................................................................... VDP TTX Filter Control Register .............................................................................................. VDP FIFO Word Count Register .............................................................................................. VDP FIFO Interrupt Threshold Register ...................................................................................... VDP FIFO Reset Register ...................................................................................................... VDP FIFO Output Control Register ........................................................................................... VDP Line Number Interrupt Register ......................................................................................... VDP Pixel Alignment Register ................................................................................................. 2-47 Output Formatter Control 2 Register 54 2-48 Output Formatter Control 3 Register 54 2-49 2-50 2-51 2-52 2-53 2-54 2-55 2-56 2-57 2-58 2-59 2-60 2-61 2-62 2-63 2-64 2-65 2-66 2-67 2-68 2-69 2-70 2-71 2-72 2-73 2-74 2-75 2-76 2-77 2-78 2-79 2-80 2-81 2-82 2-83 2-84 2-85 2-86 2-87 2-88 2-89 2-90 2-91 2-92 2-93 2-94 6 List of Tables 55 56 57 57 58 59 59 60 60 61 61 62 62 63 63 64 64 64 65 66 67 67 67 67 68 69 69 70 70 70 70 71 71 71 71 71 72 72 73 74 75 76 76 76 76 77 Copyright © 2005–2012, Texas Instruments Incorporated TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 ........................................................................................................ ........................................................................................................ VDP Global Line Mode Register ............................................................................................... VDP Full Field Enable Register ................................................................................................ VDP Full Field Mode Register ................................................................................................. VBUS Data Access With No VBUS Address Increment Register ......................................................... VBUS Data Access With VBUS Address Increment Register ............................................................. FIFO Read Data Register ...................................................................................................... VBUS Address Register ........................................................................................................ Interrupt Raw Status 0 Register ............................................................................................... Interrupt Raw Status 1 Register ............................................................................................... Interrupt Status 0 Register ..................................................................................................... Interrupt Status 1 Register ..................................................................................................... Interrupt Mask 0 Register ....................................................................................................... Interrupt Mask 1 Register ....................................................................................................... Interrupt Clear 0 Register ....................................................................................................... Interrupt Clear 1 Register ....................................................................................................... VDP Closed Caption Data Register ........................................................................................... VDP WSS Data Register ....................................................................................................... VDP VITC Data Register ....................................................................................................... VDP V-Chip TV Rating Block 1 Register ..................................................................................... VDP V-Chip TV Rating Block 2 Register ..................................................................................... VDP V-Chip TV Rating Block 3 Register ..................................................................................... VDP V-Chip MPAA Rating Data Register .................................................................................... VDP General Line Mode and Line Address Register ....................................................................... VDP VPS/Gemstar Data Register ............................................................................................. Analog Output Control 2 Register ............................................................................................. Interrupt Configuration Register ............................................................................................... 2-95 VDP Line Start Register 77 2-96 VDP Line Stop Register 77 2-97 2-98 2-99 2-100 2-101 2-102 2-103 2-104 2-105 2-106 2-107 2-108 2-109 2-110 2-111 2-112 2-113 2-114 2-115 2-116 2-117 2-118 2-119 2-120 2-121 2-122 Copyright © 2005–2012, Texas Instruments Incorporated List of Tables 77 78 78 78 78 78 79 79 80 81 82 83 84 85 86 86 87 87 88 88 88 89 90 91 92 92 7 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com NTSC/PAL/SECAM 2 11-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, and 5-Line Comb Filter Check for Samples: TVP5147M1 1 Introduction 1.1 Features 12345 • Two 30-MSPS 11-bit A/D channels with programmable gain control • Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60), and SECAM (B, D, G, K, K1, L) CVBS, and S-video • Supports analog component YPbPr video format with embedded sync • Ten analog video input terminals for multisource connection • Supports analog video output • User-programmable video output formats – 10-bit ITU-R BT.656 4:2:2 YCbCr with embedded syncs – 10-bit 4:2:2 YCbCr with separate syncs – 20-bit 4:2:2 YCbCr with separate syncs – 2x sampled raw VBI data in active video during a vertical blanking period – Sliced VBI data during a vertical blanking period or active video period (full field mode) • HSYNC/VSYNC outputs with programmable position, polarity, width, and field ID (FID) output • Composite and S-video processing – Adaptive 2-D 5-line adaptive comb filter for composite video inputs; chroma-trap available – Automatic video standard detection (NTSC/PAL/SECAM) and switching – Luma-peaking with programmable gain – Patented chroma transient improvement (CTI) – Patented architecture for locking to weak, noisy, or unstable signals – Single 14.31818-MHz reference crystal for all standards – Line-locked internal pixel sampling clock generation with horizontal and vertical lock signal outputs – Genlock output RTC format for downstream video encoder synchronization • Certified Macrovision™ copy protection detection • Available in commercial (0°C to 70°C) and industrial (−40°C to 85°C) temperature ranges • Qualified for Automotive Applications (AECQ100 Rev G − TVP5147M1IPFPQ1 or TVP5147M1IPFPRQ1) • VBI data processor – Teletext (NABTS, WST) – CC and extended data service (EDS) – Wide screen signaling (WSS) – Copy generation management system (CGMS) – Video program system (VPS/PDC) – Vertical interval time code (VITC) – Gemstar™ 1×/2× mode – V-Chip decoding – Register readback of CC, WSS (CGMS), VPS/PDC, VITC and Gemstar 1×/2× sliced data • I2C host port interface • Reduced power consumption: 1.8-V digital 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, DLP are trademarks of Texas Instruments. Gemstar is a trademark of Gemstar-TV Guide Intermational. Macrovision is a trademark of Macrovision Corporation. All other trademarks are the property of their respective owners. Copyright © 2005–2012, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 core, 3.3-V for digital I/O, and 1.8-V/3.3 V analog core with power-save and power-down modes • 80-terminal TQFP PowerPAD™ package Introduction Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 9 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 1.2 www.ti.com Description The TVP5147M1 device is a high-quality, single-chip digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video. The TVP5147M1 decoder supports the analog-to-digital (A/D) conversion of component YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-video into component YCbCr. This decoder includes two 11-bit 30-MSPS A/D converters (ADCs). Preceding each ADC in the device, the corresponding analog channel contains an analog circuit that clamps the input to a reference voltage and applies a programmable gain and offset. A total of ten video input terminals can be configured to a combination of YPbPr, CVBS, or S-video video inputs. Composite or S-video signals are sampled at 2× the ITU-R BT.601 clock frequency, line-locked alignment, and are then decimated to the 1× pixel rate. CVBS decoding uses five-line adaptive comb filtering for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter is also available. On CVBS and S-video inputs, the user can control video characteristics such as contrast, brightness, saturation, and hue via an I2C host port interface. Furthermore, luma peaking (sharpness) with programmable gain is included, as well as a patented chroma transient improvement (CTI) circuit. The following output formats can be selected: 20-bit 4:2:2 YCbCr or 10-bit 4:2:2 YCbCr. The TVP5147M1 decoder generates synchronization, blanking, field, active video window, horizontal and vertical syncs, clock, genlock (for downstream video encoder synchronization), host CPU interrupt and programmable logic I/O signals, in addition to digital video outputs. The TVP5147M1 decoder includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor (VDP) slices, parses, and performs error checking on teletext, closed caption (CC), and other VBI data. A built-in FIFO stores up to 11 lines of teletext data, and with proper host port synchronization, full-screen teletext retrieval is possible. The TVP5147M1 decoder can pass through the output formatter 2× sampled raw luma data for host-based VBI processing. The main blocks of the TVP5147M1 decoder include: • Robust sync detection for weak and noisy signals as well as VCR trick modes • Y/C separation by 2-D 5-line adaptive comb or chroma trap filter • Two 11-bit, 30-MSPS A/D converters with analog preprocessors [clamp and automatic gain control (AGC)] • Analog video output • Luminance processor • Chrominance processor • Clock/timing processor and power-down control • Software-controlled power-saving standby mode • Output formatter • I2C host port interface • VBI data processor • Macrovision™ copy protection detection circuit (Type 1, 2, 3, and separate color stripe detection) • 3.3-V tolerant digital I/O ports 10 Introduction Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 1.3 Applications • • • • • • • • • • 1.4 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 DLP™ projectors Digital TV LCD TV/monitors DVD recorders PVR PC video cards Video capture/video editing Video conferencing Automotive Industrial Related Products TVP5146M2 NTSC/PAL/SECAM 2 11-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr/RGB Inputs, and 5-Line Comb Filter TVP5150AM1 Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync Detector 1.5 Ordering Information TA 0°C to 70°C -40°C to 85°C (1) (2) (3) PACKAGED DEVICES (1) (2) 80-TERMINAL PLASTIC FLAT-PACK PowerPAD™ PACKAGE PACKAGE OPTION TVP5147M1PFP Tray TVP5147M1PFPR Tape and reel TVP5147M1IPFP Tray TVP5147M1IPFPR Tape and reel TVP5147M1IPFPQ1 (3) Tray TVP5147M1IPFPRQ1 (3) Tape and reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/package. AEC-Q100 Rev G Certified Introduction Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 11 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 1.6 www.ti.com Functional Block Diagram Copy Protection Detector VBI Data Processor CVBS/Y Analog Front End CVBS/ C/Pb VI_1_A VI_1_B Composite and S-V ideo Processor VI_1_C VI_2_A CVBS/ Y VI_2_B VI_2_C VI_3_A CVBS/ C/Pr Y/C Separation CVBS/Y 5-line Adaptive Comb C/CbCr Clamping AGC Y C Luma Processing Y[9:0] YCbCr Chroma Processing Output Formatter C[9:0] M U X 2 × 11-Bit ADC VI_3_B VI_3_C CVBS/Y VI_4_A GPIO GLCO SCL Host Interface HS/CS FID VS/VBLK AVID DATACLK PWDN RESETB XTAL2 XTAL1 Timing Processor With Sync Detector SDA Sampling Clock Figure 1-1. Functional Block Diagram 12 Introduction Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 1.7 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Terminal Assignments VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK/GPIO HS/CS/GPIO FID C_0/GPIO C_1 DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD PFP PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 C_6/GPIO C_7/GPIO C_8/GPIO C_9/GPIO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD NC NC VI_4_A NC NC AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB GPIO AVID/GPIO GLCO/I2CA IOVDD IOGND DATACLK VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF NC NC VI_3_A VI_3_B VI_3_C NC NC Figure 1-2. Terminal Assignments Diagram Introduction Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 13 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 1.8 www.ti.com Terminal Functions Table 1-1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION Analog Video VI_1_A 80 I/O VI_1_B 1 I VI_1_C 2 I VI_2_A 7 I VI_2_B 8 I VI_2_C 9 I VI_3_A 16 I VI_3_B 17 I VI_3_C 18 I VI_4_A 23 I DATACLK 40 O Line-locked data output clock XTAL1 74 I External clock reference input. It can be connected to an external oscillator with a 1.8-V compatible clock signal or a 14.31818-MHz crystal oscillator. XTAL2 75 O External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator. C_[9:0] 57, 58, 59, 60, 63, 64, 65, 66, 69, 70 I/O Digital video output of CbCr, C[9] is MSB and C[0] is LSB. C_0 and C_[9-2] can be used as programmable general purpose I/O. C_1 (pin 69) requires an external pulldown resistor and should not be used for general purpose I/0. For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected. Y[9:0] 43, 44, 45, 46, 47, 50, 51, 52, 53, 54 O Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB. For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected. VI_1_A: Analog video input for CVBS/Pb/C or analog video output (see Table 2-79) VI_1_x: Analog video input for CVBS/Pb/C VI_2_x: Analog video input for CVBS/Y VI_3_x: Analog video input for CVBS/Pr/C VI_4_A: Analog video input for CVBS/Y Up to ten composite, four S-video, and two composite or three component video inputs (or a combination thereof) can be supported. The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF. The possible input configurations are listed in the input select register at I2C subaddress 00h (see Table 2-12). Clock Signals Digital Video Miscellaneous Signals GPIO 35 I/O Programmable general-purpose I/O GLCO/I2CA 37 I/O Genlock control output (GLCO) uses real time control (RTC) format. During reset, this terminal is an input used to program the I2C address LSB. 30 O Interrupt request INTREQ 14, 15, 19, 20, 21, 22, 24, 25 NC Not connected. These terminals can be connected to power or ground (compatible with TVP5146 terminals), internally floating. PWDN 33 I Power down input: 1 = Power down 0 = Normal mode RESETB 34 I Reset input, active low (see Section 2.8) SCL 28 I I2C clock input SDA 29 I/O Host Interface I2C data bus Power Supplies AGND 26 Analog ground. Connect to analog ground. A18GND_REF 13 Analog 1.8-V return A18VDD_REF 12 Analog power for reference 1.8 V CH1_A18GND 79 Analog 1.8-V return CH2_A18GND 10 CH1_A18VDD 78 14 Analog power. Connect to 1.8 V. Introduction Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 1-1. Terminal Functions (continued) TERMINAL NAME NO. CH2_A18VDD 11 CH1_A33GND 3 CH2_A33GND 6 CH1_A33VDD 4 CH2_A33VDD 5 I/O DESCRIPTION Analog 3.3-V return Analog power. Connect to 3.3 V. DGND 27, 32, 42, 56, 68 Digital return DVDD 31, 41, 55, 67 Digital power. Connect to 1.8 V. IOGND 39, 49, 62 Digital power return IOVDD 38, 48, 61 Digital power. Connect to 3.3 V or less for reduced noise. PLL_A18GND 77 Analog power return PLL_A18VDD 76 Analog power. Connect to 1.8 V. Sync Signals HS/CS/GPIO 72 I/O Horizontal sync output or digital composite sync output Programmable general-purpose I/O VS/VBLK/GPIO 73 I/O Vertical sync output (for modes with dedicated VSYNC) or VBLK output Programmable general-purpose I/O FID 71 I/O Odd/even field indicator output. This terminal needs a pulldown resistor (see Figure 5-1). AVID/GPIO 36 I/O Active video indicator output Programmable general-purpose I/O Introduction Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 15 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2 Functional Description 2.1 Analog Processing and A/D Converters Figure 2-1 shows a functional diagram of the analog processors and A/D converters, which provide the analog interface to all video inputs. It accepts up to ten inputs and performs source selection, video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal. The TVP5147M1 supports one analog video output for the selected analog input video. I/O VI_1_A PGA M U X Analog Front End CVBS/ Pb/C VI_1_B VI_1_C VI_2_A CVBS/ Y VI_2_B VI_2_C M U CH1 A/D Clamp X M U PGA 11-Bit ADC CH2 A/D Clamp X PGA 11-Bit ADC Line-Locked Sampling Clock VI_3_A CVBS/ Pr/C VI_3_B VI_3_C CVBS/ Y M U X VI_4_A Clamp Clamp Figure 2-1. Analog Processors and A/D Converters 16 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 2.1.1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Video Input Switch Control The TVP5147M1 decoder has two analog channels that accept up to ten video inputs. The user can configure the internal analog video switches via the I2C interface. The ten analog video inputs can be used for different input configurations, some of which are: • Up to ten selectable individual composite video inputs • Up to four selectable S-video inputs • Up to three selectable analog YPbPr video inputs and one CVBS input • Up to two selectable analog YPbPr video inputs, one S-video input, and two CVBS inputs The input selection is performed by the input select register at I2C subaddress 00h (see Table 2-12). 2.1.2 Analog Input Clamping An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection between bottom and mid clamp is performed automatically by the TVP5147M1 decoder. 2.1.3 Automatic Gain Control The TVP5147M1 decoder uses two programmable gain amplifiers (PGAs), one per channel. The PGA can scale a signal with a voltage-input compliance of 0.5-VPP to 2.0-VPP to a full-scale 10-bit A/D output code range. A 4-bit code sets the coarse gain with individual adjustment per channel. Minimum gain corresponds to a code 0x0 (2.0-VPP full-scale input, -6-dB gain) while maximum gain corresponds to code 0xF (0.5 VPP full scale, +6-dB gain). The TVP5147M1 decoder also has 12-bit fine gain controls for each channel and applies independently to coarse gain controls. For composite video, the input video signal amplitude can vary significantly from the nominal level of 1 VPP. The TVP5147M1 decoder can adjust its PGA setting automatically: an automatic gain control (AGC) can be enabled and can adjust the signal amplitude such that the maximum range of the ADC is reached without clipping. Some nonstandard video signals contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts back gain to avoid clipping. If the AGC is on, then the TVP5147M1 decoder can read the gain currently being used. The TVP5147M1 AGC comprises the front-end AGC before Y/C separation and the back-end AGC after Y/C separation. The back-end AGC restores the optimum system gain whenever an amplitude reference such as the composite peak (which is only relevant before Y/C separation) forces the front-end AGC to set the gain too low. The front-end and back-end AGC algorithms can use up to four amplitude references: sync height, color burst amplitude, composite peak, and luma peak. The specific amplitude references being used by the front-end and back-end AGC algorithms can be independently controlled using the AGC white peak processing register located at subaddress 74h. The TVP5147M1 gain increment speed and gain increment delay can be controlled using the AGC increment speed register located at subaddress 78h and the AGC increment delay register located at subaddress 79h. 2.1.4 Analog Video Output One of the analog input signals is available at the analog video output terminal, which is shared with input selected by I2C registers. The signal at this terminal must be buffered by a source follower. The nominal output voltage is 2 V p-p, thus the signal can be used to drive a 75-Ω line. The magnitude is maintained with an AGC in 16 steps controlled by the TVP5147M1 decoder. To use this function, terminal VI_1_A must be set as an output terminal. The input mode selection register also selects an active analog output signal. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 17 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 2.1.5 www.ti.com A/D Converters All ADCs have a resolution of 11 bits and can operate up to 30 MSPS. All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All ADC reference voltages are generated internally. 2.2 Digital Video Processing Figure 2-2 is a block diagram of the TVP5147M1 digital video decoder processing. This block receives digitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs and YCbCr signal enhancements for CVBS and S-video inputs. It also generates horizontal and vertical syncs and other output control signals such as genlock for CVBS and S-video inputs. Additionally, it can provide field identification, horizontal and vertical lock, vertical blanking, and active video window indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with external syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material. Information present in the VBI interval can be retrieved and either inserted in the ITU-R BT.656 output as ancillary data or stored in internal FIFO and/or registers for retrieval via the host port interface. Copy Protection VBI Data Processor Detector CH1 A/D Y[9:0] Output Formatter 2× Decimation C[9:0] CVBS/Y CH2 A/D Slice VBI Data Composite Processor C/CbCr 2× Decimation XTAL1 FID XTAL2 RESETB PWDN DATACLK YCbCr VS/VBLK Timing Processor Host Interface HS/CS SCL SDA GLCO AVID Figure 2-2. Digital Video Processing Block Diagram 2.2.1 2x Decimation Filter All input signals are typically oversampled by a factor of 2 (27 MHz). The A/D outputs initially pass through decimation filters that reduce the data rate to 1× the pixel rate. The decimation filter is a half-band filter. Oversampling and decimation filtering can effectively increase the overall signal-to-noise ratio by 3 dB. 2.2.2 Composite Processor Figure 2-3 is a block diagram of the TVP5147M1 digital composite video processing circuit. This processing circuit receives a digitized composite or S-video signal from the ADCs and performs Y/C separation (bypassed for S-video input), chroma demodulation for PAL/NTSC and SECAM, and YUV signal enhancements. 18 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 The 10-bit composite video is multiplied by the subcarrier signals in the quadrature demodulator to generate color difference signals U and V. The U and V signals are then sent to low-pass filters to achieve the desired bandwidth. An adaptive 5-line comb filter separates UV from Y based on the unique property of color phase shifts from line to line. The chroma is remodulated through a quadrature modulator and subtracted from line-delayed composite video to generate luma. This form of Y/C separation is completely complementary, thus there is no loss of information. However, in some applications, it is desirable to limit the U/V bandwidth to avoid crosstalk. In that case, notch filters can be turned on. To accommodate some viewing preferences, a peaking filter is also available in the luma path. Contrast, brightness, sharpness, hue, and saturation controls are programmable through the host port. Peaking CVBS/Y Line Delay Delay Y – Y NTSC/PAL Remodulation SECAM Luma Contrast Brightness Saturation Adjust Notch Filter CVBS SECAM Color Demodulation U Burst Accumulator (V) V CVBS/C NTSC/PAL Demodulation Cr Notch Filter Color LPF ↓2 Burst Accumulator (U) Cb 5-Line Adaptive Comb Filter Color LPF ↓2 Notch Filter Delay Notch Filter Delay U V Figure 2-3. Composite and S-Video Processing Block Diagram Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 19 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 2.2.2.1 www.ti.com Color Low-Pass Filter 10 10 0 0 −10 −10 −20 −20 Amplitude − dB Amplitude − dB High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for nonstandard video sources that have asymmetrical U and V side bands, it is desirable to limit the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the three notch filters. Figure 2-4 and Figure 2-5 represent the frequency responses of the wideband color low-pass filters. −30 −40 ITU-R BT.601 −3 dB at 1.42 MHz −60 −60 1.0 1.5 2.0 2.5 3.0 3.5 4.0 −70 0.0 f − Frequency − MHz Filter 1 −3 dB at 1.03 MHz 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f − Frequency − MHz Figure 2-4. Color Low-Pass Filter Frequency Response 20 Filter 3 −3 dB at 554 kHz −40 −50 0.5 Filter 0 −3 dB at 1.41 MHz −30 −50 −70 0.0 Filter 2 −3 dB at 844 kHz Figure 2-5. Color Low-Pass Filter With Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 2.2.2.2 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Y/C Separation Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma trap filters are used which are shown in Figure 2-6 and Figure 2-7. The TI patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries. It detects and properly handles false colors in high-frequency luminance images such as a multiburst pattern or circle pattern. 10 10 0 0 −5 −5 −10 Notch 1 Filter −15 −20 Notch 3 Filter 5 Notch 3 Filter Amplitude − dB Amplitude − dB 5 Notch 2 Filter −25 −10 Notch 1 Filter −15 −20 Notch 2 Filter −25 No Notch Filter −30 −30 −35 No Notch Filter −35 −40 −40 0 1 2 3 4 5 6 7 0 f − Frequency − MHz 1 2 3 4 5 6 7 f − Frequency − MHz Figure 2-6. Chroma Trap Filter Frequency Response, Figure 2-7. Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling PAL ITU-R BT.601 Sampling Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 21 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 2.2.3 www.ti.com Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit. Figure 2-8 illustrates the basic functions of the luminance data path. In the case of S-video, the luminance signal bypasses the comb filter or chroma trap filter and is fed directly to the circuit. A peaking filter (edge enhancer) amplifies highfrequency components of the luminance signal. Figure 2-9 shows the characteristics of the peaking filter at four different gain settings that are user-programmable via the I2C interface. Gain IN Peak Detector Bandpass Filter Peaking Filter × Delay + OUT Figure 2-8. Luminance Edge-Enhancer Peaking Block Diagram 7 Peak at f = 2.64 MHz 6 Gain = 2 Amplitude − dB 5 Gain = 1 4 3 Gain = 0.5 2 1 0 Gain = 0 −1 0 1 2 3 4 5 6 7 f − Frequency − MHz Figure 2-9. Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling 2.2.4 Color Transient Improvement Color transient improvement (CTI) enhances horizontal color transients. The color difference signal transition points are maintained, but the edges are enhanced for signals that have bandwidth-limited color components. 22 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 2.3 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Clock Circuits An internal line-locked PLL generates the system and pixel clocks. A 14.318-MHz clock is required to drive the PLL. This can be input to the TVP5147M1 decoder at the 1.8-V level on terminal 74 (XTAL1), or a crystal of 14.318-MHz fundamental resonant frequency can be connected across terminals 74 and 75 (XTAL2). If a parallel resonant circuit is used as shown in Figure 2-10, then the external capacitors must have the following relationship: CL1 = CL2 = 2CL − CSTRAY (1) Where, CSTRAY is the terminal capacitance with respect to ground CL is the crystal load capacitance specified by the crystal manufacturer Figure 2-10 shows the reference clock configurations. The TVP5147M1 decoder generates the DATACLK signal used for clocking data. TVP5147M1 XTAL1 XTAL2 TVP5147M1 XTAL1 74 75 74 14.31818-MHz 1.8-V Clock CL1 NC XTAL2 75 R 14.31818-MHz Crystal CL2 NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor may be used for most crystal types. Figure 2-10. Reference Clock Configurations 2.4 Real-Time Control (RTC) Although the TVP5147M1 decoder is a line-locked system, the color burst information is used to determine accurately the color subcarrier frequency and phase. This ensures proper operation with nonstandard video signals that do not follow exactly the required frequency multiple between color subcarrier frequency and video line frequency. The frequency control word of the internal color subcarrier PLL and the subcarrier reset bit are transmitted via terminal 37 (GLCO) for optional use in an end system (for example, by a video encoder). The frequency control word is a 23-bit binary number. The instantaneous frequency of the color subcarrier can be calculated using the following equation: FPLL = (Fctrl / 223) × Fsclk (2) Where, FPLL is the frequency of the subcarrier PLL Fctrl is the 23-bit PLL frequency control word Fsclk is two times the pixel frequency This information can be generated on the GLCO terminal. Figure 2-11 shows the detailed timing diagram. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 23 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Valid Sample Invalid Sample Reserved RTC 128 CLK 18 CLK M S B L S B 22 0 S 45 CLK 23-Bit Fsc PLL Increment R 3 CLK 1 CLK Start Bit NOTE: RTC reset bit (R) is active-low, Sequence bit (S) PAL: 1 = (R-Y) line normal, 0 = (R-Y) line inverted, NTSC: 1 = no change Figure 2-11. RTC Timing 2.5 Output Formatter The output formatter sets how the data is formatted for output on the TVP5147M1 output buses. Table 2-1 shows the available output modes. Table 2-1. Output Format 24 TERMINAL NAME TERMINAL NUMBER 10-Bit 4:2:2 YCbCr 20-Bit 4:2:2 YCbCr Y_9 43 Cb9, Y9, Cr9 Y9 Y_8 44 Cb8, Y8, Cr8 Y8 Y_7 45 Cb7, Y7, Cr7 Y7 Y_6 46 Cb6, Y6, Cr6 Y6 Y_5 47 Cb5, Y5, Cr5 Y5 Y_4 50 Cb4, Y4, Cr4 Y4 Y_3 51 Cb3, Y3, Cr3 Y3 Y_2 52 Cb2, Y2, Cr2 Y2 Y_1 53 Cb1, Y1, Cr1 Y1 Cb0, Y0, Cr0 Y_0 54 C_9 57 Cb9, Cr9 C_8 58 Cb8, Cr8 C_7 59 Cb7, Cr7 C_6 60 Cb6, Cr6 C_5 63 Cb5, Cr5 C_4 64 Cb4, Cr4 C_3 65 Cb3, Cr3 C_2 66 Cb2, Cr2 C_1 69 Cb1, Cr1 C_0 70 Cb0, Cr0 Functional Description Y0 Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-2. Summary of Line Frequencies, Data Rates, and Pixel/Line Counts COLOR SUBCARRIER FREQUENCY (MHz) HORIZONTAL LINE RATE (kHz) 13.5 3.579545 15.73426 13.5 4.43361875 15.73426 525 13.5 3.57561149 15.73426 720 525 13.5 4.43361875 15.73426 720 625 13.5 4.43361875 15.625 864 720 625 13.5 4.43361875 15.625 PAL-Nc 864 720 625 13.5 3.58205625 15.625 SECAM 864 720 625 13.5 Dr = 4.406250 Db = 4.250000 15.625 PIXELS PER LINE ACTIVE PIXELS PER LINE LINES PER FRAME PIXEL FREQUENCY (MHz) NTSC-J, M 858 720 525 NTSC-4.43 858 720 525 PAL-M 858 720 PAL-60 858 PAL-B, D, G, H, I 864 PAL-N STANDARDS 601 Sampling 2.5.1 Separate Syncs VS, HS, and VBLK are independently software programmable to a 1× pixel count. This allows any possible alignment to the internal pixel count and line count. The default settings for 525-line and 625-line video outputs are given as examples below. FID changes at the same transient time when the trailing edge of vertical sync occurs. The polarity of FID is programmable by an I2C interface. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 25 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 525 Line 525 1 2 3 4 5 6 7 8 9 10 11 21 22 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 262 263 VBLK Stop 264 265 266 267 268 269 270 271 272 283 284 285 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start VBLK Stop NOTE: Line numbering conforms to ITU-R BT.470. Figure 2-12. Vertical Synchronization Signals for 525-Line System 26 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 625 Line 622 623 624 625 1 2 3 4 5 6 7 23 8 24 25 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 310 311 VBLK Stop 312 313 314 315 316 317 318 319 320 321 336 337 338 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start VBLK Stop NOTE: Line numbering conforms to ITU-R BT.470. Figure 2-13. Vertical Synchronization Signals for 625-Line System Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 27 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 0 DATACLK Y[9:0] Cb Y Cr Y EAV EAV EAV EAV 1 3 4 2 Horizontal Blanking HS Start SAV SAV SAV SAV Cb0 1 2 3 4 Y0 Cr0 Y1 HS Stop HS A C B D AVID AVID Stop AVID Start DATACLK = 2 × Pixel Clock Mode A B C D NTSC 601 106 128 42 276 PAL 601 112 128 48 288 NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference Figure 2-14. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode 28 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 0 DATACLK Y[9:0] Y Y Y Y Horizontal Blanking CbCr[9:0] Cb Cr Cb Cr Horizontal Blanking HS Start Y0 Y1 Y2 Y3 Cb0 Cr0 Cb1 Cr1 HS Stop HS A C B 2 D AVID AVID Stop AVID Start NOTE: AVID rising edge occurs four clock cycles early. DATACLK = 1 × Pixel Clock Mode A B C D NTSC 601 53 64 19 136 PAL 601 56 64 22 142 NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference Figure 2-15. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 29 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com HS First Field B/2 B/2 VS HS H/2 + B/2 Second Field H/2 + B/2 VS 10-Bit (PCLK = 2 × Pixel Clock) 20-Bit (PCLK = 1 × Pixel Clock) Mode B/2 H/2 B/2 H/2 NTSC 601 64 858 32 429 PAL 601 64 864 32 432 Figure 2-16. VSYNC Position With Respect to HSYNC 2.5.2 Embedded Syncs Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and falling edges of AVID. These codes contain the V and F bits, which also define vertical timing. Table 2-3 gives the format of the SAV and EAV codes. H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. The P bits are protection bits: P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H Table 2-3. EAV and SAV Sequence D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 Preamble 1 1 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 0 0 Status word 1 F V H P3 P2 P1 P0 0 0 2.6 I2C Host Interface Communication with the TVP5147M1 decoder is via an I2C host interface. The I2C standard consists of two signals, the serial input/output data (SDA) line and the serial input clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be multimastered, the TVP5147M1 decoder functions as a slave device only. 30 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Because SDA and SCL are kept open drain at a logic-high output level or when the bus is not driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on the board. The slave addresses select signal, terminal 37 (I2CA), enables the use of two TVP5147M1 devices tied to the same I2C bus, because it controls the least-significant bit of the I2C device address. Table 2-4. I2C Host Interface Terminal Description SIGNAL TYPE DESCRIPTION I2CA I Slave address selection SCL I Input clock line SDA I/O Input/output data line Reset and I2C Bus Address Selection 2.6.1 The TVP5147M1 decoder can respond to two possible chip addresses. The address selection is made at reset by an externally supplied level on the I2CA terminal. The TVP5147M1 decoder samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures the I2C bus address bit A0. Table 2-5. I2C Address Selection (1) A6 A5 A4 A3 A2 A1 A0 (I2CA) R/W HEX 1 0 1 1 1 0 0 (default) 1/0 B9/B8 1 0 1 1 1 0 1 (1) 1/0 BB/BA If terminal 37 is strapped to DVDD via a 2.2-kΩ resistor, I2C device address A0 is set to 1. I2C Operation 2.6.2 Data transfers occur using the following illustrated formats. S 10111000 ACK Subaddress ACK Send Data ACK P Read from I2C control registers S 10111000 ACK Subaddress ACK S 10111001 ACK Receive Data NAK P 2 S = I C bus start condition P = I2C bus stop condition ACK = Acknowledge generated by the slave NAK = Acknowledge generated by the master, for multiple-byte read master with ACK each byte except last byte Subaddress = Subaddress byte Data = Data byte. If more than one byte of data is transmitted (read and write), the subaddress pointer is automatically incremented. I2C bus address = Example shown that I2CA is in default mode. Write (B8h), read (B9h) Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 31 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 2.6.3 www.ti.com VBUS Access The TVP5147M1 decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 2-17 shows the VBUS register access. I2C Registers VBUS Registers 00h HOST Processor 00 0000h I2C 80 051Ch CC E0h VBUS Data E1h E8h WSS 80 0520h VITC 80 052Ch Line Mode VBUS[23:0] EAh 80 0700h VPS VBUS Address 80 0600h 90 1904h FIFO FF FFFFh FFh VBUS Write Single Byte S B8 ACK E8 ACK VA0 ACK VA1 ACK S B8 ACK E0 ACK Send Data ACK P VA2 ACK P ACK P Multiple Bytes S B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 S B8 ACK E1 ACK Send Data ACK • •• Send Data ACK VA1 ACK VA2 P P VBUS Read Single Byte S B8 ACK E8 ACK VA0 S B8 ACK E0 ACK S ACK B9 ACK Read Data ACK NAK P Multiple Bytes S B8 ACK E8 ACK VA0 S B8 ACK E1 ACK S ACK B9 VA1 ACK ACK VA2 Read Data ACK ACK P ••• Read Data NAK P NOTE: Examples use default I2C address ACK = Acknowledge generated by the slave NAK = No acknowledge generated by the master Figure 2-17. VBUS Access 32 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 2.7 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 VBI Data Processor The TVP5147M1 VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), program delivery control (PDC), vertical interval time code (VITC), video program system (VPS), copy generation management system (CGMS) data, and electronic program guide (Gemstar) 1x/2x. Table 2-6 shows the supported VBI system. These services are acquired by programming the VDP to enable the reception of one or more vertical blank interval (VBI) data standard(s) during the VBI. The VDP can be programmed on a line-per-line basis to enable simultaneous reception of different VBI formats, one per line. The results are stored in a FIFO and/or registers. Because of the high data bandwidth, teletext results are stored in FIFO only. The TVP5147M1 decoder provides fully decoded V-Chip data to the dedicated registers at subaddresses 80 0540h−80 0543h. Table 2-6. Supported VBI System VBI SYSTEM Teletext WST A STANDARD LINE NUMBER NUMBER OF BYTES SECAM 6-23 (Fields 1 and 2) 38 Teletext WST B PAL 6-22 (Fields 1 and 2) 43 Teletext NABTS C NTSC 10-21 (Fields 1 and 2) 34 Teletext NABTS D NTSC-J 10-21 (Fields 1 and 2) 35 Closed Caption PAL 22 (Fields 1 and 2) 2 Closed Caption NTSC 21 (Fields 1 and 2) 2 PAL 23 (Fields 1 and 2) 14 bits NTSC 20 (Fields 1 and 2) 20 bits 9 WSS WSS-CGMS VITC PAL 6-22 VITC NTSC 10-20 9 PAL 16 13 V-Chip (decoded) NTSC 21 (Fields 1 and 2) 2 Gemstar 1x NTSC 2 Gemstar 2x NTSC 5 with frame byte VPS (PDC) User Any Programmable Programmable Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 33 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 2.7.1 www.ti.com VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI data is output on the Y[9:2] terminals during the horizontal blanking period. Table 2-7 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of the FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard. Table 2-7. Ancillary Data Format and Sequence BYTE NO. D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Ancillary data preamble 2 1 1 1 1 1 1 1 1 3 NEP EP 0 1 0 DID2 DID1 DID0 4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID (SDID) 5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32 bit data (NN) 6 Video line # [7:0] 7 0 0 0 Data error Match #1 Data ID (DID) Internal data ID0 (IDID0) Match #2 Video line # [9:8] Internal data ID1 (IDID1) 8 1. Data Data byte 9 2. Data Data byte 10 3. Data Data byte 11 4. Data Data byte ⋮ ⋮ 4N+7 0 EP: NEP: DID: SDID: NN: IDID0: IDID1: CS: Fill byte: 34 DESCRIPTION 0 0 0 1st word ⋮ m. Data Data byte CS[7:0] Check sum 0 0 0 0 Nth word Fill byte Even parity for D0–D5 Negated even parity 91h: Sliced data of VBI lines of first field 53h: Sliced data of line 24 to end of first field 55h: Sliced data of VBI lines of second field 97h: Sliced data of line 24 to end of second field This field holds the data format taken from the line mode register bits [2:0] of the corresponding line. Number of Dwords beginning with byte 8 through 4N+7. This value is the number of Dwords where each Dword is 4 bytes. Transaction video line number [7:0] Bit 0/1 = Transaction video line number [9:8] Bit 2 = Match 2 flag Bit 3 = Match 1 flag Bit 4 = 1 if an error was detected in the EDC block.0 if no error was detected. Sum of D0–D7 of DID through last data byte Fill bytes make a multiple of four bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern byte. Byte 9 is the first data byte. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 2.7.2 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 VBI Raw Data Output The TVP5147M1 decoder can output raw A/D video data at twice the sampling rate for external VBI slicing. This is transmitted as an ancillary data block, although somewhat differently from the way the sliced VBI data is transmitted in the FIFO format as described in Section 2.7.1. The samples are transmitted during the active portion of the line. VBI raw data uses ITU-R BT.656 format having only luma data. The chroma samples are replaced by luma samples. The TVP5147M1 decoder inserts a four-byte preamble 000h 3FFh 3FFh 180h before data start. There are no checksum bytes and fill bytes in this mode. Table 2-8. VBI Raw Data Output Format BYTE NO. D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 0 1 1 0 0 0 0 0 0 0 VBI raw data preamble 2× pixel rate luma data (that is, NTSC 601: n = 1707) 4 1. Data 5 2. Data ⋮ ⋮ n-1 n-5. Data n n-4. Data 2.8 DESCRIPTION Reset and Initialization Reset is initiated at power up or any time terminal 34 (RESETB) is brought low. Table 2-9 describes the status of the TVP5147M1 terminals during and immediately after reset. Table 2-9. Reset Sequence SIGNAL NAME DURING RESET RESET COMPLETED Y[9:0], C[9:0] Input High impedance RESETB, PWDN, SDA, SCL, FSS, AVID, GLCO, HS, VS, FID Input Input INTREQ Input Output DATACLK Output High impedance POWER (3.3 V and 1.8 V) 1 ms (min) 200 ns (min) Normal Operation RESETB (Pin 34) Reset 1 ms (min) SDA (Pin 29) Invalid I 2C Cycle Valid Figure 2-18. Reset Timing Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 35 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com The following register writes must be made before normal operation of the device. STEP I2C SUBADDRESS I2C DATA 1 0x03 0x01 2 0x03 0x00 When using any industrial temperature range device (TVP5147M1IPFP and TVP5147M1IPFPQ1), the following I2C register writes must be executed following device power up and RESETB to properly initialize VBUS register 0xA00014. When patch code is being used, these I2C writes must be executed after the patch code has been loaded. NOTE The following I2C writes are mandatory for industrial temperature range devices but are optional for commercial temperature range devices (TVP5147M1PFP). 2.9 STEP I2C SUBADDRESS I2C DATA 1 0xE8 0x14 2 0xE9 0x00 3 0xEA 0xA0 4 0xE0 0x14 Adjusting External Syncs The proper sequence to program the following external syncs is: • To set NTSC, PAL-M, NTSC 443, PAL60 (525-line modes): – Set the video standard to NTSC (register 02h). – Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h). • To set PAL, PAL-N, SECAM (625-line modes): – Set the video standard to PAL (register 02h). – Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h). • For autoswitch, set the video standard to autoswitch (register 02h). 36 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 2.10 Internal Control Registers The TVP5147M1 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP5147M1 is through a standard I2C host port interface, as described earlier. Table 2-10 shows the summary of these registers. Detailed programming information for each register is described in the following sections. Additional registers are accessible through an indirect procedure involving access to an internal 24-bit address wide VBUS. Table 2-11 shows the summary of the VBUS registers. NOTE Do not write to reserved registers. Reserved bits in any defined register must be written with 0s, unless otherwise noted. Table 2-10. I2C Register Summary (1) REGISTER NAME I2C SUBADDRESS DEFAULT R/W Input select 00h 00h R/W AFE gain control 01h 0Fh R/W Video standard 02h 00h R/W Operation mode 03h 00h R/W Autoswitch mask 04h 23h R/W Color killer 05h 10h R/W Luminance processing control 1 06h 00h R/W Luminance processing control 2 07h 00h R/W Luminance processing control 3 08h 02h R/W Luminance brightness 09h 80h R/W Luminance contrast 0Ah 80h R/W Chrominance saturation 0Bh 80h R/W Chroma hue 0Ch 00h R/W Chrominance processing control 1 0Dh 00h R/W Chrominance processing control 2 0Eh 0Eh R/W Reserved 0Fh-15h AVID start pixel 16h-17h 055h R/W AVID stop pixel 18h-19h 325h R/W HSYNC start pixel 1Ah-1Bh 000h R/W HSYNC stop pixel 1Ch-1Dh 040h R/W VSYNC start line 1Eh-1Fh 004h R/W VSYNC stop line 20h-21h 007h R/W VBLK start line 22h-23h 001h R/W VBLK stop line 24h-25h 015h R/W 26h 00h R/W 27h 00h R/W 00h R/W Embedded Sync Offset Control 1 Embedded Sync Offset Control 2 Reserved 28h-2Ah Overlay delay 2Bh Reserved 2Ch CTI delay 2Dh 00h R/W CTI control 2Eh 00h R/W Reserved (1) 2Fh-31h R = Read only, W = Write only, R/W = Read and write Reserved register addresses must not be written to. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 37 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-10. I2C Register Summary(1) (continued) I2C SUBADDRESS DEFAULT R/W Sync control 32h 00h R/W Output formatter 1 33h 40h R/W Output formatter 2 34h 00h R/W Output formatter 3 35h FFh R/W Output formatter 4 36h FFh R/W Output formatter 5 37h FFh R/W Output formatter 6 38h FFh R/W Clear lost lock detect 39h 00h R/W Status 1 3Ah R Status 2 3Bh R 3Ch-3Dh R REGISTER NAME AGC gain status Reserved 3Eh Video standard status 3Fh R GPIO input 1 40h R GPIO input 2 41h R Reserved 42h-45h AFE coarse gain for CH1 46h 20h R/W AFE coarse gain for CH2 47h 20h R/W AFE coarse gain for CH3 48h 20h R/W AFE coarse gain for CH4 49h 20h R/W AFE fine gain for Pb 4Ah-4Bh 900h R/W AFE fine gain for chroma 4Ch-4Dh 900h R/W AFE fine gain for Pr 4Eh-4Fh 900h R/W AFE fine gain for CVBS_Luma 50h-51h 900h R/W Reserved 52h-56h 00h R/W 00h R/W 08h R/W 04h R/W Field ID control 57h Reserved 58h-68h F-bit and V-bit control 1 69h Reserved 6Ah-6Bh Back-end AGC control 6Ch Reserved 6Dh-6Eh AGC decrement speed control 6Fh ROM version 70h R 71h R RAM Version MSB Reserved 72h-73h AGC white peak processing 74h 00h R/W F and V bit control VCR trick mode control 75h 12h R/W 76h 8Ah R/W Horizontal shake increment 77h 64h R/W AGC increment speed 78h 05h R/W 79h 1Eh R/W AGC increment delay Reserved 7Ah-7Eh Analog output control 1 7Fh 00h R/W Chip ID MSB 80h 51h R Chip ID LSB 81h 47h R RAM Version LSB 82h CPLL speed control 83h 38 Functional Description R 09h R/W Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-10. I2C Register Summary(1) (continued) REGISTER NAME I2C SUBADDRESS Reserved DEFAULT R/W 00h R/W 84h-96h Status request 97h Reserved 98h-99h Vertical line count 9Ah-9Bh Reserved 9Ch-9Dh AGC decrement delay 9Eh Reserved R 00h R/W 9Fh-B0h VDP TTX filter 1 mask 1 B1h 00h R/W VDP TTX filter 1 mask 2 B2h 00h R/W VDP TTX filter 1 mask 3 B3h 00h R/W VDP TTX filter 1 mask 4 B4h 00h R/W VDP TTX filter 1 mask 5 B5h 00h R/W VDP TTX filter 2 mask 1 B6h 00h R/W VDP TTX filter 2 mask 2 B7h 00h R/W VDP TTX filter 2 mask 3 B8h 00h R/W VDP TTX filter 2 mask 4 B9h 00h R/W VDP TTX filter 2 mask 5 BAh 00h R/W VDP TTX filter control BBh 00h R/W VDP FIFO word count BCh VDP FIFO interrupt threshold BDh 80h R/W Reserved BEh VDP FIFO reset BFh 00h R/W VDP FIFO output control C0h 00h R/W VDP line number interrupt R C1h 00h R/W VDP pixel alignment C2h-C3h 01Eh R/W Reserved C4h-D5h VDP line start D6h 06h R/W VDP line stop D7h 1Bh R/W VDP global line mode D8h FFh R/W VDP full field enable D9h 00h R/W DAh FFh R/W VDP full field mode Reserved DBh-DFh VBUS data access with no VBUS address increment E0h 00h R/W VBUS data access with VBUS address increment E1h 00h R/W FIFO read data E2h Reserved R E3h-E7h VBUS address access E8h-EAh Reserved EBh-EFh 00 0000h R/W Interrupt raw status 0 F0h R Interrupt raw status 1 F1h R Interrupt status 0 F2h R Interrupt status 1 F3h Interrupt mask 0 F4h 00h R/W Interrupt mask 1 F5h 00h R/W Interrupt clear 0 F6h 00h R/W Interrupt clear 1 F7h 00h R/W Reserved R F8h-FFh Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 39 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-11. VBUS Register Summary (1) REGISTER NAME I2C SUBADDRESS DEFAULT R/W Reserved 00 0000h-80 051Bh VDP closed caption data 80 051Ch-80 051Fh R VDP WSS/CGMS data 80 0520h-80 0526h R Reserved 80 0527h-80 052Bh VDP VITC data 80 052Ch-80 0534h Reserved 80 0535h-80 053Fh VDP V-Chip data 80 0540h-80 0543h Reserved 80 0544h-80 05FFh VDP general line mode and line address 80 0600h-80 0611h Reserved 80 0612h-80 06FFh VDP VPS/Gemstar (PDC) data 80 0700h-80 070Ch Reserved 80 070Dh-90 1903h VDP FIFO read Reserved Analog output control 2 Reserved Interrupt configuration Reserved (1) 40 R R 00h, FFh R/W R 90 1904h R 90 1905h-A0 005Dh A0 05Eh B2h R/W 00h R/W A0 005Fh-B0 005Fh B0 0060h B0 0061h-FF FFFFh Writing any value to a reserved register may cause erroneous operation of the TVP5147M1 decoder. It is recommended not to access any data to/from reserved registers. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 2.11 Register Definitions Table 2-12. Input Select Register Subaddress Default 00h 00h 7 6 5 4 3 Input select [7:0] 2 1 0 Ten input terminals can be configured to support composite, S-video, and component YPbPr as listed in Table 2-13. User must follow this table properly for S-video and component applications because only the terminal configurations listed in Table 2-13 are supported. Table 2-13. Analog Channel and Video Mode Selection MODE CVBS S-video YPbPr (1) INPUT(S) SELECTED INPUT SELECT [7:0] OUTPUT (1) 7 6 5 4 3 2 1 0 HEX VI_1_A (default) 0 0 0 0 0 0 0 0 00 N/A VI_1_B 0 0 0 0 0 0 0 1 01 VI_1_B VI_1_C 0 0 0 0 0 0 1 0 02 VI_1_C VI_2_A 0 0 0 0 0 1 0 0 04 VI_2_A VI_2_B 0 0 0 0 0 1 0 1 05 VI_2_B VI_2_C 0 0 0 0 0 1 1 0 06 VI_2_C VI_3_A 0 0 0 0 1 0 0 0 08 VI_3_A VI_3_B 0 0 0 0 1 0 0 1 09 VI_3_B VI_3_C 0 0 0 0 1 0 1 0 0A VI_3_C VI_4_A 0 0 0 0 1 1 0 0 0C VI_4_A VI_2_A(Y), VI_1_A(C) 0 1 0 0 0 1 0 0 44 N/A VI_2_B(Y), VI_1_B(C) 0 1 0 0 0 1 0 1 45 VI_2_B(Y) VI_2_C(Y), VI_1_C(C) 0 1 0 0 0 1 1 0 46 VI_2_C(Y) VI_2_A(Y), VI_3_A(C) 0 1 0 1 0 1 0 0 54 VI_2_A(Y) VI_2_B(Y), VI_3_B(C) 0 1 0 1 0 1 0 1 55 VI_2_B(Y) VI_2_C(Y), VI_3_C(C) 0 1 0 1 0 1 1 0 56 VI_2_C(Y) VI_4_A(Y), VI_1_A(C) 0 1 0 0 1 1 0 0 4C N/A VI_4_A(Y), VI_1_B(C) 0 1 0 0 1 1 0 1 4D VI_4_A(Y) VI_4_A(Y), VI_1_C(C) 0 1 0 0 1 1 1 0 4E VI_4_A(Y) VI_4_A(Y), VI_3_A(C) 0 1 0 1 1 1 0 0 5C VI_4_A(Y) VI_4_A(Y), VI_3_B(C) 0 1 0 1 1 1 0 1 5D VI_4_A(Y) VI_4_A(Y), VI_3_C(C) 0 1 0 1 1 1 1 0 5E VI_4_A(Y) VI_1_A(Pb), VI_2_A(Y), VI_3_A(Pr) 1 0 0 1 0 1 0 0 94 N/A VI_1_B(Pb), VI_2_B(Y), VI_3_B(Pr) 1 0 0 1 0 1 0 1 95 VI_2_B(Y) VI_1_C(Pb), VI_2_C(Y), VI_3_C(Pr) 1 0 0 1 0 1 1 0 96 VI_2_C(Y) When VI_1_A is set to output, the total number of inputs is nine. The video output can be either CVBS or luma. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 41 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-14. AFE Gain Control Register Subaddress Default 01h 0Fh 7 6 5 4 Reserved 3 1 2 1 1 AGC chroma 0 AGC luma Bit 3: 1b must be written to this bit Bit 2: 1b must be written to this bit AGC chroma enable: Controls automatic gain in the chroma/PbPr channel 0 = Manual (if AGC luma is set to manual, AGC chroma is forced to be in manual) 1 = Enabled auto gain, applied a gain value acquired from the sync channel for S-video and component mode. When AGC luma is set, this state is valid. (default) AGC luma enable: Controls automatic gain in the embedded sync channel of CVBS, S-video, component video 0 = Manual gain, AFE coarse and fine gain frozen to the previous gain value set by AGC when this bit is set to 0. 1 = Enabled auto gain applied to only the embedded sync channel (default) These settings affect only the analog front-end (AFE). The brightness and contrast controls are not affected by these settings. Table 2-15. Video Standard Select Register Subaddress Default 02h 00h 7 6 5 Reserved 4 3 2 1 Video standard [2:0] 0 Video standard [2:0]: 000 001 010 011 100 101 110 111 CVBS and S-Video Autoswitch mode (default) (M, J) NTSC (B, D, G, H, I, N) PAL (M) PAL (Combination-N) PAL NTSC 4.43 SECAM PAL 60 Component Video Autoswitch mode (default) Interlaced 525 Interlaced 625 Reserved Reserved Reserved Reserved Reserved With the autoswitch code running, the user can force the decoder to operate in a particular video standard mode by writing the appropriate value into this register. Changing these bits causes the register settings to be reinitialized. 42 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-16. Operation Mode Control Register Subaddress Default 03h 00h 7 6 Reserved 5 4 H-PLL response time 3 2 Reserved 1 0 Power save H-PLL response time 00 = Adaptive mode (default). 01 = Reserved mode. 10 = Fast mode. 11 = Normal mode. When in the Normal mode, the horizontal PLL (H-PLL) response time is set to its slowest setting. This mode improves noise immunity and provides a more stable output line frequency for standard TV signal sources (for example, TV tuners, DVD players, video surveillance cameras, etc.). When in the Fast mode, the H-PLL response time is set to its fastest setting. This mode enables the H-PLL to respond more quickly to large variations in the horizontal timing (for example, VCR head switching intervals). This mode is recommended for VCRs and also cameras locked to the AC power-line frequency. When in the Adaptive mode, the H-PLL response time is automatically adjusted based on the measured horizontal phase error. In this mode, the H-PLL response time typically approaches its slowest setting for most standard TV signal sources and approaches its fastest setting for most VCR signal sources. Power save 0 = Normal operation (default) 1 = Power save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I2C interface is active, and all current operating settings are preserved. Table 2-17. Autoswitch Mask Register Subaddress Default 7 Reserved 04h 23h 6 PAL 60 5 SECAM 4 NTSC 4.43 3 (Nc) PAL 2 (M) PAL 1 PAL 0 (M, J) NTSC This register limits the video formats between which autoswitch is possible. PAL 60 0 = Autoswitch does not include PAL 60 (default) 1 = Autoswitch includes PAL 60 SECAM 0 = Autoswitch does not include SECAM 1 = Autoswitch includes SECAM (default) NTSC 4.43 0 = Autoswitch does not include NTSC 4.43 (default) 1 = Autoswitch includes NTSC 4.43 (Nc) PAL 0 = Autoswitch does not include (Nc) PAL (default) 1 = Autoswitch includes (Nc) PAL (M) PAL 0 = Autoswitch does not include (M) PAL (default) 1 = Autoswitch includes (M) PAL PAL 0 = Reserved 1 = Autoswitch includes (B, D, G, H, I, N) PAL (default) (M, J) NTSC 0 = Reserved 1 = Autoswitch includes (M, J) NTSC (default) Note: Bits 1 and 0 must always be 11b. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 43 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-18. Color Killer Register Subaddress Default 05h 10h 7 Reserved 6 5 Automatic color killer 4 3 2 Color killer threshold [4:0] 1 0 Automatic color killer: 00 = Automatic mode (default) 01 = Reserved 10 = Color killer enabled, the UV terminals are forced to a zero color state 11 = Color killer disabled Color killer threshold [4:0]: 11111 = 31 (maximum) 10000 = 16 (default) 00000 = 0 (minimum) Table 2-19. Luminance Processing Control 1 Register Subaddress Default 7 Reserved 06h 00h 6 Pedestal not present 5 Reserved 4 VBI raw 3 2 1 Luminance signal delay [3:0] 0 Pedestal not present: 0 = 7.5 IRE pedestal is present on the analog video input signal (default) 1 = Pedestal is not present on the analog video input signal VBI raw: 0 = Disable (default) 1 = Enable During the duration of the vertical blanking as defined by VBLK start and stop registers 22h through 25h, the chroma samples are replaced by luma samples. This feature may be used to support VBI processing performed by an external device during the vertical blanking interval. To use this bit, the output format must be the 10-bit, ITU-R BT.656 mode. Luminance signal delay [3:0]: Luminance signal delays respect to chroma signal in 1× pixel clock increments. 0111 = Reserved 0110 = 6 pixel clocks delay 0001 = 1 pixel clock delay 0000 = 0 pixel clock delay (default) 1111 = –1 pixel clock delay 1000 = –8 pixel clock delay 44 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-20. Luminance Processing Control 2 Register Subaddress Default 07h 00h 7 6 Luma filter select [1:0] 5 4 3 2 Peaking gain [1:0] Reserved 1 0 Reserved Luma filter selected [1:0]: 00 = Luminance adaptive comb enable (default on CVBS) 01 = Luminance adaptive comb disable (trap filter selected) 10 = Luma comb/trap filter bypassed (default on S-Video, component mode, and SECAM) 11 = Reserved Peaking gain [1:0]: 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 Table 2-21. Luminance Processing Control 3 Register Subaddress Default 08h 02h 7 6 5 4 3 2 Reserved 1 0 Trap filter select [1:0] Trap filter select[1:0]: Selects one of the four trap filters to produce the luminance signal by removing the chrominance signal from the composite video signal. The stop band of the chroma trap filter is centered at the chroma subcarrier frequency with the stop-band bandwidth controlled by the two control bits. Trap filter stop band bandwidth (MHz): Filter select [1:0] 00 01 10 (default) 11 NTSC ITU-R 601 1.2129 0.8701 0.7183 0.5010 PAL ITU-R 601 1.2129 0.8701 0.7383 0.5010 Table 2-22. Luminance Brightness Register Subaddress Default 7 09h 80h 6 5 4 3 2 1 0 Brightness [7:0] Brightness [7:0]: This register works for CVBS and S-Video luminance. 0000 0000 = 0 (dark) 1000 0000 = 128 (default) 1111 1111 = 255 (bright) For composite and S-Video outputs, the output black level relative to the nominal black level (64 out of 1024) as a function of the Brightness[7:0] setting is as follows. Black Level = nominal_black_level + (MB + 1) × (Brightness[7:0] – 128) Where MB is the brightness multiplier setting in the Brightness and Contrast Range Extender register at I2C subaddress 2Fh. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 45 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-23. Luminance Contrast Register Subaddress Default 0Ah 80h 7 6 5 4 3 2 1 0 Contrast [7:0] Contrast [7:0]: This register works for CVBS and S-Video luminance. See subaddress 2Fh. 0000 0000 = 0 (minimum contrast) 1000 0000 = 128 (default) 1111 1111 = 255 (maximum contrast) For composite and S-Video outputs, the total luminance gain relative to the nominal luminance gain as a function of the Contrast [7:0] setting is as follows. Luminance Gain = (nominal_luminance_gain) × [Contrast[7:0] / 64 / (2^MC) + MC – 1] Where MC is the contrast multiplier setting in the Brightness and Contrast Range Extender register at I2C subaddress 2Fh. Table 2-24. Chrominance Saturation Register Subaddress Default 0Bh 80h 7 6 5 4 3 2 1 0 Saturation [7:0] Saturation [7:0]: This register works for CVBS and S-Video chrominance. 0000 0000 = 0 (no color) 1000 0000 = 128 (default) 1111 1111 = 255 (maximum) For composite and S-Video outputs, the total chrominance gain relative to the nominal chrominance gain as a function of the Saturation [7:0] setting is as follows. Chrominance Gain = (nominal_chrominance_gain) × (Saturation[7:0] / 128) Table 2-25. Chroma Hue Register Subaddress Default 7 0Ch 00h 6 5 4 3 2 1 0 Hue [7:0] Hue [7:0]: Does not apply to a component or SECAM video 0111 1111 = +180 degrees 0000 0000 = 0 degrees (default) 1000 0000 = –180 degrees 46 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-26. Chrominance Processing Control 1 Register Subaddress Default 7 0Dh 00h 6 Reserved 5 4 Color PLL reset 3 Chroma adaptive comb enable 2 Reserved 1 0 Automatic color gain control [1:0] Color PLL reset: 0 = Color subcarrier PLL not reset (default) 1 = Color subcarrier PLL reset Chrominance adaptive comb enable: This bit is effective on composite video only. 0 = Enable (default) 1 = Disable Automatic color gain control (ACGC) [1:0]: 00 = ACGC enabled (default) 01 = Reserved 10 = ACGC disabled, ACGC set to the nominal value 11 = ACGC frozen to the previously set value Table 2-27. Chrominance Processing Control 2 Register Subaddress Default 0Eh 0Eh 7 6 5 4 Reserved 3 PAL compensation 2 WCF 1 0 Chrominance filter select [1:0] PAL compensation: 0 = Disabled 1 = Enabled (default) Wideband chroma LPF filter (WCF): 0 = Disabled 1 = Enabled (default) Chrominance filter select [1:0]: 00 = Disabled 01 = Notch 1 10 = Notch 2 (default) 11 = Notch 3 See Figure 2-6 and Figure 2-7 for characteristics. Table 2-28. R/Pr Gain (Color Saturation) Register Subaddress Default 7 10h 80h 6 5 4 3 2 1 0 R/Pr gain [7:0] R/Pr component gain (color saturation): 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum For component video, the total R/Pr gain relative to the nominal R/Pr gain as a function of the R/Pr gain [7:0] setting is as follows: R/Pr Gain = (nominal_chrominance_gain) × (R/Pr gain [7:0] / 128) Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 47 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-29. G/Y Gain (Contrast) Register Subaddress Default 11h 80h 7 6 5 4 3 2 1 0 G/Y gain [7:0] G/Y component gain (contrast): 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum For component video outputs, the total luma gain relative to the nominal luma gain as a function of the G/Y gain[7:0] is as follows: Luma gain = (nominal_luminance_gain) × (G/Y gain [7:0] / 128) Table 2-30. B/Pb Gain (Color Saturation) Register Subaddress Default 12h 80h 7 6 5 4 3 2 1 0 B/Pb gain [7:0] B/Pb component gain (color saturation): 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum For component video, the total B/Pb gain relative to the nominal B/Pb gain as a function of the B/Pb gain [7:0] setting is as follows: B/Pb Gain = (nominal_chrominance_gain) × (B/Pb gain [7:0] / 128) Table 2-31. G/Y Offset Register Subaddress Default 7 14h 80h 6 5 4 3 2 1 0 G/Y offset [7:0] G/Y component offset (brightness): 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum For component video, the output black level relative to the nominal black level (64 out of 1024) as a function of G/Y offset [7:0] is as follows: Black Level = nominal_black_level + (G/Y offset [7:0] – 128) 48 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-32. AVID Start Pixel Register Subaddress Default Subaddress 16h 17h 16h–17h 55h 7 6 5 Reserved 4 3 AVID start [7:0] AVID active 2 Reserved 1 0 AVID start [9:8] AVID active: 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK AVID start [9:0]: AVID start pixel number, this is an absolute pixel location from HSYNC start pixel 0. NTSC 601 default: is 85 (55h) PAL 601 default: is 95 (5Fh) The TVP5147M1 decoder updates the AVID start only when the AVID start MSB byte is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this device resets. The AVID start pixel register also controls the position of the SAV code. Table 2-33. AVID Stop Pixel Register Subaddress Default Subaddress 18h 19h 18h–19h 325h 7 6 5 4 3 AVID stop [7:0] 2 Reserved 1 0 AVID stop [9:8] AVID stop [9:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location from HSYNC start pixel 0. For NTSC 601, default is 805 (325h) For PAL 601, default is 815 (32Fh) The TVP5147M1 decoder updates the AVID stop only when the AVID stop MSB byte is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this device resets. The AVID start pixel register also controls the position of the EAV code. Table 2-34. HSYNC Start Pixel Register Subaddress Default Subaddress 1Ah 1Bh 1Ah–1Bh 000h 7 6 5 4 3 HSYNC start [7:0] Reserved 2 1 0 HSYNC start [9:8] HSYNC start pixel [9:0]: This is an absolute pixel location from HSYNC start pixel 0. The TVP5147M1 decoder updates the HSYNC start only when the HSYNC start MSB is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this device resets. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 49 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-35. HSYNC Stop Pixel Register Subaddress Default Subaddress 1Ch 1Dh 1Ch–1Dh 040h 7 6 5 4 3 HSYNC stop [7:0] 2 Reserved 1 0 HSYNC stop [9:8] HSYNC stop [9:0]: This is an absolute pixel location from HSYNC start pixel 0. The TVP5147M1 decoder updates the HSYNC stop only when the HSYNC stop MSB is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this device resets. Table 2-36. VSYNC Start Line Register Subaddress Default Subaddress 1Eh 1Fh 1Eh–1Fh 004h 7 6 5 4 3 VSYNC start [7:0] 2 Reserved 1 0 VSYNC start [9:8] VSYNC start [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VSYNC start only when the VSYNC start MSB is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this decoder resets. NTSC: default 004h PAL: default 001h Table 2-37. VSYNC Stop Line Register Subaddress Default Subaddress 20h 21h 20h–21h 007h 7 6 5 4 3 VSYNC stop [7:0] 2 Reserved 1 0 VSYNC stop [9:8] VSYNC stop [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VSYNC stop only when the VSYNC stop MSB is written to. If the user changes these registers, the TVP5147M1 decoder retains values in different modes until this decoder resets. NTSC: default 007h PAL: default 004h Table 2-38. VBLK Start Line Register Subaddress Default Subaddress 22h 23h 22h–23h 001h 7 6 5 4 3 VBLK start [7:0] Reserved 2 1 0 VBLK start [9:8] VBLK start [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VBLK start line only when the VBLK start MSB is written to. If the user changes these registers, the TVP5147M1 decoder retains values in different modes until this resets (see Table 2-32) NTSC: default 001h PAL: default 623 (26Fh) 50 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-39. VBLK Stop Line Register Subaddress Default 24h–25h 015h Subaddress 24h 25h 7 6 5 4 3 VBLK stop [7:0] 2 1 Reserved 0 VBLK stop [9:8] VBLK stop [9:0]: This is an absolute line number. The TVP5147M1 decoder updates the VBLK stop only when the VBLK stop MSB is written to. If the user changes these registers, then the TVP5147M1 decoder retains values in different modes until this device resets (see Table 2-32). NTSC: default 21 (015h) PAL: default 23 (017h) Table 2-40. Embedded Sync Offset Control 1 Register Subaddress Default 26h 00h 7 6 5 4 3 2 1 0 Offset [7:0] This register allows the line position of the embedded F bit and V bit signals to be offset from the 656 standard positions. This register is only applicable to input video signals with standard number of lines. 0111 1111 = 127 lines ⋮ 0000 0001 = 1 line 0000 0000 = 0 line 1111 1111 = –1 line ⋮ 1000 0000 = –128 lines Table 2-41. Embedded Sync Offset Control 2 Register Subaddress Default 7 27h 00h 6 5 4 3 2 1 0 Offset [7:0] This register allows the line relationship between the embedded F bit and V bit signals to be offset from the 656 standard positions, and moves F relative to V. This register is only applicable to input video signals with standard number of lines. 0111 1111 = 127 lines ⋮ 0000 0001 = 1 line 0000 0000 = 0 line 1111 1111 = –1 line ⋮ 1000 0000 = –128 lines Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 51 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-42. CTI Delay Register Subaddress Default 2Dh 00h 7 6 5 Reserved 4 3 2 1 CTI delay [2:0] 0 1 0 CTI delay [2:0]: Sets the delay of the Y channel with respect to Cb/Cr in the CTI block 011 = 3-pixel delay 001 = 1-pixel delay 000 = 0 delay (default) 111 = −1-pixel delay 100 = −4-pixel delay Table 2-43. CTI Control Register Subaddress Default 2Eh 00h 7 6 5 4 3 2 CTI coring [3:0] CTI gain [3:0] CTI coring [3:0]: 4-bit CTI coring limit control values, unsigned, linear control range from 0 to ±60, step size = 4 1111 = ±60 ⋮ 0001 = ±4 0000 = 0 (default) CTI gain [3:0]: 4-bit CTI gain control values, unsigned, linear control range from 0 to 15/16, step size = 1/16 1111 = 15/16 ⋮ 0001 = 1/16 0000 = 0 (default) Table 2-44. Brightness and Contrast Range Extender Register Subaddress Default 7 2Fh 00h 6 Reserved 5 4 Contrast multiplier 3 2 1 Brightness multiplier [3:0] 0 Contrast multiplier (MC): Increases the contrast control range for composite and S-Video modes. 0 = 2x contrast control range (default), Gain = n/64 – 1 where n is the contrast control and 64 ≤ n ≤ 255 1 = Normal contrast control range, Gain = n/128 where n is the contrast control and 0 ≤ n ≤ 255 Brightness multiplier [3:0] (MB): Increases the brightness control range for composite and S-Video modes from 1x to 16x. 0h = 1x 1h = 2x 3h = 4x 7h = 8x Fh = 16x Note: In general, the brightness multiplier should be set to 0h for 10-bit outputs and 3h for 8-bit outputs 52 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-45. Sync Control Register Subaddress Default 32h 00h 7 6 Reserved 5 4 Polarity FID 3 Polarity VS 2 Polarity HS 1 VS/VBLK 0 HS/CS 1 Output format [2:0] 0 Polarity FID: Determines polarity of FID terminal 0 = First field high, second field low (default) 1 = First field low, second field high Polarity VS: Determines polarity of VS terminal 0 = Active low (default) 1 = Active high Polarity HS: Determines polarity of HS terminal 0 = Active low (default) 1 = Active high VS/VBLK: 0 = VS terminal outputs vertical sync (default) 1 = VS terminal outputs vertical blank HS/CS: 0 = HS terminal outputs horizontal sync (default) 1 = HS terminal outputs composite sync Table 2-46. Output Formatter Control 1 Register Subaddress Default 7 Reserved 33h 40h 6 YCbCr code range 5 CbCr code 4 3 Reserved 2 YCbCr output code range: 0 = ITU-R BT.601 coding range (Y ranges from 64 to 940. Cb and Cr range from 64 to 960.) 1 = Extended coding range (Y, Cb, and Cr range from 4 to 1016) (default) CbCr code format: 0 = Offset binary code (2s complement + 512) (default) 1 = Straight binary code (2s complement) Output format [2:0]: 000 = 10-bit 4:2:2 (pixel x 2 rate) with embedded syncs (ITU-R BT.656) (default) 001 = 20-bit 4:2:2 (pixel rate) with separate syncs 010 = Reserved 011 = 10-bit 4:2:2 with separate syncs 100–111 = Reserved Note: 10-bit mode is also used for the raw VBI output mode when bit 4 (VBI raw) in the luminance processing control 1 register at subaddress 06h is set (see Table 2-19). Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 53 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-47. Output Formatter Control 2 Register Subaddress Default 34h 00h 7 6 Reserved 5 4 Data enable 3 2 Black Screen [1:0] 1 CLK polarity 0 Clock enable 1 0 Data enable: Y[9:0] and C[9:0] output enable 0 = Y[9:0] and C[9:0] high-impedance (default) 1 = Y [9:0] and C[9:0] active Black Screen [1:0]: 00 = Normal operation (default) 01 = Black screen out when TVP5147M1 detects lost lock (using with tuner input but not with VCR) 10 = Black screen out 11 = Black screen out CLK polarity: 0 = Data clocked out on the falling edge of DATACLK (default) 1 = Data clocked out on the rising edge of DATACLK Clock enable: 0 = DATACLK outputs are high-impedance (default) 1 = DATACLK outputs are enabled Table 2-48. Output Formatter Control 3 Register Subaddress Default 35h FFh 7 6 5 GPIO [1:0] 4 AVID [1:0] 3 2 GLCO [1:0] FID [1:0] GPIO [1:0]: FSS terminal function select 00 = GPIO is logic 0 output 01 = GPIO is logic 1 output 10 = Reserved 11 = GPIO is logic input (default) AVID [1:0]: AVID terminal function select 00 = AVID is logic 0 output 01 = AVID is logic 1 output 10 = AVID is active video indicator output 11 = AVID is logic input (default) GLCO [1:0]: GLCO terminal function select 00 = GLCO is logic 0 output 01 = GLCO is logic 1 output 10 = GLCO is genlock output 11 = GLCO is logic input (default) FID [1:0]: FID terminal function select 00 = FID is logic 0 output 01 = FID is logic 1 output 10 = FID is FID output 11 = FID is logic input (default) 54 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-49. Output Formatter Control 4 Register Subaddress Default 36h FFh 7 6 VS/VBLK [1:0] 5 4 HS/CS [1:0] 3 2 C_1 [1:0] 1 0 C_0 [1:0] VS/VBLK [1:0]: VS terminal function select 00 = VS is logic 0 output 01 = VS is logic 1 output 10 = VS/VBLK is vertical sync or vertical blank output corresponding to bit 1 (VS/VBLK) in the sync control register at subaddress 32h (see Table 2-45) 11 = VS is logic input (default) HS/CS [1:0]: HS terminal function select 00 = HS is logic 0 output 01 = HS is logic 1 output 10 = HS/CS is horizontal sync or composite sync output corresponding to bit 0 (HS/CS) in the sync control register at subaddress 32h (see Table 2-45) 11 = HS is logic input (default) C_1 [1:0]: C_1 terminal function select 00 = C_1 is logic 0 output 01 = C_1 is logic 1 output 10 = Reserved 11 = C_1 is logic input (default) C_0 [1:0]: C_0 terminal function select 00 = C_0 is logic 0 output 01 = C_0 is logic 1 output 10 = Reserved 11 = C_0 is logic input (default) Note: C_x functions are available only in the 10-bit output mode. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 55 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-50. Output Formatter Control 5 Register Subaddress Default 37h FFh 7 6 C_5 [1:0] 5 4 C_4 [1:0] 3 2 C_3 [1:0] 1 0 C_2 [1:0] C_5 [1:0]: C_5 terminal function select 00 = C_5 is logic 0 output 01 = C_5 is logic 1 output 10 = Reserved 11 = C_5 is logic input (default) C_4 [1:0]: C_4 terminal function select 00 = C_4 is logic 0 output 01 = C_4 is logic 1 output 10 = Reserved 11 = C_4 is logic input (default) C_3 [1:0]: C_3 terminal function select 00 = C_3 is logic 0 output 01 = C_3 is logic 1 output 10 = Reserved 11 = C_3 is logic input (default) C_2 [1:0]: C_2 terminal function select 00 = C_2 is logic 0 output 01 = C_2 is logic 1 output 10 = Reserved 11 = C_2 is logic input (default) Note: C_x functions are available only in the 10-bit output mode. 56 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-51. Output Formatter Control 6 Register Subaddress Default 38h FFh 7 6 5 C_9 [1:0] 4 3 C_8 [1:0] 2 1 C_7 [1:0] 0 C_6 [1:0] C_9 [1:0]: C_9 terminal function select 00 = C_9 is logic 0 output 01 = C_9 is logic 1 output 10 = Reserved 11 = C_9 is logic input (default) C_8 [1:0]: C_8 terminal function select 00 = C_8 is logic 0 output 01 = C_8 is logic 1 output 10 = Reserved 11 = C_8 is logic input (default) C_7 [1:0]: C_7 terminal function select 00 = C_7 is logic 0 output 01 = C_7 is logic 1 output 10 = Reserved 11 = C_7 is logic input (default) C_6 [1:0]: C_6 terminal function select 00 = C_6 is logic 0 output 01 = C_6 is logic 1 output 10 = Reserved 11 = C_6 is logic input (default) Table 2-52. Clear Lost Lock Detect Register Subaddress Default 7 39h 00h 6 5 4 Reserved 3 2 1 0 Clear lost lock detect Clear lost lock detect: Clear bit 4 (lost lock detect) in the status 1 register at subaddress 3Ah (see Table 2-53) 0 = No effect (default) 1 = Clears bit 4 in the status 1 register Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 57 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-53. Status 1 Register Subaddress 7 Peak white detect status 3Ah Read only 6 Line-alternating status 5 Field rate status 4 Lost lock detect 3 Color subcarrier lock status 2 Vertical sync lock status 1 Horizontal sync lock status 0 TV/VCR status Peak white detect status: 0 = Peak white is not detected 1 = Peak white is detected Line-alternating status: 0 = Non line-alternating 1 = Line-alternating Field rate status: 0 = 60 Hz 1 = 50 Hz Lost lock detect: 0 = No lost lock since this bit was last cleared 1 = Lost lock since this bit was last cleared Color subcarrier lock status: 0 = Color subcarrier is not locked 1 = Color subcarrier is locked Vertical sync lock status: 0 = Vertical sync is not locked 1 = Vertical sync is locked Horizontal sync lock status: 0 = Horizontal sync is not locked 1 = Horizontal sync is locked TV/VCR status: 0 = TV 1 = VCR 58 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-54. Status 2 Register Subaddress 3Bh Read only 7 Signal present 6 Weak signal detection 5 PAL switch polarity 4 Field sequence status 3 Color killed 2 1 Macrovision detection [2:0] 0 Signal present detection: 0 = Signal not present 1 = Signal present Weak signal detection: 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field: 0 = PAL switch is 0b 1 = PAL switch is 1b Field sequence status: 0 = Even field 1 = Odd field Color killed: 0 = Color killer not active 1 = Color killer activated Macrovision detection [2:0]: 000 = No copy protection 001 = AGC pulses/pseudo syncs present (Type 1) 010 = 2-line colorstripe only present 011 = AGC pulses/pseudo syncs and 2-line colorstripe present (Type 2) 100 = Reserved 101 = Reserved 110 = 4-line colorstripe only present 111 = AGC pulses/pseudo syncs and 4-line colorstripe present (Type 3) Table 2-55. AGC Gain Status Register Subaddress Subaddress 3Ch 3Dh 3Ch–3Dh Read only 7 6 5 4 3 Fine Gain [7:0] Coarse Gain [3:0] 2 1 0 Fine Gain [11:8] Fine gain [11:0]: This register provides the fine gain value of sync channel. 1111 1111 1111 = 1.9995 1000 0000 0000 = 1 0010 0000 0000 = 0.5 Coarse gain [3:0]: This register provides the coarse gain value of sync channel. 1111 = 2 0101 = 1 0000 = 0.5 The AGC gain status register is updated automatically by the TVP5147M1 decoder when AGC is on. In manual gain control mode, these register values are not updated by the TVP5147M1 decoder. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 59 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-56. Video Standard Status Register Subaddress 7 Autoswitch 3Fh Read only 6 5 4 3 2 Reserved 1 Video standard [2:0] 0 Autoswitch mode 0 = Single standard set 1 = Autoswitch mode enabled Video standard [2:0]: CVBS and S-Video Reserved (M, J) NTSC (B, D, G, H, I, N) PAL (M) PAL (Combination-N) PAL NTSC 4.43 SECAM PAL 60 000 001 010 011 100 101 110 111 Component Video Reserved Component 525 Component 625 Reserved Reserved Reserved Reserved Reserved This register contains information about the detected video standard that the device is currently operating. When autoswitch code is running, this register must be tested to determine which video standard has been detected. Table 2-57. GPIO Input 1 Register Subaddress 7 C_7 40h Read only 6 C_6 5 C_5 4 C_4 3 C_3 2 C_2 1 C_1 0 C_0 C_x input status: 0 = Input is low 1 = Input is high These status bits are valid only when terminals are used as inputs and are updated at every line. 60 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-58. GPIO Input 2 Register Subaddress 41h Read only 7 GPIO 6 AVID 5 GLCO 4 VS 3 HS 2 FID 1 C_9 0 C_8 1 0 GPIO input terminal status: 0 = Input is a low 1 = Input is a high AVID input terminal status: 0 = Input is a low 1 = Input is a high GLCO input terminal status: 0 = Input is a low 1 = Input is a high VS input terminal status: 0 = Input is a low 1 = Input is a high HS input status: 0 = Input is a low 1 = Input is a high FID input status: 0 = Input is a low 1 = Input is a high C_x input status: 0 = Input is a low 1 = Input is a high These status bits are valid only when terminals are used as inputs and are updated at every line. Table 2-59. AFE Coarse Gain for CH 1 Register Subaddress Default 7 46h 20h 6 5 4 3 CGAIN 1 [3:0] 2 Reserved CGAIN 1 [3:0]: Coarse Gain = 0.5 + (CGAIN 1)/10 where 0 ≤ CGAIN 1 ≤ 15 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 61 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-60. AFE Coarse Gain for CH 2 Register Subaddress Default 47h 20h 7 6 5 4 3 2 CGAIN 2 [3:0] 1 0 1 0 Reserved CGAIN 2 [3:0]: Coarse Gain = 0.5 + (CGAIN 2)/10 where 0 ≤ CGAIN 2 ≤ 15. This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 Table 2-61. AFE Coarse Gain for CH 3 Register Subaddress Default 7 48h 20h 6 5 4 3 CGAIN 3 [3:0] 2 Reserved CGAIN 3 [3:0]: Coarse Gain = 0.5 + (CGAIN 3)/10 where 0 ≤ CGAIN 3 ≤ 15. This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 62 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-62. AFE Coarse Gain for CH 4 Register Subaddress Default 49h 20h 7 6 5 4 3 2 CGAIN 4 [3:0] 1 0 Reserved CGAIN 4 [3:0]: Coarse Gain = 0.5 + (CGAIN 4)/10 where 0 ≤ CGAIN 4 ≤ 15. This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 Table 2-63. AFE Fine Gain for Pb Register Subaddress Default Subaddress 4Ah 4Bh 4Ah–4Bh 900h 7 6 5 4 3 2 1 0 FGAIN 1 [7:0] Reserved FGAIN 1 [11:8] FGAIN 1 [11:0]: This fine gain applies to component Pb. Fine Gain = (1/2048) × FGAIN 1, where 0 ≤ FGAIN 1 ≤ 4095 This register is only updated when the MSB (register 4Bh) is written to. This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125 (default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to 0000 0000 0000 = Reserved Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 63 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-64. AFE Fine Gain for Y_Chroma Register Subaddress Default Subaddress 4Ch 4Dh 4Ch–4Dh 900h 7 6 5 4 3 2 1 0 FGAIN 2 [7:0] Reserved FGAIN 2 [11:8] FGAIN 2 [11:0]: This gain applies to component Y channel or S-video chroma (see AFE fine gain for Pb register, Table 2-63). This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125 (default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to 0000 0000 0000 = Reserved Table 2-65. AFE Fine Gain for Pr Register Subaddress Default Subaddress 4Eh 4Fh 4Eh–4Fh 900h 7 6 5 4 3 2 1 0 FGAIN 3 [7:0] Reserved FGAIN 3 [11:8] FGAIN 3 [11:0]: This fine gain applies to component Pr (see AFE fine gain for Pb register, Table 2-63). This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125 (default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to 0000 0000 0000 = Reserved Table 2-66. AFE Fine Gain for CVBS_Luma Register Subaddress Default Subaddress 50h 51h 50h–51h 900h 7 6 5 4 3 2 1 0 FGAIN 4 [7:0] Reserved FGAIN 4 [11:8] FGAIN 4 [11:0]: This fine gain applies to CVBS or S-video luma (see AFE fine gain for Pb register, Table 2-63). This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125 (default) 1000 0000 0000 = 1 0100 0000 0000 = 0.5 0011 1111 1111 to 0000 0000 0000 = Reserved 64 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-67. Field ID Control Register Subaddress Default 7 57h 00h 6 5 4 3 Reserved 2 1 656 version 0 FID control 656 version: 0 = ITU-R BT.656-4 (default) 1 = ITU-R BT.656-3 FID control: 0 = 0→1 adapts to field 1, 1→0 adapts to field 1 + field 2 (default) 1 = 0→1 adapts to field 2, 1→0 adapts to field 1 + field 2 (for TVP5147M1 EVM) Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 65 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-68. F-Bit and V-Bit Decode Control 1 Register Subaddress Default 69h 00h 7 6 Reserved 5 4 VPLL 3 Adaptive 2 Reserved 1 0 F-bit Mode [1:0] VPLL: VPLL time constant control 0 = VPLL adapts the time constant to the input signal (default) 1 = VPLL time constants are fixed Adaptive: 0 = Enable F-bit and V-bit adaptation to detected lines per frame (default) 1 = Disable F-bit and V-bit adaptation to detected lines per frame F-bit mode: 00 = Auto mode. If lines per frame is standard decode F and V bits as per 656 standard from line count else decode F bit from vsync input and set V bit = 0b (default) 01 = Decode F and V bits from input syncs 10 = Reserved 11 = Always decode F and V bits from line count This register is used in conjunction with register 75h as indicated below: REGISTER 69H BIT 1 BIT 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 REGISTER 75H BIT 3 BIT 2 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 MODE Reserved TVP5160 TVP5160 Reserved Reserved Reserved Reserved Reserved Reserved Reserved STANDARD LPF F V Reserved Reserved 656 656 656 656 Reserved Reserved Reserved Reserved 656 656 656 656 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 1 0 0 TVP5146 656 656 1 1 1 1 1 1 0 1 1 1 0 1 TVP5146 TVP5146 Reserved 656 656 Reserved 656 656 Reserved NONSTANDARD LPF F V Reserved Reserved Toggle Switch9 Pulse 0 Reserved Reserved Reserved Reserved Toggle Switch9 Pulse 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Even = 1 Switch Odd = toggle Toggle Switch Pulse Switch Reserved Reserved 656 = ITU-R BT.656 standard Toggle = Toggles from field to field Pulse = Pulses low for 1 line prior to field transition Switch = V bit switches high before the F-bit transition and low after the F-bit transition Switch9 = V bit switches high 1 line prior to the F-bit transition, then low after nine lines Reserved = Not used 66 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-69. Back-End AGC Control Register Subaddress Default 6Ch 08h 7 6 5 4 Reserved 3 1 2 Peak 1 Color 0 Sync This register disables the back-end AGC when the front-end AGC uses specific amplitude references (sync-height, color burst, or composite peak) to decrement the front-end gain. For example, writing 0x09 to this register disables the back-end AGC whenever the frontend AGC uses the sync-height to decrement the front-end gain. Peak: Disables back-end AGC when the front-end AGC uses the composite peak as an amplitude reference. 0 = Disabled (default) 1 = Enabled Color: Disables back-end AGC when the front-end AGC uses the color burst as an amplitude reference. 0 = Disabled (default) 1 = Enabled Sync: Disables back-end AGC when the front-end AGC uses the sync height as an amplitude reference. 0 = Disabled (default) 1 = Enabled Table 2-70. AGC Decrement Speed Register Subaddress Default 7 6Fh 04h 6 5 Reserved 4 3 2 1 AGC decrement speed [2:0] 0 1 0 1 0 AGC decrement speed: Adjusts gain decrement speed. Only used for composite/luma peaks. 111 = 7 (slowest) 110 = 6 (default) ⋮ 000 = 0 (fastest) Table 2-71. ROM Version Register Subaddress 7 70h Read only 6 5 4 3 ROM version [7:0] 2 ROM Version [7:0]: ROM revision number Table 2-72. RAM Version MSB Register Subaddress 7 71h Read only 6 5 4 3 RAM version MSB [7:0] 2 RAM version MSB [7:0]: This register identifies the MSB of the RAM code revision number. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 67 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-73. AGC White Peak Processing Register Subaddress Default 7 Luma peak A 74h 00h 6 Reserved 5 Color burst A 4 Sync height A 3 Luma peak B 2 Composite peak 1 Color burst B 0 Sync height B Luma peak A: Use of the luma peak as a video amplitude reference for the back-end feed-forward type AGC algorithm 0 = Enabled (default) 1 = Disabled Color burst A: Use of the color burst amplitude as a video amplitude reference for the back-end Note: Not available for SECAM, component, and B/W video sources. 0 = Enabled (default) 1 = Disabled Sync height A: Use of the sync height as a video amplitude reference for the back-end feed-forward type AGC algorithm 0 = Enabled (default) 1 = Disabled Luma peak B: Use of the luma peak as a video amplitude reference for front-end feedback type AGC algorithm 0 = Enabled (default) 1 = Disabled Composite peak: Use of the composite peak as a video amplitude reference for front-end feedback type AGC algorithm Note: Required for CVBS video sources 0 = Enabled (default) 1 = Disabled Color burst B: Use of the color burst amplitude as a video amplitude reference for front-end feedback type AGC algorithm Note: Not available for SECAM, component, and B/W video sources 0 = Enabled (default) 1 = Disabled Sync height B: Use of the sync-height as a video amplitude reference for front-end feedback type AGC algorithm 0 = Enabled (default) 1 = Disabled Note: If all 4 bits of the lower nibble are set to logic 1 (that is, no amplitude reference selected), then the front-end analog and digital gains are automatically set to nominal values of 2 and 2304, respectively. If all 4 bits of the upper nibble are set to logic 1 (that is, no amplitude reference selected), then the back-end gain is set automatically to unity. If the input sync height is greater than 100% and the AGC-adjusted output video amplitude becomes less than 100%, then the back-end scale factor attempts to increase the contrast in the back end to restore the video amplitude to 100%. 68 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-74. F-Bit and V-Bit Control 2 Register Subaddress Default 75h 12h 7 Rabbit 6 5 4 Fast lock Reserved 3 2 F and V [1:0] 1 Phase detector 0 HPLL Rabbit: Enable rabbit ear 0 = Disabled (default) 1 = Enabled Fast lock: Enable fast lock where vertical PLL is reset and a 2-second timer is initialized when vertical lock is lost; during time-out the detected input VSYNC is output. 0 = Disabled 1 = Enabled (default) F and V [1:0] F AND V LINES PER FRAME Standard Nonstandard even Nonstandard odd Standard Nonstandard Standard Nonstandard 00 = (default) 01 = 10 = F BIT ITU-R BT 656 Forced to 1 Toggles ITU-R BT 656 Toggles ITU-R BT 656 Pulsed mode Reserved 11 = V BIT ITU-R BT 656 Switch at field boundary Switch at field boundary ITU-R BT 656 Switch at field boundary ITU-R BT 656 Switch at field boundary Phase detector: Enable integral window phase detector 0 = Disabled 1 = Enabled (default) HPLL: Enable horizontal PLL to free run 0 = Disabled (default) 1 = Enabled Table 2-75. VCR Trick Mode Control Register Subaddress Default 7 Switch header 76h 8Ah 6 5 4 3 2 Horizontal shake threshold [6:0] 1 0 Switch header: When in VCR trick mode, the header noisy area around the head switch is skipped. 0 = Disabled 1 = Enabled (default) Horizontal shake threshold [6:0]: 000 0000 = Zero threshold 000 1010 = 0Ah (default) 111 1111 = Largest threshold Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 69 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-76. Horizontal Shake Increment Register Subaddress Default 77h 64h 7 6 5 4 3 Horizontal shake increment [7:0] 2 1 0 1 AGC increment speed [2:0] 0 Horizontal shake increment [7:0]: 000 0000 =0 000 1010 = 64h (default) 111 1111 = FFh Table 2-77. AGC Increment Speed Register Subaddress Default 78h 06h 7 6 5 Reserved 4 3 2 AGC increment speed [2:0]: Adjusts gain increment speed. 111 = 7 (slowest) 110 = 6 (default) ⋮ 000 = 0 (fastest) Table 2-78. AGC Increment Delay Register Subaddress Default 79h 1Eh 7 6 5 4 3 AGC increment delay [7:0] 2 1 0 AGC increment delay: Number of frames to delay gain increments 1111 1111 = 255 ⋮ 0001 1110 = 30 (default) ⋮ 0000 0000 = 0 Table 2-79. Analog Output Control 1 Register Subaddress Default 7 7Fh 00h 6 5 Reserved 4 3 2 AGC enable 1 Input select 0 Analog output enable AGC enable: 0 = Enabled (default) 1 = Disabled, manual gain mode (see Table 2-121) Input select: 00 = Input selected by TVP5147M1 decoder (see Table 2-12) (default) 01 = Input selected manually (see Table 2-121) Analog output enable: 0 = VI_1_A is input (default) 1 = VI_1_A is analog video output 70 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-80. Chip ID MSB Register Subaddress 80h Read only 7 6 5 4 3 CHIP ID MSB[7:0] 2 1 0 1 0 1 0 1 0 1 0 Capture CHIP ID MSB[7:0]: This register identifies the MSB of the device ID. Value = 51h Table 2-81. Chip ID LSB Register Subaddress 81h Read only 7 6 5 4 3 CHIP ID LSB [7:0] 2 CHIP ID LSB [7:0]: This register identifies the LSB of the device ID. Value = 47h Table 2-82. RAM Version LSB Register Subaddress 82h Read only 7 6 5 4 3 RAM version LSB [7:0] 2 RAM version LSB [7:0]: This register identifies the LSB of the RAM code revision number. Example: Patch Release = v07.02.00 ROM Version = 07h RAM Version MSB = 02h RAM Version LSB = 00h Table 2-83. Color PLL Speed Control Register Subaddress Default 83h 09h 7 6 5 4 3 2 Reserved Speed[3:0] Speed [3:0]: Color PLL speed control 1001 = Faster (default) 1010 = 1011 = Slower Other = Reserved Table 2-84. Status Request Register Subaddress Default 7 97h 00h 6 5 4 Reserved 3 2 Capture: Setting a 1b in this register causes the internal processor to capture the current settings of the AGC status and the vertical line count registers. Because this capture is not immediate, it is necessary to check for completion of the capture by reading the capture bit repeatedly after setting it and waiting for it to be cleared by the internal processor. Once the capture bit is 0b, the AGC status and vertical line counters (3Ch/3Dh and 9Ah/9Bh) have been updated and can be safely read in any order. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 71 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-85. Vertical Line Count Register Subaddress 9Ah–9Bh Read only Subaddress 9Ah 9Bh 7 6 5 4 3 Vertical line [7:0] 2 1 Reserved 0 Vertical line [9:8] Vertical line [9:0]: Represent the detected a total number of lines from the previous frame. This can be used with nonstandard video signals such as a VCR in trick mode to synchronize downstream video circuitry. Because this register is a double-byte register, it is necessary to capture the setting into the register to ensure that the value is not updated between reading the lower and upper bytes. To cause this register to capture the current settings, bit 0 of the status request register (subaddress 97h) must be set to a 1b. Once the internal processor has updated and can be read. Either byte may be read first since no further update occurs until bit 0 of 97h is set to 1b again. Table 2-86. AGC Decrement Delay Register Subaddress Default 7 9Eh 1Eh 6 5 4 3 AGC decrement delay [7:0] 2 1 0 AGC decrement delay: Number of frames to delay gain decrements 1111 1111 = 255 ⋮ 0001 1110 = 30 (default) ⋮ 0000 0000 = 0 72 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-87. VDP TTX Filter and Mask Register Subaddress B1h Default 00h Subaddress B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh B2h 00h 7 B3h 00h 6 Filter Filter Filter Filter Filter Filter Filter Filter Filter Filter B4h 00h 1 1 1 1 1 2 2 2 2 2 B5h 00h 5 Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 B6h 00h 4 B7h 00h 3 B8h 00h 2 Filter Filter Filter Filter Filter Filter Filter Filter Filter Filter 1 1 1 1 1 2 2 2 2 2 B9h 00h 1 Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5 Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5 BAh 00h 0 For an NABTS system, the packet prefix consists of five bytes. Each byte contains 4 data bits (D[3:0]) interlaced with 4 Hamming protection bits (H[3:0]): Bit 7 D[3] Bit 6 H[3] Bit 5 D[2] Bit 4 H[2] Bit 3 D[1] Bit 2 H[1] Bit 1 D[0] Bit 0 H[0] Only the data portion D[3:0] from each byte is applied to a teletext filter function with corresponding pattern bits P[3:0] and mask bits M[3:0]. The filter ignores hamming protection bits. For a WST system (PAL or NTSC), the packet prefix consists of two bytes. The two bytes contain three bits of magazine number (M[2:0]) and five bits of row address (R[4:0]), interlaced with eight Hamming protection bits H[7:0]: Bit 7 R[0] R[4] Bit 6 H[3] H[7] Bit 5 M[2] R[3] Bit 4 H[2] H[6] Bit 3 M[1] R[2] Bit 2 H[1] H[5] Bit 1 M[0] R[1] Bit 0 H[0] H[4] The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1 in the LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the pattern register to the first data bit on the transaction. If these match, then a true result is returned. A 0 in a bit of mask means that the filter module must ignore that data bit of the transaction. If all 0s are programmed in the mask bits, then the filter matches all patterns returning a true result (default 00h). Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 73 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-88. VDP TTX Filter Control Register Subaddress Default 7 BBh 00h 6 Reserved 5 4 3 Filter logic [1:0] 2 Mode 1 TTX filter 2 enable 0 TTX filter 1 enable Filter logic [1:0]: Allow different logic to be applied when combining the decision of Filter 1 and Filter 2 as follows: 00 = NOR (default) 01 = NAND 10 = OR 11 = AND Mode: Indicates which teletext mode is in use: 0 = Teletext filter applies to 2 header bytes (default) 1 = Teletext filter applies to 5 header bytes TTX filter 2 enable: Provides for enabling the teletext filter function within the VDP. 0 = Disable (default) 1 = Enable TTX filter 1 enable: Provides for enabling the teletext filter function within the VDP. 0 = Disable (default) 1 = Enable If the filter matches or if the filter mask is all zeros, then a true result is returned. 74 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 1P1[3] D1[3] 1M1[3] 1P1[2] D1[2] 1M1[2] 1P1[1] D1[1] 1M1[1] 1P1[0] D1[0] 1M1[0] NIBBLE 1 D2[3:0] NIBBLE 2 1P2[3:0] 1M2[3:0] PASS 1 D3[3:0] 1P3[3:0] Filter 1 Enable NIBBLE 3 1M3[3:0] 00 D4[3:0] 01 NIBBLE 4 1P4[3:0] PASS 1M4[3:0] 10 D5[3:0] 1P5[3:0] NIBBLE 5 11 1M5[3:0] 2 Filter Logic FILTER 1 D1..D5 2P1..2P5 PASS 2 FILTER 2 2M1..2M5 Filter 2 Enable Figure 2-19. Teletext Filter Function Table 2-89. VDP FIFO Word Count Register Subaddress 7 BCh Read only 6 5 4 3 FIFO word count [7:0] 2 1 0 FIFO word count [7:0]: This register provides the number of words in the FIFO. Note: 1 word equals 2 bytes. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 75 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-90. VDP FIFO Interrupt Threshold Register Subaddress Default BDh 80h 7 6 5 4 3 2 1 0 1 0 FIFO reset Threshold [7:0] Threshold [7:0]: This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value. Note: 1 word equals 2 bytes. Table 2-91. VDP FIFO Reset Register Subaddress Default BFh 00h 7 6 5 4 Reserved 3 2 FIFO reset: Writing any data to this register clears the FIFO and VDP data register (CC, WSS, VITC and VPS). After clearing, this register is automatically cleared. Table 2-92. VDP FIFO Output Control Register Subaddress Default C0h 00h 7 6 5 4 Reserved 3 2 1 0 Host access enable Host access enable: This register is programmed to allow the host port access to the FIFO or allowing all VDP data to go out the video output. 0 = Output FIFO data to the video output Y[9:2] (default) 1 = Allow host port access to the FIFO data Table 2-93. VDP Line Number Interrupt Register Subaddress Default 7 Field 1 enable C1h 00h 6 Field 2 enable 5 4 3 2 Line number [5:0] 1 0 Field 1 interrupt enable: 0 = Disabled (default) 1 = Enabled Field 2 interrupt enable: 0 = Disabled (default) 1 = Enabled Line number [5:0]: Interrupt line number (default 00h) This register is programmed to trigger an interrupt when the video line number exceeds this value in bits [5:0]. This interrupt must be enabled at address F4h. Note: The line number value of zero or one is invalid and does not generate an interrupt. 76 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-94. VDP Pixel Alignment Register Subaddress Default C2h–C3h 01Eh Subaddress C2h C3h 7 6 5 4 3 Pixel alignment [7:0] 2 1 Reserved 0 Pixel alignment [9:0] Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP controller initiates the program from one line standard to the next line standard; for example, the previous line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be programmed before the current settings are required. The default value is 0x1E and has been tested with every standard supported here. A new value is needed only if a custom standard is in use. Table 2-95. VDP Line Start Register Subaddress Default D6h 06h 7 6 5 4 3 VDP line start [7:0] 2 1 0 VDP line start [7:0]: Sets the VDP line starting address for the global line mode register This register must be set properly before enabling the line mode registers. The VDP processor works only the VBI region set by this register and the VDP line stop register. Table 2-96. VDP Line Stop Register Subaddress Default D7h 1Bh 7 6 5 4 3 VDP line stop [7:0] 2 1 0 1 0 VDP line stop [7:0]: Sets the VDP stop line. Table 2-97. VDP Global Line Mode Register Subaddress Default 7 D8h FFh 6 5 4 3 Global line mode [7:0] 2 Global line mode [7:0]: VDP processing for multiple lines set by VDP start line register D6h and stop line register D7h. Global line mode register has the same bit definitions as the line mode registers (see Table 2-119). General line mode has priority over the global line mode. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 77 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-98. VDP Full Field Enable Register Subaddress Default D9h 00h 7 6 5 4 Reserved 3 2 1 0 Full field enable Full field enable: 0 = Disabled full field mode(default) 1 = Enabled full field mode This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode register programmed with FFh are sliced with the definition of the VDP full field mode register at subaddress DAh. Values other than FFh in the line mode registers allow a different slice mode for that particular line. Table 2-99. VDP Full Field Mode Register Subaddress Default DAh FFh 7 6 5 4 3 Full field mode [7:0] 2 1 0 Full field mode [7:0]: This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings take priority over the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field mode. The full field mode register has the same bit definition as line mode registers (default FFh). Global line mode has priority over the full field mode. Table 2-100. VBUS Data Access With No VBUS Address Increment Register Subaddress Default E0h 00h 7 6 5 4 3 2 1 0 VBUS data [7:0] VBUS data [7:0]: VBUS data register for VBUS single byte read/write transaction. Table 2-101. VBUS Data Access With VBUS Address Increment Register Subaddress Default 7 E1h 00h 6 5 4 3 2 1 0 VBUS data [7:0] VBUS data [7:0]: VBUS data register for VBUS multi-byte read/write transaction. VBUS address is auto-incremented after each data byte read/write. Table 2-102. FIFO Read Data Register Subaddress 7 E2h Read only 6 5 4 3 FIFO Read Data [7:0] 2 1 0 FIFO Read Data [7:0]: This register is provided to access VBI FIFO data through the I2C interface. All forms of teletext data come directly from the FIFO, while all other forms of VBI data can be programmed to come from registers or from the FIFO. If the host port is to be used to read data from the FIFO, then bit 0 (host access enable) in the VDP FIFO output control register at subaddress C0h must be set to 1 (see Table 2-92). 78 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-103. VBUS Address Register Subaddress Default Subaddress E8h E9h EAh E8h 00h E9h 00h 7 EAh 00h 6 5 4 3 VBUS address [7:0] VBUS address [15:8] VBUS address [23:16] 2 1 0 VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user needs to program in these registers the 24-bit address of the internal register to be accessed via host port indirect access mode. Table 2-104. Interrupt Raw Status 0 Register Subaddress 7 FIFO THRS F0h Read only 6 TTX 5 WSS/CGMS 4 VPS/Gemstar 3 VITC 2 CC F2 1 CC F1 0 Line The host Interrupt Raw Status 0 and Interrupt Raw Status 1 registers represent the interrupt status without applying mask bits. FIFO THRS: FIFO threshold passed, unmasked 0 = Not passed 1 = Passed TTX: Teletext data available unmasked 0 = Not available 1 = Available WSS/CGMS: WSS/CGMS data available unmasked 0 = Not available 1 = Available VPS/Gemstar: VPS/Gemstar data available unmasked 0 = Not available 1 = Available VITC: VITC data available unmasked 0 = Not available 1 = Available CC F2: CC field 2 data available unmasked 0 = Not available 1 = Available CC F1: CC field 1 data available unmasked 0 = Not available 1 = Available Line: Line number interrupt unmasked 0 = Not available 1 = Available Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 79 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-105. Interrupt Raw Status 1 Register Subaddress 7 F1h Read only 6 5 Reserved 4 3 H/V lock 2 Macrovision status changed 1 Standard changed 0 FIFO full H/V lock: unmasked 0 = H/V lock status unchanged 1 = H/V lock status changed Macrovision status changed: unmasked 0 = Macrovision status unchanged 1 = Macrovision status changed Standard changed: unmasked 0 = Video standard unchanged 1 = Video standard changed FIFO full: 0 = FIFO not full 1 = FIFO was full during write to FIFO The FIFO full error flag is set when the current line of VBI data cannot enter the FIFO. For example, if the FIFO has only 10 bytes left and teletext is the current VBI line, then the FIFO full error flag is set, but no data is written because the entire teletext line does not fit. However, if the next VBI line is closed caption requiring only 2 bytes of data plus the header, then this goes into the FIFO even if the full error flag is set. 80 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-106. Interrupt Status 0 Register Subaddress 7 FIFO THRS F2h Read only 6 TTX 5 WSS/CGMS 4 VPS/Gemstar 3 VITC 2 CC F2 1 CC F1 0 Line Interrupt Status 0 and Interrupt Status 1 registers represent the interrupt status after applying mask bits. Therefore, the status bits are the result of a logical AND between the raw status and mask bits. The external interrupt terminal is derived from this register as an OR function of all nonmasked interrupts in this register. Reading data from the corresponding register does not clear the status flags automatically. These flags are reset using the corresponding bits in the Interrupt Clear 0 and Interrupt Clear 1 registers. FIFO THRS: FIFO threshold passed, masked 0 = Not passed 1 = Passed TTX: Teletext data available masked 0 = Not available 1 = Available WSS/CGMS: WSS/CGMS data available masked 0 = Not available 1 = Available VPS/Gemstar: VPS/Gemstar data available masked 0 = Not available 1 = Available VITC: VITC data available masked 0 = Not available 1 = Available CC F2: CC field 2 data available masked 0 = Not available 1 = Available CC F1: CC field 1 data available masked 0 = Not available 1 = Available Line: Line number interrupt masked 0 = Not available 1 = Available Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 81 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-107. Interrupt Status 1 Register Subaddress 7 F3h Read only 6 5 Reserved 4 3 H/V lock 2 Macrovision status changed 1 Standard changed 0 FIFO full H/V lock: H/V lock status changed mask 0 = H/V lock status unchanged 1 = H/V lock status changed Macrovision status changed: Macrovision status changed masked 0 = Macrovision status not changed 1 = Macrovision status changed Standard changed: Standard changed masked 0 = Video standard not changed 1 = Video standard changed FIFO full: Masked status of FIFO 0 = FIFO not full 1 = FIFO was full during write to FIFO, see the interrupt mask 1 register at subaddress F5h for details (see Table 2-109) 82 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-108. Interrupt Mask 0 Register Subaddress 7 FIFO THRS F4h Read only 6 TTX 5 WSS/CGMS 4 VPS/Gemstar 3 VITC 2 CC F2 1 CC F1 0 Line The host Interrupt Mask 0 and Interrupt Mask 1 registers can be used by the external processor to mask unnecessary interrupt sources for the Interrupt Status 0 and Interrupt Status 1 register bits, and for the external interrupt terminal. The external interrupt is generated from all nonmasked interrupt flags. FIFO THRS: FIFO threshold passed mask 0 = Disabled (default) 1 = Enabled FIFO_THRES interrupt TTX: Teletext data available mask 0 = Disabled (default) 1 = Enabled TTX available interrupt WSS/CGMS: WSS/CGMS data available mask 0 = Disabled (default) 1 = Enabled WSS/CGMS available interrupt VPS/Gemstar: VPS/Gemstar data available mask 0 = Disabled (default) 1 = Enabled VPS/Gemstar available interrupt VITC: VITC data available mask 0 = Disabled (default) 1 = Enabled VITC available interrupt CC F2: CC field 2 data available mask 0 = Disabled (default) 1 = Enabled CC field 2 available interrupt CC F1: CC field 1 data available mask 0 = Disabled (default) 1 = Enabled CC field 1 available interrupt LINE: Line number interrupt mask 0 = Disabled (default) 1 = Enabled Line_INT interrupt Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 83 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-109. Interrupt Mask 1 Register Subaddress 7 F5h Read only 6 5 Reserved 4 3 H/V lock 2 Macrovision status changed 1 Standard changed 0 FIFO full H/V lock: H/V lock status changed masked 0 = H/V lock status unchanged (default) 1 = H/V lock status changed Macrovision status changed: Macrovision status changed mask 0 = Macrovision status unchanged 1 = Macrovision status changed Standard changed: Standard changed mask 0 = Disabled (default) 1 = Enabled video standard changed FIFO full: FIFO full mask 0 = Disabled (default) 1 = Enabled FIFO full interrupt 84 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-110. Interrupt Clear 0 Register Subaddress 7 FIFO THRS F6h Read only 6 TTX 5 WSS/CGMS 4 VPS/Gemstar 3 VITC 2 CC F2 1 CC F1 0 Line The host Interrupt Clear 0 and Interrupt Clear 1 registers are used by the external processor to clear the interrupt status bits in the host Interrupt Status 0 and Interrupt Status 1 registers. When no nonmasked interrupts remain set in the registers, the external interrupt terminal also becomes inactive. FIFO THRS: FIFO threshold passed clear 0 = No effect (default) 1 = Clear FIFO_THRES bit in status register 0 bit 7 TTX: Teletext data available clear 0 = No effect (default) 1 = Clear TTX available bit in status register 0 bit 6 WSS/CGMS: WSS/CGMS data available clear 0 = No effect (default) 1 = Clear WSS/CGMS available bit in status register 0 bit 5 VPS/Gemstar: VPS/Gemstar data available clear 0 = No effect (default) 1 = Clear VPS/Gemstar available bit in status register 0 bit 4 VITC: VITC data available clear 0 = Disabled (default) 1 = Clear VITC available bit in status register 0 bit 3 CC F2: CC field 2 data available clear 0 = Disabled (default) 1 = Clear CC field 2 available bit in status register 0 bit 2 CC F1: CC field 1 data available clear 0 = Disabled (default) 1 = Clear CC field 1 available bit in status register 0 bit 1 LINE: Line number interrupt clear 0 = Disabled (default) 1 = Clear Line interrupt available bit in status register 0 bit 0 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 85 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-111. Interrupt Clear 1 Register Subaddress F7h Read only 7 6 5 4 Reserved 3 H/V lock 2 Macrovision status changed 1 Standard changed 0 FIFO full H/V lock: Clear H/V lock status changed flag 0 = H/V lock status unchanged 1 = H/V lock status changed Macrovision status changed: Clear Macrovision status changed flag 0 = No effect (default) 1 = Clear bit 2 (Macrovision status changed) in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress F1h Standard changed: Clear standard changed flag 0 = No effect (default) 1 = Clear bit 1 (video standard changed) in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress F1h FIFO full: Clear FIFO full flag 0 = No effect (default) 1 = Clear bit 0 (FIFO full flag) in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress F1h 2.12 VBUS Register Definitions Table 2-112. VDP Closed Caption Data Register Subaddress Subaddress 80 051Ch 80 051Dh 80 051Eh 80 051Fh 80 051Ch – 80 051Fh Read only 7 6 5 4 Closed Caption Closed Caption Closed Caption Closed Caption Field Field Field Field 3 1 byte 1 byte 2 byte 2 byte 2 1 0 1 2 1 2 These registers contain the closed caption data arranged in bytes per field. 86 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-113. VDP WSS Data Register Subaddress 80 0520h – 80 0526h Read only WSS NTSC (CGMS) Subaddress 80 0520h 80 0521h 80 0522h 80 0523h 80 0524h 80 0525h 80 0526h 7 6 b13 b12 b13 b12 5 b5 b11 b19 4 3 b4 b3 b10 b9 b18 b17 Reserved b4 b3 b10 b9 b18 b17 b5 b11 b19 2 b2 b8 b16 1 b1 b7 b15 0 b0 b6 b14 Byte WSS Field 1 Byte 1 WSS Field 1 Byte 2 WSS Field 1 Byte 3 b2 b8 b16 b1 b7 b15 b0 b6 b14 WSS Field 2 Byte 1 WSS Field 2 Byte 2 WSS Field 2 Byte 3 2 b2 b10 1 b1 b9 0 b0 b8 Byte WSS Field 1 Byte 1 WSS Field 1 Byte 2 b2 b10 b1 b9 b0 b8 WSS Field 2 Byte 1 WSS Field 2 Byte 2 These registers contain the wide screen signaling data for NTSC. Bits 0 – 1 represent word 0, aspect ratio Bits 2 – 5 represent word 1, header code for word 2 Bits 6 – 13 represent word 2, copy control Bits 14 – 19 represent word 3, CRC PAL/SECAM Subaddress 80 0520h 80 0521h 80 0522h 80 0523h 80 0524h 80 0525h 80 0526h 7 b7 6 b6 5 b5 b13 b7 b6 b5 b13 4 3 b4 b3 b12 b11 Reserved Reserved b4 b3 b12 b11 Reserved These registers contain the wide screen signaling data for PAL/SECAM: Bits 0 – 3 represent Group 1, Aspect Ratio Bits 4 – 7 represent Group 2, Enhanced Services Bits 8 – 10 represent Group 3, Subtitles Bits 11 – 13 represent Group 4, Others Table 2-114. VDP VITC Data Register Subaddress Subaddress 80 052Ch 80 052Dh 80 052Eh 80 052Fh 80 0530h 80 0531h 80 0532h 80 0533h 80 0534h 80 052Ch – 80 0534h Read only 7 6 5 4 3 VITC frame byte 1 VITC frame byte 2 VITC seconds byte 1 VITC seconds byte 2 VITC minutes byte 1 VITC minutes byte 2 VITC hours byte 1 VITC hours byte 2 VITC CRC byte 2 1 0 These registers contain the VITC data. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 87 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-115. VDP V-Chip TV Rating Block 1 Register Subaddress 7 Reserved 80 0540h Read only 6 14-D 5 PG-D 4 Reserved 3 MA-L 2 14-L 1 PG-L 0 Reserved 1 PG-V 0 Y7-FV 1 TV-Y 0 None TV Parental Guidelines Rating Block 3 14-D: When incoming video program is TV-14-D rated, this bit is set high. PG-D: When incoming video program is TV-PG-D rated, this bit is set high. MA-L: When incoming video program is TV-MA-L rated, this bit is set high. 14-L: When incoming video program is TV-14-L rated, this bit is set high. PG-L: When incoming video program is TV-PG-L rated, this bit is set high. Table 2-116. VDP V-Chip TV Rating Block 2 Register Subaddress 7 MA-S 80 0541h Read only 6 14-S 5 PG-S 4 Reserved 3 MA-V 2 14-V TV Parental Guidelines Rating Block 2 MA-S: When incoming video program is TV-MA-S rated, this bit is set high. 14-S: When incoming video program is TV-14-S rated, this bit is set high. PG-S: When incoming video program is TV-PG-S rated, this bit is set high. MA-V: When incoming video program is TV-MA-V rated, this bit is set high. 14-V: When incoming video program is TV-14-V rated, this bit is set high. PG-V: When incoming video program is TV-PG-S rated, this bit is set high. Y7-FV: When incoming video program is TV-Y7-FV rated, this bit is set high. Table 2-117. VDP V-Chip TV Rating Block 3 Register Subaddress 7 None 80 0542h Read only 6 TV-MA 5 TV-14 4 TV-PG 3 TV-G 2 TV-Y7 TV Parental Guidelines Rating Block 1 None: No block intended TV-MA: When incoming video program is TV-MA rated in TV Parental Guidelines Rating, this bit is set high. TV-14: When incoming video program is TV-14 rated in TV Parental Guidelines Rating, this bit is set high. TV-PG: When incoming video program is TV-PG rated in TV Parental Guidelines Rating, this bit is set high. TV-G: When incoming video program is TV-G rated in TV Parental Guidelines Rating, this bit is set high. TV-Y7: When incoming video program is TV-Y7 rated in TV Parental Guidelines Rating, this bit is set high. TV-Y: When incoming video program is TV-G rated in TV Parental Guidelines Rating, this bit is set high. 88 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-118. VDP V-Chip MPAA Rating Data Register Subaddress 7 Not Rated 80 0543h Read only 6 X 5 NC-17 4 R 3 PG-13 2 PG 1 G 0 NA MPAA Rating Block (E5h) Not Rated: When incoming video program is Not Rated rated in MPAA Rating, this bit is set high. X: When incoming video program is X rated in MPAA Rating, this bit is set high. NC-17: When incoming video program is NC-17 rated in MPAA Rating, this bit is set high. R: When incoming video program is R rated in MPAA Rating, this bit is set high. PG-13: When incoming video program is PG-13 rated in MPAA Rating, this bit is set high. PG: When incoming video program is PG rated in MPAA Rating, this bit is set high. G: When incoming video program is G rated in MPAA Rating, this bit is set high. N/A: When incoming video program is N/A rated in MPAA Rating, this bit is set high. Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 89 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-119. VDP General Line Mode and Line Address Register Subaddress 80 0600h – 80 0611h (default line mode = FFh, line address = 00h) Subaddress 80 0600h 80 0601h 80 0602h 80 0603h 80 0604h 80 0605h 80 0606h 80 0607h 80 0608h 80 0609h 80 060Ah 80 060Bh 80 060Ch 80 060Dh 80 060Eh 80 060Fh 80 0610h 80 0611h 7 6 5 4 3 Line address 1 Line mode 1 Line address 2 Line mode 2 Line address 3 Line mode 3 Line address 4 Line mode 4 Line address 5 Line mode 5 Line address 6 Line mode 6 Line address 7 Line mode 7 Line address 8 Line mode 8 Line address 9 Line mode 9 2 1 0 Line address [7:0]: Line number to process selected line mode register on Line mode x [7:0] Bit 7 0 = Disabled filters 1 = Enabled filters for teletext and CC (null byte filter) (default) Bit 6 0 = Send sliced VBI data to registers only 1 = Send sliced VBI data to FIFO and registers, teletext data only goes to FIFO (default) Bit 5 0 = Allow VBI data with errors in the FIFO 1 = Do not allow VBI data with errors in the FIFO (default) Bit 4 0 = Disabled error detection and correction 1 = Enabled error detection and correction (teletext only) (default) Bit 3 0 = Field 1 1 = Field 2 (default) Bit [2:0] 000 = Teletext (WST625, Chinese Teletext, NABTS 525) 001 = CC (US, European, Japan, China) 010 = WSS (525, 625) 011 = VITC 100 = VPS/PDC (PAL only), Gemstar (NTSC only) 101 = USER 1 110 = USER 2 111 = Reserved (active video) (default) 90 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Table 2-120. VDP VPS/Gemstar Data Register Subaddress 80 0700h – 80 070Ch Read only VPS Subaddress 80 0700h 80 0701h 80 0702h 80 0703h 80 0704h 80 0705h 80 0706h 80 0707h 80 0708h 80 0709h 80 070Ah 80 070Bh 80 070Ch 7 6 5 4 3 2 1 0 2 1 0 VPS byte 1 VPS byte 2 VPS byte 3 VPS byte 4 VPS byte 5 VPS byte 6 VPS byte 7 VPS byte 8 VPS byte 9 VPS byte 10 VPS byte 11 VPS byte 12 VPS byte 13 These registers contain the entire VPS data line except the clock run-in code and the frame code. Gemstar Subaddress 80 0700h 80 0701h 80 0702h 80 0703h 80 0704h 80 0705h 80 0706h 80 0707h 80 0708h 80 0709h 80 070Ah 80 070Bh 80 070Ch 7 6 5 4 3 Gemstar Frame Code Gemstar byte 1 Gemstar byte 2 Gemstar byte 3 Gemstar byte 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 91 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-121. Analog Output Control 2 Register Subaddress Default A0 005Eh B2h 7 6 Reserved 5 4 Input Select [1:0] 3 2 1 0 Gain[3:0] Analog input select [1:0]: These bits are effective when manual input select bit is set to 1 at subaddress 7Fh, bit 1. 00 = CH1 selected 01 = CH2 selected 10 = CH3 selected 11= CH4 selected (default) Analog output PGA gain [3:0]: These bits are effective when analog output AGC is disabled. Gain[3:0] Mode 1 0000 1.30 0001 1.56 0010 1.82 (default) 0011 2.08 0100 2.34 0101 2.60 0110 2.86 0111 3.12 1000 3.38 1001 3.64 1010 3.90 1011 4.16 1100 4.42 1101 4.68 1110 4.94 1111 5.20 Table 2-122. Interrupt Configuration Register Subaddress Default 7 B0 0060h 00h 6 5 Reserved 4 3 2 Polarity 1 0 Reserved Polarity: Interrupt terminal polarity 0 = Active high (default) 1 = Active low 92 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 3 Electrical Specifications 3.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) IOVDD to IOGND DVDD to DGND A33VDD (2) to A33GND (3) MIN MAX UNIT 0.5 4 V –0.2 2 V –0.3 3.6 V –0.2 2 V Supply voltage range A18VDD (4) to A18GND (5) VI to DGND Digital input voltage range –0.5 4.5 V VO to DGND Digital output voltage range –0.5 4.5 V AIN to AGND Analog input voltage range –0.2 2.0 V 0 70 −40 85 –65 150 TA Operating free-air temperature Tstg Storage temperature Commercial Industrial JEDEC Human-body model (HBM) VESD ESD stress voltage (6) AEC-Q100 (8) JEDEC Charged-device model (CDM) (7) (9) AEC-Q100 (10) All pins >1000 All pins >1500 Excluding NC pins >3000 All pins >250 All pins >250 Excluding NC pins >750 °C °C V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) CH1_A33VDD, CH2_A33VDD (3) CH1_A33GND, CH2_A33GND (4) CH1_A18VDD, CH2_A18VDD, A18VDD, A18VDD_REF, PLL_A18VDD (5) CH1_A18GND, CH2_A18GND, A18GND (6) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. (7) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance. (8) Tested per AEC Q100-002 rev D (9) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance. (10) Tested per AEC Q100-011 rev B Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 93 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 3.2 www.ti.com Recommended Operating Conditions IOVDD Supply voltage, digital DVDD Supply voltage, digital AVDD33 Supply voltage, analog AVDD18 Supply voltage, analog VI(P-P) Analog input voltage, analog (ac-coupling necessary) Commercial Commercial MAX 3.3 3.6 1.65 1.8 1.95 1.7 1.8 1.9 3 3.3 3.6 1.65 1.8 1.95 1.7 1.8 1.9 0.5 1 2 Industrial (1) Input voltage high, digital VIL Input voltage low, digital (2) IOH High-level output current IOL Low-level output current TA Operating free-air temperature 3.3 NOM 3 Industrial VIH (1) (2) (3) MIN 0.7 IOVDD V V V V –4 mA VOUT = 2.4 V 4 mA Commercial Industrial 0 70 –40 85 °C Exception: 0.7 AVDD18 for XIN terminal Exception: 0.3 AVDD18 for XIN terminal Currents out of a terminal are given as a negative number Crystal Specifications Frequency NOM MAX 14.31818 Frequency tolerance (1) 94 V VOUT = 2.4 V MIN (1) V V 0.3 IOVDD (3) UNIT UNIT MHz ±50 ppm This number is the required specification for the external crystal/oscillator and is not tested. Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 3.4 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Electrical Characteristics For minimum/maximum values: IOVDD = 3 V to 3.6 V, AVDD33 = 3 V to 3.6 V, Commercial: AVDD18 = 1.65 V to 1.95 V, DVDD = 1.65 V to 1.95 V, TA = 0°C to 70°C Industrial: AVDD18 = 1.7 V to 1.9 V, DVDD = 1.7 V to 1.9 V, TA = −40°C to 85°C For typical values: IOVDD = AVDD33 = 3.3 V, AVDD18 = DVDD = 1.8 V, TA = 25°C DC Electrical Characteristics (1) 3.5 PARAMETER TEST CONDITIONS MIN TYP CVBS 6 S-Video 6 MAX UNIT IDDIO(D) 3.3-V IO digital supply current IDD(D) 1.8-V digital supply current IDD(33A) 3.3-V analog supply current IDD(18A) 1.8-V analog supply current PTOT Total power dissipation, normal operation PSAVE Total power dissipation, power save PDOWN Total power dissipation, power down Ilkg Input leakage current 10 µA CI Input capacitance (2) 8 pF VOH Output voltage high (2) VOL Output voltage low (2) (1) (2) CVBS 55 S-Video 55 CVBS 24 S-Video 39 CVBS mA mA mA 79 mA S-Video 135 S-Video 490 mW 100 mW 10 mW 0.8 IOVDD V 0.2 IOVDD V Measured with a load of 10 kΩ in parallel to 15 pF. Specified by design 3.6 Analog Processing and A/D Converters FS = 30 MSPS for CH1, CH2 PARAMETER TEST CONDITIONS Zi Input impedance, analog video inputs (1) Ci Input capacitance, analog video inputs (1) Vi(PP) Input voltage range MIN TYP MAX 200 Ccoupling = 0.1 µF (1) 0.5 UNIT kΩ 10 pF 1 2 V ΔG Input gain control range 6 dB DNL Differential nonlinearity AFE only –1 ±0.75 +1 LSB INL Integral nonlinearity AFE only –2.5 ±1 +2.5 LSB FR Frequency response Multiburst (60 IRE) XTALK Crosstalk (2) 1 MHz SNR Signal-to-noise ratio, all channels 1 MHz, 1 VPP (1) (3) –6 –0.9 dB –50 54 dB dB GM Gain match Full scale, 1 MHz 1.5 % NS Noise spectrum Luma ramp (100 kHz to full, tilt null) –58 dB DP Differential phase Modulated ramp 0.5 ° DG Differential gain Modulated ramp ±1.5 % (1) (2) (3) Specified by design By characterization only Component inputs only Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 95 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 3.7 www.ti.com Clocks, Video Data, Sync Timing PARAMETER TEST CONDITIONS MIN TYP MAX 45 50 55 Duty cycle, DATACLK t1 High time, DATACLK 18.5 t2 Low time, DATACLK 18.5 t3 Fall time, DATACLK 90% to 10% t4 Rise time, DATACLK t5 Output delay time UNIT % ns ns 4 ns 10% to 90% 4 ns Commercial 10 Industrial 12 ns t2 t1 VOH DATACLK VOL t4 t3 VOH Y, C, AVID, VS, HS, FID Valid Data Valid Data VOL t5 Figure 3-1. Clocks, Video Data, and Sync Timing 3.8 I2C Host Port Timing PARAMETER TEST CONDITIONS MIN TYP MAX 1.3 UNIT t1 Bus free time between STOP and START t2 Data hold time µs t3 Data setup time 100 ns t4 Setup time for a (repeated) START condition 0.6 µs t5 Setup time for a STOP condition 0.6 ns t6 Hold time (repeated) START condition 0.6 t7 Rise time VC1(SDA) and VC0(SCL) signal 250 ns t8 Fall time VC1(SDA) and VC0(SCL) signal 250 ns Cb Capacitive load for each bus line 400 pF fI2C I2C clock frequency 400 kHz 0 Stop 0.9 µs µs Start Stop VC1 (SDA) Data t1 t6 t7 VC0 (SCL) Change Data t6 t3 t2 t4 t8 t5 Figure 3-2. I2C Host Port Timing 96 Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 3.9 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Thermal Specifications PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT θJA Junction-to-ambient thermal resistance, still air Thermal pad soldered to 4-layer High-K PCB 19.04 °C/W θJC Junction-to-case thermal resistance, still air Thermal pad soldered to 4-layer High-K PCB 0.17 °C/W TJ(MAX Maximum junction temperature for reliable operation ) (1) 105 °C The exposed thermal pad must be soldered to a High-K PCB with adequate ground plane. Electrical Specifications Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 97 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 4 www.ti.com Example Register Settings The following example register settings are provided only as a reference. These settings (given the assumed input connector, video format, and output format) set the TVP5147M1 decoder and provide video output. Example register settings for other features and the VBI data processor are not provided here. 4.1 4.1.1 Example 1 Assumptions Input connector: Composite (VI_1_A) (default) Video format: NTSC (J, M), PAL (B, G, H, I, N) or SECAM (default) Note: NTSC-443, PAL-Nc, PAL-M, and PAL-60 are masked from the autoswitch process by default. See the autoswitch mask register at address 04h. Output format: 4.1.2 10-bit ITU-R BT.656 with embedded syncs (default) Recommended Settings Recommended I2C writes: For the given assumptions, only one write is required. All other registers are set up by default. I2C register address 08h = Luminance processing control 3 register I2C data 00h = Optimizes the trap filter selection for NTSC and PAL I2C register address 0Eh = Chrominance processing control 2 register I2C data 04h = Optimizes the chrominance filter selection for NTSC and PAL I2C register address 34h = Output formatter 2 register I2C data 11h = Enables YCbCr output and the clock output Note: HS/CS, VS/VBLK, AVID, FID, and GLCO are logic inputs by default. See output formatter 3 and 4 registers at addresses 35h and 36h, respectively. 98 Example Register Settings Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com 4.2 4.2.1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Example 2 Assumptions Input connector: S-video [VI_2_C (luma), VI_1_C (chroma)] 4.2.2 Video format: NTSC (J, M, 443), PAL (B, D, G, H, I, N, Nc, 60) or SECAM (default) Output format: 10-bit ITU-R BT.656 with discrete sync outputs Recommended Settings Recommended I2C writes: This setup requires additional writes to output the discrete sync 10-bit 4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above. I2C register address 00h = Input select register I2C data 46h = Sets luma to VI_2_C and chroma to VI_1_C I2C register address 04h = Autoswitch mask register I2C data 3Fh = Includes NTSC 443 and PAL (M, Nc, 60) in the autoswitch I2C register address 08h = Luminance processing control 3 register I2C data 00h = Optimizes the trap filter selection for NTSC and PAL I2C register address 0Eh = Chrominance processing control 2 register I2C data 04h = Optimizes the chrominance filter selection for NTSC and PAL I2C register address 33h = Output formatter 1 register I2C data 41h = Selects the 10-bit 4:2:2 output format I2C register address 34h = Output formatter 2 register I2C data 11h = Enables YCbCr output and the clock output I2C register address 36h = Output formatter 4 register I2C data 11h = Enables HS and VS sync outputs Example Register Settings Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 99 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 4.3 4.3.1 www.ti.com Example 3 Assumptions Input connector: Component [VI_1_B (Pb), VI_2_B (Y), VI_3_B (Pr)] 4.3.2 Video format: 480I, 576I Output format: 20-bit ITU-R BT.656 with discrete sync outputs Recommended Settings Recommended I2C writes: This setup requires additional writes to output the discrete sync 20-bit 4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above. I2C register address 00h = Input select register I2C data 95h = Sets Pb to VI_1_B, Y to VI_2_B, and Pr to VI_3_B I2C register address 04h = Autoswitch mask register I2C data 3Fh = Includes NTSC 443 and PAL (M, Nc, 60) in the autoswitch I2C register address 08h = Luminance processing control 3 register I2C data 00h = Optimizes the trap filter selection for NTSC and PAL I2C register address 0Eh = Chrominance processing control 2 register I2C data 04h = Optimizes the chrominance filter selection for NTSC and PAL I2C register address 33h = Output formatter 1 register I2C data 41h = Selects the 20-bit 4:2:2 output format I2C register address 34h = Output formatter 2 register I2C data 11h = Enables YCbCr output and the clock output I2C register address 36h = Output formatter 4 register I2C data AFh = Enables HS and VS sync outputs 100 Example Register Settings Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 5 Application Information 5.1 Application Example C0 FID VS/VBLK 2.2 kΩ A3.3VDD IOVDD3.3 V C3 C4 C5 XTAL1 XTAL2 A1.8VDD 22 Ω C1 C2 2.2 kΩ HS/CS DVDD1.8 V 12 kΩ 0.1 µF (2) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 VI_1_A 75 Ω 1 kΩ 22 kΩ VI_1A VI_1B VI_1C 1 2 75 Ω (3) 0.1 µF (3) 0.1 µF (2) 0.1 µF (3) VI_2A VI_2B VI_2C 75 Ω (3) 0.1 µF (3) VI_3A VI_3B VI_3C 75 Ω (3) 0.1 µF (3) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK HS/CS FID C_0 C_1 DGND DVDD C_2 C_3 C_4 C_5 IOGND IOVDD 22 µF 63 62 61 0.1 µF (2) VOUT C_6 C_7 C_8 C_9 DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF NC NC VI_3_A VI_3_B VI_3_C NC NC TVP5147M1 IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 0.1 µF C6 C7 C8 C9 Y_0 Y_1 Y_2 Y_3 Y_4 0.1 µF Y_5 Y_6 Y_7 Y_8 0.1 µF Y_9 39 40 NC VI_4A NC NC AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS AVID GLCO/I2CA IOVDD IOGND DATACLK 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 NC 0.1 µF 0.1 µF VI_4A 75 Ω IOVDD XTAL1 XTAL2 100 kΩ 14.31818 MHz CL2 CL1 A. B. C. D. 10 kΩ GLCO/I2CA 2.2 kΩ (2) 0.1 µF GND 2 1 3 0.1 µF 0.1 µF I2C Address selection 1−2 Base Addr. 0xBA 2−3 Base Addr. 0xB8 10 kΩ DATACLK GLCO/I2CA AVID FSS RESETB PWDN INTREQ SDA SCL If XTAL1 is connected to clock source, input voltage high must be 1.8 V. TVP5147 can be a drop-in replacement for TVP5146. Terminals 69 and 71 must be connected to ground through pulldown resistors. System level ESD protection is not included in this application circuit, but it is highly recommended on the analog video inputs. Figure 5-1. Example Application Circuit Application Information Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 101 TVP5147M1 SLES140G – JULY 2005 – REVISED FEBRUARY 2012 5.2 www.ti.com Designing With PowerPAD™ Devices The TVP5147 device is housed in a high-performance, thermally enhanced, 80-terminal PowerPAD package (TI package designator: 80PFP). Use of the PowerPAD package does not require special considerations except to note that the thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing the PowerPAD PCB features, the use of solder masks (or other assembly techniques) can be required to prevent any inadvertent shorting by the exposed thermal pad of connection etches or vias under the package. The recommended option, however, is not to run any etches or signal vias under the device, but to have only a grounded thermal land as in the following explanation. Although the actual size of the exposed die pad may vary, the minimum size required for the keep-out area for the 80-terminal PFP PowerPAD package is 8 mm × 8 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, under the PowerPAD package. The thermal land varies in size, depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias, depending on PCB construction. Other requirements for using thermal lands and thermal vias are detailed in the TI application report PowerPAD™ Thermally Enhanced Package (SLMA002), available via the TI web site at http://www.ti.com. For the TVP5147 device, this thermal land must be grounded to the low-impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size must be as large as possible without shorting device signal terminals. The thermal land can be soldered to the exposed thermal pad using standard reflow soldering techniques. While the thermal land can be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More information can be obtained from the TI application report PHY Layout (SLLA020). 102 Application Information Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 TVP5147M1 www.ti.com SLES140G – JULY 2005 – REVISED FEBRUARY 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. REVISION SLES140 COMMENTS Initial release SLES140A Updated Section 2.8 SLES140B Added industrial temperature orderable and updated relevant specifications in Chapter 3 Updated Section 1.2 SLES140C Updated Section 2.11.16, Section 2.11.17 Updated MAX supply voltages for Industrial temperature in Recommended Operating Conditions Added notes throughout Electrical Characteristics to indicate parameters specified by design or specified by characterization only Updated DNL Differential nonlinearity specification and INL Integral nonlinearity (page 80) Updated t5 Output delay time, Industrial (page 81) SLES140D Updated Section 2.8 SLES140E Added AEC–Q100 qualification Changed all instances of 10–bit video decoder to 11–bit Updated register descriptions at addresses 09h, 0Ah, 0Bh Added registers at addresses 11h, 12h, 14h, 26h, 27h, 2Fh Changes all instances of WSS to WSS/CGMS and VPS to VPS/Gemstar Changed A18GND (pin 24) and A18VDD (pin 25) to NC Added Section 3.4 Thermal Specification Updated Figure 5-1 Example Application Circuit SLES140F Section 2.6.1, Removed statement about internal pulldown on I2CA terminal Modified thermal specification Added maximum ESD ratings Modified I2C address 03h register and description Table 2-10, Added RAM version MSB and LSB registers (subaddresses: 71h, 82h) Table 2-72, Added RAM version MSB register (subaddress: 71h) Table 2-82, Added RAM version LSB register (subaddress: 82h) Minor editorial changes SLES140G Figure 2-10, Changed figure and added note. Figure 2-12 and Figure 2-13, Changed figures. Section 2.8, Changed description concerning initializing VBUS register 0xA00014. Figure 5-1, Added note concerning ESD protection. Application Information Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5147M1 103 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TVP5147M1IPFP ACTIVE HTQFP PFP 80 96 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TVP5147M1I TVP5147M1IPFPR ACTIVE HTQFP PFP 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TVP5147M1I TVP5147M1PFP ACTIVE HTQFP PFP 80 96 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TVP5147M1 TVP5147M1PFPR ACTIVE HTQFP PFP 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TVP5147M1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of