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UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
UCx846/7 Current Mode PWM Controller
1 Features
3 Description
•
•
•
The UC1846/7 family of control devices provides all
of the necessary features to implement fixedfrequency, current-mode control schemes while
maintaining a minimum external parts count. The
superior performance of this technique can be
measured in improved line regulation, enhanced load
response characteristics, and a simpler, easier-todesign control loop. Topological advantages include
inherent pulse-by-pulse current limiting capability,
automatic symmetry correction for push-pull
converters, and the ability to parallel power modules
while maintaining equal current sharing.
1
•
•
•
•
•
•
•
•
•
•
Automatic Feedforward Compensation
Programmable Pulse-by-Pulse Current Limiting
Automatic Symmetry Correction in Push-Pull
Configuration
Enhanced Load Response Characteristics
Parallel Operation Capability for Modular Power
Systems
Differential Current Sense Amplifier with Wide
Common Mode Range
Double-Pulse Suppression
500-mA (Peak) Totem-pole Outputs
±1% Band Gap Reference
Undervoltage Lockout
Soft-Start Capability
Shutdown Terminal
500-kHz Operation
Protection circuitry includes built-in undervoltage
lockout and programmable current limit, in addition to
soft-start capability. A shutdown function is also
available, which can initiate either a complete
shutdown with automatic restart or latch the supply
off.
Other features include fully-latched operation, doublepulse suppression, deadline adjust capability, and a
±1% trimmed band gap reference.
2 Applications
•
•
The UC1846 features low outputs in the OFF state,
while the UCx847 features high outputs in the OFF
state.
Telecommunication Power Converters
Industrial Power Converters
Device Information(1)
PART NUMBER
UC1846
UC2846, UC3846
UC2847, UC3847
PACKAGE
BODY SIZE (NOM)
LCCC (20)
8.89 mm × 8.89 mm
CDIP (16)
6.92 mm × 19.56 mm
PLCC (20)
8.96 mm × 8.96 mm
SOIC (16)
7.5 mm × 10.3 mm
PDIP (16)
6.35 mm × 19.3 mm
SOIC (16)
7.5 mm × 10.3 mm
PDIP (16)
6.35 mm × 19.3 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Block Diagram
VIN
15
2
.5k
9
.005µF
180Ÿ
2W
VIN
.1µF
VREF
VC
3.2k
AOUT
11
2N4150
68Ÿ
8
C/S+
UES1402
200µH
VO
1k
4
UCX846
5
100µF
+E/A
BOUT
68Ÿ
14
1k
7
300µF
2N4150
1N4245
UES1402
6
-E/A
.0015
.05µF
1N4245
RT
CT
3.2k
13
COMP
68k
SH-DN
16
C/S-
CS/SS
3
.5Q
.05µF
1
VREF
1.5k
GND
12
1k
3.6k
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1
11.2
11.3
11.4
11.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2010) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed soldering temperature ........................................................................................................................................... 4
Changes from Revision A (February 2002) to Revision B
•
2
Page
Updated Block Diagram. ........................................................................................................................................................ 1
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SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
J or N, DW Packages
16-Pin CDIP or PDIP, SOIC
Top View
FN or FK Packages
20-Pin PLCC or LCCC
Top View
Pin Functions
PIN
I/O
DESCRIPTION
DIL, SOIC NO.
PLCC, LCC
NO.
NAME
1
2
C/S SS
I
Current limit/soft-start programming
2
3
VREF
O
5.1-V reference voltage output
3
4
C/S –
I
Current sense comparator inverting input
4
5
C/S +
I
Current sense comparator non-inverting input
5
7
E/A +
I
Error amplifier inverting input
6
8
E/A –
I
Error amplifier inverting input
7
9
COMP
I/O
8
10
CT
I
Oscillator frequency programming capacitor pin
Oscillator frequency programming resistor pin
Error amplifier output and input to the PWM comparator
9
12
CR
I
10
13
Sync
I/O
Synchronization out from master controller or input of slave controller
11
14
A Out
O
PWM drive signal output A, Pin11 and P14 are complementary
12
15
GND
G
All signals are referenced to this node
13
17
VC
I
Bias supply input for output stage
14
18
B Out
O
PWM drive signal output B, Pin11 and P14 are complementary
15
19
VIN
I
Bias supply input
16
20
Shutdown
I
External shutdown signal input
—
1, 6, 11, 16
N/C
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply Voltage (Pin 15)
MAX
UNIT
40
V
Collector Supply Voltage (Pin 13)
40
V
Output Current, Source or Sink (Pins 11, 14)
500
mA
+VIN
V
Reference Output Current (Pin 2)
–30
mA
Sync Output Current (Pin 10)
–5
mA
Error Amplifier Output Current (Pin 7)
–5
mA
Soft Start Sink Current (Pin 1)
50
mA
Oscillator Charging Current (Pin 9)
5
mA
Power Dissipation at TA = 25°C
1000
mW
Power Dissipation at TC = 25°C
2000
mW
150
°C
Analog Inputs (Pins 3, 4, 5, 6, 16)
–0.3
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VREF terminal external capacitance
NOM
MAX
1
2.2
UNIT
µF
6.4 Thermal Information
UCx846/7
THERMAL METRIC
(1)
N or DW (PDIP or
SOIC)
J or DW (CDIP or
SOIC)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
41.8
73.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.5
34.2
°C/W
RθJB
Junction-to-board thermal resistance
21.8
38.0
°C/W
ψJT
Junction-to-top characterization parameter
13.0
7.7
°C/W
ψJB
Junction-to-board characterization parameter
21.7
37.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
6.5 Electrical Characteristics
TA=–55°C to +125°C for UC1846/7; –40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; VIN=15 V,
RT=10k, CT=4.7 nF, TA=TJ (unless otherwise noted)
PARAMETER
UC1846/7
UC2846/7
TEST CONDITIONS
UC3846/7
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
5.05
5.00
REFERENCE
Output Voltage
TJ = 25°C, IO = 1 mA
5.10
5.15
5.10
5.20
Line Regulation
VIN = 8 V to 40 V
5
20
5
20
mV
Load Regulation
IL = 1 mA to 10 mA
3
15
3
15
mV
Temperature Stability
Over Operating
Range, (1)
Total Output Variation
Line, Load, and
Temperature (1)
Output Noise Voltage
10 Hz ≤ f ≤10 kHz, TJ
= 25°C (1)
Long Term Stability
TJ = 125°C, 1000
Hrs (1)
Short Circuit Output Current
VREF = 0 V
–10
Initial Accuracy
TJ = 25°C
39
43
47
Voltage Stability
VIN =8 V to 40 V
–1%
2%
Temperature Stability
Over Operating
Range (1)
–1%
0.4
5.00
0.4
5.20
4.95
V
mV/°C
5.25
V
100
100
µV
5
5
mV
–45
mA
–45
–10
OSCILLATOR
Sync Output High Level
3.9
Sync Output Low Level
Sync Input High Level
Pin 8 = 0 V
Sync Input Low Level
Pin 8 = 0 V
Sync Input Current
Sync Voltage = 3.9 V,
Pin 8 = 0 V
43
47
–1%
2%
3.9
2.5
3.9
4.35
2.3
V
2.5
3.9
1.5
V
V
2.5
1.3
kHz
–1%
4.35
2.3
39
2.5
V
1.3
1.5
mA
ERROR AMPLIFIER
Input Offset Voltage
Input Bias Current
Input Offset Current
0.5
5
0.5
10
mV
–0.6
–1
–0.6
–2
µA
250
nA
VIN - 2 V
V
40
0
250
VIN - 2 V
40
Common Mode Range
VIN = 8 V to 40 V
Open Loop Voltage Gain
ΔVO = 1.2 to 3 V, VCM
=2V
80
105
80
105
dB
Unity Gain Bandwidth
TJ = 25°C (1)
0.7
1.0
0.7
1.0
MHz
CMRR
VCM = 0 V to 38 V,
VIN = 40 V
75
100
75
100
dB
PSRR
VIN = 8 V to 40 V
80
105
80
105
dB
Output Sink Current
VID = –15 mV to -5 V,
VPIN7 = 1.2 V
2
6
2
6
mA
Output Source Current
VID = 15 mV to -5 V,
VPIN7 = 2.5 V
–0.4
–0.5
–0.4
–0.5
mA
High Level Output Voltage
RL = (Pin 7) 15 kΩ
4.3
4.6
4.3
4.6
Low Level Output Voltage
RL = (Pin 7) 15 kΩ
0.7
1
2.75
3.0
0
V
0.7
1
V
2.75
3.0
V
CURRENT SENSE AMPLIFIER
Amplifier Gain
(1)
(2)
(3)
VPIN 3 = 0 V, Pin 1
Open (2), (3)
2.5
2.5
These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
Parameter measured at trip point of latch with VPIN 5 = VREF, VPIN 6 = 0 V.
Amplifier gain defined as: G = ΔVPIN7 / ΔVPIN4; VPIN4 = 0 to 1.0 V
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Electrical Characteristics (continued)
TA=–55°C to +125°C for UC1846/7; –40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; VIN=15 V,
RT=10k, CT=4.7 nF, TA=TJ (unless otherwise noted)
PARAMETER
UC1846/7
UC2846/7
TEST CONDITIONS
UC3846/7
MIN
TYP
1.1
1.2
MAX
MIN
TYP
1.1
1.2
UNIT
MAX
Maximum Differential Input
Signal (VPIN 4-VPIN 3)
Pin 1 Open (2); RL
(Pin 7) = 15 kW
Input Offset Voltage
VPIN 1 = 0.5 V, Pin 7
Open (2)
CMRR
VCM = 1 V to 12 V
60
83
60
83
dB
PSRR
VIN = 8 V to 40 V
60
84
60
84
dB
Input Bias Current
VPIN 1 = 0.5 V, Pin 7
Open (2)
–2.5
–10
–2.5
–10
µA
Input Offset Current
VPIN 1 = 0.5 V, Pin 7
Open (2)
0.08
1
0.08
1
µA
5
Input Common Mode Range
Delay to Outputs
0
TJ = 25°C
(1)
25
VIN-3
5
0
200
500
0.5
0.55
–10
–30
350
400
250
VIN
0
V
25
mV
VIN-3
V
200
500
ns
0.5
0.55
V
–10
–30
µA
350
400
mV
VIN
V
CURRENT LIMIT ADJUST
Current Limit Offset
VPIN 3 = 0 V, VPIN 4 =
0 V, Pin 7 Open (2)
Input Bias Current
VPIN 5 = VREF, VPIN 6
=0V
0.45
0.45
SHUTDOWN TERMINAL
Threshold Voltage
250
Input Voltage Range
0
Minimum Latching Current
(IPIN1)
(4)
3.0
Maximum Latching Current
(IPIN1)
Delay to Outputs
1.5
(5)
TJ = 25°C
(1)
VC = 40 V
(6)
3.0
1.5
mA
1.5
0.8
1.5
0.8
mA
300
600
300
600
ns
OUTPUT
Collector-Emitter Voltage
Collector Leakage Current
Output Low Level
Output High Level
40
40
V
200
200
ISINK = 20 mA
0.1
0.4
0.1
0.4
ISINK = 100 mA
0.4
2.1
0.4
2.1
ISOURCE = 20 mA
13
13.5
13
13.5
ISOURCE = 100 mA
12
13.5
12
13.5
µA
V
V
Rise Time
CL = 1 nF, TJ = 25°C
50
300
50
300
ns
Fall Time
CL = 1 nF, TJ = 25°C
50
300
50
300
ns
7.7
8.0
7.7
8.0
V
(1)
(1)
UNDERVOLTAGE LOCKOUT
Start-Up Threshold
Threshold Hysteresis
0.75
0.75
V
TOTAL STANDBY CURRENT
Supply Current
(4)
(5)
(6)
6
17
21
17
21
mA
Current into Pin 1 ensured to latch circuit in shutdown state.
Current into Pin 1 ensured not to latch circuit in shutdown state.
Applies to UC1846/UC2846/UC3846 only due to polarity of outputs.
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6.6 Typical Characteristics
Figure 1. Error Amplifier Gain and Phase vs Frequency
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Figure 2. Error amplifier Open-Logic DC Gain vs Load
Resistance
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7 Detailed Description
7.1 Overview
The UCx846/7 family of control devices provides the necessary features to implement off-line or DC-to-DC fixedfrequency, current-mode control schemes with a minimal external parts count. Internally implemented circuits
include under-voltage lockout featuring start-up current less than 1 mA, a precision reference trimmed for
accuracy at the error amplifier input, logic to insure latched operation, a PWM comparator which also provides
current limit control, and a totem pole output stage designed to source or sink high-peak current. The output
stage, suitable for driving either N-Channel MOSFETs or bipolar transistor switches, is low in the off state.
7.2 Functional Block Diagram
5.1-V
REFERENCE
REGULATOR
VIN 15
2
VREF
13 VC
UVLO
LOCKOUT
SYNC 10
RT
9
CT
8
C/S-
3
Q
UC1846
Output Stage
Q
COMP
+
X3
4
11 A OUT
T
OSC
C/S+
F/F
+
S R
UC1847
Output Inverted
Q
S
0.5 V
14 B OUT
+
0.5 mA
NI
5
12 GND
+
E/A
INV
6
1
+
COMP
7
CURRENT LIMIT
ADJUST
16 SHUTDOWN
350 mV
6 k:
7.3 Feature Description
7.3.1 Current Sense Amplifier
The current sense amplifier may be used in a variety of ways to sense peak switch current for comparison with
an error voltage. Referring to Functional Block Diagram, maximum swing on the inverting input of the PWM
comparator is limited to approximately 3.5 V by the internal regulated supply. Accordingly, for a fixed gain of 3,
maximum differential voltages must be kept below 1.2 V at the current sense inputs.
8
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Feature Description (continued)
A small RC filter may be required in some applications to reduce switch transients.
Differential input allows remote, noise free sensing.
Figure 3. Current Sense Amplifier Connection
7.3.2 Oscillator
By implementing the oscillator using all NPN transistors, the UCx846/7 achieves excellent temperature stability
and waveform clarity at frequencies in excess of 1 MHz.
Referring to Figure 4, an external resistor RT is used to generate a constant current into a capacitor CT to
produce a linear sawtooth waveform. Oscillator frequency may be approximated by selecting RT and CT such
that:
2.2
fOSC
R T CT
(1)
Figure 4. Oscillator Circuit
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7.4 Device Functional Modes
7.4.1 Current Limit
One of the most attractive features of a current-mode converter is the ability to limit peak-switch currents on a
pulse-by-pulse basis by simply limiting the error voltage to a maximum value.
7.4.2 Shutdown
The shutdown circuit was designed to provide a fast acting general purpose shutdown port for use in
implementing both protection circuitry and remote shutdown functions. The circuit may be divided into an input
section consisting of a comparator with a 350-mV temperature compensated offset, and an output section
consisting of a three transistor latch. Shutdown is accomplished by applying a signal greater than 350 mV to pin
16, causing the output latch to fire, and setting the PWM latch to provide an immediate signal to the outputs.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCx846/7 family of control devices provides all of the necessary features to implement fixed frequency,
current mode control schemes while maintaining a minimum external parts count. The superior performance of
this technique can be measured in improved line regulation, enhanced load response characteristics, and a
simpler, easier to design control loop. Topological advantages include inherent pulse-by-pulse current limiting
capability, automatic symmetry correction for push-pull converters. Protection circuitry includes undervoltage
lockout and programmable current limit in addition to soft-start capability. A shutdown function is also available
which initiates either a complete shutdown with automatic restart or latch the supply off.
8.2 Typical Application
VIN
15
180Ÿ
2W
VIN
.1µF
2
.5k
VREF
VC
13
.05µF
1N4245
9
RT
AOUT
11
2N4150
UES1402
68Ÿ
.005µF
CT
3.2k
C/S+
+E/A
BOUT
1k
68Ÿ
14
300µF
2N4150
1N4245
UES1402
6
-E/A
7
.0015
VO
4
UCX846
5
100µF
3.2k
200µH
1k
8
C/S-
COMP
68k
SH-DN
16
CS/SS
3
.5Q
.05µF
1
VREF
1.5k
GND
12
1k
3.6k
Figure 5. Typical Application Diagram
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
DESIGN PARAMETER
TARGET VALUE
Typical efficiency
85%
Switching frequency
880 kHz
Pulse by pulse current limit threshold
1A
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8.2.2 Detailed Design Procedure
This section details the design procedure based on the design requirements.
8.2.2.1 Design Switching Frequency
Output deadtime is determined by the external capacitor, CT, according to the formula:
ª
º
«
»
ID
Td(Ps) 145CT (PF) «
»
3.6 »
« ID
«¬
RT (k:) »¼
where
•
ID = Oscillator discharge current at 25°C; typically is 7.5.
(2)
For large values of RT: τd (μs ) ≈145CT (μF).
Oscillator frequency is approximated by the formula:
2.2
fT (kHz) |
R T (k:) u CT (PF)
(3)
8.2.2.2 Error Amplifier Output Configuration
Figure 6. Error Amplifier Output Configuration
12
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Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: UC1846 UC1847 UC2846 UC2847 UC3846 UC3847
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
www.ti.com
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
8.2.2.3 Parallel Operation Configuration
Figure 7. Parallel Operation
8.2.2.4 Design Pulse by Pulse Current Limit Threshold
R 2 VREF
− 0.5
R1 + R 2
Peak Current (IS) is determined by the formula: IS =
3RS
Figure 8. Pulse by Pulse Current Limiting
Copyright © 1997–2015, Texas Instruments Incorporated
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13
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
www.ti.com
8.2.2.5 Soft-Start and Shutdown, Restart Function Design
Figure 9. Soft-Start and Shutdown, Restart Functions
14
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Product Folder Links: UC1846 UC1847 UC2846 UC2847 UC3846 UC3847
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
www.ti.com
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
8.2.3 Application Curves
t = 0.2 ms/div
output response = 20 mV/div
Figure 10. Responsive to a Step Load Change of 1 A
Figure 11. Switch Current Showing Flux Balance in
UCX846/7
9 Power Supply Recommendations
The VIN power terminal for the device requires the placement of low esr noise-decoupling capacitance as directly
as possible from the VIN terminal to the GND terminal. Ceramic capacitors with stable dielectric characteristics
over temperature are recommended, such as X7R or better.
The VC power terminal for the device requires the placement of resistance as directly as possible from the VC
terminal to the VIN terminal.
Copyright © 1997–2015, Texas Instruments Incorporated
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15
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
•
•
•
•
Place a low ESR and ESL decoupling capacitor CREF in the 1-µF to 2.2-µF range, preferably ceramic, from
VREF pin to GND.
The EA+ is a non-inverting input, the EA– is an inverting input and the COMP is the output of the error
amplifier. Place resistor and capacitor series network between EA+ pin and COMP pin, and reduce the trace
of resistor and capacitor series network as much as possible.
Place a low ESR and ESL capacitor CT, preferably ceramic, from CT pin to GND, and place CT close to
UCx846/7 as much as possible.
Place a resistor RT from RT pin to GND, and place RT close to UCx846/7 as much as possible.
10.2 Layout Example
Vin
1
SHUTDOWN
16
2 VREF
VIN
15
3 C/S-
BOUT
14
C/S+
VC
13
5 E/A+
GND
12
6 E/A-
AOUT
11
SYNC
10
4
C/S SS
7 COMP
8
CT
RT
9
Figure 12. UCx84x Layout Example
16
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Product Folder Links: UC1846 UC1847 UC2846 UC2847 UC3846 UC3847
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
www.ti.com
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
UC1846
Click here
Click here
Click here
Click here
Click here
UC1847
Click here
Click here
Click here
Click here
Click here
UC2846
Click here
Click here
Click here
Click here
Click here
UC2847
Click here
Click here
Click here
Click here
Click here
UC3846
Click here
Click here
Click here
Click here
Click here
UC3847
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1997–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: UC1846 UC1847 UC2846 UC2847 UC3846 UC3847
17
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-86806012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596286806012A
UC1846L/
883B
5962-8680601EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8680601EA
UC1846J/883B
UC1846J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
UC1846J
UC1846J/80257
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
-55 to 125
UC1846J/80364
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
-55 to 125
UC1846J/80619
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
-55 to 125
UC1846J883B
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8680601EA
UC1846J/883B
UC1846L883B
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596286806012A
UC1846L/
883B
UC1847J
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
-55 to 125
UC1847J883B
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
-55 to 125
UC1847L
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
UC1847L883B
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
UC2846DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2846DW
UC2846DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2846DW
UC2846DWTR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2846DW
UC2846DWTR/81265
OBSOLETE
SOIC
DW
16
TBD
Call TI
Call TI
UC2846DWTR/81265G4
OBSOLETE
SOIC
DW
16
TBD
Call TI
Call TI
UC2846DWTRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2846DW
UC2846J
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-40 to 85
UC2846J
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
UC2846N
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UC2846N
UC2846NG4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UC2846N
UC2846QTR
ACTIVE
PLCC
FN
20
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
UC2846Q
UC2847DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2847DW
UC2847DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UC2847DW
UC3846DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3846DW
UC3846DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3846DW
UC3846DWTR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3846DW
UC3846DWTRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3846DW
UC3846N
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UC3846N
UC3846NG4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
UC3846N
UC3846Q
ACTIVE
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
UC3846Q
UC3846QTR
ACTIVE
PLCC
FN
20
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
UC3846Q
UC3847DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3847DW
UC3847J
OBSOLETE
CDIP
J
16
TBD
Call TI
Call TI
0 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1846, UC1847, UC2846, UC2846M, UC3846, UC3847 :
• Catalog: UC3846, UC3847, UC2846
• Enhanced Product: UC1846-EP, UC1846-EP
• Military: UC2846M, UC1846, UC1847
• Space: UC1846-SP, UC1846-SP
NOTE: Qualified Version Definitions:
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UC2846DWTR
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
10.75
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.7
2.7
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UC2846DWTR
SOIC
DW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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